JP2019026526A - Method for manufacturing semiconductor laminate, method for manufacturing nitride semiconductor free-standing substrate, semiconductor laminate, and semiconductor device - Google Patents

Abstract

To provide a technique capable of manufacturing a semiconductor laminate excellent in crystal quality, a nitride semiconductor free-standing substrate and a semiconductor device.SOLUTION: The method for manufacturing a semiconductor laminate comprises the steps of: preparing a substrate stored in a substrate storing body consisting of an organic based resin material and having at least a surface layer consisting of a group III nitride semiconductor; inputting the substrate into a predetermined processing chamber from the substrate storing body to etch the entire surface of at least the surface layer of the substrate over a predetermined thickness or more in the vapor phase in the processing chamber; and epitaxially growing a semiconductor layer consisting of a group III nitride semiconductor on the substrate by a vapor phase growth method. In the etching step, adhering impurities caused by the substrate storing body in the substrate preparation step and adhering to the surface of the substrate are removed together with the group III nitride semiconductor constituting at least the surface layer of the substrate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for manufacturing a semiconductor laminate, a method for manufacturing a nitride semiconductor free-standing substrate, a semiconductor laminate, and a semiconductor device.

  Group III nitride semiconductors are widely used as materials constituting semiconductor devices such as light-emitting devices and electronic devices. In order to improve the quality (semiconductor characteristics, etc.) of a semiconductor device composed of a group III nitride semiconductor, a semiconductor laminate for manufacturing a semiconductor device or a nitride semiconductor free-standing substrate is manufactured so that the crystal quality is good. Is desired.

  As a method for manufacturing a nitride semiconductor free-standing substrate, for example, a step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate, and a step of manufacturing a nitride semiconductor free-standing substrate by slicing the semiconductor layer, Are known (for example, Patent Document 1).

JP 2008-156189 A

  In recent years, it has been desired to manufacture a semiconductor laminate, a nitride semiconductor free-standing substrate, or a semiconductor device having better crystal quality than conventional methods.

  An object of the present invention is to provide a technique capable of manufacturing a semiconductor laminate, a nitride semiconductor free-standing substrate, or a semiconductor device with good crystal quality.

According to one aspect of the invention,
A step of preparing a substrate housed in a substrate container made of an organic resin material and having at least a surface layer made of a group III nitride semiconductor;
Loading the substrate from the substrate container into a predetermined processing chamber, and etching the entire surface of at least the surface layer of the substrate over a predetermined thickness in a gas phase in the processing chamber;
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by vapor phase growth;
Have
In the etching step,
A method of manufacturing a semiconductor laminate, wherein adhesion impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate are removed together with the group III nitride semiconductor constituting at least the surface layer of the substrate. , And related techniques.

  According to the present invention, it is possible to manufacture a semiconductor laminate, a nitride semiconductor free-standing substrate, or a semiconductor device with good crystal quality.

It is a flowchart which shows the manufacturing method of the semiconductor laminated body which concerns on 1st Embodiment of this invention, or the manufacturing method of the nitride semiconductor self-supporting substrate. (A) is a schematic sectional drawing which shows a board | substrate, (b) is a schematic sectional drawing which shows the board | substrate accommodated in the board | substrate container at the board | substrate preparation process, (c) is a board | substrate in a board | substrate preparation process. It is a general | schematic expanded sectional view which shows. It is a schematic block diagram of the vapor phase growth apparatus used for the manufacturing method which concerns on 1st Embodiment of this invention. It is a figure which shows the temperature change of the board | substrate from the etch process of 1st Embodiment of this invention to a vapor phase growth process. (A) is a schematic sectional drawing which shows the board | substrate in an etching process, (b) is a schematic sectional drawing which shows the board | substrate after an etching process. (A) is a schematic sectional drawing which shows the semiconductor laminated body in a vapor phase growth process, (b) is a schematic sectional drawing which shows the nitride semiconductor self-supporting substrate produced at a slicing process. It is a flowchart which shows the manufacturing method of the semiconductor laminated body which concerns on 2nd Embodiment of this invention, or the manufacturing method of a semiconductor device. (A) is a schematic sectional drawing which shows the semiconductor laminated body concerning 2nd Embodiment of this invention, (b) is a schematic sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment of this invention. (A) is a schematic sectional drawing which shows the semiconductor laminated body concerning the modification of 2nd Embodiment of this invention, (b) is the outline which shows the semiconductor device which concerns on the modification of 2nd Embodiment of this invention. It is sectional drawing. (A) is a SEM image which shows an example of an adhesion impurity, (b) is the result of having performed the EDX analysis of the adhesion impurity of (a). It is a figure which shows Si density | concentration of the substrate surface measured by the total reflection X-ray fluorescence analysis with respect to the storage days which stored the board | substrate in the substrate container. (A) is a photograph which shows the external appearance of the semiconductor laminated body of an Example, (b) is a photograph which shows the external appearance of the semiconductor laminated body of a comparative example. (A)-(c) is a figure which shows the pit and morphology abnormality part in the surface of the semiconductor laminated body of a comparative example.

<Knowledge obtained by the inventors>
First, knowledge obtained by the inventors will be described.

  The inventors of the present invention have intensively studied to manufacture a semiconductor laminate, a nitride semiconductor free-standing substrate, or a semiconductor device using a substrate housed in a substrate housing made of an organic resin material. The present inventors have found that the quality of a nitride semiconductor free-standing substrate or a semiconductor device may be deteriorated.

  When a substrate is stored in a substrate container made of an organic resin material for a long period of time, adhering impurities may adhere to the surface of the substrate due to the substrate container. Specifically, the substrate container is made of, for example, polypropylene (PP). When manufacturing the substrate container, an additive such as a stabilizer (such as an antioxidant or a light stabilizer) is added to the pellet of the resin composition as a precursor. In addition, a mold release agent is applied to the surface of the mold during mold molding. In addition, a mold release agent may be added as an additive in a resin composition. Such additives and the like may remain in the substrate container even after the substrate container is manufactured (molded). For this reason, when a substrate is accommodated in the substrate container for a long time, the additive or the like becomes outgas and is released from the substrate container, and adhering impurities adhere to the surface of the substrate.

  It is often not disclosed as a manufacturer's know-how what additives are used when manufacturing the substrate container, and the user of the substrate container specifies a detailed type of additive, etc. I can't. For this reason, even if there is a risk of adhering impurities on the substrate, it is not known what material the adhering impurities are adhering to the substrate, and the methods and conditions for removing the adhering impurities I didn't know what to do. In addition, since the amount of additives and the like remaining in the substrate container may vary depending on the lot in which the substrate container is manufactured, it is difficult to grasp the amount of adhering impurities adhering to the substrate. Furthermore, since such adhering impurities adhere with a thickness of one to several monolayers, they cannot be found even if the substrate is observed with an optical microscope or the like, and the adhering position and the adhering range in plan view can be reduced. Could not be identified. For the above reasons, it is difficult to directly remove the adhering impurities adhering to the substrate before manufacturing the semiconductor laminate and the like.

  Even when the substrate is washed with a predetermined solvent, adhering impurities may adhere and remain on the surface of the substrate. Even when the cleaning is caused, it is not known what kind of adhering impurities are deposited on the substrate. Thus, the semiconductor laminate is manufactured in the same manner as in the case of the substrate container. Previously, it was difficult to directly remove the adhering impurities adhering to the substrate.

  When a semiconductor layer is epitaxially grown by vapor deposition on a substrate to which such attached impurities are attached, there is a possibility that pits or morphology abnormalities may be generated at positions overlapping the attached impurities on the surface of the semiconductor layer. There is. Note that pits and morphology abnormal parts may be caused by inversion domains (ID: Inversion Domain) whose polarity is reversed with respect to other regions of the semiconductor layer. When pits and morphology abnormalities occur on the surface of the semiconductor layer, the concentration of oxygen (O) increases in facet growth zones other than the c-plane, such as pit slopes and slopes of morphology abnormalities. In the portion where the O concentration is high, the carrier concentration is relatively higher than in other portions, and the resistance is locally reduced. In this manner, when a low resistance portion is locally generated in the semiconductor layer, there is a possibility that the characteristics of the semiconductor device vary in the plane.

  In addition, when a semiconductor layer is epitaxially grown by vapor deposition on a substrate to which attached impurities are attached, a non-growth region in which the semiconductor layer is not grown may be formed on the attached impurities. In this case, when the nitride semiconductor free-standing substrate is manufactured by slicing the semiconductor layer, a through hole is formed at a position corresponding to the non-growth region of the semiconductor layer in the nitride semiconductor free-standing substrate. If a through-hole is formed in a nitride semiconductor free-standing substrate, various problems may occur in the process of manufacturing a semiconductor device using the nitride semiconductor free-standing substrate. Specifically, for example, when a semiconductor layer is epitaxially grown on a nitride semiconductor free-standing substrate, there is a possibility that parasitic growth occurs due to a through hole, and the growth furnace is contaminated. Further, for example, there is a possibility that the nitride semiconductor free-standing substrate cannot be transported by vacuum suction. Also, for example, when forming a resist film on a nitride semiconductor free-standing substrate by spin coating or the like, a resist solution is sucked into the nitride semiconductor free-standing substrate through a through-hole, or a vacuum suction pump is connected to the through-hole. There is a possibility that the pump may break down due to inhalation of the resist solution through the.

  In addition, when many attached impurities adhere to the substrate, outgas may be generated from the attached impurities. For this reason, there is a possibility that a large amount of impurities (impurity elements such as O) are taken into the semiconductor layer or a large number of crystal defects are formed in the semiconductor layer due to outgas derived from the attached impurities. is there.

  The present invention described below is based on the above-described new problem found by the present inventors.

<First Embodiment of the Present Invention>
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

(1) Manufacturing Method of Semiconductor Stack or Manufacturing Method of Nitride Semiconductor Freestanding Substrate With reference to FIGS. 1 to 6, a manufacturing method of a semiconductor stack or a manufacturing method of a nitride semiconductor free standing substrate according to this embodiment will be described. FIG. 1 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride semiconductor free-standing substrate according to this embodiment. Note that step is abbreviated as S. 2A is a schematic cross-sectional view showing the substrate, FIG. 2B is a schematic cross-sectional view showing the substrate accommodated in the substrate container in the substrate preparing step, and FIG. 2C is a substrate preparing step. It is a general | schematic expanded sectional view which shows this board | substrate. FIG. 3 is a schematic configuration diagram of a vapor phase growth apparatus used in the manufacturing method according to the present embodiment. FIG. 4 is a diagram showing the temperature change of the substrate from the etching process to the vapor phase growth process of the present embodiment. FIG. 5A is a schematic cross-sectional view showing the substrate in the etching process, and FIG. 5B is a schematic cross-sectional view showing the substrate after the etching process. FIG. 6A is a schematic cross-sectional view showing a semiconductor stacked body in a vapor phase growth process, and FIG. 6B is a schematic cross-sectional view showing a nitride semiconductor free-standing substrate manufactured in a slicing process.

  In the following, in various substrates used in this embodiment, the upper main surface (first main surface, upper surface) is referred to as “front surface”, and the lower main surface (second main surface, lower surface) is referred to as “back surface”. .

  In the present embodiment, as a group III nitride semiconductor, for example, a case where a semiconductor laminate 1 made of gallium nitride (GaN) or a nitride semiconductor free-standing substrate (hereinafter also simply referred to as a free-standing substrate) 2 will be described.

(S120: Substrate preparation process)
First, a substrate preparation step S120 for preparing a substrate (base substrate, seed crystal substrate) 10 having at least a surface layer made of a group III nitride semiconductor is performed.

  The substrate 10 shown in FIG. 2A is configured as, for example, a group III nitride semiconductor free-standing substrate or a group III nitride semiconductor template. Here, the substrate 10 is, for example, a GaN free-standing substrate manufactured by a vapor deposition method.

The substrate 10 has a surface 10a as a crystal growth surface and a back surface 10b opposite to the surface 10a. The surface 10a of the substrate 10 is, for example, a (0001) plane (+ C plane, Ga polar plane) or a plane having a predetermined off angle with respect to the (0001) plane. The magnitude of the off angle (off amount) is, for example, within 2 °. Further, the dislocation density (average dislocation density) on the surface 10a of the substrate 10 is, for example, 1 × 10 ³ pieces / cm ² or more and 1 × 10 ⁷ pieces / cm ² or less.

  At this time, as shown in FIG. 2B, the substrate 10 is accommodated in a substrate container 200 made of, for example, an organic resin material. Examples of the resin material constituting the substrate container 200 include polypropylene (PP), polycarbonate (PC), polytetrafluoroethylene (PTFE), perfluoroalkoxyalkane (PFA), and the like. Here, the substrate container 200 is made of PP, for example.

  In the present embodiment, the substrate container 200 that accommodates the substrate 10 is configured as a so-called wafer tray, for example. Specifically, the substrate container 200 includes, for example, a tray body part 210, a lid part 220, and a spring part 230. The tray main body 210 has, for example, a curved recess (not shown). The lid 220 is screwed (engaged) with the tray body 210 to seal the tray body 210. The spring part 230 is a curved plate-like member.

  When the substrate 10 is accommodated in the substrate container 200, first, the substrate 10 is placed in the recess of the tray body 210 so that the surface 10 a of the substrate 10 faces the recess of the tray body 210. When the substrate 10 is placed on the tray main body 210, the spring portion 230 is interposed between the back surface 10 b of the substrate 10 and the lid portion 220, and the lid portion 220 is screwed with the tray main body portion 210. Thereby, the board | substrate 10 can be accommodated in the space between the tray main-body part 210 and the cover part 220. FIG. Further, the substrate 10 can be suppressed from being displaced by pressing the substrate 10 against the recess of the tray main body 210 by the spring portion 230.

  The substrate 10 is stored in the substrate container 200 for a predetermined period until the semiconductor laminate 1 or the self-supporting substrate 2 is manufactured. When a large number of substrates 10 used for manufacturing the semiconductor laminate 1 or the self-supporting substrate 2 are prepared, the accommodation period of the substrate 10 may be long. Here, the substrate 10 is accommodated in the substrate container 200 for at least 12 hours, for example.

  As described above, when the substrate is accommodated in the organic substrate container 200 for a long period of time, as shown in FIG. 2C, the adhesion impurity 20 adheres to the surface 10a of the substrate 10 due to the substrate container 200. Sometimes. Specifically, for example, an additive or the like remaining in the substrate container 200 becomes outgas and is released from the substrate container 200, and the adhering impurities 20 may adhere to the surface 10 a of the substrate 10. For example, when a mold release agent is used when manufacturing the substrate container 200, the adhesion impurity 20 contains at least siloxane, for example. Moreover, the thickness of the adhesion impurity 20 is 1 to several monolayers, for example.

  As described above, when the accommodation period of the substrate 10 in the substrate container 200 becomes longer, the attached impurities 20 are likely to adhere to the surface 10 a of the substrate 10. In particular, when the accommodation period of the substrate 10 in the substrate container 200 is 12 hours or more as described above, the tendency becomes remarkable.

  In particular, when the substrate container 200 is configured as a wafer tray as described above, the surface 10a of the substrate 10 is close to the concave portion of the tray main body 210, and thus the adhering impurities 20 as described above are present in the substrate 10. It is easy to adhere to the surface 10a.

  Thus, once the attached impurity 20 adheres to the surface 10a of the substrate 10, it is difficult to remove the attached impurity 20 directly. This is because, as described above, the detailed types such as the additive of the substrate container 200 that causes the adhering impurities 20 are not disclosed as the know-how of the manufacturer and cannot be specified. In many cases, it is unknown or the method and conditions for removing the adhering impurities 20 are unknown. For this reason, it is difficult to directly remove the adhering impurities 20 adhering to the substrate 10. Further, such an adhesion impurity 20 may be firmly adhered to the surface 10 a of the substrate 10. For this reason, once the adhering impurity 20 adheres, it is difficult to remove the adhering impurity 20 even if it is washed with a predetermined solvent or the like. In particular, it has been found that the adhesion impurity 20 tends to remain on the surface 10a of the substrate 10 when the adhesion impurity 20 contains siloxane.

  Therefore, in the present embodiment, the following etching step S140 is performed before the vapor phase growth step S160.

(S140: Etching process)
In this embodiment, for example, using the vapor phase growth apparatus 400 shown in FIG. 3, an etching step S140 for etching the surface 10a of the substrate 10 in the vapor phase is performed.

The vapor phase growth apparatus 400 is configured as, for example, a hydride vapor phase growth apparatus (HVPE apparatus). The vapor phase growth apparatus 400 includes an airtight container 403 made of a heat resistant material such as quartz and having a processing chamber 401 formed therein. A susceptor 408 that holds the substrate 10 is provided in the processing chamber 401. The susceptor 408 is connected to a rotation shaft 415 included in the rotation mechanism 416, and is configured to be able to rotate the substrate 10 placed on the susceptor 408 in the circumferential direction (direction along the upper surface). A gas supply pipe 432a that supplies hydrogen chloride (HCl) gas into a gas generator 433a described later and a gas that supplies ammonia (NH ₃ ) gas as a film forming gas into the processing chamber 401 are provided at one end of the hermetic vessel 403. A supply pipe 432b and a gas supply pipe 432c for supplying HCl gas as an etching gas into the processing chamber 401 are connected to each other. Note that in addition to the HCl gas and the NH ₃ gas, the gas supply pipes 432a to 432c include hydrogen (H ₂ ) gas as a carrier gas or an etching gas, and nitrogen (N ₂ as an inert gas, carrier gas, or purge gas). ) It is also configured to be able to supply gas. Each of the gas supply pipes 432a to 432c includes a flow rate controller and a valve (both not shown) for each of these gas types, and individually controls the flow rate and supply start / stop of various gases for each gas type. It is configured to be able to do. A gas generator 433a that stores Ga melt as a raw material is provided downstream of the gas supply pipe 432a. The gas generator 433 a has a nozzle 449 a that supplies gallium chloride (GaCl) gas as a film forming gas generated by the reaction of HCl gas and Ga melt toward the substrate 10 held on the susceptor 408. It is connected. On the downstream side of the gas supply pipes 432b and 432c, nozzles 449b and 449c for supplying the gas supplied from these gas supply pipes toward the substrate 10 held on the susceptor 408 are respectively connected. The nozzles 449 a to 449 c are arranged to flow gas in a direction parallel to the upper surface of the substrate 10 (direction along the upper surface). On the other hand, an exhaust pipe 430 for exhausting the inside of the processing chamber 401 is provided at the other end of the airtight container 403. The exhaust pipe 430 is provided with a pump 431 via a pressure regulator (APC) 429. A zone heater 407 that heats the substrate 10 held in the gas generator 433 a and the susceptor 408 to a desired temperature is provided on the outer periphery of the hermetic container 403, and a temperature at which the temperature in the processing chamber 401 is measured in the hermetic container 403. Each sensor 409 is provided. Each member included in the vapor phase growth apparatus 400 is connected to a controller 480 configured as a computer, and is configured such that processing procedures and processing conditions described later are controlled by a program executed on the controller 480. Yes.

  The etching step S140 can be performed using the above-described vapor phase growth apparatus 400, for example, according to the following processing procedure.

First, the substrate 10 is taken out from the substrate container 200. When the substrate 10 is taken out, the substrate 10 is put (loaded) into the airtight container 403 (processing chamber 401) and held on the susceptor 408. At this time, a Ga melt as a raw material used in the vapor phase growth step S160 described later is stored in the gas generator 433a. Next, N ₂ gas is supplied into the processing chamber 401 from at least one of the gas supply pipes 432a to 432c, and the processing chamber 401 is heated and exhausted. At this time, rotation of the susceptor 408 is also started.

  As shown in FIG. 4, the temperature of the substrate 10 gradually increases due to heating in the processing chamber 401. When the temperature of the substrate 10 reaches a predetermined temperature Te and the pressure in the processing chamber 401 reaches a predetermined pressure, a predetermined etching gas is supplied to the upper surface of the substrate 10.

  As a result, as shown in FIG. 5A, the entire surface 10a of the substrate 10 can be etched in a gas phase over a predetermined thickness (depth). At this time, a portion of the substrate 10 that is etched is a portion that is exposed to the outside atmosphere of the substrate 10 and can be in contact with the outside atmosphere (for example, etching gas). In addition, not only the surface 10a of the substrate 10 but also the side surface of the substrate 10 is etched.

  At this time, as shown in FIG. 5A, the adhering impurities 20 attached to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with GaN constituting the matrix of the substrate 10. That is, the etching gas supplied to the surface 10a of the substrate 10 immediately reaches the exposed portion of the surface 10a of the substrate 10 and etches the exposed portion. At this time, the attached impurity 20 attached to the surface 10a of the substrate 10 may not be etched by the etching gas. As the exposed portion of the surface 10 a of the substrate 10 is etched, the etching gas enters between the surface 10 a of the substrate 10 and the attached impurity 20. When all the portions of the surface 10a of the substrate 10 that are in contact with the attached impurities 20 are etched, the attached impurities 20 are peeled off from the surface 10a of the substrate 10. The peeled attached impurities 20 are removed (discharged) to the outside of the substrate 10 according to the flow of the etching gas with respect to the surface 10 a of the substrate 10. In this way, the attached impurities 20 attached to the surface 10a of the substrate 10 can be removed together with GaN constituting the matrix of the substrate 10.

  In the above process of removing the adhering impurities 20 together with the matrix of the substrate 10, it is considered that the adhering impurities 20 are removed together with GaN on the principle similar to so-called “lift-off” used for patterning of a metal film or the like in a semiconductor process. May be.

  At this time, etching is performed for at least one hour or more with the temperature of the substrate 10 maintained at a predetermined temperature. If the etching time is less than 1 hour, the surface 10a of the substrate 10 may not be sufficiently etched. For this reason, there is a possibility that the adhering impurities 20 may remain in a portion that is not etched on the surface 10 a of the substrate 10. On the other hand, by setting the etching time to 1 hour or longer, the entire surface 10a of the substrate 10 can be reliably etched over a predetermined thickness. As a result, the adhered impurity 20 can be removed together with the matrix of the substrate 10 wherever the adhered impurity 20 is adhered on the surface 10 a of the substrate 10.

  At this time, the surface 10a of the substrate 10 is etched at least 10 nm in the depth direction. When the etching depth is less than 10 nm, a portion where the etching gas does not enter between the surface 10a of the substrate 10 and the attached impurity 20 is generated, and the attached impurity 20 may remain on the surface 10a of the substrate 10. is there. On the other hand, by setting the etching depth to 10 nm or more, the etching gas sufficiently enters between the surface 10a of the substrate 10 and the adhering impurities 20, and the portion of the surface 10a of the substrate 10 that contacts the adhering impurities 20 is removed. It can be removed reliably. As a result, the adhering impurities 20 can be reliably removed together with the matrix of the substrate 10.

  At this time, the surface 10a of the substrate 10 is etched under the condition that the region excluding the crystal defect portion of the surface 10a of the substrate 10 is smooth. Here, the “crystal defect portion” of the substrate 10 is a dislocation, a pit, or the like. In addition, “the condition that the region excluding the crystal defect portion of the surface 10a of the substrate 10 is smooth” here refers to the region excluding the crystal defect portion of the surface 10a of the substrate 10, that is, no etch pits. When compared in the visual field (for example, 1 μm square visual field), the difference between the surface roughness before the etching step S140 (arithmetic average roughness Ra) and the surface roughness after the etching step S140 is within 10 nm, preferably within 5 nm. It is a condition. By maintaining the surface 10a of the substrate 10 smooth under such mild etching conditions, the semiconductor layer 40 can be epitaxially grown on the surface 10a of the substrate 10 smoothly in the vapor phase growth step S160 described later.

  As shown in FIG. 5B, even when etching is performed under the above conditions, the surface 10a of the substrate 10 has an etch pit 10ep corresponding to dislocations as crystal defects in the substrate 10. Can appear.

As specific etching conditions, for example, etching is performed in an atmosphere containing HCl gas and H ₂ gas as an etching gas. For example, HCl gas and H ₂ gas as etching gases are supplied from the gas supply pipe 432c to the surface 10a of the substrate 10. By performing etching in an atmosphere containing HCl gas, GaN constituting the substrate 10 can be etched by the following reaction formula (1).
2GaN + 2HCl → 2GaCl + H ₂ + N ₂ (1)
At this time, Ga droplets may be generated as a by-product due to a reaction other than the reaction formula (1). Here, since the mild etching conditions are applied as described above, the Ga droplet is likely to be generated. Therefore, by performing etching in an atmosphere containing H ₂ gas in addition to HCl gas, Ga droplets as by-products can be vaporized and removed as gallium (GaH ₃ ) which is a hydride of Ga. .

Further, for example, etching is performed in an atmosphere containing N ₂ gas as an inert gas (dilution gas) in addition to HCl gas and H ₂ gas as the above-described etching gas, and the partial pressure of N ₂ gas is adjusted to HCl gas and Higher than the respective partial pressures of H ₂ gas. Thereby, the surface 10a of the substrate 10 can be mildly etched, and the region excluding the crystal defect portion in the surface 10a of the substrate 10 can be kept smooth.

At this time, the ratio of the partial pressures of HCl gas and H ₂ gas to the partial pressure of N ₂ gas (partial pressure ratio) is, for example, 1% or more and 10% or less. If the partial pressure ratio is less than 1%, the etching rate of GaN constituting the substrate 10 becomes low, so that the time until the attached impurity 20 is removed may become excessively long. On the other hand, by setting the partial pressure ratio to 1% or more, the etching rate of GaN constituting the substrate 10 is secured to a predetermined value or more, and the time until the adhered impurities 20 are removed is suppressed. Can do. On the other hand, if the partial pressure ratio is more than 10%, GaN constituting the substrate 10 is excessively etched, so that the surface 10a of the substrate 10 may be roughened. On the other hand, by setting the partial pressure ratio to 10% or less, the surface 10a of the substrate 10 can be mildly etched, and the region excluding the crystal defect portion of the surface 10a of the substrate 10 can be kept smooth.

Further, for example, etching is performed in an atmosphere containing no NH ₃ gas. When etching is performed in an atmosphere containing NH ₃ gas, a Ga-containing gas (GaCl or GaH ₃ ) generated by a reaction between GaN constituting the substrate 10 and each of HCl gas and H ₂ gas, NH ₃ gas, Reacts to re-grow GaN on the surface 10 a of the substrate 10. Since the regrown GaN is formed in an irregular shape, the surface 10a of the substrate 10 may be roughened. On the other hand, regrowth of GaN can be suppressed by performing etching in an atmosphere containing no NH ₃ gas. Thereby, the surface 10a of the board | substrate 10 can be maintained smooth.

  Further, the temperature (etching temperature) Te of the substrate 10 in the etching step S140 is set to, for example, a critical temperature (hereinafter referred to as an etching critical temperature) at which GaN constituting the substrate 10 starts to be etched. Thereby, the adhering impurities 20 on the surface 10a can be removed while etching the GaN constituting the surface 10a of the substrate 10.

  On the other hand, as shown in FIG. 4, the etching temperature Te of the substrate 10 in the etching step S140 is, for example, lower than the temperature (film formation temperature) Tg of the substrate 10 in the vapor phase growth step S160 described later. Thereby, the surface 10a of the substrate 10 can be mildly etched, and the region excluding the crystal defect portion in the surface 10a of the substrate 10 can be kept smooth.

Examples of more detailed etching conditions in the etching step S140 include the following.
Etching temperature Te: 500 to 900 ° C., preferably 600 to 800 ° C.
Pressure in the processing chamber 401: 90 to 105 kPa, preferably 90 to 95 kPa
HCl gas partial pressure / N ₂ gas partial pressure: 1 to 10%, preferably 1 to 5%
H ₂ gas partial pressure / N ₂ gas partial pressure: 1 to 10%, preferably 3 to 7%
Gas flow rate: 5-15 cm / s
(Note that the gas flow rate is a value calculated from the gas supply amount without considering volume expansion due to heating.)
Etching time: 1-10h, preferably 2-5h
Etching rate: 0.1 to 10 μm / h, preferably 0.5 to 3 μm / h

  By the etching described above, as shown in FIG. 5B, the attached impurities 20 attached to the surface 10a of the substrate 10 can be removed. The surface 10a of the substrate 10 is etched as indicated by the dotted arrow.

When the attached impurities 20 are removed from the surface 10a of the substrate 10, the supply of HCl gas and H ₂ gas as the etching gas into the processing chamber 401 is stopped, and the etching step S140 is ended.

(S160: Vapor growth process)
Next, a vapor phase growth step S160 is performed in which a semiconductor layer (vapor phase growth layer) 40 made of a group III nitride semiconductor is epitaxially grown on the surface 10a of the substrate 10 by a vapor phase growth method.

  In the present embodiment, for example, the semiconductor layer 40 is epitaxially grown by the HVPE method using the vapor phase growth apparatus 400 described above.

  In the present embodiment, after the etching step S140 is completed, the processing chamber 401 of the vapor phase growth apparatus 400 is not released to the atmosphere, and the substrate 10 is not carried out of the processing chamber 401. In the processing chamber 401 of the phase growth apparatus 400, the following vapor phase growth step S160 is continuously performed. In that sense, the above-described etching step S140 can be considered as an in-situ etching step (in-situ etching step).

  Specifically, the vapor phase growth step S160 can be performed, for example, by the following processing procedure.

After the supply of HCl gas and H ₂ gas as the etching gas into the processing chamber 401 is stopped in the etching step S140, the supply of N ₂ gas into the processing chamber 401, the exhaust in the processing chamber 401, and the susceptor With the substrate 10 held and rotated by 408, NH ₃ gas is supplied from the gas supply pipe 432b to the surface 10a of the substrate 10 in the processing chamber 401. That is, the atmosphere in the processing chamber 401 is switched to an atmosphere containing no etching gas, that is, an atmosphere containing NH ₃ gas and N ₂ gas. Thereby, at the time of temperature rise, decomposition | disassembly of GaN which comprises the board | substrate 10 can be suppressed, and the surface roughness of the board | substrate 10 can be suppressed. When NH ₃ gas is supplied into the processing chamber 401, the processing chamber 401 is further heated.

  As shown in FIG. 4, the temperature of the substrate 10 is raised above the etching temperature Te in the etching step S <b> 140 by heating in the processing chamber 401. At this time, the temperature of the substrate 10 is monotonously increased from the etching step S140 to the vapor phase growth step S160. That is, the temperature of the substrate 10 is not temporarily lowered or the temperature of the substrate 10 is not overshooted between the etching step S140 and the gas phase step S160. Thereby, the reattachment of the adhesion impurity 20 can be suppressed.

When the temperature of the substrate 10 reaches a predetermined temperature Tg and the pressure in the processing chamber 401 reaches a predetermined pressure, the gas is supplied from the gas supply pipe 432a in a state where NH ₃ gas is supplied to the surface 10a of the substrate 10. HCl gas is supplied into the generator 433 a and GaCl gas is supplied to the surface 10 a of the substrate 10. At this time, H ₂ gas may be supplied into the processing chamber 401.

  Thereby, as shown in FIG. 6A, the semiconductor layer 40 made of GaN is epitaxially grown on the surface 10 a of the substrate 10.

  At this time, as described above, since the surface 10a of the substrate 10 is mildly etched in the etching step S140, the semiconductor layer 40 can be epitaxially grown on the surface 10a of the substrate 10 smoothly. The generation of facets other than the crystal plane ((0001) plane) constituting 10a can be suppressed.

  At this time, as described above, the etch pits 10ep that appear on the surface 10a of the substrate 10 in the etching step S140 are filled with the semiconductor layer 40. Thereby, even if the etch pit 10ep appears on the surface 10a of the substrate 10, the semiconductor layer 40 can be epitaxially grown smoothly on the surface 10a of the substrate 10.

At this time, the dislocation density on the surface of the semiconductor layer 40 can be made equal to or less than the dislocation density on the surface 10 a of the substrate 10. Specifically, the dislocation density on the surface of the semiconductor layer 40 can be, for example, 1 × 10 ³ pieces / cm ² or more and 1 × 10 ⁷ pieces / cm ² or less.

  At this time, a GaN free-standing substrate is used as the substrate 10, and a semiconductor layer 40 made of GaN having a lattice constant equal to the lattice constant of the substrate 10 is homoepitaxially grown on the substrate 10. Layer 40 can be formed. In addition, by making the linear expansion coefficient of the substrate 10 and the linear expansion coefficient of the semiconductor layer 40 equal, even when the temperature of the substrate 10 is lowered after the growth of the semiconductor layer 40, cracks in the substrate 10 and the semiconductor layer 40 can be obtained. Can be suppressed. As a result, the semiconductor layer 40 can be formed in a thick film. Specifically, the thickness of the semiconductor layer 40 can be, for example, 45 μm or more and 5 mm or less, preferably 150 μm or more and 2 mm or less.

Examples of the growth conditions for performing the vapor phase growth step S160 include the following.
Growth temperature Tg: 980-1100 ° C., preferably 1050-1100 ° C.
Pressure in the processing chamber 401: 90 to 105 kPa, preferably 90 to 95 kPa
GaCl gas partial pressure: 1.5 to 15 kPa
NH ₃ gas partial pressure / GaCl gas partial pressure: 2-6
N ₂ gas flow rate / H ₂ gas flow rate: 1 to 20
Gas flow rate: 5-15 cm / s
(Note that the gas flow rate is a value calculated from the gas supply amount without considering volume expansion due to heating.)

  By growing the semiconductor layer 40 under the above growth conditions, the semiconductor laminate 1 having the substrate 10 and the semiconductor layer 40 can be manufactured.

When the growth of the semiconductor layer 40 is completed, the supply of HCl gas into the gas generator 433a and the processing chamber are performed while the processing chamber 401 is exhausted while supplying the NH ₃ gas and the N ₂ gas into the processing chamber 401. Supply of H ₂ gas into 401 and heating by the heater 407 are stopped. When the temperature in the processing chamber 401 becomes 500 ° C. or lower, the supply of NH ₃ gas is stopped, and then the atmosphere in the processing chamber 401 is replaced with N ₂ gas to return to the atmospheric pressure. After the temperature is lowered to a temperature at which it can be carried out, the semiconductor laminate 1 is carried out from the processing chamber 401.

(S180: Slicing step)
Next, as shown in FIG. 6B, the semiconductor layer 40 of the semiconductor stacked body 1 is sliced to produce a plurality of free-standing substrates 2 as GaN free-standing substrates.

  Thereafter, at least the surface of the free-standing substrate 2 is polished to make the surface of the free-standing substrate 2 an epi-ready surface. After the polishing of the freestanding substrate 2 is completed, the freestanding substrate 2 is subjected to predetermined cleaning.

  As described above, the self-supporting substrate 2 of the present embodiment is manufactured.

The surface of the self-standing substrate 2 manufactured in this way is the (0001) plane or a plane having a predetermined off angle with respect to the (0001) plane, like the substrate 10. Further, the dislocation density on the surface of the free-standing substrate 2 is, for example, 1 × 10 ³ pieces / cm ² or more and 1 × 10 ⁷ pieces / cm ² or less, similarly to the dislocation density on the surface of the semiconductor layer 40 described above.

  Note that the above-described vapor phase growth step S160 may be performed again using the substrate 10 or the semiconductor stack 1 left after slicing the free-standing substrate 2 or the sliced free-standing substrate 2. Thereby, the self-supporting substrate 2 with good crystal quality can be repeatedly manufactured.

(2) Effects Obtained by the Present Embodiment According to the present embodiment, one or more effects shown below can be obtained.

(A) In the etching step S140, the entire surface 10a of the substrate 10 is etched in a gas phase over a predetermined thickness. At this time, the adhering impurities 20 adhered to the surface 10a of the substrate 10 due to the substrate container 200 in the substrate preparation step S120 are removed together with GaN constituting the matrix of the substrate 10. Thereby, in vapor phase growth process S160, generation | occurrence | production of the pit and the morphology abnormal part in the surface of the semiconductor layer 40 can be suppressed, and local uptake | capture of O in the semiconductor layer 40 can be suppressed. As a result, the carrier concentration in the semiconductor layer 40 can be made uniform in the plane, and the resistance of the semiconductor layer 40 can be made uniform in the plane.

  In addition, in the etching step S140, by removing the adhering impurities 20 attached to the surface 10a of the substrate 10 together with GaN, formation of a non-growth region where the semiconductor layer 40 is not grown can be suppressed. By suppressing the formation of the non-growth region in the semiconductor layer 40, the formation of the through hole in the free-standing substrate 2 can be suppressed when the semiconductor layer 40 is sliced and the free-standing substrate 2 is manufactured in the slicing step S180.

  Further, even if many adhering impurities 20 are adhering to the surface 10a of the substrate 10, the adhering impurities 20 are removed together with GaN in the etching step S140, so that the adhering impurities 20 are removed in the vapor phase growth step S160. Generation | occurrence | production of the outgas originating can also be suppressed. The semiconductor layer 40 is epitaxially grown while suppressing the generation of outgas originating from the attached impurities 20, thereby suppressing the incorporation of impurities into the semiconductor layer 40 and suppressing the formation of crystal defect portions in the semiconductor layer 40. be able to.

  Thus, according to the present embodiment, it is possible to manufacture the semiconductor laminate 1 or the self-supporting substrate 2 with good crystal quality.

(B) In the etching step S140, the attached impurities 20 are removed by etching the matrix of the substrate 10 to which the attached impurities 20 are attached, instead of directly etching the attached impurities 20. Thus, even if the material of the adhering impurity 20, the amount of the adhering impurity 20, the position of the adhering impurity 20, or the adhering range of the adhering impurity 20 in a plan view is unknown, the adhering impurity 20 is removed from the matrix of the substrate 10. And can be removed reliably.

(C) In the etching step S140, the surface 10a of the substrate 10 is etched under a condition that the region excluding the crystal defect portion of the surface 10a of the substrate 10 is smooth. By maintaining the surface 10a of the substrate 10 smooth under such mild etching conditions, the semiconductor layer 40 can be epitaxially grown smoothly on the surface 10a of the substrate 10 in the vapor phase growth step S160. At this time, the generation of facets other than the crystal planes constituting the surface of the semiconductor layer 40 can be suppressed. If facets other than the crystal planes constituting the surface of the semiconductor layer 40 occur during the growth of the semiconductor layer 40, the incorporation of impurities into the semiconductor layer 40 increases. On the other hand, in the present embodiment, the incorporation of impurities into the semiconductor layer 40 can be suppressed by suppressing the occurrence of such facets.

(D) The etching step S140 and the vapor phase growth step S160 are continuously performed in the same processing chamber 401 without opening the processing chamber 401 of the vapor phase growth apparatus 400 to the atmosphere. Thereby, it can suppress that an oxide layer is formed in the surface 10a of the board | substrate 10 between etching process S140 to vapor phase growth process S160. That is, the semiconductor layer 40 can be grown directly on the surface 10a of the substrate 10 purified by the etching step S140. Thus, by not interposing the oxide layer between the substrate 10 and the semiconductor layer 40, the semiconductor layer 40 can take over without reducing the crystallinity of the substrate 10.

<Second Embodiment of the Present Invention>
In the above-described embodiment, the case where the free-standing substrate 2 is manufactured has been described. However, the etching step S140 may be applied when the semiconductor device 3 is manufactured as in the following second embodiment. Hereinafter, only elements different from the above-described embodiment will be described, and elements substantially the same as those described in the above-described embodiment will be denoted by the same reference numerals and description thereof will be omitted.

(1) Issues in the present embodiment As a group III nitride semiconductor-based semiconductor device, for example, an electron transit layer made of GaN and an electron supply layer made of AlGaN are arranged in this order on a semi-insulating GaN free-standing substrate. There is known a high electron mobility transistor (HEMT) formed by stacking layers of. When manufacturing a semiconductor device as a HEMT, when a GaN free-standing substrate is stored in a substrate container made of an organic resin material for a long period of time, the substrate container is used as a cause of the GaN free-standing substrate as in the above-described embodiment. Adhering impurities may adhere to the surface. Specifically, for example, Si may pile up as an adhering impurity at the interface between the GaN free-standing substrate and the electron transit layer. When Si piles up at the interface between the GaN free-standing substrate and the electron transit layer, a conductive GaN: Si layer is formed by the Si at the interface, and a leak path or parasitic capacitance may be generated. As a result, for example, the withstand voltage of the HEMT may decrease, or the high-frequency characteristics of the HEMT may deteriorate.

Therefore, a technique of doping Fe or the like in the vicinity of the interface between the GaN free-standing substrate and the electron transit layer in the electron transit layer is known. When doping Fe, for example, biscyclopentadienyl iron (Cp ₂ Fe) gas is used. Thus, by doping Fe in the vicinity of the interface between the GaN free-standing substrate and the electron transit layer in the electron transit layer, Si piled up on the interface is compensated, and the region in the vicinity of the interface has a high resistance. It can be made.

However, the Cp ₂ Fe gas used when doping Fe can cause a so-called memory effect. That is, even shed Cp 2 _Fe gas in growing a region near the interface between the GaN freestanding substrate and the electron transit layer of the electron transit layer, then, Ya the pipe supplying Cp 2 _Fe gas Cp ₂ Fe gas remains in the processing chamber. For this reason, Fe is unintentionally doped to the area | region of the interface vicinity between an electron transit layer and an electron supply layer among electron transit layers. As a result, the two-dimensional electron gas (2DEG) generated in the region near the interface between the electron transit layer and the electron supply layer in the electron transit layer is reduced.

  Further, when Fe is doped in the vicinity of the interface between the GaN free-standing substrate and the electron transit layer in the electron transit layer, the interface between the electron transit layer and the electron supply layer in the electron transit layer from the Fe-doped region. Fe diffuses in a nearby region. From this point of view, 2DEG decreases.

  Also, when the concentration of Si piled up near the interface between the GaN free-standing substrate and the electron traveling layer in the electron transit layer is high, the piled-up Si is sufficient even if Fe is doped near the interface. May not be able to compensate.

  The present embodiment described below is based on the above problem.

(2) Semiconductor Stack Manufacturing Method or Semiconductor Device Manufacturing Method With reference to FIGS. 7 and 8, the semiconductor stack manufacturing method or the semiconductor device manufacturing method according to the present embodiment will be described. FIG. 7 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a semiconductor device according to this embodiment. FIG. 8A is a schematic cross-sectional view showing the semiconductor stacked body according to the present embodiment, and FIG. 8B is a schematic cross-sectional view showing the semiconductor device according to the present embodiment.

(S120: Substrate preparation process)
First, the substrate 10 is prepared. At this time, the substrate 10 is, for example, a semi-insulating GaN free-standing substrate. The concentration of Fe in the substrate 10, for example, a 5.0 × ¹⁰ 17 at · ^{cm -3} or more 5.0 × ¹⁰ 18 at · ^{cm -3} or less.

  At this time, the substrate 10 is housed in the substrate housing body 200 made of an organic resin material. When the substrate 10 is accommodated in the substrate container 200, for example, siloxane may adhere as the attached impurity 20.

(S140: Etching process)
In the present embodiment, for example, a metal organic vapor phase epitaxy (MOVPE) apparatus is used as the vapor phase growth apparatus. After the substrate preparation step S120, the substrate 10 is taken out from the substrate container 200, and the substrate 10 is put into the processing chamber of the MOVPE apparatus. When the substrate 10 is put into the processing chamber of the MOVPE apparatus, the entire surface 10a of the substrate 10 is etched in a gas phase in the processing chamber over a predetermined thickness. At this time, the adhering impurities 20 attached to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with GaN constituting the matrix of the substrate 10. The etching conditions at this time are the same as the etching conditions of the first embodiment described above.

  Thus, by removing the adhering impurities 20 together with the matrix of the substrate 10, it is possible to suppress Si as the adhering impurities 20 from being piled up on the surface of the substrate 10 (interface between the substrate 10 and the semiconductor layer 40). be able to.

(S160: Vapor growth process)
Next, the semiconductor layer 40 is epitaxially grown on the surface 10a of the substrate 10 using a MOVPE apparatus. At this time, the etching step S140 and the vapor phase growth step S160 are continuously performed in the same processing chamber without opening the processing chamber of the MOVPE apparatus to the atmosphere.

  In the present embodiment, as the semiconductor layer 40, for example, an electron transit layer (channel layer) 42 and an electron supply layer (barrier layer) 44 are grown.

Specifically, first, by supplying trimethylgallium (TMG) gas and NH ₃ gas to the substrate 10 heated to a predetermined temperature, the electron transit layer 42 made of GaN is formed on the substrate 10. Homoepitaxial growth. At this time, the thickness of the electron transit layer 42 is, for example, not less than 500 nm and not more than 2500 nm.

Note that when the electron transit layer 42 is grown, the Cp ₂ Fe gas is not doped.

Next, an electron supply layer 44 made of AlGaN is epitaxially grown on the electron transit layer 42 by supplying TMA gas, TMG gas, and NH ₃ gas to the substrate 10 heated to a predetermined temperature. At this time, the thickness of the electron supply layer 44 is, for example, not less than 5 nm and not more than 50 nm.

  Thereby, as shown to Fig.8 (a), the semiconductor laminated body 1 of this embodiment is manufactured.

(S220: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S220 for manufacturing the semiconductor device 3 using the semiconductor stacked body 1 described above is performed. Specifically, a gate electrode 61 made of nickel (Ni) / gold (Au) is formed on the electron supply layer 44. A source electrode 62 made of titanium (Ti) / Al is formed on the electron supply layer 44 at a position away from the gate electrode 61 by a predetermined distance, and at a position away from the source electrode 62 with the gate electrode 61 in between. A drain electrode 63 made of Ti / Al is formed. After forming each electrode, the semiconductor laminate 1 is annealed at a predetermined temperature for a predetermined time in an N ₂ atmosphere. Note that a protective film made of silicon nitride (SiN) may be formed so as to cover the electron supply layer 44 and each electrode after the annealing treatment.

  As described above, as shown in FIG. 8B, the semiconductor device 3 configured as the HEMT of this embodiment is manufactured.

(3) Semiconductor Stack and Semiconductor Device In this embodiment, as described above, before the semiconductor layer 40 is formed on the substrate 10 in the vapor phase growth step S160, the adhesion on the surface 10a of the substrate 10 in the etching step S140. Impurity 20 is removed. Thereby, the semiconductor laminate 1 and the semiconductor device 3 have the following characteristics.

  Since the adhered impurities 20 are removed from the surface 10a of the substrate 10, for example, Si pileup is suppressed at the interface between the substrate 10 and the semiconductor layer 40. That is, Si is not accumulated at the interface between the substrate 10 and the semiconductor layer 40 at a concentration 10 times or higher of the higher Si concentration in the substrate 10 or Si concentration in the semiconductor layer 40. In other words, the Si concentration at the interface between the substrate 10 and the semiconductor layer 40 is less than 10 times the higher of the Si concentration in the substrate 10 or the Si concentration in the semiconductor layer 40.

Further, in the semiconductor laminate 1 and the semiconductor device 3, the occurrence of a morphology abnormality portion on the surface of the semiconductor layer 40 is suppressed. Specifically, the surface density of the morphology abnormal portion in the surface of the semiconductor layer 40 is, for example, 10 cm ^-2 or more 1000 cm ^-2 or less.

In the semiconductor laminate 1 and the semiconductor device 3, formation of pits on the surface of the semiconductor layer 40 is suppressed. Specifically, the surface density of pits in the surface of the semiconductor layer 40 is, for example, 10 cm ⁻² or less, preferably 1 cm ⁻² or less.

(4) Effects Obtained by the Present Embodiment According to the present embodiment, one or more effects shown below can be obtained.

(A) In the etching step S140, the adhering impurities 20 attached to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with GaN constituting the matrix of the substrate 10. Thereby, it can suppress that Si as the adhesion impurity 20 piles up at the interface between the board | substrate 10 and the semiconductor layer 40. FIG. By suppressing Si pileup at the interface between the substrate 10 and the semiconductor layer 40, it is possible to suppress the formation of a conductive GaN: Si layer near the interface and to suppress the generation of leak paths and parasitic capacitance. can do. As a result, the breakdown voltage and high frequency characteristics of the semiconductor device 3 can be improved. Thus, according to the present embodiment, it is possible to manufacture the semiconductor device 3 with good crystal quality and good characteristics.

(B) By removing the adhering impurities 20 from the surface 10a of the substrate 10 in the etching step S140, in the vapor phase growth step S160, generation of pits and morphology abnormal portions on the surface of the semiconductor layer 40 can be suppressed. Thereby, local electric field concentration in the electron supply layer 44 can be suppressed. As a result, the breakdown voltage of the semiconductor device 3 can be improved.

(C) The etching step S140 and the vapor phase growth step S160 are continuously performed in the same processing chamber without opening the processing chamber of the MOVPE apparatus to the atmosphere.

  Here, for reference, when Si is attached to the surface of the GaN free-standing substrate, the surface of the GaN free-standing substrate is wet etched before the semiconductor layer is grown on the GaN free-standing substrate. It is conceivable to remove this. However, in this method, even if the adhering impurities can be removed from the surface of the GaN free-standing substrate by wet etching, if the GaN free-standing substrate is accommodated in the substrate container after the wet etching, it immediately adheres to the surface of the GaN free-standing substrate. Impurities may be reattached.

  On the other hand, in this embodiment, the adhesion impurity 20 is reattached to the surface 10a of the substrate 10 after the etching step S140 by continuously performing the etching step S140 and the vapor phase growth step S160 in the same processing chamber. This can be suppressed. Thereby, it is possible to reliably suppress the Si as the attached impurity 20 from being piled up at the interface between the substrate 10 and the semiconductor layer 40.

(5) Modification of this Embodiment In the above-described embodiment, the case where the semiconductor device 3 is configured as a HEMT has been described. However, the semiconductor device 3 is not limited to a HEMT, for example, as a Schottky barrier diode (SBD). It may be configured. Hereinafter, only elements different from the above-described embodiment will be described.

(5-1) Semiconductor Stack Manufacturing Method or Nitride Crystal Substrate Manufacturing Method A semiconductor stack manufacturing method or a semiconductor device manufacturing method according to this modification will be described with reference to FIGS. 7 and 9. FIG. 9A is a schematic cross-sectional view showing a semiconductor stacked body according to a modification of the present embodiment, and FIG. 9B is a schematic cross-sectional view showing a semiconductor device according to the modification of the present embodiment.

(S120: Substrate preparation process)
First, the substrate 10 is prepared. At this time, the substrate 10 is an n-type GaN free-standing substrate containing an n-type impurity such as silicon (Si). Further, the concentration of the n-type impurity in the substrate 10 is, for example, 5.0 × 10 ¹⁷ at · cm ⁻³ or more and 1.0 × 10 ¹⁹ at · cm ⁻³ or less.

  At this time, the substrate 10 is housed in the substrate housing body 200 made of an organic resin material.

(S140: Etching process)
Next, the substrate 10 is put into the processing chamber of the MOVPE apparatus from the substrate container 200, and the entire surface 10a of the substrate 10 is etched in a gas phase in the processing chamber over a predetermined thickness. At this time, the adhering impurities 20 attached to the surface 10a of the substrate 10 in the substrate preparation step S120 are removed together with GaN constituting the matrix of the substrate 10.

(S160: Vapor growth process)
Next, the semiconductor layer 40 is epitaxially grown on the surface 10a of the substrate 10 using a MOVPE apparatus. In the present embodiment, as the semiconductor layer 40, for example, a base n-type semiconductor layer 46 and a drift layer 48 are grown.

Specifically, first, a base n-type semiconductor layer 46 as an n-type GaN layer is epitaxially grown on the substrate 10. At this time, for example, by doping Si or Ge as an n-type impurity, the concentration of the n-type impurity in the base n-type semiconductor layer 46 is substantially equal to that of the substrate 10, for example, 5.0 × 10 ¹⁷ at · cm ^{−. 3 to} 1.0 × 10 ¹⁹ at · cm ⁻³ .

Next, a drift layer 48 as an n − -type GaN layer is epitaxially grown on the base n-type semiconductor layer 46. At this time, the n-type impurity concentration in the drift layer 48 is lower than the n-type impurity concentration of the substrate 10 and the underlying n-type semiconductor layer 46, for example, 1.0 × 10 ¹⁵ at · cm ⁻³ or more. 0 × 10 ¹⁶ at · cm ⁻³ or less.

  Thereby, as shown to Fig.9 (a), the semiconductor laminated body 1 of this modification is manufactured.

(S220: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S220 for manufacturing the semiconductor device 3 using the semiconductor stacked body 1 described above is performed. Specifically, the protective film 50 having a circular opening in plan view is formed on the semiconductor layer 40. At this time, the protective film 50 is, for example, a silicon oxide (SiO ₂ ) film. When the protective film 50 is formed, a p-type electrode 64 as a field plate electrode is formed so as to be in contact with the semiconductor layer 40 in the opening of the protective film 50 and to cover a wider area than the opening of the protective film 50 in plan view. At this time, the p-type electrode 64 is, for example, a palladium (Pd) / nickel (Ni) film. In addition, an n-type electrode 65 is formed on the back side of the substrate 10. At this time, the n-type electrode 65 is a titanium (Ti) / (Al) film, for example.

  As described above, as shown in FIG. 9B, the semiconductor device 3 configured as the Schottky barrier diode (SBD) of the present modification is manufactured.

(5-2) Semiconductor Stack and Semiconductor Device The semiconductor stack 1 and the semiconductor device 3 of the present embodiment also have the following characteristics, as in the above-described embodiment. In the semiconductor laminate 1 and the semiconductor device 3, the surface density of the morphology abnormal portion in the surface of the semiconductor layer 40 is, for example, 10 cm ^-2 or more 1000 cm ^-2 or less. The surface density of pits in the surface of the semiconductor layer 40 is, for example, 10 cm ⁻² or less, preferably 1 cm ⁻² or less. Note that Si is not accumulated at the interface between the substrate 10 and the semiconductor layer 40 at a concentration that is 10 times or more of the higher of the Si concentration in the substrate 10 or the Si concentration in the semiconductor layer 40.

(5-3) Effects Obtained by the Present Embodiment (a) By suppressing the growth of pits and morphology abnormal portions in the semiconductor layer 40, desired rectification can be obtained in the semiconductor device 3 configured as SBD. .

  Here, if there are pits and morphology abnormal portions on the surface of the semiconductor layer, even if the carrier concentration around the pits and morphology abnormal portions is low, the O concentration in the portion of the semiconductor layer where the pits and morphology abnormal portions have grown is as described above. The carrier concentration increases. Since the Schottky barrier width of the semiconductor layer is inversely proportional to the square root of the carrier concentration, a tunnel current easily flows when a reverse bias is applied in a portion of the semiconductor layer where the carrier concentration is high. That is, this corresponds to the formation of a parallel circuit having an SBD and a resistor. For this reason, there is a possibility that desired rectification cannot be obtained in a semiconductor device configured as an SBD.

  On the other hand, by suppressing the growth of pits and morphology abnormal portions in the semiconductor layer 40, formation of a portion having a locally high O concentration and a high carrier concentration can be suppressed. Thereby, it is possible to suppress a tunnel current from flowing locally when a reverse bias is applied. As a result, desired rectification can be obtained in the semiconductor device 3 configured as the SBD.

(B) By suppressing the generation of pits and morphology abnormalities on the surface of the semiconductor layer 40, local electric field concentration in the drift layer 48 can be suppressed. As a result, the breakdown voltage of the semiconductor device 3 can be improved.

<Other embodiments>
The embodiment of the present invention has been specifically described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention.

In the above-described embodiment, the case where each of the substrate 10 and the nitride semiconductor free-standing substrate 2 is a GaN free-standing substrate has been described. However, each of the substrate 10 and the nitride semiconductor free-standing substrate 2 is not limited to a GaN free-standing substrate, for example, Group III nitride semiconductors such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), that is, Al _x In _y Ga _{1 -x-y N (0 ≦ x} ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) may be a self-supporting substrate made of a III group nitride semiconductor represented by the composition formula.

Further, the substrate 10 may be a substrate whose surface layer is made of a group III nitride semiconductor. For example, a support substrate made of sapphire or the like, and Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, A group III nitride semiconductor template having a semiconductor layer made of a group III nitride semiconductor represented by a composition formula of 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) may be used.

  Although the case where the substrate container 200 is configured as a wafer tray has been described in the above-described embodiment, the substrate container 200 may be configured as a wafer box that stores a plurality of substrates 10.

  In the first embodiment described above, the doping in the vapor phase growth step S160 has not been described. However, in order to provide the semiconductor layer 40 with predetermined conductivity or insulation, the semiconductor layer 40 is subjected to the vapor phase growth step S160. Impurities may be doped.

  In the above-described embodiment, the case where the etching process S140 and the vapor deposition process S160 are continuously performed in the processing chamber 401 of the same vapor deposition apparatus 400 has been described. However, the etching process S140, the vapor deposition process S160, May be performed by different devices. However, it is preferable that the etching step S140 and the vapor phase growth step S160 are continuously performed in the processing chamber 401 of the same vapor phase growth apparatus 400 in terms of suppressing formation of an oxide layer on the exposed portion of the substrate 10.

  In the modification of the second embodiment described above, the case where the semiconductor layer 40 is grown by the MOVPE method has been described. However, the semiconductor layer 40 may be grown by the HVPE method. Since the HVPE method has a high growth rate, it is possible to improve throughput when manufacturing a semiconductor device.

  In the modification of the second embodiment described above, in the vapor phase growth step S160 after the etching step S140, first, the base n-type semiconductor layer 46 as an n-type GaN layer is grown on the substrate 10, and then, Although the case where the drift layer 48 as the n − -type GaN layer is grown has been described, the adhering impurity 20 (for example, piled-up Si) on the surface 10a of the substrate 10 is removed by the etching step S140, and thus the etching step S140. In the subsequent vapor phase growth step S160, the drift layer 48 as the n − -type GaN layer may be directly grown on the substrate 10 without the base n-type semiconductor layer 46 as the n-type GaN layer. Thereby, the drift layer 48 with good crystal quality can be directly grown on the substrate 10.

  In the above-described second embodiment and the modification thereof, the case where HEMT or SBD is manufactured as the semiconductor device 3 has been described. As the semiconductor device 3, for example, a junction barrier Schottky diode (JBS), a pn junction diode, and a light emitting diode are used. A laser diode, a gate injection transistor (GIT), a bipolar transistor, or the like may be manufactured.

[Other Modifications of Second Embodiment]
Here, another modification of the second embodiment will be described. In this modification, for example, a case where a pn junction diode is manufactured as a semiconductor device will be described. This will be described with reference to the flowchart of FIG.

(S120: Substrate preparation process)
First, a base substrate made of an n-type GaN free-standing substrate is prepared.

  Here, for example, in order to obtain a high breakdown voltage pn junction diode as a semiconductor device, it is necessary to grow a drift layer as an n− type GaN layer having a thickness of several tens of μm on a base substrate. Since the growth rate by the MOVPE method is about several μm / h, it takes a very long time to grow the drift layer by the MOVPE method, resulting in a low throughput. Therefore, in this modification, a drift layer as an n − -type GaN layer is grown on the base substrate by the HVPE method having a high growth rate.

  As described above, a substrate whose surface layer is a drift layer as an n-type GaN layer is manufactured. When the substrate is manufactured, the substrate is accommodated in a substrate container made of an organic resin material.

(S140: Etching process)
Next, the substrate is introduced from the substrate container into the processing chamber of the MOVPE apparatus, and the entire surface of the drift layer constituting the surface layer of the substrate is etched in a gas phase in the processing chamber over a predetermined thickness. At this time, the adhering impurities adhering to the surface of the substrate (namely, the surface of the drift layer) in the substrate preparation step S120 are removed together with GaN constituting the matrix of the surface layer (namely, the drift layer) of the substrate.

(S160: Vapor growth process)
Next, using a MOVPE apparatus, a first p-type semiconductor layer as a p-type GaN layer is epitaxially grown on the drift layer. An example of the p-type impurity in the first p-type semiconductor layer is magnesium (Mg). The p-type impurity concentration in the first p-type semiconductor layer is, for example, not less than 1.0 × 10 ¹⁷ at · cm ^{−3 and not} more than 2.0 × 10 ¹⁹ at · cm ⁻³ .

Next, a second p-type semiconductor layer as a p-type GaN layer is epitaxially grown on the first p-type semiconductor layer. The p-type impurity concentration in the second p-type semiconductor layer is higher than the p-type impurity concentration in the first p-type semiconductor layer, for example, 5.0 × 10 ¹⁹ at · cm ⁻³ or more and 2.0 × 10 ²⁰ at ··. cm ⁻³ or less.

  Thereby, the semiconductor laminated body of this modification is manufactured.

(S220: Semiconductor device manufacturing process)
Next, a semiconductor device manufacturing step S220 for manufacturing a semiconductor device using the above-described semiconductor stack is performed. Specifically, a p-type electrode (for example, Pd / Ni) is formed on the second p-type semiconductor layer, and an n-type electrode (for example, Ti / Al) is formed on the back side of the base substrate.

  As described above, the semiconductor device of this modification is manufactured.

  According to this modification, the throughput when manufacturing a pn junction diode as a semiconductor device can be improved by growing a drift layer as an n-type GaN layer on the base substrate by the HVPE method having a high growth rate. it can.

  Further, according to the present modification, in the etching step S140, the adhering impurities attached to the surface of the drift layer in the substrate preparation step S120 are removed together with GaN constituting the drift layer matrix. Thereby, it can suppress that Si as an adhesion impurity piles up at the interface between a drift layer and a 1st p-type semiconductor layer. By suppressing the pile-up of Si at the interface between the drift layer and the first p-type semiconductor layer, the p-type impurities in the first p-type semiconductor layer can be prevented from being compensated by the piled-up Si. it can.

  In this modification, the case where the first p-type semiconductor layer as the p-type GaN layer is directly epitaxially grown on the drift layer in the vapor phase growth step S160 after the etching step S140 has been described. In the phase growth step S160, a thin n-type GaN layer may be grown on the drift layer, and then a first p-type semiconductor layer may be grown on the n-type GaN layer.

  Hereinafter, various experimental results supporting the effects of the present invention will be described.

(1) Confirmation of adhered impurities (1-1) Preparation of substrate First, a GaN free-standing substrate having a diameter of 2 inches and a thickness of 400 μm was prepared as a substrate. Next, the substrate was stored in a wafer tray as a substrate container and stored for a predetermined period.

(1-2) Evaluation The surface of the substrate accommodated in the wafer tray for 240 days was observed with a scanning electron microscope (SEM), and the surface of the substrate was observed with energy dispersive X-ray spectroscopy (EDX). A compositional analysis was performed.

  Moreover, the composition analysis of each surface of the board | substrate accommodated in the wafer tray for 0 to 240 days was performed by total reflection X-ray fluorescence analysis (TXRF).

(1-3) Results FIG. 10A is an SEM image showing an example of the adhering impurities, and FIG. 10B is a result of the EDX analysis of the adhering impurities in FIG.
As shown in FIG. 10A, adhering impurities adhered to the surface of the substrate accommodated in the wafer tray. As a result of composition analysis by EDX for the adhering impurities, it was confirmed that the adhering impurities contained Si, C and O as shown in FIG. From this result, it is presumed that the adhering impurities contain siloxane derived from the release agent used in manufacturing the wafer tray.

FIG. 11 is a diagram showing the Si concentration on the substrate surface measured by total reflection X-ray fluorescence analysis with respect to the number of storage days in which the substrate is stored in the substrate container.
As shown in FIG. 11, it was confirmed that the Si concentration on the substrate surface monotonously increased with respect to the storage days in the wafer tray. That is, it was confirmed that Si as an adhesion impurity may adhere more as the storage days are longer.

(2) Confirmation of effect of etching process (2-1) Preparation of substrate First, a plurality of GaN free-standing substrates having a diameter of 2 inches and a thickness of 400 μm were prepared as substrates. Next, each of the plurality of substrates was stored in a wafer tray as a substrate container and stored for 240 days.

(2-2) Manufacture of a semiconductor laminate The semiconductor laminate of the comparative example and the semiconductor laminate of the example were manufactured under the following conditions.

(Comparative example)
Etching process: Not implemented Vapor phase growth process:
Method: HVPE method Semiconductor layer material: GaN
Growth temperature: 1050 ° C
Processing chamber pressure: constant NH ₃ gas partial pressure / GaCl gas partial pressure: 3
N ₂ gas flow rate / H ₂ gas flow rate: 5
Semiconductor layer thickness: 200 μm

(Example)
Etching process: Implementation Equipment: HVPE equipment same as vapor phase growth process Etching temperature: 650 ° C
Processing chamber pressure: constant Gas: N ₂ gas, HCl gas, H ₂ gas HCl gas partial pressure / N ₂ gas partial pressure: 3%
H ₂ gas partial pressure / N ₂ gas partial pressure: 5%
Etching time: 3h
Vapor growth process:
Same as comparative example

(2-3) Evaluation Regarding the semiconductor laminates of the comparative example and the example, the presence or absence of pits and morphology abnormal portions on the surface of the semiconductor layer and the presence or absence of non-growth regions in the semiconductor layer were observed.

(2-4) Result A result is demonstrated using FIG. 12 and FIG. FIG. 12A is a photograph showing the appearance of the semiconductor laminate of the example, and FIG. 12B is a photograph showing the appearance of the semiconductor laminate of the comparative example. FIGS. 13A to 13C are diagrams showing pits and morphology abnormal portions on the surface of the semiconductor laminate of the comparative example.

  In the semiconductor laminate of the comparative example, as shown in FIG. 12B, a non-growth region (arrow) was generated in the semiconductor layer. In the semiconductor laminate of the comparative example, as shown in FIGS. 13A to 13C, pits and morphology abnormal portions were generated on the surface of the semiconductor layer. In the comparative example, because impurities adhered to the surface of the substrate due to the wafer tray, pits and morphology abnormalities are formed on the surface of the semiconductor layer, or non-growth regions are formed in the vapor phase growth process. It is thought that it has been.

  On the other hand, in the semiconductor stacked body of the example, as shown in FIG. 12A, no non-growth region was generated in the semiconductor layer. Moreover, the surface of the semiconductor layer was smooth.

  In the embodiment, it is confirmed that the formation of non-growth regions of the semiconductor layer can be suppressed in the vapor phase growth process by removing the adhering impurities adhering to the surface of the substrate in the etching process together with GaN constituting the matrix of the substrate. did. Moreover, it was confirmed that the semiconductor layer can be epitaxially grown smoothly in the vapor phase growth process by etching the surface of the substrate under mild conditions in the etching process. As a result, it was confirmed that a semiconductor laminate having good crystal quality can be produced.

<Preferred embodiment of the present invention>
Hereinafter, preferred embodiments of the present invention will be additionally described.

(Appendix 1)
A step of preparing a substrate housed in a substrate container made of an organic resin material and having at least a surface layer made of a group III nitride semiconductor;
Loading the substrate from the substrate container into a predetermined processing chamber, and etching the entire surface of at least the surface layer of the substrate over a predetermined thickness in a gas phase in the processing chamber;
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by vapor phase growth;
Have
In the etching step,
A method of manufacturing a semiconductor laminate, wherein adhesion impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate are removed together with the group III nitride semiconductor constituting at least the surface layer of the substrate. .

(Appendix 2)
In the etching step,
The manufacturing method of the semiconductor laminated body of Additional remark 1 which etches the said surface of the said surface layer on the conditions from which the area | region except a crystal defect part becomes smooth among the said surfaces of the said surface layer.

(Appendix 3)
In the etching step,
The method for manufacturing a semiconductor stacked body according to appendix 1 or 2, wherein the etching is performed in an atmosphere containing hydrogen chloride gas and hydrogen gas.

(Appendix 4)
In the etching step,
Performing the etching under an atmosphere containing the hydrogen chloride gas, the hydrogen gas and an inert gas,
The method for manufacturing a semiconductor stacked structure according to appendix 3, wherein the partial pressure of the inert gas is higher than the partial pressures of the hydrogen chloride gas and the hydrogen gas.

(Appendix 5)
In the etching step,
The method for manufacturing a semiconductor stacked structure according to appendix 4, wherein a ratio of a partial pressure of each of the hydrogen chloride gas and the hydrogen gas to a partial pressure of the inert gas is 1% or more and 10% or less.

(Appendix 6)
In the etching step,
The method for manufacturing a semiconductor stacked body according to any one of appendices 1 to 5, wherein the etching is performed in an atmosphere containing no ammonia gas.

(Appendix 7)
The method for manufacturing a semiconductor stacked body according to any one of appendices 1 to 6, wherein the temperature of the substrate in the etching step is lower than the temperature of the substrate in the step of epitaxially growing the semiconductor layer.

(Appendix 8)
The method for manufacturing a semiconductor stacked structure according to appendix 7, wherein the temperature of the substrate is monotonously increased from the etching step to the step of epitaxially growing the semiconductor layer.

(Appendix 9)
The method for manufacturing a semiconductor laminate according to any one of appendices 1 to 8, wherein the etching step and the step of epitaxially growing the semiconductor layer are performed continuously in the same processing chamber.

(Appendix 10)
In the etching step,
10. The method for manufacturing a semiconductor stacked body according to any one of appendices 1 to 9, wherein the etching is performed for at least one hour or more while maintaining the temperature of the substrate at a predetermined temperature.

(Appendix 11)
In the etching step,
11. The method for manufacturing a semiconductor stacked body according to any one of appendices 1 to 10, wherein the entire surface of the surface layer of the substrate is etched at least 10 nm in the depth direction.

(Appendix 12)
In the etching step,
Etch pits corresponding to dislocations in the surface layer appear on the surface of the surface layer of the substrate,
In the step of epitaxially growing the semiconductor layer,
12. The method for manufacturing a semiconductor laminate according to any one of appendices 1 to 11, wherein the etch pits appearing on the surface of the surface layer are embedded with the semiconductor layer.

(Appendix 13)
In the step of preparing the substrate,
The method for producing a semiconductor laminate according to any one of appendices 1 to 12, wherein the substrate is accommodated in the substrate housing body for at least 12 hours.

(Appendix 14)
In the step of preparing the substrate,
14. The method for manufacturing a semiconductor laminate according to any one of appendices 1 to 13, wherein the substrate is housed in the substrate housing body made of polypropylene.

(Appendix 15)
The method for manufacturing a semiconductor stacked body according to any one of appendices 1 to 14, wherein the adhesion impurity includes at least siloxane.

(Appendix 16)
The method for manufacturing a semiconductor stacked body according to any one of appendices 1 to 15, wherein the group III nitride semiconductor constituting at least the surface layer of the substrate is gallium nitride.

(Appendix 17)
The method for manufacturing a semiconductor stacked structure according to appendix 16, wherein the surface of the surface layer of the substrate is a + C plane or a plane having an off angle of 2 ° or less with respect to the + C plane.

(Appendix 18)
A step of preparing a substrate housed in a substrate container made of an organic resin material and having at least a surface layer made of a group III nitride semiconductor;
Loading the substrate from the substrate container into a predetermined processing chamber, and etching the entire surface of at least the surface layer of the substrate over a predetermined thickness in a gas phase in the processing chamber;
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by vapor phase growth;
Have
In the etching step,
A method for manufacturing a semiconductor device, comprising: removing impurities adhered to the surface of the substrate due to the substrate container in the step of preparing the substrate together with the group III nitride semiconductor constituting at least the surface layer of the substrate.

(Appendix 19)
A step of preparing a substrate housed in a substrate container made of an organic resin material and having at least a surface layer made of a group III nitride semiconductor;
Loading the substrate from the substrate container into a predetermined processing chamber, and etching the entire surface of at least the surface layer of the substrate over a predetermined thickness in a gas phase in the processing chamber;
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by vapor phase growth;
Slicing the semiconductor layer to produce a nitride semiconductor free-standing substrate;
Have
In the etching step,
A nitride semiconductor free-standing substrate that removes adhering impurities attached to the surface of the substrate due to the substrate container in the step of preparing the substrate together with the group III nitride semiconductor constituting at least the surface layer of the substrate. Production method.

(Appendix 20)
A substrate having at least a surface layer made of a group III nitride semiconductor;
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor;
Have
A semiconductor laminate in which silicon is not integrated at the interface between the substrate and the semiconductor layer at a concentration of 10 times or more of the silicon concentration in the substrate or the silicon concentration in the semiconductor layer, whichever is higher.

(Appendix 21)
A substrate having at least a surface layer made of a group III nitride semiconductor;
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor;
Have
A semiconductor device in which silicon is not integrated at the interface between the substrate and the semiconductor layer at a concentration of 10 times or more of the silicon concentration in the substrate or the silicon concentration in the semiconductor layer, whichever is higher.

DESCRIPTION OF SYMBOLS 1 Semiconductor laminated body 2 Nitride semiconductor free-standing substrate 10 Substrate (substrate)
20 Adhering impurities 40 Semiconductor layer

Claims (17)

A step of preparing a substrate housed in a substrate container made of an organic resin material and having at least a surface layer made of a group III nitride semiconductor;
Loading the substrate from the substrate container into a predetermined processing chamber, and etching the entire surface of at least the surface layer of the substrate over a predetermined thickness in a gas phase in the processing chamber;
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by vapor phase growth;
Have
In the etching step,
A method of manufacturing a semiconductor laminate, wherein adhesion impurities adhering to the surface of the substrate due to the substrate container in the step of preparing the substrate are removed together with the group III nitride semiconductor constituting at least the surface layer of the substrate. . In the etching step,
The manufacturing method of the semiconductor laminated body of Claim 1 which etches the said surface of the said surface layer on the conditions from which the area | region except a crystal defect part becomes smooth among the said surfaces of the said surface layer. In the etching step,
The manufacturing method of the semiconductor laminated body of Claim 1 or 2 which performs the said etching in the atmosphere containing hydrogen chloride gas and hydrogen gas. The manufacturing method of the semiconductor laminated body of any one of Claims 1-3 which makes the temperature of the said board | substrate in the said process to etch lower than the temperature of the said board | substrate in the process of epitaxially growing the said semiconductor layer. The manufacturing method of the semiconductor laminated body of Claim 4 which raises the temperature of the said substrate monotonically from the process of etching to the process of epitaxially growing the semiconductor layer. 6. The method for manufacturing a semiconductor laminate according to claim 1, wherein the step of etching and the step of epitaxially growing the semiconductor layer are performed continuously in the same processing chamber. In the etching step,
The manufacturing method of the semiconductor laminated body of any one of Claims 1-6 which perform the said etching for at least 1 hour or more in the state which maintained the temperature of the said board | substrate at predetermined temperature. In the etching step,
The manufacturing method of the semiconductor laminated body of any one of Claims 1-7 which etches 10 nm or more of the whole surface of the said surface layer of the said board | substrate at least in the depth direction. In the etching step,
Etch pits corresponding to dislocations in the surface layer appear on the surface of the surface layer of the substrate,
In the step of epitaxially growing the semiconductor layer,
The method for manufacturing a semiconductor laminate according to claim 1, wherein the etch pits appearing on the surface of the surface layer are filled with the semiconductor layer. In the step of preparing the substrate,
The method for manufacturing a semiconductor laminate according to claim 1, wherein the substrate is accommodated in the substrate housing body for at least 12 hours. In the step of preparing the substrate,
The manufacturing method of the semiconductor laminated body of any one of Claims 1-10 which accommodates the said board | substrate in the said board | substrate accommodation body which consists of a polypropylene. The method for manufacturing a semiconductor stacked body according to claim 1, wherein the adhesion impurity includes at least siloxane. The method for producing a semiconductor laminate according to any one of claims 1 to 12, wherein the group III nitride semiconductor constituting at least the surface layer of the substrate is gallium nitride. The method for producing a semiconductor stacked body according to claim 13, wherein the surface of the surface layer of the substrate is a + C plane or a plane having an off angle of 2 ° or less with respect to the + C plane. A step of preparing a substrate housed in a substrate container made of an organic resin material and having at least a surface layer made of a group III nitride semiconductor;
Loading the substrate from the substrate container into a predetermined processing chamber, and etching the entire surface of at least the surface layer of the substrate over a predetermined thickness in a gas phase in the processing chamber;
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the substrate by vapor phase growth;
Slicing the semiconductor layer to produce a nitride semiconductor free-standing substrate;
Have
In the etching step,
A nitride semiconductor free-standing substrate that removes adhering impurities attached to the surface of the substrate due to the substrate container in the step of preparing the substrate together with the group III nitride semiconductor constituting at least the surface layer of the substrate. Production method. A substrate having at least a surface layer made of a group III nitride semiconductor;
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor;
Have
A semiconductor laminate in which silicon is not integrated at the interface between the substrate and the semiconductor layer at a concentration of 10 times or more of the silicon concentration in the substrate or the silicon concentration in the semiconductor layer, whichever is higher. A substrate having at least a surface layer made of a group III nitride semiconductor;
A semiconductor layer provided on the substrate and made of a group III nitride semiconductor;
Have
A semiconductor device in which silicon is not integrated at the interface between the substrate and the semiconductor layer at a concentration of 10 times or more of the silicon concentration in the substrate or the silicon concentration in the semiconductor layer, whichever is higher.