JP2019021768A - Electronic device - Google Patents

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JP2019021768A
JP2019021768A JP2017139062A JP2017139062A JP2019021768A JP 2019021768 A JP2019021768 A JP 2019021768A JP 2017139062 A JP2017139062 A JP 2017139062A JP 2017139062 A JP2017139062 A JP 2017139062A JP 2019021768 A JP2019021768 A JP 2019021768A
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Prior art keywords
circuit board
printed circuit
filler
solder
layer
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Japanese (ja)
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松本 栄一
Eiichi Matsumoto
栄一 松本
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Denso Corp
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Denso Corp
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Priority to JP2017139062A priority Critical patent/JP2019021768A/en
Priority to DE102018208724.5A priority patent/DE102018208724A1/en
Publication of JP2019021768A publication Critical patent/JP2019021768A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K5/00Casings, cabinets or drawers for electric apparatus
    • H05K5/0026Casings, cabinets or drawers for electric apparatus provided with connectors and printed circuit boards [PCB], e.g. automotive electronic control units
    • H05K5/0047Casings, cabinets or drawers for electric apparatus provided with connectors and printed circuit boards [PCB], e.g. automotive electronic control units having a two-part housing enclosing a PCB
    • H05K5/0056Casings, cabinets or drawers for electric apparatus provided with connectors and printed circuit boards [PCB], e.g. automotive electronic control units having a two-part housing enclosing a PCB characterized by features for protecting electronic components against vibration and moisture, e.g. potting, holders for relatively large capacitors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06Thermal details
    • H05K2201/068Thermal details wherein the coefficient of thermal expansion is important
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1305Moulding and encapsulation
    • H05K2203/1327Moulding over PCB locally or completely
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/284Applying non-metallic protective coatings for encapsulating mounted components

Abstract

To provide an electronic device in which deterioration of solder life due to stress can be restrained, even when a filler added to resin is settled upon resin curing.SOLUTION: A print circuit board 3 is formed by laminating a core layer 3a on an upper surface and a surface layer 3b on a lower surface. Electronic components 4 are mounted on both surfaces of the print circuit board 3 by a solder 8. The print circuit board 3 is housed in an enclosure, and is filled with liquid sealant added with a filler so as to form resin layers 5, 6. On the lower surface of the print circuit board 3, a low distribution layer 6a is formed in contact with the electronic component 4 by settlement of the filler. The low distribution layer 6a has a large linear coefficient of expansion compared with the resin layer 6 containing the filler, and the stress of thermal strain due to temperature change is applied to the solder 8. Since the degree of elasticity (Young's modulus) is set low, the surface layer 3b can absorb stress, and thereby stress to the solder 8 is reduced and deterioration of solder life can be suppressed.SELECTED DRAWING: Figure 1

Description

本発明は、電子装置に関する。   The present invention relates to an electronic device.

電子装置として、プリント基板などに電子部品を実装してケース内に配置した状態で樹脂封止をする構成のものがある。樹脂封止をするのは、電子部品を実装したプリント基板を樹脂で封止することで、防水、防塵、耐振動性を向上させるためである。この場合、一般に封止樹脂では、密着させるプリント基板・はんだ・ケースとの熱膨張による歪みを小さくするため、樹脂に無機フィラを添加している。   As an electronic device, there is a configuration in which an electronic component is mounted on a printed board or the like and resin-sealed in a state where the electronic component is disposed in a case. The reason for resin sealing is to improve waterproofness, dustproofing, and vibration resistance by sealing a printed circuit board on which electronic components are mounted with resin. In this case, generally, in the sealing resin, an inorganic filler is added to the resin in order to reduce distortion due to thermal expansion with the printed circuit board, solder, and case to be adhered.

しかしながら、樹脂層として液状封止材を用いる場合に、ケース内への樹脂注入から硬化までの間に、そのフィラが沈降するため、樹脂上面にはフィラを含まない層が形成されることがある。プリント基板に電子部品を両面実装で配置する電子装置を樹脂封止する場合には、プリント基板の裏面側すなわち下面側では、樹脂とプリント基板の界面にフィラを含まない層が形成される。このため、フィラを含まない樹脂層の熱膨張の歪みが大きく、電子部品を実装する部分に設けているはんだは、寿命が低下するという課題がある。   However, when a liquid sealing material is used as the resin layer, the filler settles during the period from the injection of the resin into the case to the curing, so that a layer that does not contain the filler may be formed on the upper surface of the resin. . When an electronic device in which electronic components are arranged on a printed board by double-side mounting is resin-sealed, a layer that does not include filler is formed at the interface between the resin and the printed board on the back side, that is, the lower side of the printed board. For this reason, the distortion of the thermal expansion of the resin layer which does not contain a filler is large, and there is a problem that the life of the solder provided on the portion where the electronic component is mounted is reduced.

これに対して材料組成を変更することにより、樹脂中のフィラの沈降を抑制することができるようにした技術がある。しかし、実際の工程では、100℃で樹脂硬化させる工程があるため、はんだ付け部の高さまでフィラを残すようにフィラ沈降を抑制するのは現実的に不可能である。また、工程で高粘度化することでフィラ沈降はある程度抑制することはできるが、樹脂粘度が高くなると注型性が悪化する課題が発生する。   On the other hand, there is a technique in which the sedimentation of filler in the resin can be suppressed by changing the material composition. However, in the actual process, since there is a process of curing the resin at 100 ° C., it is practically impossible to suppress the filler sedimentation so as to leave the filler up to the height of the soldering portion. In addition, the filler sedimentation can be suppressed to some extent by increasing the viscosity in the process, but if the resin viscosity increases, a problem that the castability deteriorates occurs.

特開2008−181989号公報Japanese Patent Laid-Open No. 2008-181989 特開2009−203431号公報JP 2009-203431 A

本発明は、上記事情を考慮してなされたもので、その目的は、樹脂に添加するフィラが樹脂硬化の際に沈降する場合でも、応力の影響によるはんだ寿命の低下を抑制できるようにした電子装置を提供することにある。   The present invention has been made in consideration of the above circumstances, and the purpose of the present invention is to make it possible to suppress a decrease in solder life due to the influence of stress even when the filler added to the resin settles during resin curing. To provide an apparatus.

請求項1に記載の電子装置は、電子部品がはんだを用いて実装されたプリント基板と、前記プリント基板が格納される筐体と、前記筐体内に前記プリント基板の両面を覆うように充填されフィラを含む樹脂層とを備え、前記プリント基板は、板厚方向に弾性率が異なる2以上の基材を積層して構成され、前記樹脂層のフィラの粗密分布に対応して前記基材が配置される。   The electronic device according to claim 1 is filled with a printed circuit board on which electronic components are mounted using solder, a housing in which the printed circuit board is stored, and a cover that covers both surfaces of the printed circuit board. And the printed circuit board is configured by laminating two or more base materials having different elastic moduli in the thickness direction, and the base material corresponds to the density distribution of the filler of the resin layer. Be placed.

上記構成を採用することにより、筐体に樹脂層で充填された状態で格納されたプリント基板は、板厚方向に弾性率が異なる2以上の基材を積層して構成されると共に、樹脂層のフィラの粗密分布に対応して基材が配置されるので、電子部品が実装されている部分のはんだが熱歪による応力の影響で寿命低下するのを抑制することができる。   By adopting the above configuration, the printed circuit board stored in a state where the casing is filled with the resin layer is configured by laminating two or more base materials having different elastic moduli in the thickness direction, and the resin layer Since the base material is disposed corresponding to the density distribution of the filler, it is possible to suppress the life of the solder in the portion where the electronic component is mounted from being affected by the stress due to thermal strain.

これは、フィラを含む樹脂層は、添加後の硬化過程でフィラの粗密分布が発生することがあり、フィラの粗密分布の状態に応じて線膨張係数が異なることに対応してプリント基板に弾性率の異なる2以上の基材を積層する構成とすることで電子部品の実装部分のはんだにおよぼす応力を分散させることができるからである。   This is because the filler-containing resin layer may have a filler density distribution in the curing process after addition, and the linear expansion coefficient varies depending on the filler density distribution state. This is because the stress exerted on the solder of the mounting part of the electronic component can be dispersed by adopting a configuration in which two or more base materials having different rates are laminated.

第1実施形態を示すプリント基板の縦断側面図1 is a longitudinal side view of a printed circuit board showing a first embodiment. 全体の縦断側面図Overall profile side view 本実施形態の応力関係を説明する作用説明図(その1)Action explanatory drawing explaining the stress relation of this embodiment (the 1) 本実施形態の応力関係を説明する作用説明図(その2)Action explanatory drawing explaining the stress relation of this embodiment (the 2) 比較例の応力関係を説明する作用説明図(その1)Action explanatory drawing explaining the stress relation of a comparative example (the 1) 比較例の応力関係を説明する作用説明図(その2)Action explanatory drawing explaining the stress relation of a comparative example (part 2) 比較結果を示す作用説明図Action explanatory diagram showing comparison results 本実施形態と比較例とのはんだクラック率の相関図Correlation diagram of solder crack rate between this embodiment and comparative example 第2実施形態を示すプリント基板の縦断側面図Vertical side view of a printed circuit board showing a second embodiment

(第1実施形態)
以下、本発明の第1実施形態について、図1〜図8を参照して説明する。
(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.

全体構成を示す図2において、筐体1は、上面が開口された矩形容器状をなす樹脂製のもので、内部には2段に凹部1a、1bが形成され、凹部1aの底部に凹部1aよりも狭い範囲で凹部1bが設けられている。筐体1には、外部に突出するリード部1cが形成され、リード部1cの内部に金属製のリード2が埋め込み成型されている。リード2の一端は外部に導出され、内部で屈曲されて上方に指向する他端は凹部1aの底面から上方に突出されている。   In FIG. 2 showing the overall configuration, a housing 1 is made of a resin having a rectangular container shape with an open upper surface, and is internally formed with recesses 1a and 1b in two steps, and a recess 1a at the bottom of the recess 1a. The recess 1b is provided in a narrower range. The housing 1 is formed with a lead portion 1c that protrudes to the outside, and a metal lead 2 is embedded in the lead portion 1c. One end of the lead 2 is led out to the outside, and the other end bent upward and directed upward projects upward from the bottom surface of the recess 1a.

プリント基板3は、両面に複数の電子部品4が実装されている。電子部品4は、トランジスタ、抵抗、コイル、コンデンサなどの種々の電子部品であり、ここでは、後述するようにはんだにより面実装されている。プリント基板3は、筐体1の凹部1a内に格納され、下面は凹部1b内に面する状態とされている。   The printed circuit board 3 has a plurality of electronic components 4 mounted on both sides. The electronic component 4 is various electronic components such as a transistor, a resistor, a coil, and a capacitor. Here, the electronic component 4 is surface-mounted by solder as described later. The printed circuit board 3 is stored in the recess 1a of the housing 1, and the lower surface faces the recess 1b.

筐体1の凹部1a内には樹脂層5が充填形成され、凹部1b内には樹脂層6が充填形成されている。樹脂層5および6には内部にフィラが添加されており、樹脂硬化の過程でフィラが沈降するためフィラの粗密分布ができる。この場合、樹脂層5、6の上層にフィラの存在が粗で分布密度が低い低分布層5a、6aが形成されている。   A resin layer 5 is filled in the recess 1a of the housing 1, and a resin layer 6 is filled in the recess 1b. Fillers are added to the resin layers 5 and 6, and the filler settles during the resin curing process, so that the filler can be distributed in a dense and dense manner. In this case, low distribution layers 5a and 6a having a coarse filler and a low distribution density are formed on the upper layers of the resin layers 5 and 6, respectively.

図1はプリント基板3の詳細な断面構成を示している。図1において、プリント基板3は、複数の基材としてコア層3aと表層3bを積層した構成とされている。コア層3aは一般的なプリント基板を形成する素材であり、弾性率であるヤング率が例えば27〜30GPaである。また、表層3bは図1では下面側に位置して設けられている。表層3bは、一般的なプリント基板を形成する素材よりも弾性率が低く設定されたもので、ヤング率が例えば5〜10GPaである。   FIG. 1 shows a detailed cross-sectional configuration of the printed circuit board 3. In FIG. 1, the printed circuit board 3 has a configuration in which a core layer 3a and a surface layer 3b are stacked as a plurality of base materials. The core layer 3a is a material for forming a general printed circuit board, and the Young's modulus, which is an elastic modulus, is, for example, 27 to 30 GPa. Further, the surface layer 3b is provided on the lower surface side in FIG. The surface layer 3b is set to have a lower elastic modulus than a material forming a general printed circuit board, and has a Young's modulus of, for example, 5 to 10 GPa.

また、コア層3aおよび表層3bのXY方向すなわち面内方向の線膨張率係数αは共に例えば13である。コア層3aは、プリント基板3の主要部分を構成しており、表層3bは、コア層3aよりも薄く形成されている。   Further, the linear expansion coefficient α in the XY direction, that is, the in-plane direction, of the core layer 3a and the surface layer 3b is, for example, 13. The core layer 3a constitutes a main part of the printed circuit board 3, and the surface layer 3b is formed thinner than the core layer 3a.

プリント基板3に実装された電子部品4は、例えば直方体状をなす形状で、両端の接続端子部に電極4aが形成されている。電子部品4の2つの電極4aは、プリント基板3のコア層3a、表層3bの各表面に設けられた銅箔をパターニングしたランド7とはんだ8により電気的に接続された状態に実装されている。はんだ8は、ランド7の面と電子部品4の電極4aとの間に接触するように設けられている。はんだ8は、例えば車載用の鉛フリーはんだを用いており、線膨張係数αは例えば21である。   The electronic component 4 mounted on the printed circuit board 3 has, for example, a rectangular parallelepiped shape, and electrodes 4a are formed on the connection terminal portions at both ends. The two electrodes 4a of the electronic component 4 are mounted in a state where they are electrically connected by lands 7 and solder 8 patterned copper foil provided on the surfaces of the core layer 3a and the surface layer 3b of the printed circuit board 3. . The solder 8 is provided so as to be in contact between the surface of the land 7 and the electrode 4 a of the electronic component 4. For example, a lead-free solder for vehicle use is used as the solder 8, and the linear expansion coefficient α is, for example, 21.

樹脂層5、6は、例えばエポキシ樹脂にシリカなどのフィラを添加した液状封止材を用いている。樹脂層5、6の形成時には、筐体1の凹部1aに電子部品4を両面に実装した状態で格納載置し、リード2と電気的に接続した状態に保持する。この状態で、筐体1の凹部1a、1b内に樹脂の液状封止材を流し込んで充填する。これは所謂ポッティングといわれる樹脂層形成方法である。流し込まれた液状封止材は、時間の経過とともに硬化して樹脂層5、6として形成される。   For the resin layers 5 and 6, for example, a liquid sealing material in which a filler such as silica is added to an epoxy resin is used. When the resin layers 5 and 6 are formed, the electronic components 4 are stored and mounted in the recesses 1 a of the housing 1 on both sides, and are held in an electrically connected state with the leads 2. In this state, a resin liquid sealing material is poured into the recesses 1a and 1b of the housing 1 and filled. This is a so-called potting method for forming a resin layer. The poured liquid sealing material is cured with the passage of time and formed as resin layers 5 and 6.

このとき、樹脂層5、6には、プリント基板3で分断されているので、液状封止材の内部に添加されているフィラが凹部1a内および凹部1b内のそれぞれで沈降して上層部にフィラの分布密度が低い低分布層5a、6aが発生する。プリント基板3の上面のコア層3aに実装された電子部品4が接触する部分の樹脂層5は、フィラが十分に添加された状態の樹脂として形成されており、低分布層5aは電子部品4から離れた上面の表層部に形成されている。一方、プリント基板3の下面の表層3bに実装された電子部品4が接触する部分の樹脂層6は、フィラが低分布となる低分布層6aが電子部品4の一部を覆うように形成されている。   At this time, since the resin layers 5 and 6 are divided by the printed circuit board 3, the filler added to the inside of the liquid sealing material settles in the recess 1a and the recess 1b, respectively, and becomes an upper layer portion. Low distribution layers 5a and 6a having a low filler density are generated. A portion of the resin layer 5 in contact with the electronic component 4 mounted on the core layer 3a on the upper surface of the printed circuit board 3 is formed as a resin in which filler is sufficiently added, and the low distribution layer 5a is formed of the electronic component 4. It is formed in the surface layer part of the upper surface away from. On the other hand, a portion of the resin layer 6 in contact with the electronic component 4 mounted on the surface layer 3b on the lower surface of the printed circuit board 3 is formed such that the low distribution layer 6a having a low filler distribution covers a part of the electronic component 4. ing.

樹脂層5、6は、内部にフィラが十分に添加された状態では、線膨張係数αが例えば10〜12である。ところが、フィラの分布が粗となる低分布層5aや6aでは、線膨張係数αが例えば40〜50の範囲まで増大する。   The resin layers 5 and 6 have a linear expansion coefficient α of, for example, 10 to 12 in a state where the filler is sufficiently added inside. However, in the low distribution layers 5a and 6a where the filler distribution is coarse, the linear expansion coefficient α increases to a range of 40 to 50, for example.

この場合、温度変化による樹脂層5、6の変位に対してプリント基板3は、コア層3a、表層3bの線膨張係数αが樹脂層5、6と同程度であるので共に変位するため、実装されている電子部品4のはんだ8への熱歪による応力は少ない。   In this case, since the linear expansion coefficient α of the core layer 3a and the surface layer 3b is approximately the same as that of the resin layers 5 and 6, the printed circuit board 3 is displaced with respect to the displacement of the resin layers 5 and 6 due to temperature change. The stress caused by thermal strain on the solder 8 of the electronic component 4 is small.

これに対して、低分布層5a、6aの線膨張係数αは、プリント基板3のコア層3a、表層3bの線膨張係数αよりも大きいので、表層3b側に実装される電子部品4のはんだ8には熱歪による応力を大きく受ける状態となる。そこで、表層3bの膨張率であるヤング率が低く設定されているので、温度による変位は少ないが、変形することで応力を吸収することができる。
一般に、熱歪εの値は、線膨張係数αおよび温度変化量ΔTに対して次式(1)の関係を有する。
ε[ppm]=α[ppm/℃]×ΔT[℃] …(1)
On the other hand, since the linear expansion coefficient α of the low distribution layers 5a and 6a is larger than the linear expansion coefficient α of the core layer 3a and the surface layer 3b of the printed board 3, the solder of the electronic component 4 mounted on the surface layer 3b side. 8 is in a state of being greatly subjected to stress due to thermal strain. Therefore, since the Young's modulus, which is the expansion coefficient of the surface layer 3b, is set low, the displacement due to temperature is small, but stress can be absorbed by deformation.
In general, the value of the thermal strain ε has a relationship of the following equation (1) with respect to the linear expansion coefficient α and the temperature change amount ΔT.
ε [ppm] = α [ppm / ° C.] × ΔT [° C.] (1)

この関係を用いると、例えば、車両などの使用環境の温度変化が激しい場合を想定して、温度変動範囲を25℃から125℃の温度変化量ΔTで計算すると、熱歪εは、次式(2)のように計算することができる。
ε=((40〜50)−21)×100=1900〜2900ppm …(2)
Using this relationship, for example, assuming that the temperature change in the environment of use such as a vehicle is severe, calculating the temperature fluctuation range with a temperature change amount ΔT from 25 ° C. to 125 ° C., the thermal strain ε is expressed by the following equation ( It can be calculated as in 2).
ε = ((40-50) -21) × 100 = 1900-2900 ppm (2)

これに対して、図3に示すように、電子部品4が実装されたプリント基板3の表層3bのヤング率は前述のように低く設定されている。これにより、図4に白抜き矢印示しているように、低分布層6aからはんだ8に向かう熱歪εの応力に対応して、表層3bは図4中黒矢印で示すように大きく変形して応力成分が表層3bに分散されるようになる。この結果、はんだ8にかかる応力が小さくなる。なお、図4では樹脂層6の表示は省略している。   On the other hand, as shown in FIG. 3, the Young's modulus of the surface layer 3b of the printed circuit board 3 on which the electronic component 4 is mounted is set low as described above. As a result, as shown by the white arrow in FIG. 4, the surface layer 3b is greatly deformed as shown by the black arrow in FIG. 4 in response to the stress of the thermal strain ε from the low distribution layer 6a toward the solder 8. The stress component is dispersed in the surface layer 3b. As a result, the stress applied to the solder 8 is reduced. In FIG. 4, the display of the resin layer 6 is omitted.

従来技術に相当する比較例として、例えば、図5に示すように、表層3bが設けられず、プリント基板3がコア層3aのままであるとする。この場合には、コア層3aのヤング率が高いので、図6中白抜き矢印で示す低分布層6aからはんだ8に向かう熱歪εの応力に対応して、コア層3aは図4中黒矢印で示すように変形量が小さいため、熱歪の応力成分があまり分散されることはない。この結果、図6に示すように、はんだ8は、熱歪により受ける応力が大きくなるので寿命が低下する。なお、図6では樹脂層6の表示は省略している。   As a comparative example corresponding to the prior art, for example, as shown in FIG. 5, it is assumed that the surface layer 3b is not provided and the printed board 3 remains the core layer 3a. In this case, since the Young's modulus of the core layer 3a is high, the core layer 3a corresponds to the stress of the thermal strain ε directed from the low distribution layer 6a to the solder 8 indicated by the white arrow in FIG. Since the amount of deformation is small as shown by the arrow, the stress component of thermal strain is not dispersed so much. As a result, as shown in FIG. 6, the life of the solder 8 is reduced because the stress received by thermal strain increases. In FIG. 6, the display of the resin layer 6 is omitted.

上記したように、図3に示した表層3bを設ける本実施形態の構成の場合と、図5に示した表層3bを設けない比較例の構成の場合とで、各部に設定しているヤング率、線膨張係数、応力などについて図7にまとめて示している。   As described above, the Young's modulus set for each part in the case of the configuration of the present embodiment in which the surface layer 3b shown in FIG. 3 is provided and the case of the configuration of the comparative example in which the surface layer 3b shown in FIG. FIG. 7 collectively shows the linear expansion coefficient, stress, and the like.

この結果、プリント基板3のコア層3aおよび表層3bが共に線膨張係数αが小さく、同程度である場合でも、表層3bのようにヤング率を低く設定した層を設けることで、熱歪によるはんだ8への応力を基板側で分散して小さくすることができている。   As a result, even when both the core layer 3a and the surface layer 3b of the printed circuit board 3 have a small linear expansion coefficient α, a layer with a low Young's modulus is provided as in the surface layer 3b, so that solder due to thermal strain is provided. The stress to 8 can be dispersed and reduced on the substrate side.

図8は上記のようにしてプリント基板3の表層3bについて、弾性率すなわちヤング率を変化させた場合に、表面実装している電子部品4のはんだ8のクラック率を低減することができるかを発明者による測定結果を示している。なお、ここではんだクラック率は、値(%)が大きい方がクラック状態の程度が大きくなり、はんだ寿命が短いことを示している。そして、はんだクラック率100%は、クラックによりはんだ部分で断線(オープン)状態になっていることを示している。   FIG. 8 shows whether or not the crack rate of the solder 8 of the surface-mounted electronic component 4 can be reduced when the elastic modulus, that is, the Young's modulus is changed for the surface layer 3b of the printed circuit board 3 as described above. The measurement result by an inventor is shown. Here, the solder crack rate indicates that the larger the value (%), the greater the degree of cracking and the shorter the solder life. The solder crack rate of 100% indicates that the solder portion is disconnected (open) due to the crack.

この結果からわかるように、従来相当の比較例では、プリント基板3のコア層3aに相当するヤング率が27〜30GPaであり、それ以下の20GPaや25GPaでもはんだクラック率が低減できておらず、そのレベルを100%としている。そして、本実施形態のように、表層3bとしてヤング率を10GPaあるいは15GPa程度に設定した場合には、30%あるいは40%と大幅に低減できている。   As can be seen from this result, in the conventional comparative example, the Young's modulus corresponding to the core layer 3a of the printed circuit board 3 is 27 to 30 GPa, and the solder crack rate cannot be reduced even at 20 GPa or 25 GPa below that, That level is 100%. And like this embodiment, when the Young's modulus is set to about 10 GPa or 15 GPa as the surface layer 3b, it can be greatly reduced to 30% or 40%.

したがって、表層3bのヤング率は、好ましくは10〜15GPaの範囲に設定すると確実にはんだクラック率を低減することができており、比較例との間のレベルを考慮すると、上限としてヤング率17GPa程度まで本効果が期待できることがわかる。すなわち、表層3bのヤング率は、10〜17GPaの範囲で設定することで上記した効果を得ることができる。   Therefore, when the Young's modulus of the surface layer 3b is preferably set in the range of 10 to 15 GPa, the solder crack rate can be reliably reduced, and considering the level between the comparative example and the upper limit, the Young's modulus is about 17 GPa. It can be seen that this effect can be expected. That is, the above-described effects can be obtained by setting the Young's modulus of the surface layer 3b in the range of 10 to 17 GPa.

このような本実施形態によれば、樹脂層5、6にフィラの沈降により低分布層5a、6aが発生する場合でも、この低分布層6aと接するプリント基板3の表層3bのヤング率をコア層3aよりも低く設定することで熱歪による応力を分散することができる。この結果、表層3b側に実装した電子部品4のはんだ8のはんだ寿命低下を抑制することができる。   According to this embodiment, even when the low distribution layers 5a, 6a are generated in the resin layers 5, 6 due to sedimentation of the filler, the Young's modulus of the surface layer 3b of the printed circuit board 3 in contact with the low distribution layer 6a is determined as the core. By setting it lower than the layer 3a, the stress due to thermal strain can be dispersed. As a result, a decrease in the solder life of the solder 8 of the electronic component 4 mounted on the surface layer 3b side can be suppressed.

また、これによって、電子部品4のはんだ付後にフラックス残渣を洗浄せずに電子部品を樹脂層6で封止する場合、電子部品4とプリント基板3の表層3bとの間に残留するフラックス残渣による悪影響を緩和できる。   Further, when the electronic component is sealed with the resin layer 6 without cleaning the flux residue after the soldering of the electronic component 4, the flux residue remaining between the electronic component 4 and the surface layer 3b of the printed circuit board 3 can be used. Adverse effects can be mitigated.

すなわち、一般に、フラックス残渣が、熱膨張により電子部品4を押上げ、はんだ寿命を低下させるが、表層3bの弾性率(ヤング率)を低く設定することで、その表層3bを変形させることでこれを吸収できるため、はんだ8のはんだ寿命低下を抑制するという効果がある。換言すれば、電子部品4のはんだ付け時のフラックス残渣を除去しなければならないという制約を緩和できるという効果がある。   That is, in general, the flux residue pushes up the electronic component 4 due to thermal expansion and reduces the solder life. However, by setting the elastic modulus (Young's modulus) of the surface layer 3b to be low, this can be achieved by deforming the surface layer 3b. Therefore, there is an effect of suppressing the solder life reduction of the solder 8. In other words, there is an effect that the restriction that the flux residue when the electronic component 4 is soldered must be removed can be relaxed.

(第2実施形態)
図9は第2実施形態を示すもので、以下、第1実施形態と異なる部分について説明する。この実施形態では、プリント基板3に代えて、プリント基板10を設ける構成としている。プリント基板10は、コア層10aを中心として両面に表層10bを設けている。コア層10aはコア層3aと同等であり、表層10bは表層3bと同等のものである。
(Second Embodiment)
FIG. 9 shows the second embodiment. Hereinafter, parts different from the first embodiment will be described. In this embodiment, a printed circuit board 10 is provided instead of the printed circuit board 3. The printed circuit board 10 is provided with a surface layer 10b on both sides with a core layer 10a as a center. The core layer 10a is equivalent to the core layer 3a, and the surface layer 10b is equivalent to the surface layer 3b.

このような構成を採用する場合でも、プリント基板10が樹脂層5と接する側の表層10bは、線膨張係数αが樹脂層5と同等であるから、この面に実装された電子部品4のはんだ8が熱歪の応力による悪影響を大きく受けることがない。   Even when such a configuration is adopted, the surface layer 10b on the side where the printed circuit board 10 is in contact with the resin layer 5 has a linear expansion coefficient α equivalent to that of the resin layer 5, and therefore the solder of the electronic component 4 mounted on this surface 8 is not greatly affected by the thermal strain stress.

したがって、このような第2実施形態によっても第1実施形態と同様の作用効果を得ることができる。また、本実施形態で採用するプリント基板10は、両面に表層10bを配置しているので、上下面の区別なく実装作業やポッティング作業を行うことができるという製造工程上の利点もある。   Therefore, the same operational effects as those of the first embodiment can be obtained also by the second embodiment. In addition, since the printed circuit board 10 employed in the present embodiment has the surface layer 10b on both surfaces, there is an advantage in the manufacturing process that mounting work and potting work can be performed without distinction between the upper and lower surfaces.

(他の実施形態)
なお、本発明は、上述した実施形態のみに限定されるものではなく、その要旨を逸脱しない範囲で種々の実施形態に適用可能であり、例えば、以下のように変形または拡張することができる。
(Other embodiments)
In addition, this invention is not limited only to embodiment mentioned above, In the range which does not deviate from the summary, it is applicable to various embodiment, For example, it can deform | transform or expand as follows.

実施形態においては、電子部品4をプリント基板3の両面に実装する場合を示したが、低分布層6aが接触する側の表層3bを設けた面だけに電子部品4を実装する場合でも適用することができる。
実施形態においては、はんだ8は、車両用の鉛フリーはんだを用いた場合を示したが、これに限らず、他のはんだを用いることもできる。
In the embodiment, the case where the electronic component 4 is mounted on both surfaces of the printed circuit board 3 has been described. be able to.
In the embodiment, the case where the solder 8 is a lead-free solder for a vehicle is shown, but the present invention is not limited to this, and other solders can also be used.

実施形態においては、2層のプリント基板3、3層のプリント基板10の例を示したが、低分布層6aが接触する部分にヤング率の低い表層3bあるいは10bを設ける構成を採用するものであれば、他に4層以上の基層を積層したプリント基板を採用することもできる。   In the embodiment, the example of the two-layer printed circuit board 3 and the three-layer printed circuit board 10 has been described. However, a configuration in which the surface layer 3b or 10b having a low Young's modulus is provided in a portion where the low distribution layer 6a contacts is adopted. If so, a printed circuit board in which four or more base layers are laminated can also be adopted.

本開示は、実施例に準拠して記述されたが、本開示は当該実施例や構造に限定されるものではないと理解される。本開示は、様々な変形例や均等範囲内の変形をも包含する。加えて、様々な組み合わせや形態、さらには、それらに一要素のみ、それ以上、あるいはそれ以下、を含む他の組み合わせや形態をも、本開示の範疇や思想範囲に入るものである。   Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

図面中、1は筐体、3、10はプリント基板、3a、10aはコア層(基材)、3b、10bは表層(弾性率が低い基材)、4は電子部品、5、6は樹脂層、5a、6aは低分布層、8ははんだである。   In the drawings, 1 is a casing, 3, 10 is a printed circuit board, 3a and 10a are core layers (base materials), 3b and 10b are surface layers (base materials having a low elastic modulus), 4 is an electronic component, and 5 and 6 are resins. Layers 5a and 6a are low distribution layers, and 8 is solder.

Claims (7)

電子部品(4)がはんだ(8)を用いて実装されたプリント基板(3、10)と、
前記プリント基板が格納される筐体(1)と、
前記筐体内に前記プリント基板の両面を覆うように充填されフィラを含む樹脂層(5、6)とを備え、
前記プリント基板は、板厚方向に弾性率が異なる2以上の基材(3a、3b、10a、10b)を積層して構成され、前記樹脂層のフィラの粗密分布に対応して前記基材が配置される電子装置。
Printed circuit boards (3, 10) on which electronic components (4) are mounted using solder (8);
A housing (1) in which the printed circuit board is stored;
A resin layer (5, 6) filled in the casing so as to cover both sides of the printed circuit board and including a filler;
The printed circuit board is configured by laminating two or more base materials (3a, 3b, 10a, 10b) having different elastic moduli in the thickness direction, and the base material corresponds to the density distribution of the filler of the resin layer. Electronic device to be placed.
前記プリント基板(3)は、前記樹脂層のうちのフィラが粗な低分布層(6a)が接する側の面に前記基材のうちの弾性率が低い基材(3b)が配置される請求項1に記載の電子装置。   In the printed circuit board (3), a base material (3b) having a low elastic modulus among the base materials is disposed on a surface of the resin layer on a side where a low distribution layer (6a) having a rough filler is in contact. Item 2. The electronic device according to Item 1. 前記樹脂層は、前記フィラを添加した液状封止材を硬化させたものである請求項1または2に記載の電子装置。   The electronic device according to claim 1, wherein the resin layer is obtained by curing a liquid sealing material to which the filler is added. 前記プリント基板は、前記電子部品が両面に実装されている請求項1から3のいずれか一項に記載の電子装置。   The electronic device according to any one of claims 1 to 3, wherein the electronic component is mounted on both sides of the printed circuit board. 前記プリント基板(10)は、両面に前記基材のうちの弾性率が低い基材(10b)が配置される請求項1から4のいずれか一項に記載の電子装置。   5. The electronic device according to claim 1, wherein a base material (10 b) having a low elastic modulus among the base materials is disposed on both sides of the printed circuit board (10). 前記プリント基板の基材のうち弾性率が低い基材(3b、10b)の弾性率は、5〜17GPaの範囲である請求項1から5のいずれか一項に記載の電子装置。   The electronic device according to any one of claims 1 to 5, wherein an elastic modulus of a base material (3b, 10b) having a low elastic modulus among base materials of the printed circuit board is in a range of 5 to 17 GPa. 前記樹脂層は、前記フィラが均一に混ざった状態で硬化されたものの線膨張係数が前記プリント基板の基材とほぼ同じに設定されている請求項1から6のいずれか一項に記載の電子装置。   The electron according to any one of claims 1 to 6, wherein the resin layer is hardened in a state where the filler is uniformly mixed, and has a linear expansion coefficient set to be substantially the same as that of the base material of the printed circuit board. apparatus.
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