JP2019020687A - Display device - Google Patents

Abstract

To reduce a production cost or an occupied area of a driver IC.SOLUTION: A display device comprises a display unit, a first circuit, and a second circuit. The first circuit has a function to convert a first digital signal to a plurality of digital signals and a function to serially output the plurality of second digital signals to the second circuit. The second circuit has a function to convert the plurality of second digital signals to a plurality of analog signals and a function to output the analog signals to a wiring of the display unit. A transistor constituting the first circuit is formed on a single crystal semiconductor substrate or a compound semiconductor substrate. Transistors constituting the second circuit and the display unit are formed on a substrate having an insulation surface using a metal oxide as a semiconductor layer. A transistor having a shorter channel length than the transistor included in the display unit is used as a transistor included in the second circuit.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a display device. One embodiment of the present invention relates to a driver circuit of a display device.

  Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof , Or a method for producing them, can be mentioned as an example.

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. In addition, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.

  A driver circuit of a display device is required to have high performance in order to cope with high definition and multi-gradation of a display portion. For this reason, an IC (Integrated Circuit: hereinafter also referred to as a driver IC) is employed for a driver circuit of a display device, particularly a source driver.

  The driver IC includes a shift register, a latch, a level shifter, a digital / analog conversion circuit (also referred to as a DAC), an analog buffer, and the like. The shift register and latch are circuits that handle digital signals, the level shifter and DAC are circuits that convert digital signals into analog signals, and the analog buffers are circuits that generate and output gradation voltages.

  A circuit that handles a digital signal is required to operate at a high speed, so that the transistors that form the circuit operate at a low voltage. On the other hand, a circuit handling an analog signal is required to operate at a higher voltage than a circuit handling a digital signal in order to handle a voltage for driving the display unit.

  Patent Document 1 discloses that a circuit that requires high pressure resistance is manufactured using a semiconductor having a higher band gap than silicon or germanium on a substrate different from a circuit that does not require pressure resistance.

JP 2011-227479 A

  As the display device has higher definition and multi-gradation, the area of the driver IC increases, and the cost per driver IC has become a problem. Therefore, the area of the driver IC is being reduced by manufacturing the driver IC with a finer technology.

  However, since the withstand voltage of the element is reduced with the miniaturization, there is a problem that in the driver IC, the portion handling the analog signal is difficult to miniaturize compared to the portion handling the digital signal. As the area for handling digital signals is reduced, the ratio of the area for handling analog signals to the total area of the driver ICs increases. Therefore, as the technology becomes more miniaturized, the effect on the area reduction of the driver IC itself becomes more effective. There is a problem that it is difficult to obtain.

  Even if the area of the driver IC is reduced, if the number of output terminals is large, the occupied area of the terminals and wiring on the display panel side on which the driver IC is mounted is increased. Occupied area) also increases.

  An object of one embodiment of the present invention is to reduce the production cost of a driver IC. Another object is to reduce the area occupied by a driver IC. Another object is to provide a display device with a narrow frame. Another object is to provide a display device in which a display portion can have high definition and multiple gradations.

  Another object of one embodiment of the present invention is to provide a highly reliable display device. Another object is to provide a novel display device.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these can be extracted from the description, drawings, claims, and the like.

  One embodiment of the present invention is a display device including a first circuit, a second circuit, and a display portion. The display unit includes a plurality of pixels and a plurality of wirings respectively connected to the pixels. The first circuit has a function of converting the first digital signal into a plurality of second digital signals and a function of serially outputting the plurality of second digital signals to the second circuit. The second circuit has a function of converting a plurality of second digital signals into a plurality of analog signals and a function of outputting the analog signals to a wiring. The first circuit includes a first transistor formed over the first substrate, the second circuit includes a second transistor formed over the second substrate, and the display portion includes a pixel A third transistor formed over the second substrate. The first substrate is a single crystal semiconductor substrate or a compound semiconductor substrate, and the second substrate is a substrate having an insulating surface. The first transistor includes silicon or germanium in a semiconductor in which a channel is formed, and the second transistor and the third transistor include a metal oxide in a semiconductor in which a channel is formed. The second transistor has a portion with a channel length shorter than that of the third transistor.

  In the above, the second transistor preferably includes a portion having a channel length of 0.1 μm to 1.0 μm.

  In the above, it is preferable to include a third circuit having a plurality of buffer amplifier circuits. At this time, the analog signal output from the second circuit is preferably output to the wiring through the buffer amplifier circuit.

  In the above, the third circuit preferably includes a fourth transistor formed over the second substrate. At this time, the fourth transistor preferably uses a metal oxide for a semiconductor in which a channel is formed.

  Alternatively, in the above, the third circuit preferably includes a fifth transistor formed over the first substrate. At this time, the fifth transistor preferably uses silicon or germanium for a semiconductor in which a channel is formed.

  According to one embodiment of the present invention, the production cost of a driver IC can be reduced. Alternatively, the area occupied by the driver IC can be reduced. Alternatively, a display device with a narrow frame can be provided. Alternatively, a display device in which the display portion can have high definition and multiple gradations can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description, drawings, claims, and the like.

2 shows a configuration example of a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 6 shows a structural example of a circuit that can be applied to a display device. 2 shows a structure example of a transistor. 2 shows a structure example of a transistor. Configuration examples of a transistor, a capacitor, and the like. 10A and 10B illustrate an example of a method for manufacturing a transistor, a capacitor, and the like. 10A and 10B illustrate an example of a method for manufacturing a transistor, a capacitor, and the like. 10A and 10B illustrate an example of a method for manufacturing a transistor, a capacitor, and the like. FIG. 6 illustrates an electrical device. A configuration example of a display module. Configuration example of an electronic device. Configuration example of an electronic device. Configuration example of an electronic device. 2 shows a configuration example of a television device. Circuit diagram and layout pattern. The perspective schematic diagram of a circuit.

  Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.

  Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated. In addition, in the case where the same function is indicated, the hatch pattern is the same, and there is a case where no reference numeral is given.

  Note that in each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggerated for simplicity in some cases. Therefore, it is not necessarily limited to the scale.

  In the present specification and the like, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

  A transistor is a kind of semiconductor element, and can realize amplification of current and voltage, switching operation for controlling conduction or non-conduction, and the like. The transistor in this specification includes an IGFET (Insulated Gate Field Effect Transistor) and a thin film transistor (TFT: Thin Film Transistor).

  In this specification and the like, a display panel which is one embodiment of a display device has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is one mode of the output device.

  Further, in this specification and the like, a display panel substrate, for example, a connector such as a FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached, or the substrate is integrated with a COG (Chip On Glass) method or the like. In some cases, is mounted a display panel module, a display module, or simply a display panel.

  In this specification and the like, the touch sensor has a function of detecting that a detection target such as a finger or a stylus touches, presses, or approaches. Moreover, you may have the function to detect the positional information. Therefore, the touch sensor is an aspect of the input device. For example, the touch sensor can be configured to have one or more sensor elements.

  In this specification and the like, a substrate having a touch sensor may be referred to as a touch sensor panel or simply a touch sensor. In addition, in this specification and the like, a touch sensor panel substrate, for example, a connector such as an FPC or TCP attached, or a substrate in which an IC is mounted by a COG method, a touch sensor panel module, a touch sensor It may be called a module, a sensor module, or simply a touch sensor.

  Note that in this specification and the like, a touch panel which is one embodiment of a display device has a function of displaying (outputting) an image or the like on a display surface, and a detection target such as a finger or a stylus touches, presses, or approaches the display surface. And a function as a touch sensor for detecting the above. Accordingly, the touch panel is an embodiment of an input / output device.

  The touch panel can also be referred to as, for example, a display panel with a touch sensor (or display device) or a display panel with a touch sensor function (or display device).

  The touch panel can be configured to include a display panel and a touch sensor panel. Alternatively, the display panel may have a function as a touch sensor inside or on the surface.

  In this specification and the like, a touch panel substrate having a connector such as an FPC or TCP attached, or a substrate having an IC mounted on the substrate by a COG method, a touch panel module, a display module, or simply a touch panel And so on.

(Embodiment 1)
In this embodiment, a display device, a semiconductor device, a driving method thereof, and the like of one embodiment of the present invention will be described.

  A display device of one embodiment of the present invention includes a first substrate having a first driver circuit portion, and a second substrate having a second driver circuit portion and a display portion.

  The first drive circuit unit and the second drive circuit unit can convert an input serial video signal into a parallel video signal and output it to the display unit. Here, the input serial video signal is preferably digital data, and the output parallel video signal is preferably analog data.

  Furthermore, the video signal transmitted from the first drive circuit unit to the second drive circuit unit is preferably a plurality of serial signals. More preferably, the number of video signals transmitted from the first driver circuit portion to the second driver circuit portion is equal to or less than the number of source signal lines (also referred to as source lines) included in the display portion. It is preferable that they are a plurality of serial signals respectively transmitted through wiring. Thereby, the number of wirings and the number of terminals between the first drive circuit unit and the second drive circuit unit can be reduced. At this time, the number of wirings and terminals is determined by the number of pixels (more specifically, the number of source lines) included in the display portion regardless of the gradation value of the video signal to be handled. Even when the display unit is compatible with the above, the number of wirings and the number of terminals do not increase.

  The first substrate provided with the first drive circuit is preferably packaged in the form of an IC chip. The first substrate can be mounted on the second substrate by a mounting method such as a COG method. As the first substrate, a single crystal semiconductor substrate, a compound semiconductor substrate, or the like can be used. Thereby, the operating frequency of the first drive circuit can be made extremely high.

  For the second substrate, a substrate having at least an insulating surface can be used. For example, the second substrate is preferably an insulating substrate such as a glass substrate or a flexible substrate. Further, in the transistor included in the second driver circuit and the transistor included in the display portion, a metal oxide formed over the second substrate is applied to a semiconductor in which a channel is formed. preferable. Further, these transistors are preferably formed on the same surface. In particular, these transistors are preferably formed through the same process.

  Since a transistor using a metal oxide can preferably reduce off-state current as compared with a transistor using silicon, a transistor can be used even when analog data is transmitted or when the analog data is temporarily stored. Fluctuation of the data value due to the influence of the leakage current is hardly generated. In addition, a transistor using a metal oxide can have higher withstand voltage than a transistor using silicon. As a result, by using a transistor to which a metal oxide is applied as the second driver circuit, analog signal processing and transmission with a relatively high voltage can be performed with high reliability.

  In addition, the channel length of the transistor included in the second driver circuit is preferably shorter than the channel length of the transistor included in the display portion. In particular, the channel length of the transistor included in the second driver circuit is less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, and further preferably 0.8 μm. Hereinafter, it is more preferably 0.6 μm or less, and preferably 0.1 μm or more. As a result, the drive frequency of the second drive circuit can be increased. In addition, since the area occupied by the second drive circuit can be reduced, the area of the drive circuit portion is increased as compared with the case where the first drive circuit and the second drive circuit are configured by one IC chip. Can be prevented.

  The first drive circuit preferably includes a portion that mainly processes digital data. Thereby, digital data with a large amount of data can be processed at high speed. The second driving circuit preferably includes a portion for processing analog data. Thereby, analog data having a relatively high voltage can be processed with high reliability.

  The power supply voltage supplied to the first drive circuit and the voltage of the digital data signal to be handled (that is, the drive voltage of the first drive circuit) are the power supply voltage supplied to the second drive circuit and the analog to be handled. The voltage is preferably lower than the voltage of the data signal (that is, the driving voltage of the second driving circuit).

  The second driving circuit preferably includes a circuit that converts digital data into analog data. In particular, a circuit having a function of outputting an analog signal having a potential corresponding to the gradation value when digital data indicating a predetermined gradation value is input is preferably included. As one of such circuits, there is a pass transistor logic (PTL) circuit.

  In the PTL circuit, it is necessary to provide an extremely large number of transistors depending on the number of gradations of the video signal. Furthermore, it is necessary to apply a high breakdown voltage transistor to each transistor constituting the PTL circuit. Therefore, for example, when configured with silicon or the like, the PTL circuit hardly contributes to the reduction of the chip area even if the miniaturization technique is improved as compared with a circuit configured with a low-voltage driving transistor that processes a digital signal. Therefore, by providing at least the PTL circuit on the second substrate and not mounting the PTL circuit on the chip side, the chip area can be greatly reduced, and the production cost can be reduced.

  The PTL circuit included in the second driver circuit can include a plurality of transistors to which a metal oxide is applied.

  It is preferable to provide a buffer amplifier circuit having at least one of a function of stabilizing the output signal of the second driver circuit and a function of boosting. At this time, the buffer amplifier circuit can be formed over the second substrate using a transistor to which a metal oxide is applied. Accordingly, since the second driver circuit, the buffer amplifier circuit, and the display portion can be provided adjacent to each other, wiring can be simplified.

  Alternatively, the buffer amplifier circuit may be formed on the first substrate. At this time, serial analog data is output from the second substrate to the first substrate, and serial analog data is supplied from the buffer amplifier circuit on the first substrate to the display unit. By forming the buffer amplifier circuit on the first substrate, it is possible to further increase the current supply capability as compared with a case where transistors of the same size are formed on the second substrate. As a result, the charge / discharge time of the source line by the buffer amplifier circuit can be shortened, and higher-speed data writing to the display portion can be stably performed. In such a configuration, when the frame frequency of the image displayed on the display unit is high, when the number of source lines in the display unit is extremely large (that is, when the resolution is high), or when the size of the display unit is large and the length of the source line is long. This is suitable when the length is long.

  Note that in this specification and the like, the channel length direction of a transistor refers to one of directions parallel to a straight line connecting the source and the drain with the shortest distance. That is, the channel length direction corresponds to the direction of current flowing through the semiconductor layer when the transistor is on. The channel width direction is a direction orthogonal to the channel length direction. Note that depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be determined as one.

  In this specification and the like, the channel length of a transistor refers to the length in a channel length direction of a region where a semiconductor layer and a gate electrode overlap in a top view or a cross-sectional view of the transistor, for example. The channel width of the transistor refers to the length of the region in the channel width direction.

  Note that depending on the structure and shape of the transistor, the channel length and the channel width may not be determined as one value. Therefore, in this specification and the like, the channel length and the channel width can be the maximum value, the minimum value, or the average value, or any value between the maximum value and the minimum value. Typically, the channel length and the channel width are the minimum values.

  Further, depending on the structure of the transistor, the transistor may include a pair of gate electrodes (a first gate electrode and a second gate electrode) that sandwich the semiconductor layer. At this time, two channel lengths and channel widths of the transistor can be defined corresponding to each gate electrode. Therefore, in the present specification and the like, when simply referred to as a channel length, one of the longer or shorter of the two channel lengths, both, or an average value thereof is indicated. Similarly, in the present specification and the like, when simply referred to as a channel width, it refers to either the longer or the shorter of the two channel widths, both, or an average value thereof.

  Hereinafter, more specific examples will be described with reference to the drawings.

[Configuration example 1]
FIG. 1 shows a block diagram of the display device 10. The display device 10 includes a first drive circuit 11, a second drive circuit 12, a display unit 13, a buffer amplifier circuit AMP, a gate drive circuit GD, and the like.

  The first drive circuit 11 includes a receiver circuit RCV, a serial parallel converter circuit SPC, a shift register SR, a latch circuit LAT1, a first circuit TC, a shift register circuit LS, and the like.

  The second drive circuit 12 includes a second circuit RC, a latch circuit LAT2, a pass transistor logic circuit PTL, a voltage generation circuit GEN, and the like.

  The first drive circuit 11 is provided on the substrate 20. As the substrate 20 on which the first driver circuit 11 is provided, a single crystal semiconductor substrate such as silicon or germanium, a compound semiconductor substrate such as silicon carbide or silicon germanium, an SOI substrate, or the like can be used. The transistor included in the first driver circuit 11 is preferably formed so that a channel is formed in a semiconductor included in the substrate 20.

  The second drive circuit 12, the display unit 13, the buffer amplifier circuit AMP, and the gate drive circuit GD are provided on the substrate 30. As the substrate 30 provided with these, various materials other than the semiconductor substrate can be used. For example, glass, metal, ceramics, resin, etc. are mentioned. In addition, by using a material that is thin enough to have flexibility as the substrate 30, a display device that can bend the display portion 13 can be realized.

  As the transistors constituting the second driver circuit 12, the display unit 13, and the buffer amplifier circuit AMP, it is preferable to use a thin film transistor provided over the substrate 30. In the thin film transistor, a thin film of single crystal silicon, polycrystalline silicon, amorphous silicon, metal oxide, or the like can be used for a semiconductor layer in which a channel is formed.

  In particular, a metal oxide having a band gap larger than that of silicon is preferably used for the transistors included in the second driver circuit 12, the display portion 13, and the buffer amplifier circuit AMP. In particular, it is preferable to use a metal oxide having crystallinity. Transistors using metal oxides with sufficiently reduced carrier concentration are higher than transistors using amorphous silicon, have field effect mobility comparable to transistors using polycrystalline silicon, and extremely low off-state current. Can be realized.

  In addition, it is preferable to use a transistor having a channel length shorter than that of a transistor provided in the pixel of the display portion 13 as a transistor included in the second driver circuit 12 and the buffer amplifier circuit AMP. As a result, the drive frequency of the second drive circuit 12 and the buffer amplifier circuit AMP can be increased.

  The display unit 13, the second drive circuit 12, and the buffer amplifier circuit AMP are preferably configured by unipolar transistors. In particular, it is preferably composed of an n-type transistor. Accordingly, it is not necessary to separately form an n-type transistor and a p-type transistor, so that manufacturing cost can be reduced.

[Display unit 13]
The display unit 13 has a configuration in which a plurality of pixels PIX are arranged in a matrix. At least one source line SL and one gate line GL are connected to one pixel PIX. The gate line GL is connected to the gate driving circuit GD and supplied with a selection signal for selecting a pixel. The source line SL is supplied with an analog video signal for writing to the pixel from the buffer amplifier circuit AMP.

  The pixel PIX includes at least one display element and at least one transistor. As the display element, for example, a light emitting element such as a liquid crystal element or an organic electroluminescence (EL) element can be used. Note that the display element is not limited to this, and various elements can be used.

  Here, the display unit 13 shows an example in which m pixels in the column direction and n pixels in the row direction are arranged. The display unit 13 is connected to m gate lines GL (gate lines GL [1] to [m]) and n source lines SL (source lines SL [1] to [n]). In the following, when a plurality of source lines and the like are described together, they are expressed as a source line SL [1: n].

[First drive circuit 11]
The first drive circuit 11 samples a video signal D0, which is a digital video signal input serially, and outputs a digital data signal (data signal D3t) capable of serial output equal to or less than the number n of the source lines SL. And has a function of outputting to the second drive circuit 12. Here, an example in which a digital data signal is output to the second drive circuit 12 through the same number of wires as the number n of source lines SL will be described.

  The receiver circuit RCV is a circuit that receives the video signal D0 serially input to the first drive circuit 11. As the configuration of the receiver circuit RCV, various circuits can be used depending on the transmission method of the video signal D0. As a method of transmitting data from the outside to the first drive circuit 11, encoding methods and interfaces defined by various standards can be used. For example, a standard such as LVDS (Low Voltage Differential Signaling), mini-LVDS, DP (Display Port), or eDP (embedded DP), or MIPI (registered trademark) -Mobile Industry Interface Allocation Standard) There are interface standards such as PHY or M-PHY (registered trademark).

The serial video signal received by the receiver circuit RCV is input to the serial / parallel converter circuit SPC. The serial parallel converter circuit SPC generates a clock signal S _CLK and a start pulse signal S _SP based on the input signal and outputs the clock signal S _CLK and the start pulse signal S _SP to the shift register SR.

  The serial-parallel converter circuit SPC divides the serially input video signal into p serial data signals D1 (data signal D1 [1: p]) (p is an integer not smaller than 1 and not larger than n). Output to each of the latch circuits LAT1 [1: p].

Shift register SR includes a serial-parallel converter circuit clock signal inputted from the SPC _{S CLK,} a start pulse signal _{S SP,} generates a sampling signal, n number of the latch circuits LAT1 [1: p] to output respectively.

When the clock signal to one of the latch circuits LAT1 (e.g. j-th latch circuit LRAT1 [j]) _{S CLK} and the start pulse signal _{S SP} is input, these according to the data signals D1 [j] is sampled, each bit The data is held in the memory element of the latch circuit LAT1 [j]. That is, the serially input data signal D1 [j] is written to the latch circuit LAT1 [j] as parallel data.

  The time until data writing to the latch circuit LAT1 [1: p] is completed is called a line period.

  When the writing of data to the latch circuit LAT1 [1: p] is completed, the n first circuits TC [1: in accordance with a pulse of a latch signal (not shown) input to the latch circuit LAT1 [1: p]. n] simultaneously outputs the data signal D2 [1: n] as parallel data. Here, when the number of latch circuits LAT1 is smaller than n, one latch circuit LAT1 outputs the data signal D2 to the plurality of first circuits TC.

  Here, the data signal D2 [k] input to the kth first circuit TC [k] is a parallel data signal having the same number of bits as the number of gradations of the video signal. For example, in the case of an 8-bit video signal, the data signal D2 [k] is an 8-bit parallel data signal. In the case of a 12-bit gradation video signal, the data signal D2 [k] is a 12-bit parallel data signal.

  Each of the n first circuits TC [1: n] converts the parallel data signal D2 input from the latch circuit LAT into a serial data signal D3 and outputs the serial data signal D3 to the level shifter circuit LS.

  When the data signal D2 [k] is input to the k-th first circuit TC [k], the first circuit TC [k] converts it into a serial data signal D3 [k], and the level shifter circuit LS [ k].

  Here, the data signal D3 [k] output from the k-th first circuit TC [k] is a serial data signal having the same number of bits as the number of gradations of the video signal. Therefore, for example, in the case of an 8-bit gradation video signal, the data signal D3 [k] is a signal including 8-bit serial data, and in the case of a 12-bit gradation video signal, the data signal D3 [k] is The signal includes 12-bit serial data.

  The kth data signal D3 [k] is converted by the level shifter circuit LS [k] into a data signal D3t [k] whose voltage amplitude is increased, and is output to the kth second circuit RC [k]. The Similarly to the data signal D3 [k], the data signal D3t [k] is a signal including serial data having the same number of bits as the number of gradations of the video signal.

  In this way, the data signal between the n level shifter circuits [1: n] of the first drive circuit 11 and the n second circuits RC [1: n] of the second drive circuit 12. By transmitting D3 [1: n] serially, the number of terminals and wirings provided for transmitting video signals between the substrate 20 and the substrate 30 is the same as or equal to the number n of the source lines LS. It can be as follows. At this time, even if the number of gradations included in the video signal is increased, the number of terminals and wirings is not increased. In addition to terminals and wiring for transmitting video signals, terminals and wiring for transmitting timing signals and control signals, or for supplying power may be provided separately.

[Second drive circuit 12]
The second drive circuit 12 converts a plurality of digital data signals D3 serially input from the first drive circuit 11 into analog signals, and is connected to each source line SL included in the display unit 13. It has a function to output to AMP.

  Each of the n second circuits RC [1: n] converts the serially input data signal D3t [k] into a parallel data signal D4 [k] and outputs it to the latch circuit LAT2 [1: n]. It has a function.

  Here, the data signal D4 [k] output from the k-th second circuit RC [k] is a parallel data signal having the same number of bits as the number of gradations of the video signal. Therefore, for example, in the case of an 8-bit gradation video signal, the data signal D4 [k] includes 8-bit serial data, and in the case of a 12-bit gradation video signal, the data signal D4 [k] is a 12-bit serial data. It becomes a signal containing the data.

  One latch circuit LAT2 [k] outputs the parallel data signal D4 [k] input from the second circuit RC [k] to the pass transistor logic circuit PTL. Each of the latch circuits LAT [1: n] holds the data signal D4 [1: n] that is output until a latch signal (not shown) is input.

  The pass transistor logic circuit PTL is a circuit having a function of converting an input digital data signal D4 [1: n] into a data signal D5 [1: n] that is an analog signal. The n data signals D5 [1: n] converted by the pass transistor logic circuit PTL are respectively output to the buffer amplifier circuit AMP.

  Further, the voltage generation circuit GEN has a function of generating a gradation voltage. The plurality of gradation voltages generated by the voltage generation circuit GEN are input to the pass transistor logic circuit PTL. For example, when the video signal has 8-bit gradation data, the voltage generation circuit GEN generates a 256-level gradation voltage and outputs it to the pass transistor logic circuit PTL. For example, in the case of 12-bit gradation, a gradation voltage of 4096 levels is generated and output to the pass transistor logic circuit PTL.

[Buffer amplifier circuit]
Each of the n buffer amplifier circuits AMP [1: n] is connected to any one of the n source lines SL [1: n]. The buffer amplifier circuit AMP has at least one function of stabilizing or boosting the data signal D5 [k] that is the output signal of the second drive circuit 12. As the buffer amplifier circuit AMP, for example, a voltage follower circuit (voltage follower circuit), a source follower circuit, or the like can be used.

  Here, FIG. 1 shows an example in which the buffer amplifier circuit AMP is provided on the second substrate 30. As a result, the second driving circuit 12, the buffer amplifier circuit AMP, and the display unit 13 can be provided adjacent to each other, so that wiring can be simplified.

[Configuration example of each circuit]
<Pass transistor logic circuit PTL, voltage generation circuit GEN>
FIG. 2 shows a configuration example of the pass transistor logic circuit PTL. FIG. 2 also shows a configuration example of the voltage generation circuit GEN connected to the pass transistor logic circuit PTL.

  The pass transistor logic circuit PTL shown in FIG. 2 is a circuit having a function of converting an input digital signal into an analog signal. The voltage generation circuit GEN is a circuit having a function of generating a voltage of an output analog signal. It can also be said that the pass transistor logic circuit PTL and the voltage generation circuit GEN constitute a D / A (digital / analog) conversion circuit.

  The pass transistor logic circuit PTL shown in FIG. 2 is a circuit that outputs an analog signal corresponding to the 8-bit data signal D4 to the output terminal (OUT). The number of bits of the input data signal D4 is not limited to this.

  First, the voltage generation circuit GEN will be described. FIG. 2 shows an example of a voltage dividing circuit (resistance string type) voltage generation circuit GEN. The voltage generation circuit GEN is a circuit for generating a plurality of voltages (here, 256 voltages), and has a configuration in which a plurality of resistance elements RES are connected in series.

In the voltage generation circuit GEN shown in FIG. 2, the potential V ₂₅₅ is applied to one end of the string of the resistance elements RES connected in series, and the potential V ₀ is applied to the other end. The plurality of resistance elements RES divide the voltage V ₂₅₅ -V ₀ into 256 and output it as an output voltage to the pass transistor logic circuit PTL. Here, the potential V ₂₅₅ corresponds to the output potential corresponding to the gradation value 255, and the potential V ₀ corresponds to the output potential corresponding to the gradation value 0.

Note here as a reference and made potential (reference _potential), and _{V 255,} it has been described configuration using two of _{V 0,} the reference potential of the potential between the potential _{V 255} and the potential _{V 0,} using one or more May be. The larger the number of reference potentials, the better the stability of the output potential of the voltage generation circuit GEN.

  Note that the configuration of the voltage generation circuit GEN is not limited to this, and various configurations can be used as long as the circuit can generate a plurality of potentials.

  FIG. 2 shows a configuration in which one voltage generation circuit GEN is connected to one pass transistor logic circuit PTL. However, one voltage generation circuit GEN is connected to a plurality of pass transistor logic circuits PTL. It is preferable to supply a potential.

  Next, the pass transistor logic circuit PTL will be described. The pass transistor logic circuit PTL includes input k-th data signals D4 [k] (0) to D4 [k] (7) and inverted data signals D4B [k] (0) to D4B [ k] (7) has a plurality of switches SW whose conduction state is controlled. Here, for example, the data signal D4 [k] (0) is a signal corresponding to the first bit data of the kth 8-bit data signal D4 [k], and the data signal D4B [k] (7 ) Is a signal corresponding to the inverted signal of the eighth bit of data.

  By controlling the conduction state of the switch SW included in the pass transistor logic circuit PTL, the voltage of the data signal converted from digital to analog and output from the output terminal (OUT) corresponds to the gradation voltage of the display unit 13. Voltage.

  Here, FIG. 3 shows an example in which a transistor is applied as the plurality of switches SW. Here, “OS” is added to indicate a transistor to which an oxide semiconductor (a metal oxide having semiconductor characteristics) is applied.

  The plurality of transistors included in the pass transistor logic circuit PTL preferably have channel lengths shorter than those of the transistors provided in each pixel of the display portion 13. The channel length is, for example, less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, further preferably 0.8 μm or less, and further preferably 0.6 μm or less. And preferably 0.1 μm or more.

  Here, the voltage of the data signal output from the pass transistor logic circuit PTL varies depending on the display element included in the display unit 13, but the data signal D1, the data signal D2, and the data signal D3 are digital. It needs to be larger than the signal voltage. Therefore, the voltage required to drive the transistor for generating the analog data signal is converted into a large voltage by the level shifter circuit LS.

  A transistor in which a metal oxide is used for a channel formation region has characteristics such that the withstand voltage characteristic is higher than that of a transistor in which silicon is used, and thus can be preferably used for a circuit with a high driving voltage as described above. Further, by applying a transistor having a short channel length as described above to the transistor included in the pass transistor logic circuit PTL, the current value in the on state can be equal to or higher than that when polysilicon or the like is applied. it can. As a result, the drive circuit 12 including the pass transistor logic circuit PTL, which requires a high drive frequency and high breakdown voltage characteristics, can be formed on the same substrate 30 as the display unit 31.

<Latch circuit LAT2>
FIG. 4A is a circuit diagram of the latch circuit LAT2 [k] (i) applicable to the latch circuit LAT2. A latch circuit LAT2 [k] (i) illustrated in FIG. 4A is a sample-and-hold circuit that can latch 1-bit digital data.

The latch circuit LAT2 [k] (i) includes two transistors and two capacitors. The latch circuit LAT2 [k] (i) samples the data signal D4 [k] (i) according to the sampling signal S _SAMP and the latch signal S _LAT , and holds output data to the pass transistor logic circuit PTL. It has a function. Further, the latch circuit LAT2 [k] (i) can be precharged to the voltage V _PRE in accordance with the precharge signal SPRE.

  FIG. 4B illustrates an example in which two capacitors are formed using transistors. Each capacitor element has a configuration in which a source and a drain of a transistor are connected. Thus, two transistors and two capacitors can be formed in the same process.

  FIG. 4C illustrates a configuration example of the latch circuit LAT2 [k] (i) having two holding nodes. With such a configuration, it is possible to write data of the next frame to a node close to the input side in a state where the output data is held by the node close to the output side of the two hold nodes. Note that each capacitor illustrated in FIG. 4C may be formed using a transistor as in the case of FIG.

  Here, as the plurality of transistors included in the latch circuit LAT2 [k] (i), it is preferable to use a transistor to which a metal oxide is applied which is manufactured in a process common to the display portion 13 and other circuits. .

<First circuit TC, second circuit RC>
The first circuit TC [k] has a function of serially outputting digital data signals input in parallel. As the first circuit TC [k], for example, a parallel input serial output (PISO: Parallel-In, Serial-Out) type shift register circuit can be used.

  FIG. 5A illustrates an example of one first circuit TC [k]. Here, a configuration for processing 8-bit digital data is shown as an example of the first circuit TC [k].

  The first circuit TC [k] illustrated in FIG. 5A includes eight flip-flop circuits FF. The configuration of the flip-flop circuit FF is not particularly limited, but a flip-flop circuit FF capable of clock operation can be used. In the first circuit TC [k], data signals D2 [k] (0) to (7) which are parallel digital data are input to one flip-flop circuit FF, respectively. Further, a digital data signal D3 [k] is serially output from the output terminal of the flip-flop circuit FF at the final stage.

  FIG. 5B shows an example of one second circuit RC. Here, similarly to the above, a configuration for processing 8-bit digital data is shown as an example.

  The second circuit RC [k] illustrated in FIG. 5B includes eight flip-flop circuits FF. The digital data signal D3 [k] is serially input to the flip-flop circuit FF located at the first stage. In addition, digital data signals D4 [k] (0) to (7) are output as parallel data from the output terminals of the flip-flop circuits FF.

  Here, as the transistor included in the second circuit RC [k], it is preferable to use a transistor to which a metal oxide is applied, similar to the display portion 13. The channel length of the transistor is preferably shorter than that of a transistor provided in each pixel of the display portion 13. The channel length is, for example, less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, further preferably 0.8 μm or less, and further preferably 0.6 μm or less. And preferably 0.1 μm or more.

<Buffer amplifier circuit>
The buffer amplifier circuit AMP located between the pass transistor logic circuit PTL and the source line SL increases (amplifies) the amount of current that can be output to the source line SL, and suppresses a decrease in output potential. A circuit having a function can be used. For example, as shown in FIG. 6, a voltage follower circuit using an amplification operation circuit (OP amplifier) can be applied.

FIG. 7 shows a configuration example of the buffer amplifier circuit AMP [k] using the source follower circuit. The buffer amplifier circuit AMP shown in FIG. 7 has two transistors connected in series. A power supply potential VDD is supplied to one of a source and a drain of one transistor, and a data signal D5 [k] is input to a gate. The one of the source and the drain of the other transistor is supplied with the power supply potential VSS, and the bias voltage V _B is input to the gate. A node between the two transistors corresponds to an output terminal and is connected to the source line SL.

FIG. 7 illustrates an example in which a precharge circuit PRE [k] having a function of precharging the potential of the source line SL to two potentials (potential V _PREL and potential V _PREH ) is connected. The precharge circuit PRE [k] can apply each potential to the source line SL in accordance with the precharge signal _SPL and the precharge signal _SPH .

  When the buffer amplifier circuit AMP is provided on the substrate 30, it is preferable that the plurality of transistors included in the buffer amplifier circuit AMP and the precharge circuit PRE have shorter channel lengths than the transistors provided in each pixel of the display unit 13. The channel length is, for example, less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, further preferably 0.8 μm or less, and further preferably 0.6 μm or less. And preferably 0.1 μm or more.

<Display section>
The display unit 13 can have a configuration in which a plurality of pixels PIX each including at least one display element and one transistor are arranged in a matrix.

  FIG. 8A shows an example of a circuit diagram of the display portion 13a in the case where a light-emitting element is applied as the display element.

  A pixel PIXa included in the display portion 13a illustrated in FIG. 8A includes a transistor 41, a transistor 42, a capacitor 43, and a light-emitting element 44. The pixel PIXa is connected to the source line SL, the gate line GL, and the wiring VL1 and VL2 to which the power supply potential is supplied.

  The transistor 41 has a gate connected to the gate line GL, one of a source and a drain connected to the source line SL, and the other connected to one electrode of the capacitor 43 and the gate of the transistor 42. In the transistor 42, one of a source and a drain is connected to one electrode of the light emitting element 44, and the other is connected to the wiring VL 1. The other electrode of the capacitor 43 is connected to the wiring VL1. The other electrode of the light emitting element 44 is connected to the wiring VL2.

  The pixel PIX is selected by a signal supplied from the gate line GL. Further, by controlling the current flowing through the light-emitting element 44 by the potential written from the source line SL to the node to which the gate of the transistor 42 is connected through the transistor 41, the light emission luminance of the light-emitting element 44 can be controlled.

  As the light-emitting element 44, an organic electroluminescence element (also referred to as an organic EL element) or the like can be typically used. Note that the light-emitting element 44 is not limited to this, and an inorganic EL element containing an inorganic material, a light-emitting diode, or the like may be used.

  FIG. 8B shows a circuit diagram of the display portion 13b in the case where a display element capable of expressing gradation by voltage is applied.

  A pixel PIXb included in the display portion 13 b illustrated in FIG. 8B includes a transistor 51, a capacitor 53, and a display element 54. Further, the source line SL, the gate line GL, the wiring VL3 to which a common potential is supplied, and the wiring VL4 to which a power supply potential is supplied are connected to the pixel PIXb.

  The transistor 51 has a gate connected to the gate line GL, one of a source and a drain connected to the source line SL, and the other connected to one electrode of the capacitor 53 and one electrode of the display element 54. The other electrode of the capacitor 53 is connected to the wiring VL4. The other electrode of the display element 54 is connected to the wiring VL3.

  The pixel PIX is selected by a signal supplied from the gate line GL. In addition, the gray level expressed by the display element 54 is controlled by controlling the voltage applied to the display element 54 by the potential written to the node to which one electrode of the display element 54 is connected from the source line SL through the transistor 51. can do.

  As the display element 54, a liquid crystal element can be typically used. As the liquid crystal element, a transmissive, reflective, or transflective liquid crystal element can be used. The display element 54 is not limited to this. For example, in addition to a shutter type MEMS (Micro Electro Mechanical Systems) element and an optical interference type MEMS element, a microcapsule type, an electrophoretic type, an electrowetting type, an electronic type An element to which a powder fluid (registered trademark) system or the like is applied can be used.

  Here, as the transistor 41 and the transistor 42 provided in the pixel PIXa or the transistor 51 provided in the pixel PIXb, a transistor in which a metal oxide is used for a channel formation region is preferably used. Thereby, even when the area of the display unit 13 is increased, a display device with low power consumption and high display quality can be realized. In addition, each transistor provided in the display portion 13 preferably has a longer channel length than a transistor having the shortest channel length among transistors included in the second driver circuit 12. For example, the channel length of the transistor provided in the display portion is 1 μm or more, preferably 1.2 μm or more, more preferably 1.4 μm or more, and 20 μm or less, preferably 15 μm or less, more preferably 10 μm or less. preferable.

  In particular, when a transistor with a relatively long channel length (1.5 μm or more) is used as the transistor connected to the gate line GL, leakage current (off current) in an off state can be extremely low. Thus, the fluctuation of the potential written to the pixel can be reduced as much as possible. On the other hand, in the pixel PIXa, a transistor having a short channel length (for example, 1.0 μm or less) may be used as the transistor 42 connected to the light emitting element 44.

  The above is the description of the configuration example of each circuit.

[Configuration example 2]
When the number of pixels PIX provided in the display unit 13 of the display device 10 is large, or when the area of the display unit 13 is large, the load on the source line SL connected to the buffer amplifier circuit AMP increases. For this reason, the buffer amplifier circuit AMP is required to have a driving capability capable of promptly performing charge / discharge of the source line SL.

  Therefore, when driving the source line SL having a larger load, the buffer amplifier circuit AMP may be formed on the substrate 20. For example, the buffer amplifier circuit AMP can be configured by a transistor having a channel formed in single crystal silicon or the like constituting the substrate 20.

  FIG. 9 shows a block diagram of a display device 10 a in which the buffer amplifier circuit AMP is provided on the substrate 20.

  In the configuration shown in FIG. 9, the data signal D5 [1: n] output from the pass transistor logic circuit PTL is output to each of the n buffer amplifier circuits AMP [1: n]. The data signal D5 [1: n] is a parallel analog signal.

  Further, the n buffer amplifier circuits AMP [1: n] can supply analog signals having voltages corresponding to the gradation values to the source lines SL connected thereto.

  Such a configuration has more transmission paths (wirings, terminals, etc.) between the substrate 20 and the substrate 30 than the configuration example 1, but is high even when the load of the source line SL is large. The display device can be operated at the driving frequency.

  The above is the description of the configuration example 2.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, a transistor that can be applied to the display device described in Embodiment 1 will be described.

  One embodiment of the present invention is a transistor including a semiconductor layer in which a channel is formed, a gate insulating layer, and a gate electrode over a formation surface. The semiconductor layer preferably includes a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor).

  Here, the transistor is preferably a so-called top gate transistor in which a gate electrode is provided over a semiconductor layer with a gate insulating layer interposed therebetween. At this time, a structure in which the second gate electrode is provided on the surface to be formed side of the semiconductor layer with the second gate insulating layer interposed therebetween may be employed.

  It is preferable that the upper surface shape of the gate electrode and the gate insulating layer are approximately the same. In other words, the gate electrode and the gate insulating layer are preferably processed so that the side surfaces are continuous. For example, an insulating film to be a gate insulating layer and a conductive film to be a gate electrode can be stacked and then processed successively using the same etching mask. Alternatively, the gate insulating layer may be formed by processing the insulating film using the previously processed gate electrode as a hard mask.

  Here, when a region overlapping with the gate electrode and the gate insulating layer of the semiconductor layer is a first region and a region not overlapping with the second region is a second region, the first region functions as a channel formation region, The region 2 functions as a source region or a drain region. At this time, it is desired that the second region has a lower resistance than the first region.

  Hereinafter, more specific examples will be described with reference to the drawings.

[Configuration example 1]
FIG. 10A is a top view of the transistor 100, FIG. 10B corresponds to a cross-sectional view of a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 10A, and FIG. FIG. 10A corresponds to a cross-sectional view of a cut surface along a dashed-dotted line B1-B2 in FIG. Note that in FIG. 10A, some components (such as a gate insulating layer) of the transistor 100 are omitted. The direction of the alternate long and short dash line A1-A2 may be referred to as the channel length direction, and the direction of the alternate long and short dash line B1-B2 may be referred to as the channel width direction. Further, in the top view of the transistor, in the following drawings, some components may be omitted in the same manner as in FIG.

  The transistor 100 includes an insulating layer 104, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a conductive layer 112, a metal oxide layer 117, an insulating layer 118, and the like. The semiconductor layer 108 is provided over the insulating layer 104. The insulating layer 110, the metal oxide layer 114, and the conductive layer 112 are stacked over the semiconductor layer 108 in this order. The metal oxide layer 117 is provided to cover the top surface and side surfaces of the insulating layer 104 and the semiconductor layer 108, the side surface of the insulating layer 110, the side surface of the metal oxide layer 114, and the top surface and side surfaces of the conductive layer 112. The insulating layer 118 is provided so as to cover the metal oxide layer 117.

  Part of the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top gate transistor in which a gate electrode is provided over the semiconductor layer 108.

  The semiconductor layer 108 preferably contains a metal oxide. The semiconductor layer 108 includes a region 108i that is in contact with the insulating layer 110 and a pair of regions 108n that sandwich the region 108i.

  A region 108 i of the semiconductor layer 108 that overlaps with the conductive layer 112 functions as a channel formation region of the transistor 100. On the other hand, the pair of regions 108 n provided with the region 108 i interposed therebetween functions as a source region or a drain region of the transistor 100.

  The region 108n is a part of the semiconductor layer 108 and has a lower resistance than the region 108i that is a channel formation region. The region 108n is a region having a higher carrier density than the region 108i, a region having a high oxygen defect density, a region having a high nitrogen concentration, a region that is n-type, or a region having a high hydrogen concentration.

  Further, the upper surface shape of the conductive layer 112, the metal oxide layer 114, and the insulating layer 110 is substantially the same.

  Note that in this specification and the like, “the top surface shape is approximately the same” means that at least a part of the contour overlaps between the stacked layers. For example, the case where the upper layer and the lower layer are processed by the same mask pattern or a part thereof by the same mask pattern is included. However, strictly speaking, the contours do not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer.

  Here, as illustrated in FIGS. 10A and 10B, the channel length L in the transistor 100 is the width of the conductive layer 112 in the channel length direction. 10A and 10C, the channel width W in the transistor 100 is a width in the channel width direction in a portion where the conductive layer 112 of the semiconductor layer 108 overlaps.

  10A and 10B, the transistor 100 may include a conductive layer 120a and a conductive layer 120b over the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to the region 108n through the opening 141a or the opening 141b provided in the metal oxide layer 117 and the insulating layer 118, respectively.

  The insulating layer 110 functioning as a gate insulating layer preferably has a function of releasing oxygen by heating. Accordingly, oxygen can be supplied into the semiconductor layer 108 by heat treatment after the formation of the insulating layer 110. Accordingly, oxygen vacancies that can be formed in the semiconductor layer 108 can be filled; thus, a highly reliable semiconductor device can be provided.

  The metal oxide layer 114 located between the insulating layer 110 and the conductive layer 112 functions as a barrier film that prevents oxygen released from the insulating layer 110 from diffusing to the conductive layer 112 side. For the metal oxide layer 114, for example, a material that transmits at least less oxygen than the insulating layer 110 can be used.

  In this structure, since the metal oxide layer 114 having a high barrier property is provided between the conductive layer 112 and the insulating layer 110, a metal that easily absorbs oxygen such as aluminum or copper is used for the conductive layer 112. Even in this case, oxygen can be prevented from diffusing from the insulating layer 110 to the conductive layer 112. Further, even when the conductive layer 112 contains hydrogen, supply of hydrogen from the conductive layer 112 to the semiconductor layer 108 through the insulating layer 110 is suppressed. As a result, the carrier density of the region 108 i that is a channel formation region of the semiconductor layer 108 can be reduced.

  As the metal oxide layer 114, an insulating material or a conductive material can be used. In the case where the metal oxide layer 114 has an insulating property, it functions as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductivity, it functions as a part of the gate electrode.

  In particular, as the metal oxide layer 114, an insulating material having a dielectric constant higher than that of silicon oxide is preferably used. In particular, an aluminum oxide film, a hafnium oxide film, a hafnium aluminate film, or the like is preferably used.

Alternatively, a metal oxide film containing no nitrogen as a main component, such as an aluminum oxide film or a hafnium oxide film, can be used between the semiconductor layer 108 and the conductive layer 112 functioning as a gate electrode. Therefore, the metal oxide layer 114 can form a level in the film of nitrogen oxide (NO _x , x is larger than 0 and 2 or less, preferably 1 or more and 2 or less, typically NO ₂ or NO). It can be set as the structure with very little content. Thereby, a transistor having excellent electrical characteristics and reliability can be realized.

  Aluminum oxide films, hafnium oxide films, hafnium aluminate films, etc. have sufficiently high barrier properties even when they are thin (for example, about 5 nm thick), so they can be formed thin and improve productivity. Can be made. For example, the thickness of the metal oxide layer 114 can be 1 nm to 50 nm, preferably 3 nm to 30 nm. Furthermore, an aluminum oxide film, a hafnium oxide film, and a hafnium aluminate film have a feature that the dielectric constant is higher than that of a silicon oxide film or the like. As described above, since an insulating film having a high dielectric constant can be formed thin as the metal oxide layer 114, the strength of the gate electric field applied to the semiconductor layer 108 can be increased as compared with the case where a silicon oxide film or the like is used. As a result, the drive voltage can be lowered and the power consumption can be reduced.

  The metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when an aluminum oxide film is formed using a sputtering apparatus, oxygen can be preferably added to the semiconductor layer 108 by being formed in an atmosphere containing oxygen gas. In addition, when an aluminum oxide film is formed using a sputtering apparatus, the film density can be increased, which is preferable.

  In the case where a conductive material is used for the metal oxide layer 114, an oxide conductive material such as indium oxide or indium tin oxide can be used. Alternatively, a metal oxide that can be used for the semiconductor layer 108 may be used. In particular, a material containing the same element as the semiconductor layer 108 is preferably used. At this time, for example, it is preferable to form by a sputtering method using the same metal oxide target as the semiconductor layer 108 because a film formation apparatus can be shared.

  In addition, it is preferable that the metal oxide layer 114 hardly diffuses water or hydrogen. Thus, even when the conductive layer 112 uses a material that easily diffuses water or hydrogen, it is possible to prevent water and hydrogen from diffusing into the insulating layer 110 and the semiconductor layer 108. In particular, an aluminum oxide film or a hafnium oxide film is preferable because of its high barrier property against water and hydrogen.

  The metal oxide layer 117 is preferably formed using a material that does not easily transmit oxygen. Thus, oxygen can be prevented from being released from the semiconductor layer 108, the insulating layer 110, and the like due to heat applied during the process and diffused to the insulating layer 118 side. Therefore, an increase in carrier density in the region 108i functioning as a channel formation region can be prevented, and a highly reliable transistor can be realized.

  As the metal oxide layer 117, a film similar to the metal oxide layer 114 can be used. By providing the metal oxide layer 117 and the metal oxide layer 114, the carrier density of the region 108i functioning as a channel formation region of the semiconductor layer 108 can be more effectively reduced.

  Here, the semiconductor layer 108 and oxygen vacancies that can be formed in the semiconductor layer 108 are described.

  Oxygen deficiency formed in the semiconductor layer 108 is a problem because it affects transistor characteristics. For example, when an oxygen vacancy is formed in the semiconductor layer 108, hydrogen is bonded to the oxygen vacancy and can serve as a carrier supply source. When a carrier supply source is generated in the semiconductor layer 108, a change in electrical characteristics of the transistor 100, typically, a threshold voltage shift occurs. Therefore, it is preferable that the semiconductor layer 108 has fewer oxygen vacancies.

  Therefore, in one embodiment of the present invention, the insulating film in the vicinity of the semiconductor layer 108, specifically, the insulating layer 110 formed over the semiconductor layer 108 includes oxygen that can be released by heating. By transferring oxygen from the insulating layer 110 to the semiconductor layer 108, oxygen vacancies in the semiconductor layer 108 can be reduced.

  Note that the insulating layer 104 located below the semiconductor layer 108 may contain oxygen that can be released by heating. At this time, oxygen vacancies in the semiconductor layer 108 can be further reduced by transferring oxygen also from the insulating layer 104 to the semiconductor layer 108.

  The semiconductor layer 108 preferably contains a metal oxide. For example, the semiconductor layer 108 includes In and M (M is gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, One or more selected from hafnium, tantalum, tungsten, or magnesium) and Zn are preferable. In particular, M is preferably Al, Ga, Y, or Sn.

  In particular, the semiconductor layer 108 is preferably formed using an oxide containing In, Ga, and Zn.

  The semiconductor layer 108 preferably has a region where the atomic ratio of In is larger than the atomic ratio of M. As the In atomic ratio increases, the field-effect mobility of the transistor can be improved.

  Here, in the case of a metal oxide containing In, Ga, and Zn, since the bonding force between In and oxygen is weaker than the bonding force between Ga and oxygen, when the atomic ratio of In is large, the metal oxide film Oxygen vacancies are easily formed inside. Further, even when the metal element represented by M is used instead of Ga, there is a similar tendency. When many oxygen vacancies exist in the metal oxide film, the electrical characteristics and reliability of the transistor are deteriorated.

  However, in one embodiment of the present invention, a very large amount of oxygen can be supplied into the semiconductor layer 108 containing a metal oxide; thus, a metal oxide material having a large atomic ratio of In can be used. Thus, a transistor having extremely high field effect mobility, stable electrical characteristics, and high reliability can be realized.

  For example, a metal oxide in which the atomic ratio of In is 1.5 times or more, or 2 times or more, or 3 times or more, or 3.5 times or more, or 4 times or more of the atomic ratio of M Can be preferably used.

  In particular, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 is preferably In: M: Zn = 5: 1: 6 or the vicinity thereof. Here, in the vicinity, when In is 5, M is 0.5 or more and 1.5 or less, and Zn is 5 or more and 7 or less.

  Note that the semiconductor layer 108 is not limited to the above composition. For example, the ratio of the number of In, M, and Zn atoms in the semiconductor layer 108 is preferably In: M: Zn = 4: 2: 3 or the vicinity thereof.

  Further, as the composition of the semiconductor layer 108, the ratio of the number of atoms of In, M, and Zn in the semiconductor layer 108 may be approximately equal. That is, the ratio of the number of atoms of In, M, and Zn may include In: M: Zn = 1: 1: 1 or a material in the vicinity thereof.

When the semiconductor layer 108 has a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility of the transistor 100 can be increased. Specifically, the field effect mobility of the transistor 100 exceeds 10 cm ² / V _s , and more preferably, the field effect mobility of the transistor 100 can exceed 30 cm ² / V _s .

  For example, a display device with a narrow frame width (also referred to as a narrow frame) can be provided by using the above transistor with high field-effect mobility for a gate driver that generates a gate signal. In addition, a transistor having high field effect mobility may be a source driver that supplies a signal from a signal line included in a display device (in particular, a demultiplexer connected to an output terminal of a shift register included in the source driver), or When used in part, a display device with a small number of wirings connected to the display device can be provided.

  Note that even when the semiconductor layer 108 has a region where the atomic ratio of In is larger than the atomic ratio of M, the field-effect mobility may be low when the semiconductor layer 108 has high crystallinity.

  The crystallinity of the semiconductor layer 108 can be analyzed by, for example, analyzing using X-ray diffraction (XRD: X-Ray Diffraction), or analyzing using a transmission electron microscope (TEM: Transmission Electron Microscope). .

  Here, impurities such as hydrogen or moisture mixed in the semiconductor layer 108 are problematic because they affect the transistor characteristics. Therefore, it is preferable that the semiconductor layer 108 have fewer impurities such as hydrogen or moisture.

As the semiconductor layer 108, a metal oxide film with a low impurity concentration and a low density of defect states is preferably used because a transistor having excellent electrical characteristics can be manufactured. Here, low impurity concentration and low defect level density (low oxygen deficiency) are referred to as high purity intrinsic or substantially high purity intrinsic. A metal oxide film that is highly purified intrinsic or substantially highly purified intrinsic has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the metal oxide film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has an extremely small off-state current, a channel width of 1 × 10 ⁶ μm, and a channel length of 10 μm. When the voltage between the electrodes (drain voltage) is in the range of 1V to 10V, the off-state current can be less than the measurement limit of the semiconductor parameter analyzer, that is, 1 × 10 ⁻¹³ A or less.

  Further, the semiconductor layer 108 may have a stacked structure of two or more layers.

  For example, the semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used.

  For example, when an In—Ga—Zn oxide is used, the ratio of the number of atoms of In, M, and Zn is In: M: Zn = 5: 1: 6, In: M: Zn = 4: 2: 3. In: M: Zn = 1: 1: 1, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 2, or a film formed with a sputtering target in the vicinity thereof Of these, it is preferable to use two or more layers.

  Alternatively, the semiconductor layer 108 in which two or more metal oxide films having different crystallinity are stacked can be used.

  For example, in the case where the semiconductor layer 108 is formed by stacking two metal oxide films with different crystallinity, the same oxide target is used and the film formation conditions are different, so that the semiconductor layer 108 is continuously formed without being exposed to the atmosphere. Is preferred.

  For example, the oxygen flow rate ratio at the time of forming the first metal oxide film formed first is made smaller than the oxygen flow rate ratio at the time of forming the second metal oxide film formed later. Alternatively, oxygen is not allowed to flow when the first metal oxide film is formed. Thereby, oxygen can be effectively supplied when forming the second metal oxide film. In addition, the first metal oxide film can be a film having lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, the second metal oxide film provided on the top is a film having higher crystallinity than the first metal oxide film, so that damage during the processing of the semiconductor layer 108 or the film formation of the insulating layer 110 is caused. Can be suppressed. For example, a CAC-OS film can be used for the first metal oxide film, and a CAAC-OS film can be used for the second metal oxide film.

  More specifically, the oxygen flow rate ratio during the formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less. Specifically, it is 10%. The oxygen flow rate ratio during the formation of the second metal oxide film is 50% to 100%, preferably 60% to 100%, more preferably 80% to 100%, and still more preferably 90% or more. 100% or less, typically 100%. In addition, the first metal oxide film and the second metal oxide film may have different conditions such as pressure, temperature, and power at the time of film formation, but the conditions other than the oxygen flow rate ratio are the same. This is preferable because the time required for the film forming process can be shortened.

  When the semiconductor layer 108 has such a stacked structure, a transistor with excellent electrical characteristics and high reliability can be realized.

  The above is the description of the configuration example 1.

  Hereinafter, a configuration example of a transistor having a part of the configuration different from the configuration example 1 will be described. In addition, below, description may be abbreviate | omitted about the part which overlaps with the said structural example 1. FIG. Moreover, in the drawings shown below, portions having the same functions as those of the above configuration example 1 have the same hatching pattern and may not be denoted by reference numerals.

[Configuration example 2]
11A is a top view of the transistor 100A, FIG. 11B is a cross-sectional view in the channel length direction of the transistor 100A, and FIG. 11C is a cross-sectional view in the channel width direction of the transistor 100A. .

  The transistor 100A is mainly different from the configuration example 1 in that the conductive layer 106 is provided between the substrate 102 and the insulating layer 104. The conductive layer 106 has a portion overlapping with the semiconductor layer 108 with the insulating layer 104 interposed therebetween.

  In the transistor 100A, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the conductive layer 112 functions as a second gate electrode (also referred to as a top gate electrode). . A part of the insulating layer 104 functions as a first gate insulating layer, and a part of the insulating layer 110 functions as a second gate insulating layer.

  A portion of the semiconductor layer 108 that overlaps with at least one of the conductive layer 112 and the conductive layer 106 functions as a channel formation region. Note that a portion overlapping with the conductive layer 112 of the semiconductor layer 108 (a portion corresponding to the region 108 i) is sometimes referred to as a channel formation region in the following description for ease of explanation. In addition, a channel can be formed in a portion overlapping with the conductive layer 106 (a portion corresponding to the region 108n).

  Here, as illustrated in FIGS. 11A and 11B, the channel length L in the transistor 100 </ b> A is the width in the channel length direction of the conductive layer 112 located above the semiconductor layer 108. 11A and 11C, the channel width W in the transistor 100A is a width in a channel width direction in a portion where the conductive layer 112 of the semiconductor layer 108 overlaps.

  In addition, as illustrated in FIG. 11C, the conductive layer 106 may be electrically connected to the conductive layer 112 through an opening 142 provided in the insulating layer 104 and the insulating layer 110. Accordingly, the same potential can be applied to the conductive layer 106 and the conductive layer 112.

  The conductive layer 106 can be formed using a material similar to that of the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, the conductive layer 106 is preferably formed using a material containing copper because resistance can be reduced.

  11A and 11C, it is preferable that the conductive layer 112 and the conductive layer 106 protrude outward from the end portion of the semiconductor layer 108 in the channel width direction. At this time, as illustrated in FIG. 11C, the entire semiconductor layer 108 in the channel width direction is covered with the conductive layer 112 and the conductive layer 106 with the insulating layer 110 and the insulating layer 104 interposed therebetween.

  With such a structure, the semiconductor layer 108 can be electrically surrounded by an electric field generated by the pair of gate electrodes. At this time, it is particularly preferable to apply the same potential to the conductive layer 106 and the conductive layer 112. Accordingly, an electric field for inducing a channel can be effectively applied to the semiconductor layer 108, so that the on-state current of the transistor 100A can be increased. Therefore, the transistor 100A can be miniaturized.

  Note that the conductive layer 112 and the conductive layer 106 may not be connected to each other. At this time, a constant potential may be supplied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be supplied to the other. At this time, the threshold voltage when the transistor 100A is driven by the other electrode can be controlled by the potential applied to the one electrode.

  The above is the description of the configuration example 2.

  In the transistor illustrated in Structural Example 1 and Structural Example 2, the metal oxide layer 117 and the insulating layer 118 are provided between the gate electrode located above the semiconductor layer 108 and the source and drain electrodes. Compared to a bottom-gate transistor, the parasitic capacitance between them is reduced. In particular, the insulating layer 118 has little influence on the electrical characteristics of the transistor even when the thickness is increased, and thus parasitic capacitance can be further reduced. Therefore, the transistor exemplified in Structure Example 1 and Structure Example 2 can be easily driven at a high frequency, and thus can be preferably used for a display portion of a display device or a driver circuit portion.

  Further, when the transistor exemplified in Structural Example 1 and Structural Example 2 is applied to a driver circuit, the channel length L can be formed extremely small. More specifically, the channel length L is less than 1.5 μm, preferably 1.2 μm or less, more preferably 1.0 μm or less, further preferably 0.9 μm or less, more preferably 0.8 μm or less, and further preferably It is preferably 0.6 μm or less and preferably 0.1 μm or more. As a result, the value of current that can be passed through the transistor increases and high-speed operation is possible, so that the transistor can be used favorably.

  On the other hand, in the case where the transistor exemplified in Structure Example 1 and Structure Example 2 is applied to a pixel, the channel length L can be formed larger than that of the transistor provided in the driver circuit. More specifically, the channel length L is 1 μm or more, preferably 1.2 μm or more, more preferably 1.4 μm or more, and is 20 μm or less, preferably 15 μm or less, more preferably 10 μm or less.

  Note that the channel length L of the transistor is not necessarily within the above range, and can be set according to the transistor characteristics required in the driver circuit and the display portion. For example, one or more of the plurality of transistors applied to the driver circuit may have a channel length L longer than that of the transistor provided in the pixel. One or more of the transistors provided in the pixel may have a channel length L shorter than that of the transistor applied to the driver circuit.

[Application example]
Hereinafter, a configuration example in which a low-resistance metal oxide layer formed on the same surface as the semiconductor layer 108 in the above configuration example is applied to one electrode of a capacitor will be described.

[Application 1]
FIG. 12A is a cross-sectional view of the transistor 100 illustrated in Structural Example 1 and a capacitor 130A that can be formed in the same process.

  The capacitor 130A includes a metal oxide layer 108C that functions as one electrode, a conductive layer 120b that functions as the other electrode, and a part of the metal oxide layer 117 that functions as a dielectric, located between these layers. And part of the insulating layer 118.

  The metal oxide layer 108 </ b> C is a layer formed by processing the same metal oxide film as the semiconductor layer 108. Further, the metal oxide layer 108 </ b> C is a layer whose resistance is reduced as in the region 108 n of the semiconductor layer 108.

  FIG. 12A illustrates an example in which an insulating layer 119 is provided so as to cover the conductive layer 120a, the conductive layer 120b, and the insulating layer 118, and the conductive layer 109 is provided over the insulating layer 119.

  The conductive layer 109 is a layer that can be used as one electrode (pixel electrode) of the display element. A material that reflects visible light, a material that transmits visible light, or the like can be used for the conductive layer 109 depending on the structure of the display element.

  The conductive layer 109 is electrically connected to the conductive layer 120b through an opening provided in the insulating layer 119.

  The insulating layer 119 functions as a planarization film. Accordingly, the flatness of the formation surface of the conductive layer 109 functioning as a pixel electrode can be improved, so that the optical characteristics of the display element can be improved.

[Application 2]
FIG. 12B is a cross-sectional view of the transistor 100A exemplified in Structural Example 2 and a capacitor 130B that can be formed in the same process.

  The capacitor 130B includes a metal oxide layer 108C that functions as one electrode, a conductive layer 106C that functions as the other electrode, and a portion of the insulating layer 104 that functions as a dielectric. The

  The conductive layer 106C is a layer formed by processing the same conductive film as the conductive layer 106 functioning as the first gate electrode of the transistor 100A.

  The conductive layer 120b is electrically connected to the metal oxide layer 108C through an opening provided in the insulating layer 118 and the metal oxide layer 117. Accordingly, one of the source and the drain of the transistor 100A and the capacitor 130B are electrically connected.

[Application Example 3]
FIG. 12C is a cross-sectional view of the transistor 100A illustrated in Structural Example 2 and a capacitor 130C that can be formed in the same process.

  The capacitor 130C includes a part of the region 108n of the semiconductor layer 108 that functions as one electrode, the conductive layer 106C that functions as the other electrode, and the insulating layer 104 that functions as a dielectric and is positioned between the conductive layer 106C. Consists of part.

  The structure illustrated in FIG. 12C can also be referred to as a structure in which the region 108n of the semiconductor layer 108 and the metal oxide layer included in one electrode of the capacitor 130C are seamlessly continuous.

  Part of the semiconductor layer 108 (specifically, the region 108n) of the transistor 108A extends to a region overlapping with the conductive layer 106C, and forms one electrode of the capacitor 130C. Accordingly, the transistor 108A and the capacitor 130C are electrically connected.

  Note that FIG. 12C illustrates an example in which the conductive layer 109 is electrically connected to the region 108n through the conductive layer 120b; however, the conductive layer 109 and the region 108n are not provided without the conductive layer 120b. It is good also as a structure which touches directly.

  The above is the description of the application example.

[Components of semiconductor devices]
Next, components included in the semiconductor device of the present embodiment will be described in detail.

〔substrate〕
There is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element is provided over these substrates. A substrate may be used as the substrate 102. When a glass substrate is used as the substrate 102, the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), the tenth generation. A large display device can be manufactured by using a large-sized substrate such as a generation (2950 mm × 3400 mm), or a 10.5th generation, an 11th generation, or a 12th generation.

  Alternatively, a flexible substrate may be used as the substrate 102, and the transistor 100 or the like may be formed directly over the flexible substrate. Alternatively, a separation layer may be provided between the substrate 102 and the transistor 100 or the like. The separation layer can be used for separation from the substrate 102 and transfer to another substrate after the semiconductor device is partially or entirely completed thereon. At that time, the transistor 100 or the like can be transferred to a substrate having poor heat resistance or a flexible substrate.

[Insulating layer 104]
The insulating layer 104 can be formed using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like as appropriate. As the insulating layer 104, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a stacked layer. Note that in order to improve interface characteristics with the semiconductor layer 108, at least a region in contact with the semiconductor layer 108 in the insulating layer 104 is preferably formed using an oxide insulating film. Further, by using an oxide insulating film from which oxygen is released by heating as the insulating layer 104, oxygen contained in the insulating layer 104 can be transferred to the semiconductor layer 108 by heat treatment.

  The thickness of the insulating layer 104 can be greater than or equal to 50 nm, or greater than or equal to 100 nm and less than or equal to 3000 nm, or greater than or equal to 200 nm and less than or equal to 1000 nm. By increasing the thickness of the insulating layer 104, the amount of oxygen released from the insulating layer 104 can be increased, and interface states at the interface between the insulating layer 104 and the semiconductor layer 108 and oxygen vacancies included in the semiconductor layer 108 can be reduced. Is possible.

  As the insulating layer 104, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide can be used, and the insulating layer 104 can be provided as a single layer or a stacked layer. In this embodiment, a stacked structure of a silicon nitride film and a silicon oxynitride film is used as the insulating layer 104. In this manner, oxygen can be efficiently introduced into the semiconductor layer 108 by using the insulating layer 104 as a stacked structure and using a silicon nitride film on the lower layer side and a silicon oxynitride film on the upper layer side.

  Alternatively, a film other than an oxide film such as a silicon nitride film can be used on the side in contact with the semiconductor layer 108 of the insulating layer 104. At this time, it is preferable to perform pretreatment such as oxygen plasma treatment on the surface of the insulating layer 104 in contact with the semiconductor layer 108 to oxidize the surface of the insulating layer 104 or the vicinity thereof.

[Conductive film]
As the conductive layer 112 and the conductive layer 106 functioning as a gate electrode, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode, chromium (Cr), copper (Cu), aluminum (Al), gold ( Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt ( Co), an alloy containing the above-described metal element as a component, an alloy combining the above-described metal elements, or the like can be used.

  The conductive layer 112 and the conductive layer 106 functioning as gate electrodes, the conductive layer 120a functioning as a source electrode, and the conductive layer 120b functioning as a drain electrode include an oxide containing indium and tin (In-Sn oxide). , Oxide containing indium and tungsten (In-W oxide), oxide containing indium, tungsten and zinc (In-W-Zn oxide), oxide containing indium and titanium (In-Ti oxidation) ), An oxide containing indium, titanium and tin (In-Ti-Sn oxide), an oxide containing indium and zinc (In-Zn oxide), an oxide containing indium, tin and silicon ( In-Sn-Si oxide), oxide conductors such as oxide containing indium, gallium, and zinc (In-Ga-Zn oxide) or gold It is also possible to apply the oxide film.

  Here, the oxide conductor will be described. In this specification and the like, the oxide conductor may be referred to as OC (Oxide Conductor). As an oxide conductor, for example, when an oxygen vacancy is formed in a metal oxide and hydrogen is added to the oxygen vacancy, a donor level is formed in the vicinity of the conduction band. As a result, the metal oxide becomes highly conductive and becomes a conductor. The conductive metal oxide can be referred to as an oxide conductor. In general, a metal oxide has a large energy gap and thus has a light-transmitting property with respect to visible light. On the other hand, an oxide conductor is a metal oxide having a donor level near the conduction band. Therefore, the oxide conductor is less affected by the absorption due to the donor level and has a light-transmitting property similar to that of the metal oxide with respect to visible light.

  Alternatively, the conductive layer 112 may have a stacked structure of a conductive film including the oxide conductor (metal oxide) and a conductive film including a metal or an alloy. By using a conductive film containing a metal or an alloy, wiring resistance can be reduced. At this time, a conductive film including an oxide conductor is preferably applied to a side in contact with the insulating layer functioning as a gate insulating film.

  Further, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) is applied to the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. Also good. By using a Cu-X alloy film, it can be processed by a wet etching process, and thus manufacturing costs can be suppressed.

  In addition, the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b each include any one or more selected from titanium, tungsten, tantalum, and molybdenum among the above metal elements. Is preferred. In particular, a tantalum nitride film is preferably used as the conductive layer 112, the conductive layer 106, the conductive layer 120a, and the conductive layer 120b. The tantalum nitride film has conductivity and high barrier properties against copper or hydrogen. Further, since the tantalum nitride film emits less hydrogen from itself, it can be preferably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[Insulating layer 110]
As the insulating layer 110 functioning as a gate insulating film of the transistor 100 or the like, a silicon oxide film, a silicon oxynitride film, a oxynitride film, or the like is formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like. Includes one or more of silicon film, silicon nitride film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film and neodymium oxide film An insulating layer can be used. Note that the insulating layer 110 may have a two-layer structure or a three-layer structure.

  The insulating layer 110 in contact with the semiconductor layer 108 functioning as a channel region of the transistor 100 or the like is preferably an oxide insulating film, and a region containing oxygen in excess of the stoichiometric composition (excess oxygen region). It is more preferable to have. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. In order to provide an excess oxygen region in the insulating layer 110, for example, the insulating layer 110 may be formed in an oxygen atmosphere, or the insulating layer 110 after film formation may be heat-treated in an oxygen atmosphere.

  Further, when hafnium oxide is used as the insulating layer 110, the following effects are obtained. Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, since the thickness of the insulating layer 110 can be increased as compared with the case where silicon oxide is used, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

The insulating layer 110 preferably has few defects. Typically, it is preferable that the number of signals observed by an electron spin resonance (ESR) method is small. For example, the signal described above includes the E ′ center where the g value is observed at 2.001. The E ′ center is caused by silicon dangling bonds. As the insulating layer 110, a silicon oxide film or a silicon oxynitride film whose spin density due to the E ′ center is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less is used. Good.

[Semiconductor layer]
In the case where the semiconductor layer 108 is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide preferably satisfies In> M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 4.1, In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8, In: M: Zn = 6: 1: 6, In: M: Zn = 5: 2: 5, and the like.

  In the case where the semiconductor layer 108 is an In-M-Zn oxide, a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target including a polycrystalline In—M—Zn oxide, the semiconductor layer 108 having crystallinity can be easily formed. Note that the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element included in the sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In: Ga: Zn = 4: 2: 4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed is In: Ga: Zn = It may be in the vicinity of 4: 2: 3 [atomic ratio].

  The semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.

  The semiconductor layer 108 preferably has a non-single crystal structure. The non-single-crystal structure includes, for example, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

  The above is the description of the components of the semiconductor device.

[Example of production method]
Hereinafter, a method for manufacturing a transistor and a capacitor of one embodiment of the present invention is described. Here, the transistor 100A and the capacitor 130B illustrated in FIG. 12B are described as examples.

  Note that a thin film (an insulating film, a semiconductor film, a conductive film, or the like) included in the semiconductor device can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, or pulse laser deposition (PLD). ) Method, atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma enhanced chemical vapor deposition (PECVD) method and a thermal CVD method. As one of thermal CVD methods, there is a metal organic chemical vapor deposition (MOCVD) method.

  Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices are spin coat, dip, spray coating, ink jet, dispense, screen printing, offset printing, doctor knife, slit coat, roll coat, curtain coat. It can be formed by a method such as knife coating.

  Further, when a thin film included in the semiconductor device is processed, the thin film can be processed using a photolithography method or the like. In addition, the thin film may be processed by a nanoimprint method, a sand blast method, a lift-off method, or the like. Further, the island-shaped thin film may be directly formed by a film forming method using a shielding mask such as a metal mask.

  As a photolithography method, there are typically the following two methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which a thin film having photosensitivity is formed and then exposed and developed to process the thin film into a desired shape.

  In photolithography, light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

  For etching the thin film, a dry etching method, a wet etching method, a sand blasting method, or the like can be used.

  13 to 15 are cross-sectional views in the channel length direction for describing a method for manufacturing the transistor 100A and the capacitor 130B.

[Formation of Conductive Layer 106 and Conductive Layer 106C]
A conductive film is formed over the substrate 102 and processed by etching, so that the conductive layer 106 functioning as a gate electrode and the conductive layer 106C functioning as one electrode of the capacitor are formed at the same time (FIG. 13A). ).

[Formation of Insulating Layer 104]
Next, the insulating layer 104 is formed so as to cover the substrate 102, the conductive layer 106, and the conductive layer 106C (FIG. 13B). The insulating layer 104 can be formed by a plasma CVD method, an ALD method, a sputtering method, or the like.

[Formation of Semiconductor Layer 108 and Metal Oxide Layer 108C]
Subsequently, a metal oxide film 108f is formed over the insulating layer 104 (FIG. 13C).

  The metal oxide film 108f is preferably formed by a sputtering method using a metal oxide target.

  In forming the metal oxide film 108f, an inert gas (eg, helium gas, argon gas, xenon gas, or the like) may be mixed in addition to the oxygen gas. Note that the ratio of oxygen gas to the entire deposition gas when forming the metal oxide film (hereinafter also referred to as oxygen flow ratio) is 0% to 100%, preferably 5% to 20%. It is preferable to do. A transistor with an increased on-state current can be obtained by reducing the oxygen flow rate ratio and forming the metal oxide film 108f with relatively low crystallinity.

  The metal oxide film 108f may be formed at a substrate temperature of room temperature to 180 ° C., preferably the substrate temperature of room temperature to 140 ° C. It is preferable that the substrate temperature at the time of forming the metal oxide film 108f be, for example, room temperature or higher and lower than 140 ° C. because productivity is increased. In addition, when the metal oxide film 108f is formed with the substrate temperature set to room temperature or without intentional heating, the metal oxide film 108f with low crystallinity can be easily formed.

  The thickness of the metal oxide film 108f may be 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 60 nm.

  Note that when a large glass substrate (for example, the sixth generation to the twelfth generation) is used as the substrate 102, the substrate temperature when the metal oxide film 108f is formed is 200 ° C. or higher and 300 ° C. or lower. 102 may be deformed (distorted or warped). Therefore, in the case of using a large glass substrate, deformation of the glass substrate can be suppressed by setting the substrate temperature at the time of forming the metal oxide film 108f to a room temperature or higher and lower than 200 ° C.

  In addition, it is necessary to increase the purity of the sputtering gas. For example, oxygen gas or argon gas used as a sputtering gas is a gas having a dew point of −40 ° C. or lower, preferably −80 ° C. or lower, more preferably −100 ° C. or lower, more preferably −120 ° C. or lower. By using it, moisture and the like can be prevented from being taken into the metal oxide film 108f as much as possible.

In the case where the metal oxide film 108f is formed by a sputtering method, the chamber in the sputtering apparatus is provided with an adsorption-type vacuum exhaust pump such as a cryopump so as to remove water or the like that is an impurity for the metal oxide as much as possible. It is preferable to use and exhaust to a high vacuum (from about 5 × 10 ⁻⁷ Pa to about 1 × 10 ⁻⁴ Pa). In particular, the partial pressure of gas molecules corresponding to H ₂ O in the chamber (gas molecules corresponding to m / z = 18) in the standby state of the sputtering apparatus is 1 × 10 ⁻⁴ Pa or less, preferably 5 × 10 ^−5. It is preferable to set it to Pa or less.

  Further, before the metal oxide film 108f is formed, heat treatment for desorbing water or hydrogen adsorbed on the surface of the insulating layer 104 is preferably performed. For example, the heat treatment can be performed at a temperature of 70 ° C. or higher and 200 ° C. or lower in a reduced pressure atmosphere. At this time, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 104 to the atmosphere. For example, the film formation apparatus preferably has a structure in which a heating chamber for heating the substrate and a film formation chamber for forming the metal oxide film 108f are connected to each other through a gate valve or the like.

  Subsequently, the metal oxide film 108f is processed to form the island-shaped semiconductor layer 108 and the metal oxide layer 108C at the same time (FIG. 13D).

  Either or both of a wet etching method and a dry etching method may be used for processing the metal oxide film 108f.

  Alternatively, after the metal oxide film 108f is formed or processed into the semiconductor layer 108, heat treatment may be performed to dehydrogenate or dehydrate the metal oxide film 108f or the semiconductor layer 108. The temperature of the heat treatment is typically 150 ° C. or higher and lower than the strain point of the substrate, 250 ° C. or higher and 450 ° C. or lower, or 300 ° C. or higher and 450 ° C. or lower.

  The heat treatment can be performed in an inert atmosphere containing nitrogen, a rare gas such as helium, neon, argon, xenon, or krypton. Alternatively, after heating in an inert atmosphere, heating may be performed in an oxygen atmosphere. Note that it is preferable that the inert atmosphere and the oxygen atmosphere do not contain hydrogen, water, or the like. The treatment time may be 3 minutes or more and 24 hours or less.

  For the heat treatment, an electric furnace, an RTA apparatus, or the like can be used. By using the RTA apparatus, heat treatment can be performed at a temperature equal to or higher than the strain point of the substrate for a short time. Therefore, the heat treatment time can be shortened.

The metal oxide film 108f is formed while being heated, or after the metal oxide film 108f is formed, heat treatment is performed, whereby the hydrogen concentration in the metal oxide film 108f obtained by SIMS is set to 5 × 10 ¹⁹ atoms. / Cm ³ or less, or 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less, or 5 × 10 ¹⁷ atoms / cm ³ or less, or 1 × 10 ¹⁶ atoms / cm ³ or less.

[Formation of Insulating Film 110f]
Subsequently, an insulating film 110 f to be the insulating layer 110 is formed over the semiconductor layer 108, the metal oxide layer 108 </ b> C, and the insulating layer 104.

  As the insulating film 110f, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma chemical vapor deposition apparatus (a PECVD apparatus or simply a plasma CVD apparatus). In this case, it is preferable to use a deposition gas and an oxidation gas containing silicon as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide.

  In addition, as the insulating film 110f, PECVD is performed such that the flow rate of the oxidizing gas with respect to the flow rate of the deposition gas is greater than 20 times and less than 100 times, or 40 times or more and 80 times or less, and the pressure in the processing chamber is less than 100 Pa or 50 Pa or less. By using the apparatus, a silicon oxynitride film with a small amount of defects can be formed.

  In addition, as the insulating film 110f, the substrate placed in the processing chamber evacuated in the PECVD apparatus is held at 280 ° C. or higher and 350 ° C. or lower, and a source gas is introduced into the processing chamber so that the pressure in the processing chamber is 20 Pa or higher and 250 Pa. Hereinafter, a dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 110f under the condition where the pressure is higher than or equal to 100 Pa and lower than or equal to 250 Pa and high-frequency power is supplied to the electrode provided in the processing chamber.

  Alternatively, the insulating film 110f may be formed using a PECVD method using microwaves. Microwave refers to the frequency range from 300 MHz to 300 GHz. Microwaves have a low electron temperature and a low electron energy. In addition, in the supplied power, the ratio used for accelerating electrons is small, it can be used for dissociation and ionization of more molecules, and high density plasma (high density plasma) can be excited. . Therefore, the insulating film 110f with less plasma damage and less defects on the deposition surface and the deposit can be formed.

[Formation of Metal Oxide Film 114f]
Subsequently, a metal oxide film 114f to be the metal oxide layer 114 is formed over the insulating film 110f.

  The metal oxide film 114f is preferably formed, for example, in an atmosphere containing oxygen. In particular, it is preferably formed by a sputtering method in an atmosphere containing oxygen. Accordingly, oxygen can be supplied to the insulating film 110f when the metal oxide film 114f is formed.

  For example, as a film formation condition of the metal oxide film 114f, it is preferable to form the metal oxide film by a reactive sputtering method using oxygen as a film formation gas and using a metal target. When aluminum is used as the metal target, for example, an aluminum oxide film can be formed.

  When the metal oxide film 114f is formed, the higher the ratio (oxygen flow ratio) of the oxygen flow rate to the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus or the higher the oxygen partial pressure in the film formation chamber, the higher The oxygen supplied into the film 110f can be increased. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% to 100%, preferably 65% to 100%, more preferably 80% to 100%, and still more preferably 90% to 100%. In particular, it is preferable that the oxygen flow rate ratio is 100% and the oxygen partial pressure is as close as possible to 100%.

  In this manner, by forming the metal oxide film 114f by a sputtering method in an atmosphere containing oxygen, oxygen is supplied to the insulating film 110f when the metal oxide film 114f is formed, and oxygen is supplied from the insulating film 110f. Desorption can be prevented. As a result, a very large amount of oxygen can be confined in the insulating film 110f. A large amount of oxygen can be supplied to the semiconductor layer 108 by heat treatment performed later. As a result, oxygen vacancies in the semiconductor layer 108 can be reduced and a highly reliable transistor can be realized.

  Further, after the metal oxide film 114f is formed, an opening reaching the conductive layer 106 is formed by etching part of the metal oxide film 114f, the insulating film 110f, and the insulating layer 104. Accordingly, the conductive layer 112 and the conductive layer 106 to be formed later can be electrically connected through the opening.

[Formation of Conductive Film 112f]
Subsequently, a conductive film 112f to be the conductive layer 112 is formed over the metal oxide film 114f (FIG. 13E).

  The conductive film 112f is preferably formed by a sputtering method using a metal or alloy sputtering target.

[Etching of Conductive Film 112f, Metal Oxide Film 114f, and Insulating Film 110f]
Subsequently, part of the conductive film 112f, the metal oxide film 114f, and the insulating film 110f is etched to expose part of the semiconductor layer 108 and the metal oxide layer 108C (FIG. 13F).

  Here, the conductive film 112f, the metal oxide film 114f, and the insulating film 110f are each preferably processed using the same resist mask. Alternatively, the metal oxide layer 114 and the insulating layer 110 may be etched using the etched conductive layer 112 as a hard mask.

  Accordingly, the island-shaped conductive layer 112, the metal oxide layer 114, and the insulating layer 110 whose upper surface shapes are approximately the same can be formed.

  Note that when the conductive film 112f, the metal oxide film 114f, and the insulating film 110f are etched, part of the semiconductor layer 108 that is not covered with the insulating layer 110 and the metal oxide layer 108C may be etched to be thinned. .

  Here, when the resist mask is formed on the conductive film 112f, the pattern width of the resist mask can be reduced more than the minimum processing dimension in an apparatus such as an exposure machine or a developing machine by adjusting the exposure time. For example, a resist pattern finer than the minimum processing dimension can be formed by using a photomask having a pattern width thinner than the minimum processing dimension and shortening the exposure time as compared with the conventional case. Alternatively, a resist pattern finer than the minimum processing dimension may be formed by using a photomask having a pattern width equal to or larger than the minimum processing dimension, for example, by making the exposure time longer than the conventional one.

  Alternatively, the resist mask formed over the conductive film 112f may be subjected to slimming treatment to reduce the width of the resist mask, and the processed conductive layer 112 may be reduced in width in the channel length direction. Alternatively, in the case where the conductive film 112f or the like is etched using a hard mask, a slimming process can be performed on the resist mask used when the hard mask is processed. As the slimming treatment, for example, after forming a resist mask, the pattern width of the resist mask is increased by plasma treatment or heat treatment in an atmosphere containing oxygen, or treatment of irradiating ultraviolet light in a state exposed to an ozone atmosphere. Can be reduced.

  By the above-described method, a resist pattern having a width smaller than the minimum processing dimension can be formed. For example, even when an apparatus having a minimum pattern width processing size of about 2.0 μm or about 1.5 μm is used, the pattern width is less than 1.5 μm, preferably less than 1.0 μm, more preferably less than 0.5 μm. It becomes possible to reduce.

[Formation of the first layer 116]
Subsequently, the first layer 116 is formed (FIG. 14A).

  Here, as the first layer 116, an insulating film or a conductive film can be formed.

  As the first layer 116, a film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium is formed. In particular, at least one of aluminum, titanium, tantalum, and tungsten is preferably included. In particular, a nitride containing at least one of these metal elements or an oxide containing at least one of these metal elements can be preferably used. As the insulating film, a nitride film such as an aluminum titanium nitride film, a titanium nitride film, or an aluminum nitride film, an oxide film such as an aluminum titanium oxide film, or the like can be preferably used.

  For example, as the first layer 116, a metal film or an alloy film containing at least one of metal elements such as aluminum, titanium, tantalum, tungsten, chromium, and ruthenium can be formed in addition to the above. In particular, at least one of aluminum, titanium, tantalum, and tungsten is preferably included.

  Here, the first layer 116 is preferably formed by a sputtering method using nitrogen gas or oxygen gas as a deposition gas. Thereby, even when the same sputtering target is used, the film quality can be easily controlled by controlling the flow rate of the film forming gas.

[Heat treatment]
Subsequently, heat treatment is performed (FIG. 14B). By the heat treatment, the resistance of the region in contact with the first layer 116 of the semiconductor layer 108 is reduced, and the low resistance region 108 n is formed in the semiconductor layer 108. At the same time, the resistance of the metal oxide layer 108C can be reduced.

  The heat treatment is preferably performed in an inert gas atmosphere such as nitrogen or a rare gas. The higher the temperature of the heat treatment, the better, but the temperature can be set in consideration of the heat resistance of the substrate 102, the conductive layer 106, the conductive layer 112, and the like. For example, the temperature can be 120 ° C. or higher and 500 ° C. or lower, preferably 150 ° C. or higher and 450 ° C. or lower, more preferably 200 ° C. or higher and 400 ° C. or lower, and even more preferably 250 ° C. or higher and 400 ° C. or lower. For example, by setting the temperature of the heat treatment to about 350 ° C., a semiconductor device can be manufactured with high yield using a production facility using a large glass substrate.

  By the heat treatment, oxygen in the semiconductor layer 108 and the metal oxide layer 108C is extracted to the first layer 116, whereby oxygen vacancies are generated. The oxygen vacancies are combined with hydrogen contained in the semiconductor layer 108 or the metal oxide layer 108C, whereby the carrier concentration is increased and the resistance of the portion in contact with the first layer 116 is reduced.

  Alternatively, the metal element contained in the first layer 116 is diffused into the semiconductor layer 108 and the metal oxide layer 108C by the heat treatment, so that part of the semiconductor layer 108 and the metal oxide layer 108C is alloyed and reduced. In some cases, it is made resistant.

  Alternatively, when nitrogen contained in the first layer 116 or nitrogen contained in the atmosphere of the heat treatment is diffused into the semiconductor layer 108 and the metal oxide layer 108C by the heat treatment, which reduces resistance. There is also.

  The region 108n of the semiconductor layer 108 and the metal oxide layer 108C, which have been reduced in resistance by such a combined action, are extremely stable and low-resistance regions. The region 108n and the metal oxide layer 108C formed in this manner have a characteristic that, for example, even if a process for supplying oxygen is performed in a later process, the resistance is not increased again.

  In particular, a film that releases hydrogen by heating is provided in contact with part of the semiconductor layer 108, and the resistance is reduced by supplying the hydrogen to part of the semiconductor layer 108, so that it is less diffusible than hydrogen. It is preferable to use a method of reducing resistance by supplying a metal element or an element such as nitrogen to part of the semiconductor layer 108. Accordingly, an increase in carrier concentration in the region 108i functioning as a channel formation region can be suppressed. As a result, good switching characteristics can be obtained even when the channel length of the transistor is extremely short. For example, good switching characteristics can be obtained even with a fine transistor with a channel length of 100 nm or less.

[Removal of the first layer 116]
Subsequently, the first layer 116 is removed by etching (FIG. 14C).

  When the first layer 116a is etched, part of the conductive layer 112, the metal oxide layer 114, the insulating layer 110, the semiconductor layer 108, the metal oxide layer 108C, and the like may be etched. In particular, when a metal film or an alloy film is used for the first layer 116, it is preferable to select an etching method using a material different from that of the conductive layer 112 and having a high selectivity of the etching rate.

  Note that in the case where an insulating material is used for the first layer 116 or a material which is insulated by the heat treatment is used, the first layer 116 may be left without being etched.

[Formation of Metal Oxide Layer 117]
Subsequently, a metal oxide layer 117 is formed over the first layer 116 (FIG. 14D). The metal oxide layer 117 can be formed by a method similar to that of the metal oxide film 114f.

  When the metal oxide layer 117 is formed, oxygen may be added to the region 108n of the semiconductor layer 108 or the metal oxide layer 108C, but the low resistance state is not increased without increasing the resistance again as described above. Kept.

  Further, oxygen can be supplied from the side surface of the insulating layer 110 functioning as a gate insulating layer through the first layer 116 when the metal oxide layer 117 is formed. In some cases, oxygen can be supplied to the insulating layer 104 through the semiconductor layer 108.

  Heat treatment may be performed after the metal oxide layer 117 is formed. By performing heat treatment in a state where the semiconductor layer 108 is covered with the metal oxide layer 117 functioning as a barrier layer, the region 108 i which is a channel formation region of the semiconductor layer 108 is preferably oxygenated from the insulating layer 110 or the insulating layer 104. And the carrier concentration can be reduced.

[Formation of Insulating Layer 118]
Subsequently, an insulating layer 118 is formed so as to cover the metal oxide layer 117 (FIG. 14E).

  The insulating layer 118 can be formed by a plasma CVD method, a sputtering method, or the like.

[Formation of Openings 141a, 141b, 141c]
Subsequently, after a mask is formed by lithography at a desired position of the insulating layer 118, the insulating layer 118 and a part of the metal oxide layer 117 are etched, whereby an opening 141a and an opening 141b reaching the region 108n are obtained. And an opening 141c reaching the metal oxide layer 108C.

[Formation of Conductive Layers 120a and 120b]
Subsequently, a conductive film is formed over the insulating layer 118 so as to cover the opening 141a, the opening 141b, and the opening 141c, and the conductive film is processed into a desired shape, whereby the conductive layer 120a and the conductive layer are formed. 120b is formed (FIG. 15A).

  Through the above steps, the electrically connected transistor 100A and the capacitor 130B can be manufactured. In the following, a process for forming a pixel electrode of the display element will be further described.

[Formation of Insulating Layer 119]
Next, an insulating layer 119 is formed so as to cover the conductive layer 120a, the conductive layer 120b, and the insulating layer 118 (FIG. 15B).

  An organic resin is preferably used for the insulating layer 119 because flatness is increased. Typically, the insulating layer 119 can be formed by a method such as spin coating, dispensing, screen printing, or slit coating.

  Note that an inorganic insulating material may be used for the insulating layer 119. In that case, the insulating layer 118 can be formed by the same method.

  In addition, by using a photosensitive resin material for the insulating layer 119, an opening reaching the conductive layer 120b can be formed at the same time as the insulating layer 119 is formed. Note that in the case where a non-photosensitive material is used for the insulating layer 119, an opening may be formed by etching using a mask.

[Formation of Conductive Layer 109]
Subsequently, a conductive layer 109 is formed (FIG. 15C). The conductive layer 109 can be formed by a method similar to that of the conductive layer 112 or the like.

  Through the above steps, a pixel electrode, a transistor, and a capacitor can be formed. Note that FIG. 15C is the same as FIG.

  Note that the capacitor 130A illustrated in FIG. 12A can be manufactured by processing the conductive layer 120b so as to overlap with the metal oxide layer 108C.

  In the case of manufacturing the capacitor 130C illustrated in FIG. 12C, the photomask used when the semiconductor layer 108 and the metal oxide layer 108C are processed is changed to be processed into one island shape. Can be formed.

  The above is the description of the manufacturing method example.

[Appendix]
In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and between the source and drain via the channel formation region. A current can flow. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

  Further, in this specification and the like, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.

  In this specification and the like, the terms “film” and “layer” can be interchanged with each other. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

  In this specification and the like, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth.

  The off-state current of the transistor may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, when the threshold voltage Vth is 0.5 V, the drain current when Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ⁻¹³ A. Assume that the n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

  In this specification and the like, the off-state current of a transistor having a channel width W may be represented by a current value flowing around the channel width W. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current / length (for example, A / μm).

  The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one temperature of 5 ° C. to 35 ° C.). May represent off-state current. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. There may be a case where there is a value of Vgs at which the off-state current of the transistor is equal to or lower than I at a temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.).

  The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V There is a value of Vgs at which the off-state current of the transistor is less than or equal to Vds at which Vds guarantees the reliability of the semiconductor device including the transistor or Vds used in the semiconductor device or the like including the transistor. May be pointed to.

  In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

  In this specification and the like, the term “leakage current” may be used in the same meaning as off-state current. In this specification and the like, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

In this specification and the like, the threshold voltage of a transistor refers to a gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor is a maximum slope in a curve (Vg-√Id characteristic) in which the gate voltage (Vg) is plotted on the horizontal axis and the square root of the drain current (Id) is plotted on the vertical axis. In some cases, a gate voltage (Vg) at the intersection of a straight line obtained by extrapolating a certain tangent and the square root of the drain current (Id) is 0 (Id is 0 A) may be indicated. Alternatively, the threshold voltage of the transistor is a gate in which the channel length is L, the channel width is W, and the value of Id [A] × L [μm] / W [μm] is 1 × 10 ⁻⁹ [A]. It may refer to voltage (Vg).

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. Further, the boundary between “semiconductor” and “insulator” is ambiguous, and there is a case where it cannot be strictly distinguished. Therefore, the “semiconductor” and the “insulator” described in this specification and the like can be interchangeable in some cases.

  In this specification and the like, even when expressed as “semiconductor”, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. Further, the boundary between the “semiconductor” and the “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, the term “semiconductor” and “conductor” in this specification and the like can be interchangeable in some cases.

  In this specification and the like, the atomic ratio is In: Ga: Zn = 4: 2: 3 or the vicinity thereof, when the ratio of In to the total number of In, Ga and Zn atoms is 4. In addition, the Ga ratio is 1 or more and 3 or less, and the Zn ratio is 2 or more and 4 or less. Also, the atomic ratio is In: Ga: Zn = 5: 1: 6 or the vicinity thereof, when the ratio of In to the total number of In, Ga and Zn atoms is 5, the Ga ratio is It is greater than 0.1 and less than or equal to 2 and the Zn ratio is greater than or equal to 5 and less than or equal to 7. Also, the atomic ratio is In: Ga: Zn = 1: 1: 1 or the vicinity thereof, when the ratio of In to the total number of In, Ga and Zn atoms is 1, the Ga ratio is It is assumed that the ratio of Zn is greater than 0.1 and 2 or less, and the Zn ratio is greater than 0.1 and 2 or less.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In the case of “OS FET”, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  In this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Further, in this specification and the like, there are cases where they are described as CAAC (c-axis aligned crystal) and CAC (Cloud-aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  In this specification and the like, a CAC-OS or a CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material is a semiconductor. It has the function of. Note that in the case where a CAC-OS or a CAC-metal oxide is used for an active layer of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is an electron serving as carriers. It is a function that does not flow. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

  In this specification and the like, a CAC-OS or a CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

  An example of the crystal structure of the metal oxide will be described. Note that in the following, an example of a metal oxide formed by a sputtering method using an In—Ga—Zn oxide target (In: Ga: Zn = 4: 2: 4.1 [atomic ratio]) will be described. Will be described. A metal oxide formed by a sputtering method at a substrate temperature of 100 ° C. to 130 ° C. using the above target is called sIGZO, and the substrate temperature is set to room temperature (RT) using the above target. The metal oxide formed by the method is referred to as tIGZO. For example, sIGZO has a crystal structure of one or both of nc (nano crystal) and CAAC. TIGZO has an nc crystal structure. Note that the room temperature (RT) here includes a temperature when the substrate is not intentionally heated.

  The CAAC structure is one of crystal structures such as a thin film having a plurality of nanocrystals (a crystal region having a maximum diameter of less than 10 nm), and each nanocrystal has a c-axis oriented in a specific direction, and The a-axis and the b-axis are crystal structures having the characteristics that the nanocrystals are continuously connected without forming a grain boundary without having orientation. In particular, a thin film having a CAAC structure has a feature that the c-axis of each nanocrystal is easily oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

Here, in crystallography, it is common to take a unit cell having a specific axis as the c-axis among the three axes (crystal axis) of the a-axis, b-axis, and c-axis constituting the unit cell. . In particular, in a crystal having a layered structure, two axes parallel to the plane direction of the layer are generally defined as an a axis and a b axis, and an axis intersecting the layer is generally defined as a c axis. As a typical example of a crystal having such a layered structure, there is graphite classified as a hexagonal system, the a-axis and b-axis of the unit cell are parallel to the cleavage plane, and the c-axis is orthogonal to the cleavage plane. To do. For example, an InGaZnO ₄ crystal having a YbFe ₂ O ₄ type crystal structure can be classified into a hexagonal system, the a-axis and b-axis of the unit cell being parallel to the plane direction of the layer, and the c-axis being a layer (ie a-axis and b-axis).

  The structure example, the manufacturing method example, the drawings corresponding to the structure example, and the like exemplified in this embodiment can be implemented in appropriate combination with at least part of the structure example, the manufacturing method example, the drawing, or the like.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 3)
An electronic device to which the display device of one embodiment of the present invention can be applied is described below. Here, an electronic device including a power generation device and a power reception device will be described as an example.

  An example of a portable information terminal as an example of electric devices will be described with reference to FIGS.

  FIG. 16A is a perspective view illustrating a front surface and a side surface of the portable information terminal 8040. For example, the portable information terminal 8040 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. A portable information terminal 8040 includes a display portion 8042, a camera 8045, a microphone 8046, and a speaker 8047 on the front surface of the housing 8041, an operation button 8043 on the left side surface of the housing 8041, and a connection terminal 8048 on the bottom surface. .

  The display module or the display panel of one embodiment of the present invention is used for the display portion 8042.

  A portable information terminal 8040 illustrated in FIG. 16A is an example in which one display portion 8042 is provided in a housing 8041. However, the present invention is not limited to this, and the display portion 8042 may be provided on the back surface of the portable information terminal 8040. In addition, two or more display units may be provided as a foldable portable information terminal.

  Further, the display portion 8042 is provided with a touch panel capable of inputting information by an instruction unit such as a finger or a stylus as an input unit. Accordingly, the icon 8044 displayed on the display unit 8042 can be easily operated by the instruction unit. In addition, since the area for arranging the keyboard on the portable information terminal 8040 is not necessary due to the arrangement of the touch panel, the display portion can be arranged in a wide area. In addition, since information can be input with a finger or a stylus, a user-friendly interface can be realized. As the touch panel, various methods such as a resistive film method, a capacitance method, an infrared method, an electromagnetic induction method, a surface acoustic wave method, and the like can be used. However, since the display portion 8042 is curved, it is particularly resistant. It is preferable to use a film system or a capacitance system. Further, such a touch panel may be a so-called in-cell type combined with the above-described display module or display panel.

  In addition, the touch panel may function as an image sensor. In this case, for example, personal authentication can be performed by touching the display unit 8042 with a palm or a finger and imaging a palm print, fingerprint, or the like. In addition, when a backlight that emits near-infrared light or a sensing light source that emits near-infrared light is used for the display portion 8042, finger veins, palm veins, and the like can be imaged.

  Further, a keyboard may be provided without providing the touch panel in the display portion 8042, and both the touch panel and the keyboard may be provided.

  The operation button 8043 can have various functions depending on applications. For example, the button 8043 may be a home button, and the home screen may be displayed on the display unit 8042 by pressing the button 8043. Alternatively, the main power source of the portable information terminal 8040 may be turned off by continuously pressing the button 8043 for a predetermined time. Further, when the state is shifted to the sleep mode, the user may be caused to return from the sleep mode by pressing a button 8043. In addition, it can be used as a switch that activates various functions when the button is kept pressed or when it is pressed simultaneously with other buttons.

  Further, the button 8043 may be a volume adjustment button or a mute button, and may have a function of adjusting the volume of the speaker 8047 for sound output. From the speaker 8047, various sounds such as a sound set by a specific process such as an operating system (OS) startup sound, a sound by a sound file executed in various applications such as music from a music reproduction application software, an e-mail ringtone, etc. Is output. Although not shown, a connector for outputting sound to a device such as a headphone, an earphone, or a headset may be provided together with the speaker 8047 or instead of the speaker 8047.

  As described above, the button 8043 can be provided with various functions. In FIG. 16A, a portable information terminal 8040 provided with two buttons 8043 on the left side is shown, but of course, the number and arrangement positions of the buttons 8043 are not limited to this, and can be designed as appropriate. it can.

  The microphone 8046 can be used for voice input and recording. In addition, an image acquired by the camera 8045 can be displayed on the display portion 8042.

  For the operation of the portable information terminal 8040, in addition to the touch panel and the button 8043 provided in the display unit 8042 described above, the user's action (gesture) is recognized using a camera 8045, a sensor built in the portable information terminal 8040, or the like. It can also be operated (called gesture input). Alternatively, an operation can be performed by recognizing a user's voice using the microphone 8046 (referred to as voice input). As described above, the operability of the portable information terminal 8040 can be further improved by implementing the NUI (Natural User Interface) technology for inputting to the electric device by natural human behavior.

  The connection terminal 8048 is a signal or power input terminal for communication with an external device and power supply. For example, the connection terminal 8048 can be used to drive an external memory to the portable information terminal 8040. As an external memory drive, for example, an external HDD (hard disk drive), flash memory drive, DVD (Digital Versatile Disk), DVD-R (DVD-Recordable), DVD-RW (DVD-ReWriteable), CD (Compact Disc), CD -R (Compact Disc Recordable), CD-RW (Compact Disc Rewriteable), MO (Magneto Optical Disc), FDD (Floppy Disk Drive), or other non-volatile solid-state drive (SolidSdStDSt) Recording media drive. Further, although the portable information terminal 8040 has a touch panel on the display portion 8042, a keyboard may be provided on the housing 8041 instead, or a keyboard may be externally attached.

  FIG. 16A illustrates a portable information terminal 8040 provided with one connection terminal 8048 on the bottom surface; however, the number and arrangement positions of the connection terminals 8048 are not limited thereto, and can be designed as appropriate. .

  FIG. 16B is a perspective view illustrating a back surface and a side surface of the portable information terminal 8040. A portable information terminal 8040 includes a solar cell 8049 and a camera 8050 on a surface of a housing 8041, and includes a charge / discharge control circuit 8051, a battery 8052, a DCDC converter 8053, and the like. 16B illustrates a structure including a battery 8052 and a DCDC converter 8053 as an example of the charge / discharge control circuit 8051. The battery 8052 includes the battery according to one embodiment of the present invention described in the above embodiment. Use the recovery method.

  Power can be supplied to a display portion, a touch panel, a video signal processing portion, or the like by a solar cell 8049 mounted on the back surface of the portable information terminal 8040. Note that the solar cell 8049 can be provided on one or both surfaces of the housing 8041. By mounting the solar battery 8049 on the portable information terminal 8040, the battery 8052 of the portable information terminal 8040 can be charged even in places where there is no power supply means such as outdoors.

As the solar cell 8049, a silicon-based solar cell made of single crystal silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, or a laminate thereof, InGaAs-based, GaAs-based, CIS-based, Cu ₂ ZnSnS _{4 is used.} , CdTe-CdS solar cells, dye-sensitized solar cells using organic dyes, organic thin-film solar cells using conductive polymers, fullerenes, etc., and quantum dot structures made of silicon or the like in the i layer of the pin structure A quantum dot solar cell or the like can be used.

  Here, an example of a structure and operation of the charge / discharge control circuit 8051 illustrated in FIG. 16B is described with reference to a block diagram illustrated in FIG.

  FIG. 16C illustrates a solar cell 8049, a battery 8052, a DCDC converter 8053, a converter 8057, a switch 8054, a switch 8055, a switch 8056, and a display portion 8042. The battery 8052, the DCDC converter 8053, the converter 8057, and the switch 8054, a switch 8055, and a switch 8056 are portions corresponding to the charge / discharge control circuit 8051 illustrated in FIG.

  The power generated by the solar cell 8049 by external light is boosted or lowered by the DCDC converter 8053 in order to obtain a voltage necessary for charging the battery 8052. When power from the solar cell 8049 is used for the operation of the display portion 8042, the switch 8054 is turned on, and the converter 8057 boosts or lowers the voltage to a voltage necessary for the display portion 8042. When display on the display portion 8042 is not performed, the switch 8054 is turned off and the switch 8055 is turned on to charge the battery 8052.

  Note that although the solar battery 8049 is shown as an example of the power generation means, the invention is not limited thereto, and the battery 8052 is charged using another power generation means such as a piezoelectric element (piezo element) or a thermoelectric conversion element (Peltier element). May be. Further, the charging method for the battery 8052 of the portable information terminal 8040 is not limited to this, and for example, charging may be performed by connecting the connection terminal 8048 described above and a power source. Moreover, you may use the non-contact electric power transmission module which transmits / receives electric power wirelessly, and may combine the above charging method.

  Here, the state of charge of the battery 8052 (SOC, an abbreviation for “State of Charge”) is displayed on the upper left of the display unit 8042 (in the broken line frame). Accordingly, the user can grasp the state of charge of the battery 8052 and can select the portable information terminal 8040 as the power saving mode in accordance with this. When the user selects the power saving mode, for example, the above-described button 8043 or icon 8044 is operated to configure a display module or display panel mounted on the portable information terminal 8040, an arithmetic device such as a CPU, a memory, or the like. The part can be switched to the power saving mode. Specifically, in each of these components, the use frequency of an arbitrary function is reduced and stopped. In the power saving mode, it is also possible to adopt a configuration that automatically switches to the power saving mode by setting according to the state of charge. Further, the portable information terminal 8040 is provided with detection means such as an optical sensor, and the display luminance is optimized by detecting the amount of external light when the portable information terminal 8040 is used, thereby suppressing the power consumption of the battery 8052. Can do.

  Further, at the time of charging with the solar battery 8049 or the like, as shown in FIG. 16A, an image or the like indicating it may be displayed on the upper left portion (inside the broken line frame) of the display portion 8042.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 4)
In this embodiment, a display module that can be manufactured using one embodiment of the present invention will be described.

  A display module 6000 illustrated in FIG. 17A includes a display device 6006 connected to an FPC 6005, a frame 6009, a printed board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

  For example, a display device manufactured using one embodiment of the present invention can be used for the display device 6006. With the display device 6006, a display module with extremely low power consumption can be realized.

  The shapes and dimensions of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the size of the display device 6006.

  Further, a touch panel may be provided over the display device 6006. As the touch panel, a resistive film type or capacitive type touch panel can be used by being superimposed on the display device 6006. Further, without providing a touch panel, the display device 6006 can have a touch panel function.

  The frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 6010 in addition to a protective function of the display device 6006. The frame 6009 may function as a heat sink.

  The printed board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal. The power source for supplying power to the power supply circuit may be an external commercial power source or a power source using a battery 6011 provided separately. The battery 6011 can be omitted when a commercial power source is used.

  FIG. 17B is a schematic cross-sectional view of a display module 6000 including an optical touch sensor.

  The display module 6000 includes a light emitting unit 6015 and a light receiving unit 6016 provided on the printed board 6010. Further, a region surrounded by the upper cover 6001 and the lower cover 6002 has a pair of light guide portions (light guide portion 6017a and light guide portion 6017b).

  For the upper cover 6001 and the lower cover 6002, for example, plastic can be used. Further, the upper cover 6001 and the lower cover 6002 can each be thin (for example, 0.5 mm to 5 mm). Therefore, the display module 6000 can be made extremely light. Further, since the upper cover 6001 and the lower cover 6002 can be manufactured with a small amount of material, manufacturing cost can be reduced.

  The display device 6006 is provided so as to overlap the printed board 6010 and the battery 6011 with a frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide unit 6017a and the light guide unit 6017b.

  Light 6018 emitted from the light emitting unit 6015 passes through the upper portion of the display device 6006 by the light guide unit 6017a and reaches the light receiving unit 6016 through the light guide unit 6017b. For example, the touch operation can be detected by blocking the light 6018 by a detection target such as a finger or a stylus.

  For example, a plurality of light emitting units 6015 are provided along two adjacent sides of the display device 6006. A plurality of light receiving units 6016 are provided at positions facing the light emitting unit 6015. Thereby, the information on the position where the touch operation is performed can be acquired.

  The light emitting unit 6015 can use a light source such as an LED element. In particular, it is preferable to use a light source that emits infrared rays that are not visually recognized by the user and harmless to the user as the light emitting unit 6015.

  The light receiving unit 6016 can be a photoelectric element that receives light emitted from the light emitting unit 6015 and converts the light into an electrical signal. Preferably, a photodiode capable of receiving infrared light can be used.

  As the light guide portion 6017a and the light guide portion 6017b, a member that transmits at least the light 6018 can be used. By using the light guide unit 6017a and the light guide unit 6017b, the light emitting unit 6015 and the light receiving unit 6016 can be arranged below the display device 6006, and external light reaches the light receiving unit 6016 and the touch sensor malfunctions. Can be suppressed. In particular, it is preferable to use a resin that absorbs visible light and transmits infrared rays. Thereby, malfunction of a touch sensor can be controlled more effectively.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 5)
In this embodiment, an electronic device including a display device manufactured using one embodiment of the present invention will be described.

  FIG. 18A is a diagram illustrating the appearance of the camera 8000 with the viewfinder 8100 attached.

  A camera 8000 includes a housing 8001, a display portion 8002, operation buttons 8003, a shutter button 8004, and the like. The camera 8000 is attached with a detachable lens 8006.

  Here, the camera 8000 is configured such that the lens 8006 can be removed from the housing 8001 and replaced, but the lens 8006 and the housing may be integrated.

  The camera 8000 can take an image by pressing a shutter button 8004. In addition, the display portion 8002 has a function as a touch panel and can capture an image by touching the display portion 8002.

  A housing 8001 of the camera 8000 includes a mount having an electrode, and a strobe device or the like can be connected in addition to the finder 8100.

  The viewfinder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

  The housing 8101 has a mount that engages with the mount of the camera 8000, and the finder 8100 can be attached to the camera 8000. In addition, the mount includes an electrode, and an image received from the camera 8000 via the electrode can be displayed on the display portion 8102.

  The button 8103 has a function as a power button. A button 8103 can be used to switch display on the display portion 8102 on and off.

  The display device of one embodiment of the present invention can be applied to the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100.

  Note that in FIG. 18A, the camera 8000 and the viewfinder 8100 are separate electronic devices and can be attached to and detached from each other. However, a finder including a display device is incorporated in the housing 8001 of the camera 8000. Also good.

  FIG. 18B is a diagram illustrating the appearance of the head mounted display 8200.

  The head mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. In addition, a battery 8206 is built in the mounting portion 8201.

  A cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver and the like, and can display video information such as received image data on the display portion 8204. In addition, it is possible to use the user's viewpoint as an input unit by capturing the movement of the user's eyeball or eyelid with a camera provided in the main body 8203 and calculating the coordinates of the user's viewpoint based on the information. it can.

  In addition, the mounting portion 8201 may be provided with a plurality of electrodes at a position where the user touches the user. The main body 8203 may have a function of recognizing the user's viewpoint by detecting a current flowing through the electrode in accordance with the movement of the user's eyeball. Moreover, you may have a function which monitors a user's pulse by detecting the electric current which flows into the said electrode. The mounting portion 8201 may have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display portion 8204. Further, the movement of the user's head or the like may be detected, and the video displayed on the display unit 8204 may be changed in accordance with the movement.

  The display device of one embodiment of the present invention can be applied to the display portion 8204.

  18C, 18D, and 18E are views showing the appearance of the head mounted display 8300. FIG. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

  The user can view the display on the display portion 8302 through the lens 8305. Note that the display portion 8302 is preferably arranged curved. By arranging the display portion 8302 to be curved, the user can feel a high sense of realism. Note that although a structure in which one display portion 8302 is provided is described in this embodiment mode, the present invention is not limited thereto, and for example, a structure in which two display portions 8302 are provided may be employed. In this case, if one display unit is arranged in one eye of the user, three-dimensional display using parallax or the like can be performed.

  Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. Since the display device including the semiconductor device of one embodiment of the present invention has extremely high definition, the pixel is not visually recognized by the user even when the display device is enlarged using the lens 8305 as illustrated in FIG. More realistic video can be displayed.

  Next, examples of electronic devices that are different from the electronic devices illustrated in FIGS. 18A to 18E are illustrated in FIGS. 19A to 19G.

  An electronic device illustrated in FIGS. 19A to 19G includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (force , Displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical, voice, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration , Including a function of measuring odor or infrared light), a microphone 9008, and the like.

  The electronic devices illustrated in FIGS. 19A to 19G have various functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that the functions of the electronic devices illustrated in FIGS. 19A to 19G are not limited to these, and can have various functions. Although not illustrated in FIGS. 19A to 19G, the electronic device may have a plurality of display portions. In addition, the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.

  Details of the electronic devices illustrated in FIGS. 19A to 19G are described below.

  FIG. 19A is a perspective view illustrating a television device 9100. FIG. The television device 9100 can incorporate a display portion 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

  FIG. 19B is a perspective view showing the portable information terminal 9101. The portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 may include a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001. Further, information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001. As an example of the information 9051, a display for notifying an incoming call such as an e-mail, SNS (social networking service), a telephone call, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date and time, and a time , Battery level, antenna reception strength and so on. Alternatively, an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.

  FIG. 19C is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different planes. For example, the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes. Specifically, the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102. The user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.

  FIG. 19D is a perspective view showing a wristwatch-type portable information terminal 9200. The portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games. Further, the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface. In addition, the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. In addition, the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.

  19E, 19F, and 19G are perspective views illustrating a foldable portable information terminal 9201. FIG. 19E is a perspective view of a state in which the portable information terminal 9201 is expanded, and FIG. 19F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other. FIG. 19G is a perspective view of the portable information terminal 9201 folded. The portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area. A display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.

  The electronic device described in this embodiment includes a display portion for displaying some information. Note that the semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not include a display portion.

  The structure examples exemplified in this embodiment and the corresponding drawings can be implemented by combining at least part of the structure examples with other structure examples or the drawings as appropriate.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 6)
In this embodiment, electronic devices of one embodiment of the present invention are described with reference to drawings.

  An electronic device exemplified below includes the display device of one embodiment of the present invention in the display portion. Therefore, the electronic device has a high resolution. In addition, the electronic device can achieve both high resolution and a large screen.

  The display portion of the electronic device of one embodiment of the present invention can display an image having a resolution of, for example, full high vision, 4K2K, 8K4K, 16K8K, or higher. In addition, the screen size of the display unit may be 20 inches or more diagonal, 30 inches or more diagonal, 50 inches diagonal, 60 inches diagonal, or 70 inches diagonal.

  Examples of electronic devices include relatively large screens such as television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and large game machines such as pachinko machines. In addition to the electronic devices provided, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device, and the like can be given.

  The electronic device or the lighting device of one embodiment of the present invention can be incorporated along a curved surface of an inner wall or an outer wall of a house or a building, or an interior or exterior of an automobile.

  The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. In the case where the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

  The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).

  The electronic device of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.

  FIG. 20A illustrates an example of a television set. In the television device 7100, a display portion 7500 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.

  The display device of one embodiment of the present invention can be applied to the display portion 7500.

  Operation of the television device 7100 illustrated in FIG. 20A can be performed with an operation switch included in the housing 7101 or a separate remote controller 7111. Alternatively, the display portion 7500 may be provided with a touch sensor, and may be operated by touching the display portion 7500 with a finger or the like. The remote controller 7111 may include a display unit that displays information output from the remote controller 7111. Channels and volume can be operated with an operation key or a touch panel included in the remote controller 7111, and an image displayed on the display portion 7500 can be operated.

  Note that the television device 7100 is provided with a receiver, a modem, and the like. A general television broadcast can be received by the receiver. In addition, by connecting to a wired or wireless communication network via a modem, information communication is performed in one direction (from the sender to the receiver) or in two directions (between the sender and the receiver or between the receivers). It is also possible.

  FIG. 20B illustrates a laptop personal computer 7200. A laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7500 is incorporated in the housing 7211.

  The display device of one embodiment of the present invention can be applied to the display portion 7500.

  FIGS. 20C and 20D show examples of digital signage (digital signage).

  A digital signage 7300 illustrated in FIG. 20C includes a housing 7301, a display portion 7500, a speaker 7303, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.

  FIG. 20D illustrates a digital signage 7400 attached to a columnar column 7401. The digital signage 7400 includes a display portion 7500 provided along the curved surface of the pillar 7401.

  20C and 20D, the display device of one embodiment of the present invention can be applied to the display portion 7500.

  The wider the display portion 7500, the more information can be provided at one time. In addition, the wider the display portion 7500, the easier it is to be noticed by humans. For example, the advertising effect of advertisement can be enhanced.

  By applying a touch panel to the display portion 7500, not only an image or a moving image is displayed on the display portion 7500, but also a user can operate intuitively, which is preferable. In addition, when it is used for providing information such as route information or traffic information, usability can be improved by an intuitive operation.

  20C and 20D, the digital signage 7300 or the digital signage 7400 can be linked with the information terminal 7311 or the information terminal 7411 such as a smartphone possessed by the user by wireless communication. Is preferred. For example, advertisement information displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Further, by operating the information terminal 7311 or the information terminal 7411, the display of the display unit 7500 can be switched.

  Further, the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). Thereby, an unspecified number of users can participate and enjoy the game at the same time.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 7)
In this embodiment, an example of a television device to which a display device including the semiconductor device of one embodiment of the present invention can be applied will be described with reference to drawings.

  FIG. 21A shows a block diagram of the television device 600.

  In the drawings attached to the present specification, the components are classified by function and the block diagram is shown as an independent block. However, it is difficult to completely separate actual components by function. A component may be involved in multiple functions.

  The television apparatus 600 includes a control unit 601, a storage unit 602, a communication control unit 603, an image processing circuit 604, a decoder circuit 605, a video signal receiving unit 606, a timing controller 607, a source driver 608, a gate driver 609, a display panel 620, and the like. Have

  The display device described as an example in the above embodiment can be applied to the display panel 620 in FIG. Accordingly, the television device 600 having a large size and high resolution and excellent visibility can be realized.

  The control unit 601 can function as, for example, a central processing unit (CPU). For example, the control unit 601 has a function of controlling components such as the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, and the video signal receiving unit 606 via the system bus 630.

  A signal is transmitted between the control unit 601 and each component via the system bus 630. In addition, the control unit 601 has a function of processing a signal input from each component connected via the system bus 630, a function of generating a signal output to each component, and the like, thereby being connected to the system bus 630. Each component can be controlled centrally.

  The storage unit 602 functions as a register, a cache memory, a main memory, a secondary memory, or the like that can be accessed by the control unit 601 and the image processing circuit 604.

  As a storage device that can be used as the secondary memory, for example, a storage device to which a rewritable nonvolatile storage element is applied can be used. For example, a flash memory, an MRAM (Magnetostatic Random Access Memory), a PRAM (Phase change RAM), a ReRAM (Resistive RAM), an FeRAM (Ferroelectric RAM), or the like can be used.

  In addition, as a storage device that can be used as a temporary memory such as a register, a cache memory, or a main memory, a volatile storage element such as a DRAM (Dynamic RAM) or an SRAM (Static Random Access Memory) may be used.

  For example, as a RAM provided in the main memory, for example, a DRAM is used, and a memory space is virtually allocated and used as a work space of the control unit 601. The operating system, application program, program module, program data, etc. stored in the storage unit 602 are loaded into the RAM for execution. These data, programs, and program modules loaded in the RAM are directly accessed and operated by the control unit 601.

  On the other hand, the ROM can store BIOS (Basic Input / Output System), firmware and the like that do not require rewriting. As the ROM, a mask ROM, an OTPROM (One Time Programmable Read Only Memory), an EPROM (Erasable Programmable Read Only Memory), or the like can be used. Examples of EPROM include UV-EPROM (Ultra-Violet Erasable Programmable Read Only Memory) and EEPROM (Electrically Erasable Programmable Read Only Memory) capable of erasing stored data by ultraviolet irradiation.

  In addition to the storage unit 602, a removable storage device may be connected. For example, it has a terminal for connecting to a recording medium drive such as a hard disk drive (HDD) or a solid state drive (SSD) that functions as a storage device, a recording medium such as a flash memory, a Blu-ray disc, or a DVD. Is preferred. Thereby, a video can be recorded.

  The communication control unit 603 has a function of controlling communication performed via a computer network. For example, the control signal for connecting to the computer network is controlled in accordance with a command from the control unit 601, and the signal is transmitted to the computer network. As a result, the Internet, intranet, extranet, PAN (Personal Area Network), LAN (Local Area Network), CAN (Camper Area Network, and MAN (MetroApolNetwork), which are the foundations of the World Wide Web (WWW). Communication can be performed by connecting to a computer network such as Wide Area Network (GA) or GAN (Global Area Network).

  The communication control unit 603 has a function of communicating with a computer network or other electronic devices using a communication standard such as Wi-Fi (registered trademark), Bluetooth (registered trademark), or ZigBee (registered trademark). Also good.

  The communication control unit 603 may have a function of communicating wirelessly. For example, an antenna and a high frequency circuit (RF circuit) may be provided to transmit and receive an RF signal. The high-frequency circuit is a circuit for mutually converting an electromagnetic signal and an electric signal in a frequency band determined by the legislation of each country and performing communication with other communication devices wirelessly using the electromagnetic signal. Several tens of kHz to several tens of GHz is generally used as a practical frequency band. The high-frequency circuit connected to the antenna includes a high-frequency circuit unit corresponding to a plurality of frequency bands, and the high-frequency circuit unit includes an amplifier (amplifier), a mixer, a filter, a DSP, an RF transceiver, and the like. it can.

  The video signal receiving unit 606 includes, for example, an antenna, a demodulation circuit, an A / D conversion circuit (analog-digital conversion circuit), and the like. The demodulation circuit has a function of demodulating a signal input from the antenna. The A-D conversion circuit has a function of converting the demodulated analog signal into a digital signal. The signal processed by the video signal receiving unit 606 is sent to the decoder circuit 605.

  The decoder circuit 605 has a function of decoding video data included in a digital signal input from the video signal receiving unit 606 in accordance with the specification of a broadcast standard to be transmitted, and generating a signal to be transmitted to the image processing circuit. For example, as a broadcasting standard in 8K broadcasting, H.264 265 | MPEG-H High Efficiency Video Coding (abbreviation: HEVC).

  Examples of broadcast radio waves that can be received by the antenna included in the video signal receiving unit 606 include ground waves or radio waves transmitted from satellites. Broadcast radio waves that can be received by an antenna include analog broadcast and digital broadcast, and also includes video and audio, or audio-only broadcast. For example, broadcast radio waves transmitted in a specific frequency band in the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz) can be received. In addition, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. Accordingly, an image having a resolution exceeding full high-definition can be displayed on the display panel 620. For example, an image having a resolution of 4K2K, 8K4K, 16K8K, or higher can be displayed.

  Further, the video signal receiving unit 606 and the decoder circuit 605 may be configured to generate a signal to be transmitted to the image processing circuit 604 using broadcast data transmitted by a data transmission technique via a computer network. At this time, when the signal to be received is a digital signal, the video signal receiving unit 606 may not include a demodulation circuit, an A-D conversion circuit, and the like.

  The image processing circuit 604 has a function of generating a video signal to be output to the timing controller 607 based on the video signal input from the decoder circuit 605.

  The timing controller 607 also outputs a signal (a signal such as a clock signal or a start pulse signal) to be output to the gate driver 609 and the source driver 608 based on a synchronization signal included in the video signal or the like processed by the image processing circuit 604. It has a function to generate. The timing controller 607 has a function of generating a video signal to be output to the source driver 608 in addition to the above signals.

  The display panel 620 includes a plurality of pixels 621. Each pixel 621 is driven by signals supplied from the gate driver 609 and the source driver 608. Here, an example of a display panel having a resolution according to the 8K4K standard having the number of pixels of 7680 × 4320 is shown. Note that the resolution of the display panel 620 is not limited to this, and may be a resolution according to a standard such as full high-definition (pixel number 1920 × 1080) or 4K2K (pixel number 3840 × 2160).

  As the control unit 601 and the image processing circuit 604 illustrated in FIG. 21A, for example, a structure including a processor can be employed. For example, the control unit 601 can use a processor that functions as a central processing unit (CPU). Further, as the image processing circuit 604, for example, other processors such as a DSP (Digital Signal Processor) and a GPU (Graphics Processing Unit) can be used. In addition, the control unit 601 and the image processing circuit 604 may have a configuration in which the processor is realized by a PLD (Programmable Logic Device) such as an FPGA (Field Programmable Gate Array) or an FPAA (Field Programmable Analog Array).

  The processor performs various data processing and program control by interpreting and executing instructions from various programs. The program that can be executed by the processor may be stored in a memory area of the processor, or may be stored in a storage device provided separately.

  In addition, two or more functions among the functions of the control unit 601, the storage unit 602, the communication control unit 603, the image processing circuit 604, the decoder circuit 605, the video signal receiving unit 606, and the timing controller 607 are provided. A system LSI may be configured by concentrating on one IC chip. For example, a system LSI including a processor, a decoder circuit, a tuner circuit, an A / D conversion circuit, a DRAM, and an SRAM may be used.

  Note that a transistor in which an oxide semiconductor is used for a channel formation region and an extremely low off-state current is realized can be used for the controller 601, an IC included in another component, or the like. Since the transistor has extremely low off-state current, the use of the transistor as a switch for holding charge (data) flowing into the capacitor functioning as a memory element can ensure a data holding period for a long time. it can. By using this characteristic for a register such as the control unit 601 or a cache memory, the control unit 601 is operated only when necessary, and in other cases, information on the immediately preceding process is saved in the storage element, so that it is normally. Off-computing becomes possible. Thereby, the power consumption of the television apparatus 600 can be reduced.

  Note that the structure of the television device 600 illustrated in FIG. 21A is just an example, and it is not necessary to include all of the components. The television set 600 only needs to include necessary components from among the components illustrated in FIG. In addition, the television device 600 may include a component other than the components illustrated in FIG.

  For example, the television device 600 may include an external interface, an audio output unit, a touch panel unit, a sensor unit, a camera unit, and the like in addition to the configuration illustrated in FIG. For example, as an external interface, for example, a USB (Universal Serial Bus) terminal, a LAN (Local Area Network) connection terminal, a power receiving terminal, an audio output terminal, an audio input terminal, an image output terminal, an image input terminal, etc. External connection terminals, transceivers for optical communication using infrared rays, visible light, ultraviolet rays, etc., physical buttons provided on the housing, and the like. For example, the sound input / output unit includes a sound controller, a microphone, a speaker, and the like.

  Hereinafter, the image processing circuit 604 will be described in more detail.

  The image processing circuit 604 preferably has a function of executing image processing based on the video signal input from the decoder circuit 605.

  Examples of image processing include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing. Examples of color tone correction processing and luminance adjustment processing include gamma correction.

  The image processing circuit 604 preferably has a function of executing processing such as inter-pixel interpolation processing associated with resolution up-conversion and inter-frame interpolation processing associated with frame frequency up-conversion.

  For example, as noise removal processing, various noises such as mosquito noise generated around the outline of characters, block noise generated in high-speed moving images, flickering random noise, and dot noise generated by resolution up-conversion are removed.

  The gradation conversion process is a process for converting the gradation of an image into a gradation corresponding to the output characteristics of the display panel 620. For example, when the number of gradations is increased, a process for smoothing the histogram can be performed by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. Further, the dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.

  The inter-pixel interpolation process interpolates data that does not originally exist when the resolution is up-converted. For example, referring to pixels around the target pixel, the data is interpolated so as to display the intermediate colors.

  The color tone correction process is a process for correcting the color tone of an image. The brightness correction process is a process for correcting the brightness (brightness contrast) of the image. For example, the type, brightness, or color purity of the illumination arranged in the space where the television apparatus 600 is provided is detected, and the brightness and color tone of the image displayed on the display panel 620 are corrected accordingly. . Or, it has a function to compare the image to be displayed with the images of various scenes in the image list stored in advance, and to correct the image displayed with brightness and color tone suitable for the image of the closest scene. May be.

  Interframe interpolation generates an image of a frame (interpolation frame) that does not originally exist when the frame frequency of a video to be displayed is increased. For example, an interpolation frame image to be inserted between two images is generated from the difference between two images. Alternatively, an image of a plurality of interpolation frames can be generated between two images. For example, when the frame frequency of the video signal input from the decoder circuit 605 is 60 Hz, the frame frequency of the video signal output to the timing controller 607 is doubled by 120 Hz by generating a plurality of interpolation frames, or It can be increased to 4 times 240 Hz or 8 times 480 Hz.

  The image processing circuit 604 preferably has a function of executing image processing using a neural network. FIG. 21A illustrates an example in which the image processing circuit 604 includes a neural network 610.

  For example, the neural network 610 can perform feature extraction from image data included in a video, for example. The image processing circuit 604 can select an optimal correction method according to the extracted features, or can select parameters used for correction.

  Alternatively, the neural network 610 itself may have a function of performing image processing. That is, the image data that has been subjected to image processing may be output by inputting the image data before being subjected to image processing to the neural network 610.

  In addition, weight coefficient data used for the neural network 610 is stored in the storage unit 602 as a data table. The data table including the weighting coefficient can be updated to the latest one via the computer network by the communication control unit 603, for example. Alternatively, the image processing circuit 604 may have a learning function so that a data table including a weighting factor can be updated.

  FIG. 21B shows a schematic diagram of a neural network 610 included in the image processing circuit 604.

  In this specification and the like, a neural network refers to a general model that imitates a biological neural network, determines the connection strength between neurons by learning, and has problem solving ability. The neural network has an input layer, an intermediate layer (also referred to as a hidden layer), and an output layer. A neural network having two or more intermediate layers is called deep learning (or deep neural network (DNN)).

  In this specification and the like, when describing a neural network, determining the connection strength (also referred to as a weighting factor) between neurons from existing information may be referred to as “learning”. Further, in this specification and the like, there is a case where “inference” refers to constructing a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom.

  The neural network 610 includes an input layer 611, one or more intermediate layers 612, and an output layer 613. Input data is input to the input layer 611. Output data is output from the output layer 613.

  The input layer 611, the intermediate layer 612, and the output layer 613 each have a neuron 615. Here, the neuron 615 indicates a circuit element (product-sum operation element) capable of realizing product-sum operation. In FIG. 21, the input / output direction of data between two neurons 615 included in two layers is indicated by arrows.

Arithmetic processing in each layer is executed by a product-sum operation between the output of the neuron 615 included in the previous layer and the weight coefficient. For example, if the output of the i-th neuron in the input layer is x _i and the connection strength (weight coefficient) between the output x _i and the j-th neuron in the next intermediate layer 612 is w _ji , The output y _j of the j-th neuron is y _j = f (Σw _ji · x _i ). Note that i and j are integers of 1 or more. Here, f (x) is an activation function, and a sigmoid function, a threshold function, or the like can be used. Similarly, the output of the neuron 615 of each layer is a value obtained by calculating the activation function on the product-sum operation result of the output of the neuron 615 of the previous layer and the weight coefficient. The connection between layers may be a total connection in which all neurons are connected, or a partial connection in which some neurons are connected. FIG. 21B shows the case of full coupling.

  FIG. 21B illustrates an example having three intermediate layers 612. Note that the number of the intermediate layers 612 is not limited to this, and it is only necessary to include one or more intermediate layers. In addition, the number of neurons included in one intermediate layer 612 may be changed as appropriate according to specifications. For example, the number of neurons 615 included in one intermediate layer 612 may be larger or smaller than the number of neurons 615 included in the input layer 611 or the output layer 613.

  A weighting factor that is an index of the strength of connection between the neurons 615 is determined by learning. The learning may be executed by a processor included in the television apparatus 600, but is preferably executed by a computer having an excellent arithmetic processing capability such as a dedicated server or a cloud. The weighting coefficient determined by learning is stored in the storage unit 602 as a table and is used by being read out by the image processing circuit 604. The table can be updated via a computer network as necessary.

  This completes the description of the neural network.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

  In this example, a circuit that can be used for one embodiment of the present invention will be described.

  A circuit illustrated in FIG. 22A functions as a latch circuit. This circuit can be suitably used for the latch circuit LAT2 and the like exemplified in Embodiment 1.

  The circuit illustrated in FIG. 22A includes transistors M1 to M10 and capacitor elements C1 to C3. The circuit also has an input terminal to which the data signal DATA, the latch signal LAT, and the reset signal RES are input, and an output terminal OUT. The circuit is connected to a wiring to which power supply voltages VDD and VSS are applied.

  The circuit illustrated in FIG. 22A functions as a sample-and-hold circuit that can acquire (sample) an input data signal DATA in accordance with the latch signal LAT and hold an output in accordance with the data signal. . Further, it has a function of erasing (resetting) held data in response to the reset signal RES.

  FIG. 22B illustrates an example of a layout pattern of the circuit illustrated in FIG. Here, transistors having a channel length L of 0.75 μm and a channel width W of 20 μm were applied to the transistors M1 to M10, respectively. The transistor M5 has a configuration in which three transistors of the size described above are connected in parallel.

  As each transistor in FIG. 22B, a transistor in which a metal oxide is applied to a channel formation region and a channel length L is extremely short, which is exemplified in Embodiment 2, can be used.

  FIG. 23 is a schematic perspective view of the layout pattern shown in FIG. As shown in FIG. 23, in the circuit, the first conductive layer ML1, the semiconductor layer OSL, the second conductive layer ML2, the third conductive layer ML3, and the fourth conductive layer ML4 are sequentially stacked from the bottom. It becomes the composition. Note that an insulating layer provided between the layers is omitted. In addition, a vertical thin line in FIG. 23 represents a connection region (contact region) for connecting two overlapping layers.

  With such a structure, a latch circuit capable of high-speed operation can be manufactured over the second substrate over which the display portion exemplified in Embodiment 1 is provided. Further, by using similar transistors, each circuit of the second driver circuit exemplified in Embodiment 1 can be formed.

  The above is the description of this embodiment.

  This embodiment can be implemented in combination with any of the embodiments described at least in this specification as appropriate.

DESCRIPTION OF SYMBOLS 10 Display apparatus 10a Display apparatus 11 Drive circuit 12 Drive circuit 13 Display part 13a Display part 13b Display part 20 Substrate 30 Substrate 31 Display part 41 Transistor 42 Transistor 43 Capacitor element 44 Light emitting element 50 Diagonal element 51 Transistor 53 Capacitor element 54 Display element 60 Diagonal 70 Diagonal 100 Transistor 100A Transistor 102 Substrate 104 Insulating layer 106 Conductive layer 106C Conductive layer 108 Semiconductor layer 108A Transistor 108C Metal oxide layer 108f Metal oxide film 108i Region 108n Region 109 Conductive layer 110 Insulating layer 110f Insulating film 112 Conductive Layer 112f conductive film 114 metal oxide layer 114f metal oxide film 116 layer 116a layer 117 metal oxide layer 118 insulating layer 119 insulating layer 120a conductive layer 120b conductive layer 130A capacitor element 130B capacitor element 130C Capacitance element 141a Opening 141b Opening 141c Opening 142 Opening 255 Opening 255 Tone value 600 Television apparatus 601 Control unit 602 Storage unit 603 Communication control unit 604 Image processing circuit 605 Decoder circuit 606 Video signal receiving unit 607 Timing controller 608 Source Driver 609 Gate driver 610 Neural network 611 Input layer 612 Intermediate layer 613 Output layer 615 Neuron 620 Display panel 621 Pixel 630 System bus 6000 Display module 6001 Upper cover 6002 Lower cover 6005 FPC
6006 Display device 6009 Frame 6010 Printed circuit board 6011 Battery 6015 Light emitting unit 6016 Light receiving unit 6017a Light guiding unit 6017b Light guiding unit 6018 Light 7100 Television apparatus 7101 Case 7103 Stand 7111 Remote control device 7200 Notebook personal computer 7211 Case 7212 Keyboard 7213 Pointing device 7214 External connection port 7300 Digital signage 7301 Case 7303 Speaker 7311 Information terminal 7400 Digital signage 7401 Pillar 7411 Information terminal 7500 Display unit 8000 Camera 8001 Case 8002 Display unit 8003 Operation button 8004 Shutter button 8006 Lens 8040 Portable information terminal 8041 Housing 8042 Display unit 8043 Button 8044 Eye Con 8045 Camera 8046 Microphone 8047 Speaker 8048 Connection terminal 8049 Solar battery 8050 Camera 8051 Charge / discharge control circuit 8052 Battery 8053 DCDC converter 8054 Switch 8055 Switch 8056 Switch 8057 Converter 8100 Viewfinder 8101 Housing 8102 Display unit 8103 Button 8200 Head mount display 8201 Mounting unit 8202 Lens 8203 Body 8204 Display unit 8205 Cable 8206 Battery 8300 Head mounted display 8301 Case 8302 Display unit 8304 Fixing tool 8305 Lens 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Broadcast 9052 Information 9053 Information 9054 Information 9055 hinge 9100 television device 9101 portable information terminal 9102 portable information terminal 9200 portable information terminal 9201 portable information terminal

Claims (5)

A display device having a first circuit, a second circuit, and a display unit,
The display unit includes a plurality of pixels and a plurality of wirings connected to the pixels,
The first circuit has a function of converting a first digital signal into a plurality of second digital signals, and a function of serially outputting the plurality of second digital signals to the second circuit,
The second circuit has a function of converting a plurality of the second digital signals into a plurality of analog signals, and a function of outputting the analog signals to the wiring.
The first circuit includes a first transistor formed on a first substrate;
The second circuit includes a second transistor formed on a second substrate,
The display unit includes a third transistor formed on the second substrate in the pixel,
The first substrate is a single crystal semiconductor substrate or a compound semiconductor substrate;
The second substrate is a substrate having an insulating surface;
The first transistor includes silicon or germanium in a semiconductor in which a channel is formed,
The second transistor and the third transistor include a metal oxide in a semiconductor in which a channel is formed,
The second transistor has a portion whose channel length is shorter than that of the third transistor.
Display device. In claim 1,
The second transistor has a portion having a channel length of 0.1 μm or more and 1.0 μm or less,
Display device. In claim 2 or claim 3,
A third circuit having a plurality of buffer amplifier circuits;
The analog signal output from the second circuit is output to the wiring via the buffer amplifier circuit.
Display device. In claim 3,
The third circuit includes a fourth transistor formed on the second substrate,
In the fourth transistor, the metal oxide is used for a semiconductor in which a channel is formed.
Display device. In claim 3,
The third circuit includes a fifth transistor formed on the first substrate,
In the fifth transistor, silicon or germanium is used for a semiconductor in which a channel is formed.
Display device.