JP2019012989A - Encoder, decoder, transmitter, and receiver - Google Patents

Abstract

To provide a transmitter and a receiver of digital data excellent in noise resistance by applying an LDPC code as an error correcting code for terrestrial broadcasting and improving its performance for each of LDPC coding rates 2/16, 4/16, 5/16, 6/16, for a code length 69120 bits, and for each of the LDPC coding rates 2/16, 3/16, 4/16, 5/16, 6/16 for a code length of 17280 bits.SOLUTION: An encoder (LDPC encoding unit 114) of the present invention includes means for performing LDPC encoding by using a check matrix including a partial matrix formed using a predetermined check matrix initial value table as an initial value for each coding rate with a code length of 69120 bits or 17280, and is provided in a transmitter 1 of the present invention. A decoder (LDPC decoding unit 212) of the present invention includes means for decoding digital data encoded by the encoder and is provided in a receiver 2 of the present invention.SELECTED DRAWING: Figure 4

Description

  The present invention relates to the technical fields of satellite broadcasting and terrestrial broadcasting, fixed communication, and mobile communication, and more particularly to a digital data encoder, decoder, transmitter, and receiver.

  In the digital transmission system, a multi-level modulation system is often used so that more information can be transmitted in the frequency bandwidth available for each service. In order to increase the frequency utilization efficiency, it is effective to increase the number of bits (modulation order) allocated per symbol of the modulation signal, but the relationship between the upper limit of the information rate that can be transmitted per 1 Hz of frequency and the signal-to-noise ratio is The modulation signal is limited by the achievable communication capacity.

  In terrestrial digital broadcasting currently used, information correction is performed in a receiving apparatus using an error correction code. By adding a redundant signal called a parity bit to information to be sent, it is possible to control the redundancy (coding rate) of the signal and increase the resistance to noise. The error correction code and the modulation scheme are closely related, and the theoretical upper limit of the frequency utilization efficiency with respect to the signal-to-noise ratio is called the Shannon limit. In this paper, the communication capacity that can be achieved by the modulation signal is defined as the Shannon limit for convenience. As a powerful error correction code having a performance approaching the Shannon limit, an LDPC (Low Density Parity Check) code was proposed by Gallagher in 1962 (see, for example, Non-Patent Document 1).

  The LDPC code is a linear code defined by a very sparse check matrix H (the elements of the check matrix are 0 and 1 and the number of 1 is very small).

  The LDPC code is a powerful error correction code that can obtain transmission characteristics approaching the Shannon limit by increasing the code length and using an appropriate check matrix. Transmission of 4K / 8K super high-definition satellite broadcasting, the next-generation broadcasting service. The LDPC code is also adopted in ARIB STD-B44 (hereinafter referred to as an advanced satellite broadcasting system, for example, see Non-Patent Document 2) that defines the system. By combining multi-level modulation and a powerful error correction code such as an LDPC code, transmission with higher frequency utilization efficiency has become possible.

  In the case of the advanced satellite broadcasting system as an example, the code length of the LDPC code in this system is composed of a forward error correction (FEC) frame, which is 44880 bits, and has a BPSK limit (the signal point arrangement is BPSK). (Theoretical upper limit value of the frequency utilization efficiency with respect to the signal-to-noise ratio) is shown to have a performance within about 1 dB (for example, see Non-Patent Document 3).

  In the advanced satellite broadcasting system, the LDPC coding rates are 41/120 (≈1 / 3), 49/120 (≈2 / 5), 61/120 (≈1 / 2), 73/120 (≈ 3/5), 81/120 (≈2 / 3), 89/120 (≈3 / 4), 93/120 (≈7 / 9), 97/120 (≈4 / 5), 101/120 (≈ 11 types of 5/6), 105/120 (≈7 / 8), and 109/120 (≈9 / 10) are defined.

R. G Gallager, “Low Density Parity Check Codes,” in Research Monograph series Cambridge, MIT Press, 1963 "Transmission system of advanced broadband satellite digital broadcasting standard ARIB STD-B44 2.1 version, revised on March 25, 2016, Japan Radio Industry Association (ARIB) Suzuki et al., “Design of LDPC codes for advanced BS digital broadcasting”, Journal of the Institute of Image Information and Television Engineers, The Institute of Image Information and Television Engineers, Image Information Media vol.62, No.12, December 1, 2008, pp.1997 -2004

  Recently, in addition to the current 2K service by satellite / terrestrial broadcasting and 4K / 8K super high-definition by satellite broadcasting, 4K / 8K super high-definition (hereinafter referred to as next-generation terrestrial broadcasting) by terrestrial broadcasting is expected. However, 4K / 8K Super Hi-Vision (hereinafter referred to as 4K / 8K) has an enormous amount of information. To build a next-generation terrestrial broadcasting network while maintaining a sufficiently high service time rate, noise caused by a poor propagation environment A sufficiently high transmission power that is not buried is required. In satellite broadcasting, non-linear distortion in satellite repeaters and power reduction due to rain attenuation are the main signal degradation factors. In terrestrial broadcasting, signal degradation peculiar to terrestrial propagation such as multipath fading and urban noise occurs. Occur. Therefore, the basic performance of the error correction code in next-generation terrestrial broadcasting is required to have a very high error correction capability that approaches the Shannon limit as much as possible by applying an LDPC code having a long code length. Furthermore, since the method of balancing broadcast quality and service time rate differs depending on the broadcaster, the selection of information bit rate can be changed flexibly by switching multiple coding rates in a timely manner, and at least the above-mentioned advanced satellite It is desirable to prepare options that are equal to or better than the method.

  As coding rate options in next-generation terrestrial broadcasting, the code length is 69120 or 17280 bits, and the coding rates are 2/16, 3/16, 4/16, 5/16, 6/16, and 7/16. , 8/16, 9/16, 10/16, 11/16, 12/16, 13/16, 14/16 in total, 13 types are being studied. While this coding rate number is a sufficiently broader choice than the 11 types adopted in the advanced satellite broadcasting system, it is necessary to design an LDPC code check matrix having performance close to the Shannon limit for each coding rate. is there. Therefore, there is a need for a technique for taking into account the occurrence of signal degradation peculiar to terrestrial propagation in terrestrial broadcasting, and for making a check matrix optimized for the coding rate.

  The present invention relates to an LDPC code rate of 2/16, 4/16, 5/16, and 6/16 for an LDPC code with a code length of 69120 bits, and an LDPC code rate of 2 for an LDPC code with a code length of 17280 bits. / 16, 3/16, 4/16, 5/16, and 6/16, the application of LDPC code as an error correction code for terrestrial broadcasting and the improvement of its performance, An object is to provide an encoder, a decoder, a transmission device, and a reception device.

  In the transmitting apparatus and the receiving apparatus according to the first aspect of the present invention, the encoder and decoder according to the first aspect of the present invention use an LDPC code rate of 2/16, 4/16, 5 / A check matrix initial value table that includes processing related to each of 16 and 6/16 LDPC codes, and further effectively improves the characteristics of each of the LDPC code rates 2/16, 4/16, 5/16, and 6/16 Is used to execute processing related to the LDPC code. Also, the transmitting apparatus and the receiving apparatus according to the first aspect of the present invention perform LDPC code inspection using the parity check matrix initial value tables of the LDPC code rates 2/16, 4/16, 5/16, and 6/16, respectively. The matrix is configured to include a submatrix that has been parity interleaved to produce a bit interleaving function.

  That is, the encoder according to the first aspect of the present invention is an encoder that performs LDPC encoding of digital data using a check matrix unique to each encoding rate, and has an encoding rate of 69120 bits. Each element of the sub-matrix corresponding to the information length corresponding to each of the coding rates 2/16, 4/16, 5/16, and 6/16 is set as an initial value in a parity check matrix initial value table that is predetermined every time. And means for performing LDPC coding using a parity check matrix including a partial matrix configured by periodically arranging a plurality of types of cycles in the column direction.

  In the encoder according to the first aspect of the present invention, the parity check matrix based on the parity check matrix initial value table of each of the coding rates 2/16, 4/16, 5/16, and 6/16 is the partial matrix. A first sub-matrix in which one element is periodically arranged in the column direction at the first cycle number, and one element is periodically arranged at a second cycle number different from the first cycle number. And a second submatrix arranged in the direction.

  In the encoder according to the first aspect of the present invention, the parity check matrix based on the parity check matrix initial value table of each of the coding rates 2/16, 4/16, 5/16, and 6/16 is the first matrix. And a third sub-matrix that is parity interleaved by shifting in the row direction every cycle number and periodically arranging one element in the column direction at the second cycle number.

  In the encoder of the first aspect according to the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 1) of the coding rate 2/16 indicating the initial value of is composed of the following table.

  In the encoder of the first aspect according to the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 2) having the coding rate of 4/16 indicating the initial value of is composed of the following table.

  In the encoder of the first aspect according to the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 3) of the coding rate 5/16 indicating the initial value of is composed of the following table.

  In the encoder of the first aspect according to the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 4) of the coding rate 6/16 indicating the initial value of is composed of the following table.

  The decoder according to the first aspect of the present invention is characterized by LDPC decoding the data encoded by the encoder according to the first aspect of the present invention based on the check matrix.

  Moreover, the transmitter of the 1st aspect by this invention is provided with the encoder of the 1st aspect by this invention, It is characterized by the above-mentioned.

  The receiving device according to the first aspect of the present invention includes the decoder according to the first aspect of the present invention.

  Furthermore, in the transmitting apparatus and the receiving apparatus according to the second aspect of the present invention, the encoder and decoder according to the second aspect of the present invention are LDPC code rates 2/16, 3/16 for LDPC codes having a code length of 17280 bits. 4/16, 5/16, and 6/16 processing for each LDPC code, and the characteristics of each LDPC code rate 2/16, 3/16, 4/16, 5/16, and 6/16 The processing related to the LDPC code is executed using the parity check matrix initial value table that is effectively improved. Also, the transmitting apparatus and the receiving apparatus according to the second aspect of the present invention use the parity check matrix initial value tables of the LDPC code rates 2/16, 3/16, 4/16, 5/16, and 6/16, respectively. The parity check matrix of the LDPC code is configured to include a partial matrix subjected to parity interleaving in order to generate a bit interleaving function.

  That is, the encoder according to the second aspect of the present invention is an encoder that performs LDPC encoding of digital data using a check matrix unique to each encoding rate, and has an encoding rate with a code length of 17280 bits. The initial value of the parity check matrix initial value table defined for each is used as the initial value, and the partial matrix corresponding to the information length corresponding to each of the coding rates 2/16, 3/16, 4/16, 5/16, 6/16 It is characterized by comprising means for performing LDPC encoding using a parity check matrix including a partial matrix configured by arranging one element periodically in the column direction with a plurality of types of cycles.

  In the encoder according to the second aspect of the present invention, a parity check matrix based on a parity check matrix initial value table of each of the coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 is: As the partial matrix, a first partial matrix in which elements of 1 are periodically arranged in the column direction at a first cycle number, and a periodicity of 1 at a second cycle number different from the first cycle number. And a second sub-matrix arranged in the column direction.

  In the encoder according to the second aspect of the present invention, a parity check matrix based on a parity check matrix initial value table of each of the coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 is: , Further including a third submatrix that is parity-interleaved by shifting in the row direction every first cycle number and periodically arranging one element in the column direction in the second cycle number. Features.

  In the encoder according to the second aspect of the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 5) of the coding rate 2/16 indicating the initial value of is composed of the following table.

  In the encoder according to the second aspect of the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 6) having the coding rate of 3/16 indicating the initial value is composed of the following table.

  In the encoder according to the second aspect of the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 7) of the coding rate 4/16 indicating the initial value of the following is composed of the following tables.

  In the encoder according to the second aspect of the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 8) of the coding rate 5/16 indicating the initial value of is composed of the following table.

  In the encoder according to the second aspect of the present invention, when the first partial matrix is a partial matrix A, the second partial matrix is a partial matrix C, and the third partial matrix is a partial matrix D. The parity check matrix initial value table (Table 9) of the coding rate 6/16 indicating the initial value of is composed of the following table.

  The decoder according to the second aspect of the present invention is characterized in that the data encoded by the encoder according to the second aspect of the present invention is subjected to LDPC decoding based on the parity check matrix.

  Moreover, the transmission apparatus according to the second aspect of the present invention includes the encoder according to the second aspect of the present invention.

  A receiving apparatus according to the second aspect of the present invention includes the decoder according to the second aspect of the present invention.

  According to the present invention, it is possible to improve the performance of the LDPC code and improve the frequency utilization efficiency even in a very poor noise environment in terrestrial broadcasting.

It is a block diagram which shows roughly only the main components of the transmitter in the transmission system of one Example by this invention. It is a block diagram which shows roughly only the main components of the receiver in the transmission system of one Example by this invention. (A), (b) is a figure which shows the structure of the transmission frame in the transmission system of the LDPC code rate 2/16 of one Example which concerns on the LDPC code of code length 69120 bits by this invention, respectively. It is a figure which shows the check matrix H of LDPC code rate 2/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix B of the LDPC code rate 2/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix I of the LDPC code rate 2/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix A of the LDPC code rate 2/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix C of the LDPC code rate 2/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix D of the LDPC code rate 2/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of applying QPSK modulation of LDPC code rate 2/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the difference with C / N which achieves the Shannon limit at the time of QPSK modulation application of the LDPC code rate 2/16 concerning the LDPC code of code length 69120 bits by this invention. (A), (b) is a figure which shows the structure of the transmission frame in the transmission system of the LDPC code rate 4/16 of one Example concerning the LDPC code of code length 69120 bits by this invention, respectively. It is a figure which shows the check matrix H of the LDPC code rate 4/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix B of LDPC code rate 4/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix I of the LDPC code rate 4/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix A of the LDPC code rate 4/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix C of the LDPC code rate 4/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix D of the LDPC code rate 4/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of QPSK modulation of LDPC code rate 4/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the difference with C / N which achieves the Shannon limit at the time of QPSK modulation application of the LDPC code rate 4/16 concerning the LDPC code of code length 69120 bits by this invention. (A), (b) is a figure which shows the structure of the transmission frame in the transmission system of LDPC code rate 5/16 of one Example which concerns on the LDPC code of code length 69120 bits by this invention, respectively. It is a figure which shows the check matrix H of LDPC code rate 5/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix B of LDPC code rate 5/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix I of the LDPC code rate 5/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix A of LDPC code rate 5/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix C of LDPC code rate 5/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix D of the LDPC code rate 5/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of the QPSK modulation of LDPC code rate 5/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the difference with the Shannon limit at the time of applying QPSK modulation of LDPC code rate 5/16 concerning the LDPC code of code length 69120 bits by this invention. (A), (b) is a figure which shows the structure of the transmission frame in the transmission system of the LDPC code rate 6/16 of one Example which concerns on the LDPC code of code length 69120 bits by this invention, respectively. It is a figure which shows the check matrix H of the LDPC code rate 6/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix B of the LDPC code rate 6/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix I of the LDPC code rate 6/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix A of the LDPC code rate 6/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix C of the LDPC code rate 6/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the partial matrix D of the LDPC code rate 6/16 which concerns on the LDPC code of code length 69120 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of the QPSK modulation of LDPC code rate 6/16 concerning the LDPC code of code length 69120 bits by this invention. It is a figure which shows the difference with C / N which achieves the Shannon limit at the time of QPSK modulation application of the LDPC code rate 6/16 concerning the LDPC code of code length 69120 bits by this invention. (A), (b) is a figure which shows the structure of the transmission frame in the transmission system of the LDPC code rate 2/16 of one Example which concerns on the LDPC code of code length 17280 bits by this invention, respectively. It is a figure which shows the check matrix H of LDPC code rate 2/16 concerning the LDPC code of code length 17280 bits by this invention. It is a figure which shows the partial matrix B of the LDPC code rate 2/16 which concerns on the LDPC code of code length 17280 bits by this invention. It is a figure which shows the partial matrix I of LDPC code rate 2/16 concerning the LDPC code of code length 17280 bits by this invention. It is a figure which shows the partial matrix A of the LDPC code rate 2/16 which concerns on the LDPC code of code length 17280 bits by this invention. It is a figure which shows the partial matrix C of the LDPC code rate 2/16 which concerns on the LDPC code of code length 17280 bits by this invention. It is a figure which shows the partial matrix D of the LDPC code rate 2/16 which concerns on the LDPC code of code length 17280 bits by this invention. It is a figure which compares and shows the parameter which concerns on each of LDPC code rate 2/16, 3/16, 4/16, 5/16, 6/16 concerning the LDPC code of code length 17280 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of applying QPSK modulation of LDPC code rate 2/16 concerning the LDPC code of code length 17280 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of applying QPSK modulation of LDPC code rate 3/16 concerning the LDPC code of code length 17280 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of the QPSK modulation of LDPC code rate 4/16 concerning the LDPC code of code length 17280 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of QPSK modulation of LDPC code rate 5/16 concerning the LDPC code of the code length 17280 bits by this invention. It is a figure which shows the C / N vs. BER characteristic at the time of the QPSK modulation of LDPC code rate 6/16 concerning the LDPC code of code length 17280 bits by this invention. The C / C achieves the Shannon limit when the QPSK modulation is applied to each of the LDPC code rates 2/16, 3/16, 4/16, 5/16, and 6/16 according to the LDPC code having a code length of 17280 bits according to the present invention. It is a figure which shows the difference with N.

  Hereinafter, a transmission apparatus 1 and a reception apparatus 2 in a transmission system according to an embodiment of the present invention will be described with reference to the drawings. A transmission system according to an embodiment of the present invention includes a transmitter 1 shown in FIG. 1 assuming a next-generation terrestrial broadcast transmission system and a receiver 2 shown in FIG. 2, and an LDPC code used in the next-generation terrestrial broadcast transmission system. Is optimized as a forward error correction code.

  First, with reference to FIG. 1, the transmission apparatus 1 of one Example by this invention is demonstrated.

[Transmitter]
FIG. 1 is a block diagram schematically showing only main components of a transmission apparatus 1 according to an embodiment of the present invention. The transmission apparatus 1 includes a frame generation unit 111, an energy spreading unit 112, a BCH encoding unit 113, an LDPC encoding unit 114, and a modulation unit 115. When transmitting an input bit string of a main signal, the transmission apparatus 1 is shown in FIG. A series of processing from generation of the signal of the transmission frame shown to generation of the modulation signal is performed. Hereinafter, the LDPC encoding unit 114 is also simply referred to as an encoder. The transmission apparatus 1 also includes a TMCC generation unit 12 as means for generating a TMCC signal including parameters related to transmission such as a modulation scheme and a coding rate and transmitting the TMCC signal before the main signal. The TMCC generation unit 12 is connected by a configuration different from the main signal processing unit 11 that performs signal processing of the main signal, and transmits the TMCC signal to the main signal generated from the transmission frame generation unit 111 by time division multiplexing. Thus, it is possible to transmit parameters related to transmission to the receiving device 2 independently of the main signal. In addition, the TMCC generation unit 12 sets an LDPC coding rate (hereinafter also simply referred to as “coding rate”) and a modulation scheme specified by the TMCC signal to the LDPC coding unit 114 and the modulation unit 115 described later. Has the function to specify. Hereinafter, each component of the transmission apparatus 1 illustrated in FIG. 1 will be described.

  Based on the transmission frame configuration corresponding to the LDPC coding rate, the transmission frame generation unit 111 divides the input bit string of the main signal into a predetermined length and generates a transmission frame that enables LDPC coding. For example, for the LDPC coding rate 2/16, as shown in FIG. 3, the input bit string of the main signal is divided every 8640 bits as the information bit length, and is output to the subsequent functional block each time.

[LDPC code with a code length of 69120 bits]
First, with reference to FIGS. 3 to 38, encoders and decoders for LDPC code rates 2/16, 4/16, 5/16, and 6/16 in an LDPC code having a code length of 69120 bits will be described. To do.

(Code length 69120 bits, LDPC coding rate 2/16 transmission frame configuration)
FIGS. 3A and 3B show the structure of a transmission frame in an LDPC code rate 2/16 transmission system according to an embodiment of an LDPC code having a code length of 69120 bits according to the present invention. In particular, FIG. 3A shows the structure of a transmission frame when only an LDPC code having an LDPC coding rate of 2/16 is used as an error correction code, and FIG. 3B shows an error correction code as an error correction code. The structure of a transmission frame in the case of using a concatenated code including a BCH code as an outer code and an LDPC code having an LDPC code rate of 2/16 as an inner code is shown. The transmission frames shown in FIGS. 3A and 3B are assumed to be transmission frames based on LDPC codes used in the next-generation terrestrial broadcasting transmission system.

  First, the transmission frame shown in FIG. 3A is composed of information bits and LDPC parity satisfying the LDPC coding rate 2/16. The transmission apparatus 1 according to an embodiment of the present invention performs encoding and modulation by using the transmission frame configuration shown in FIG. Then, the receiving device 2 (see FIG. 2; details will be described later) of the embodiment according to the present invention performs demodulation and decoding of the error correction code based on this transmission frame configuration.

  The transmission frame shown in FIG. 3 (b) is composed of information bits, BCH parity, and LDPC parity as a modification of FIG. 3 (a), and is similar to the transmission frame shown in FIG. 3 (a). The present invention is applicable to the transmission device 1 and the reception device 2 according to the embodiment. In FIG. 3B, K_bch corresponds to the parity bit length of the BCH code. As an example of the outer code, a case where a BCH code that can be used in the advanced satellite broadcasting system is applied is shown, and K_bch is 192 bits. BCH parity is basically handled as a part of information bits and has a role of protecting minor bit errors that cannot be corrected by an LDPC code. When the LDPC parity length is equal, FIGS. 3A and 3B have the same LDPC code correction capability. However, since most of the error correction capability depends on the LDPC code, the description will mainly be made on the assumption of the transmission frame shown in FIG.

  As shown in FIG. 3A, in the case of LDPC coding rate 2/16, the transmission frame length assuming the next-generation terrestrial broadcasting transmission system corresponds to 69120 bits which is the LDPC code length. The 69120 bits are composed of an integral multiple of 360 and can be divided by 360 × 192. Further, since the information bit length is 8640 bits and 8640/69120 = 2/16, this transmission frame satisfies the LDPC coding rate 2/16. Moreover, since the code length 69120 bits is sufficiently longer than the LDPC code length 44880 bits in the advanced satellite broadcasting system, an error correction capability closer to the Shannon limit can be expected.

  As shown in FIG. 1, the energy spreading unit 112 performs energy spreading (bit randomization) on the output bit string of the transmission frame generating unit 111. This is realized by generating pseudo-random “1” and “0” patterns using M-sequences and adding this with data in the slot by MOD2. As a result, “1” or “0” does not continue, so that the synchronous reproduction can be stabilized in the receiving apparatus 2 described later.

  The BCH encoding unit 113 is an error correction encoding process provided as necessary as an outer code, and performs BCH encoding on predetermined data. The encoding process of BCH encoding can be the same as that specified in Non-Patent Document 2, and the details thereof are omitted. When the transmission frame configuration shown in FIG. 3A is used, the processing of the BCH encoding unit 113 is unnecessary in the transmission apparatus 1 shown in FIG.

  The LDPC encoding unit 114 is input through predetermined data (or BCH encoding unit 113) input via the energy spreading unit 112 based on a predetermined encoding rate specified by the TMCC signal generated by the TMCC generation unit 12. (BCH encoded data) is subjected to LDPC encoding. Details of LDPC encoding using an LDPC code check matrix at the LDPC encoding rate 2/16 of the encoder (LDPC encoding unit 114) according to the present invention will be described later.

  The modulation unit 115 performs quadrature modulation based on a predetermined modulation method specified by the TMCC signal generated by the TMCC generation unit 12, and generates a modulation signal. Examples of the modulation method include BPSK (π / 2 shift BPSK (Binary Phase Shift Keying)), QPSK (Quadrature Phase Shift Keying), 8PSK, 16APSK (Amplitude and Phase-Shift Keying) (or 16QAM (Quadrature Amplitude Modulation)). , 32APSK (32QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and the like.

  Next, with reference to FIG. 2, the receiver 2 of one Example by this invention is demonstrated.

[Receiver]
FIG. 2 is a block diagram schematically showing only main components of the receiving apparatus 2 according to an embodiment of the present invention. The receiving apparatus 2 includes a main signal processing unit 21 that performs signal processing of a main signal including a demodulation unit 211, an LDPC decoding unit 212, a BCH decoding unit 213, and an energy despreading unit 214, and a TMCC demodulation / decoding unit 22. I have.

  The demodulator 211 performs quadrature demodulation on the input modulation signal, and outputs the demodulated IQ signal (the quadrature signal of the in-phase component I and the quadrature component Q) to the LDPC decoding unit 212. The TMCC demodulator / decoder 22 demodulates and decodes the TMCC signal prior to the demodulator 211 and designates the modulation scheme applied to the modulation of the main signal to the demodulator 211. For the LDPC decoding unit 212 described later, a coding rate applied to LDPC coding of the main signal is designated. The encoding rate when the LDPC encoding process is performed by the encoder (LDPC encoding unit 114) according to the present invention corresponds to 2/16, 4/16, 5/16, and 6/16.

  The LDPC decoding unit 212 is configured as a decoder for LDPC codes. The IQ signal is input from the demodulation unit 211 and the modulation scheme and LDPC coding rate information detected by the TMCC demodulation / decoding unit 22 are input. Then, decoding according to a predetermined modulation scheme and LDPC coding rate is performed. The details of LDPC decoding using a parity check matrix at each of the LDPC coding rates 2/16, 4/16, 5/16, and 6/16 of the encoder (LDPC encoder 114) according to the present invention are as follows. It will be described later.

  The BCH decoding unit 213 performs decoding on the signal BCH encoded by the BCH encoding unit 113 of the transmission apparatus 1. Note that when the configuration of the transmission frame shown in FIG. 3A is used, the processing of the BCH decoding unit 213 is unnecessary in the receiving apparatus 2 shown in FIG.

  The energy despreading unit 214 performs the energy despreading process by adding the same pseudorandom code again with MOD2 in order to restore the process in which the pseudorandom code is added by MOD2 in the energy spreading unit 112 of the transmission apparatus 1. As a result, the signal processing unit 21 in the receiving device 2 restores the output bit string corresponding to the input bit string of the main signal transmitted from the transmitting device 1 and outputs it to the outside.

  As described above, the transmission apparatus 1 and the reception apparatus 2 according to an embodiment of the present invention can freely change the modulation scheme and the coding rate using the transmission frame corresponding to the error correction code based on the LDPC code having a long code length. Can be combined. Therefore, it is possible to efficiently transmit MPEG-2 TS or other digital data stream transmitted as a main signal.

  Next, for each of the LDPC coding rates 2/16, 4/16, 5/16, and 6/16, the encoder (LDPC encoder 114) and decoder (LDPC decoder 212) according to the present invention. Each process will be described in turn.

  First, the process of the encoder (LDPC encoder 114) at an LDPC code rate of 2/16 according to an embodiment relating to an LDPC code having a code length of 69120 bits will be described.

(Processing of encoder at code length 69120 bits and LDPC code rate 2/16)
The encoder according to the present embodiment (LDPC encoding unit 114) generates a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. To generate LDPC code parity. FIG. 4 shows a basic configuration of parity check matrix H at LDPC coding rate 2/16. The length in the row direction of parity check matrix H corresponds to the LDPC code length, and LDPC code length N = 69120 is set. Since the coding rate of the parity check matrix is 2/16, the length in the column direction of the parity check matrix H corresponds to the LDPC parity length, and the LDPC parity length P = 60480 bits.

  In FIG. 4, partial matrices A, C, and D are partial matrices configured using the parity check matrix initial value table shown in Table 1 above, and the LDGM structure (FIG. 5) is applied to the partial matrix B. . The row weight of the LDGM structure (number of 1 in the row direction of the check matrix) is 1 for the first row, the remaining row weights are all 2, and the column weights are 2 for all columns (however, only the last column is 1). It is a matrix. The size of the submatrix B is 1800 bits in both the row direction and the column direction. Further, a diagonal matrix (FIG. 6) is applied to the submatrix I. The row weights of the diagonal matrix are all 1. The size of the submatrix I is 58680 bits in both the row direction and the column direction. The submatrix O corresponds to a zero matrix.

  As shown in FIG. 7, the size of the submatrix A is 1800 bits (rows) × 8640 bits (columns).

  The size of the submatrix C is 58680 bits (rows) × 8640 bits (columns) as shown in FIG.

  Further, the size of the submatrix D is 58680 bits (rows) × 1800 bits (columns) as shown in FIG.

In any of the partial matrices A, C, and D, since the sizes of these partial matrices are finite, the position of 1 in the parity check matrix is calculated based on the following equation (1).
H _q−j = mod {(h _i−j + mod ((q−1), 360)) × Q), P} (1)
Here, _i in h _i−j is a row number in the parity check matrix initial value table, and _j in h _i− j is a column number in the parity check matrix initial value table. H _q−j indicates the row number of 1 in the q column of the check matrix H. _J of H _q-j indicates the order of the number of elements of the column weight. Therefore, for a column weight of 9, j = 1-9. q = 1 uses the first row of the parity check matrix initial value table. Mod (x, y) means a remainder obtained by dividing x by y. Q in equation (1) is the number of cycles having a value determined for each coding rate, and Q is obtained by equation (2).

  Q = row size of each submatrix / 360 (2)

  Therefore, in the LDPC coding rate 2/16 of the present embodiment, in the case of the submatrix A, Q = 5 (first cycle number Q1), the submatrix C, and the submatrix D, Q = 163 (second Cycle number Q2).

  Hereinafter, a method for generating a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O at LDPC coding rate 2/16 will be described in more detail.

  First, the submatrix A (FIG. 7) will be described. In order to form the partial matrix A, the encoder (LDPC encoding unit 114) of the present embodiment reads a numerical value from a part of the parity check matrix initial value table shown in Table 1 above, and The position of 1 in the region of the matrix A is periodically arranged. In the parity check matrix initial value table shown in Table 1, numerical values of 29 in the column direction and 21 at the maximum in the row direction are described. This numerical value corresponds to the first position (initial value) of 1 of the parity check matrix used in the partial matrices A, C, and D. That is, the first position of 1 in the partial matrices A, C, and D in the check matrix H shown in FIG. 4 is designated by the numerical coordinates hi-j (numerical value) of the i-th row and j-th column in Table 1. As an example, in FIG. 7, h1-1 (743) corresponds to placing 1 in the first column of the submatrix A in the 743th row in the check matrix H, and h1-2 (1242) is the submatrix. This corresponds to arranging 1 in the first column of A in the 1242th row in the check matrix H. H2-1 (247) arranges 1 of the 361th column of the submatrix A in the 247th row of the check matrix H, and h2-2 (723) sets 1 of the 361th column of the submatrix A to the check matrix. This corresponds to the arrangement in line 723 in H.

  Based on the above relationship, as shown in FIG. 7, the encoder (LDPC encoding unit 114) of this embodiment arranges 1 for every 360 columns of the submatrix A from the parity check matrix initial value table in Table 1. All of the 24 rows and j columns (3 columns) of numerical coordinates hi-j (numerical values) for designating the row position to be performed are read out, and 1 is first assigned to the position in the designated submatrix A. 1 bit assigned to 1 is used as a reference and 1 bit is shifted rightward in the row direction, and 1 is repeatedly assigned to the position shifted downward in the column direction at the first cycle number Q1 = 5 (5 bits). Thus, the partial matrix A in the check matrix H is configured.

<Numerical coordinates hi-j (numerical value) for submatrix A of parity check matrix initial value table in Table 1>
First line: h1-1 (743) to h1-3 (1354)
2nd line: h2-1 (247) to h2-3 (965)
3rd line: h3-1 (97) to h3-3 (1430)
...
24th line: h24-1 (789) to h24-3 (1730)

  In this way, the numerical values of 24 rows in the numerical coordinates hi-j (numerical value) for the submatrix A in Table 1 (each row of 24 rows corresponds to the first column for every 360 columns of the submatrix A) is 1 column. By reading out each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix A) and repeating the first cycle number Q1 = 5 shift as shown in FIG. It is possible to designate the position of 1 of the submatrix A in the check matrix H corresponding to 24 = 8640 bits (columns). The number of rows of the submatrix A is 360 × Q1 = 1800, and the size of the submatrix A is 8640 bits in the row direction and 1800 bits in the column direction.

  Next, the partial matrix C (FIG. 8) will be described. In order to form the partial matrix C, the encoder (LDPC encoding unit 114) of the present embodiment reads a numerical value from a part of the parity check matrix initial value table shown in Table 1 above, and The position of 1 in the region of the matrix C is periodically arranged. In the parity check matrix initial value table shown in Table 1, numerical values of 29 in the column direction and 21 at the maximum in the row direction are described. The difference between the submatrix C and the submatrix A is the read position in the parity check matrix initial value table and the number of cycles.

  As shown in FIG. 8, the encoder (LDPC encoder 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix C is arranged from the parity check matrix initial value table in Table 1. All of the 24 rows and j columns (maximum 18 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the designated submatrix C, and the first assigned 1 4 by shifting 1 bit rightward in the row direction with respect to the position and assigning 1 to the position shifted downward in the column direction at the second cycle number Q2 = 163 (163 bits). A submatrix C in the check matrix H is constructed.

<Numerical coordinates hi-j (numerical value) for submatrix C of parity check matrix initial value table in Table 1>
First line: h1-4 (5424) to h1-21 (56501)
2nd line: h2-4 (2900) to h2-21 (60274)
3rd line: h3-4 (8209) to h3-21 (57501)
...
7th line: h7-4 (3142) to h3-21 (57058)
8th line: h8-4 (2072) to h8-20 (60322)
...
24th line: h24-4 (7596) to h24-20 (60025)

  In this way, the numerical values of 24 rows in the numerical coordinates hi-j (numerical value) for the submatrix C in Table 1 (each row of the 24 rows corresponds to the first column for every 360 columns of the submatrix C) is 1 column. 360 × is read out every time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix C), and the second cycle number Q2 = 163 shift is repeated as shown in FIG. It is possible to designate the position of 1 in the submatrix C in the check matrix H corresponding to 24 = 8640 bits (columns). The number of rows of the submatrix C is 360 × Q2 = 58680, and the size of the submatrix C is 8640 bits in the row direction and 58680 bits in the column direction.

  Next, the partial matrix D (FIG. 9) will be described. In order to form the partial matrix D, the encoder (LDPC encoding unit 114) of the present embodiment forms part of the parity check matrix initial value table shown in Table 1 above (from Table 25, line 25 to 29). A numerical value is read from (line), and the position of 1 in the region of the partial matrix D in the check matrix H is periodically arranged. However, the sub-matrix D applies the same second cycle number Q2 = 163 as that of the sub-matrix C. However, the sub-matrix C differs from the sub-matrix C in the read cycle in the parity check matrix initial value table in the first cycle number Q1 = By using a bit shift in the row direction corresponding to 5, parity interleaving is applied.

  As shown in FIG. 9, the encoder (LDPC encoder 114) of the present embodiment designates the row position where 1 is assigned for every 360 columns of the submatrix D from the parity check matrix initial value table in Table 1. All of the 5 rows and j columns (17 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the specified submatrix D, and this first assigned position of 1 The first cycle number Q1 = 5 bits is shifted to the right in the row direction with reference to, and 1 is repeatedly assigned to the position shifted downward in the column direction with the second cycle number Q2 = 163 (163 bits). Thus, the partial matrix D in the check matrix H in FIG. 4 is configured.

<Numerical coordinates hi-j (numerical value) for submatrix D of parity check matrix initial value table in Table 1>
25th line: h25-1 (15518) to h25-17 (56990)
26th line: h26-1 (4450) to h26-17 (57923)
27th line: h27-1 (4716) to h27-17 (59748)
28th line: h28-1 (2114) to h28-17 (59654)
29th line: h29-1 (5752) to h29-17 (57376)

  As described above, the parity check matrix initial value table reading method to which parity interleaving is applied is a different reading method from the partial matrices A and C, and is 5 in the numerical coordinates hi-j (numerical value) for the partial matrix D in Table 1. Read the numerical values of the rows (each row of these 5 rows corresponds to the first 5 columns of the submatrix D) for each column (the numerical value for each column corresponds to the row position of the first 5 columns of the submatrix D). The readout of one row of the numerical coordinates hi-j (numerical value) for the submatrix D in Table 1 is taken as one set. Then, as shown in FIG. 9, 360 right shifts Q1 = 5 bits corresponding to the first cycle number and Q2 = 163 minutes downward shift corresponding to the second cycle number are repeated 360 times. It becomes possible to designate the position of 1 of the submatrix D in the check matrix H corresponding to x5 = 1800 bits (columns). The number of rows of the submatrix D is 360 × Q2 = 58680, and the size of the submatrix D is 1800 bits in the row direction and 58680 bits in the column direction.

That is, the relationship between the parity check matrix initial value table in the partial matrix D shown in Table 1 and the column numbers in the parity check matrix H is shown below.
The numerical value in the 25th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 8641st column (that is, the first column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 26th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 8642th column (that is, the second column of the submatrix D) in the parity check matrix H. Line position) is described.
The value in the 27th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 8643th column (that is, the third column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value of the 28th row in the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 8644th column (that is, the fourth column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 29th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 8645th column (that is, the fifth column of the submatrix D) in the parity check matrix H. Line position) is described.

  In FIG. 9, the numerical value read from the 25th row of the parity check matrix initial value table is shifted by Q2 = 163 every Q1 = 5 bits. By repeating this operation 360 times, the position of 1 in the submatrix D is determined for a total of 360 columns. Similarly, the numerical value read from the 26th row of the parity check matrix initial value table is also shifted by Q2 = 163 every Q1 = 5 bits, and the position of 1 in the submatrix D is determined for a total of 360 columns. . Thereafter, the same process is repeated in the 27th, 28th, and 29th rows, thereby determining the position of 1 in the submatrix D corresponding to 360 columns × 5 sets = 1800 bits. Therefore, the size of the submatrix D is 1800 bits in the row direction and 58680 bits in the column direction. In this way, by including in the check matrix H the partial matrix D to which the parity interleaving that shifts Q2 for each Q1 is applied, the generation of the cycle 4 that occurs between the partial matrix B and the partial matrix B that is connected to the higher rank with respect to the partial matrix D Thus, it is possible to improve the decoding performance of the LDPC code. That is, one of the causes of transmission characteristic deterioration in the LDPC code is the generation of an error floor. As the generation factor of this error floor, if one arrangement included in the check matrix H has many shape arrangements of cycle 4, for example, an error occurs. It has been found that floors are more likely to occur. Therefore, a check matrix H including a partial matrix D is used as a means for solving this problem.

  The parity check equation (3) is used to check the LDPC parity using the parity check equation (3) using the parity check matrix H that is a set matrix of the partial matrices A, B, C, D, I, and O at the LDPC coding rate 2/16 obtained by the above processing. Is calculated. In the case of coding rate 2/16, since the information bit length is 8640 bits, the parity check based on the LDGM structure is applied from the first row to the 1800th row of the parity check matrix H in the parity check equation. The parity calculation based on the diagonal structure is applied from the 1801st line to the 60480th line.

H · C ^T = 0 (3)

  The encoder (LDPC encoder 114) of this embodiment has 69120 bits as a basic unit, and 69120 is a value divisible by the values 1, 2, 3, 4, 5, 6, 8, 10, 12. is there. Therefore, when applied as a functional block of the transmission apparatus 1 shown in FIG. 1, the encoder of the present embodiment can use a very wide variety of modulation multilevel numbers. For example, BPSK (π / 2 shift BPSK) ), QPSK, 8PSK, 16APSK (16QAM), 32APSK (32QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and the like. Therefore, the transmission apparatus 1 according to the present embodiment can perform signal transmission combining a very flexible modulation scheme and coding rate. Note that the parity check matrix initial value table for the parity check matrix used for LDPC encoding can be transmitted from the transmission apparatus 1 to the reception apparatus 2 as auxiliary information, or may be held in advance by the reception apparatus 2. . Alternatively, the check matrix itself can be transmitted from the transmission apparatus 1 to the reception apparatus 2, or the check matrix itself may be held in advance by the reception apparatus 2.

  Next, the process of the decoder (LDPC decoding unit 212) at the LDPC coding rate 2/16 of this embodiment will be described.

(Processing of decoder at code length 69120 bits and LDPC coding rate 2/16)
The decoder (LDPC decoding unit 212) of this embodiment performs decoding processing of an LDPC code using a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. . In the following description, for the sake of simplicity, the modulation method is assumed to be BPSK.

Decoder of the present embodiment (LDPC decoder 212) first calculates the log likelihood ratio lambda _n to (n = from 1 to 69120) on the basis of the transmitted symbols _{x n} and the received symbol _{y n.} It is a natural logarithm of the ratio of the probability of the bit 0 Send the log likelihood ratio lambda _n 1, represented by formula (4) using the transmission symbols x _n and the received symbol y _n.

λ _n = ln {P (y _n | x _n = 0) / P (y _n | x _n = 1)} (4)

  An LDPC decoding method such as a sum-product decoding method is performed using the log likelihood ratio obtained by Expression (4) and a check matrix H (corresponding to FIG. 4) corresponding to the coding rate 2/16 described above. The number of iteration decoding is an arbitrary value. In LDPC decoding, various means such as a min-sum decoding method have been proposed in addition to the sum-product decoding method. Various methods for maximizing the likelihood ratio using a parity check matrix are used in the present invention. This is applicable to such LDPC decoding.

FIG. 10 shows C / N versus BER characteristics (computer simulation) in QPSK modulation for LDPC coding rate 2/16 according to the parity check matrix initial value table (Table 1). FIG. 10 shows the result after error correction using a BCH code (correction capability 12 bits) based on Non-Patent Document 2 (ARIB STD-B44). The decoding algorithm is a sum-product decoding method (for example, non-patent document). 1). The number of decoding iterations of the sum-product decoding method is 50 times. FIG. 11 shows a comparison result between C / N that achieves the Shannon limit of QPSK at a coding rate of 2/16 and C / N at BER = 1 × 10 ⁻⁷ obtained from FIG. From FIG. 11, it can be seen that decoding performance approaching the Shannon limit can be obtained by applying the encoder, decoder, transmitter 1 and receiver 2 based on this parity check matrix. Therefore, by adopting the check matrix H based on Table 1, it is possible to obtain a preferable transmission performance that is less than 1 dB with respect to the Shannon limit that is difficult in the current digital terrestrial broadcasting.

  In the above-described example, mainly, a transmission frame configuration related to LDPC code rate 2/16, a check matrix H based on a parity check matrix initial value table (Table 1) related to LDPC code rate 2/16, and an effect of improving the transmission performance thereof However, the LDPC encoding unit 114 in the transmission device 1 shown in FIG. 1 and the LDPC decoding unit 212 in the reception device 2 shown in FIG. 2 are each of LDPC code rates 4/16, 5/16, and 6/16. The same can be configured.

  Hereinafter, a transmission frame configuration according to each of LDPC code rates 4/16, 5/16, and 6/16, a parity check matrix H based on a parity check matrix initial value table according to each LDPC code rate, and an effect of improving the transmission performance thereof Will be described in order.

(Transmission frame configuration of code length 69120 bits, LDPC coding rate 4/16)
FIGS. 12 (a) and 12 (b) show the structure of a transmission frame in an LDPC code rate 4/16 transmission system according to an embodiment of an LDPC code having a code length of 69120 bits according to the present invention. In particular, FIG. 12A shows the configuration of a transmission frame when using only an LDPC code having an LDPC coding rate of 4/16 as an error correction code, and FIG. 12B shows an error correction code as an error correction code. The structure of a transmission frame in the case of using a concatenated code composed of a BCH code as an outer code and an LDPC code having an LDPC code rate of 4/16 as an inner code is shown. The transmission frames shown in FIGS. 12A and 12B are assumed to be transmission frames based on LDPC codes used in the next-generation terrestrial broadcasting transmission system.

  First, the transmission frame shown in FIG. 12A is composed of information bits and LDPC parity that satisfy the LDPC coding rate 4/16. The transmission apparatus 1 according to an embodiment of the present invention performs encoding and modulation by using the transmission frame configuration shown in FIG. The receiving device 2 according to an embodiment of the present invention performs demodulation and decoding of an error correction code based on this transmission frame configuration.

  The transmission frame shown in FIG. 12 (b) is composed of information bits, BCH parity, and LDPC parity as a modification of FIG. 12 (a), and is similar to the transmission frame shown in FIG. 12 (a). The present invention is applicable to the transmission device 1 and the reception device 2 according to the embodiment. In FIG. 12B, K_bch corresponds to the parity bit length of the BCH code. As an example of the outer code, a case where a BCH code that can be used in the advanced satellite broadcasting system is applied is shown, and K_bch is 192 bits. BCH parity is basically handled as a part of information bits and has a role of protecting minor bit errors that cannot be corrected by an LDPC code. When the LDPC parity lengths are equal, FIGS. 12A and 12B have the same LDPC code correction capability. However, since most of the error correction capability depends on the LDPC code, the description will mainly be made on the assumption of the transmission frame shown in FIG.

  As shown in FIG. 12 (a), the transmission frame length assuming the next generation terrestrial broadcasting transmission system corresponds to 69120 bits which is the LDPC code length. The 69120 bits are composed of an integral multiple of 360 and can be divided by 360 × 192. Further, since the information bit length is 17280 bits and 17280/69120 = 4/16, this transmission frame satisfies the LDPC coding rate 4/16. Moreover, since the code length 69120 bits is sufficiently longer than the LDPC code length 44880 bits in the advanced satellite broadcasting system, an error correction capability closer to the Shannon limit can be expected.

  Next, the processing steps of the encoder (LDPC encoder 114) and decoder (LDPC decoder 212) according to the present invention will be described in order.

  First, the process of the encoder (LDPC encoder 114) at an LDPC encoding rate of 4/16 according to an embodiment will be described.

(Processing of encoder at code length 69120 bits and LDPC code rate 4/16)
The encoder according to the present embodiment (LDPC encoding unit 114) generates a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. To generate LDPC code parity. FIG. 13 shows a basic configuration of parity check matrix H at LDPC coding rate 4/16. The length in the row direction of parity check matrix H corresponds to the LDPC code length, and LDPC code length N = 69120 is set. Since the coding rate of this parity check matrix is 4/16, the length in the column direction of parity check matrix H corresponds to the LDPC parity length, and LDPC parity length P = 51840 bits.

  In FIG. 13, partial matrices A, C, and D are partial matrices configured using the parity check matrix initial value table shown in Table 2 above, and the LDGM structure (FIG. 14) is applied to the partial matrix B. . The row weight of the LDGM structure (number of 1 in the row direction of the check matrix) is 1 for the first row, the remaining row weights are all 2, and the column weights are 2 for all columns (however, only the last column is 1). It is a matrix. The size of the submatrix B is 1800 bits in both the row direction and the column direction. Further, a diagonal matrix (FIG. 15) is applied to the submatrix I. The row weights of the diagonal matrix are all 1. The size of the submatrix I is 50040 bits in both the row direction and the column direction. The submatrix O corresponds to a zero matrix.

  As shown in FIG. 16, the size of the submatrix A is 1800 bits (rows) × 17280 bits (columns).

  The size of the submatrix C is 50040 bits (rows) × 17280 bits (columns) as shown in FIG.

  The size of the submatrix D is 50040 bits (rows) × 1800 bits (columns) as shown in FIG.

  In any of the partial matrices A, C, and D, since the size of these partial matrices is finite, the position of 1 of the parity check matrix is calculated based on the above-described equation (1), and Q in equation (1) is , The number of cycles having a value determined for each coding rate, and Q is obtained by the above-described equation (2).

  Therefore, in the LDPC coding rate 4/16 of the present embodiment, in the case of the submatrix A, Q = 5 (first cycle number Q1), the submatrix C, and the submatrix D, Q = 139 (second Cycle number Q2).

  Hereinafter, a method for generating a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O at an LDPC coding rate of 4/16 will be described in more detail.

  First, the submatrix A (FIG. 16) will be described. In order to form the partial matrix A, the encoder (LDPC encoding unit 114) of the present embodiment reads a numerical value from a part of the parity check matrix initial value table shown in Table 2 above, and The position of 1 in the region of the matrix A is periodically arranged. In the parity check matrix initial value table shown in Table 2, numerical values of 53 in the column direction and up to 13 in the row direction are described. This numerical value corresponds to the first position (initial value) of 1 of the parity check matrix used in the partial matrices A, C, and D. That is, the first position of 1 in the partial matrices A, C, and D in the check matrix H shown in FIG. 13 is designated by the numerical coordinates hi-j (numerical value) of the i-th row and j-th column in Table 2. As an example, in FIG. 16, h1-1 (88) corresponds to arranging 1 in the first column of the submatrix A in the 88th row in the check matrix H, and h1-2 (324) is the submatrix. This corresponds to arranging 1 in the first column of A in the 324th row in the check matrix H. H2-1 (1136) places 1 in the 361th column of the submatrix A in the 1136th row of the check matrix H, and h2-2 (1229) sets 1 in the 361th column of the submatrix A to the check matrix. This corresponds to the arrangement on the 1229th line in H.

  Based on the above relationship, as shown in FIG. 16, the encoder (LDPC encoding unit 114) of the present embodiment arranges 1 for every 360 columns of the submatrix A from the parity check matrix initial value table in Table 2. All the 48 rows and j columns (3 columns) of numerical coordinates hi-j (numerical values) for designating the row position to be designated are read out, and 1 is first assigned to the position in the designated submatrix A. 1 bit assigned to 1 is used as a reference and 1 bit is shifted rightward in the row direction, and 1 is repeatedly assigned to the position shifted downward in the column direction at the first cycle number Q1 = 5 (5 bits). Thus, the partial matrix A in the check matrix H is configured.

<Numerical coordinates hi-j (numerical value) for submatrix A of parity check matrix initial value table in Table 2>
First line: h1-1 (88) to h1-3 (940)
2nd line: h2-1 (1136) to h2-3 (1707)
3rd line: h3-1 (965) to h3-3 (1794)
...
48th line: h48-1 (67) to h48-3 (1246)

  As described above, the numerical values of 48 rows in the numerical coordinates hi-j (numerical values) for the submatrix A in Table 2 (each row of the 48 rows corresponds to the first column for every 360 columns of the submatrix A) is 1 column. By reading out each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix A) and repeating the first cycle number Q1 = 5 shift as shown in FIG. 16, 360 × It is possible to designate the position of 1 of the submatrix A in the check matrix H corresponding to 48 = 17280 bits (columns). The number of rows of the submatrix A is 360 × Q1 = 1800, and the size of the submatrix A is 17280 bits in the row direction and 1800 bits in the column direction.

  Subsequently, the submatrix C (FIG. 17) will be described. In order to form the partial matrix C, the encoder (LDPC encoding unit 114) of the present embodiment reads numerical values from a part of the parity check matrix initial value table shown in Table 2 above, and The position of 1 in the region of the matrix C is periodically arranged. In the parity check matrix initial value table shown in Table 2, numerical values of 53 in the column direction and up to 13 in the row direction are described. The difference between the submatrix C and the submatrix A is the read position in the parity check matrix initial value table and the number of cycles.

  As illustrated in FIG. 17, the encoder (LDPC encoding unit 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix C is arranged from the parity check matrix initial value table in Table 2. All of the 48 rows and j columns (10 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the specified submatrix C, and this first assigned position of 1 13 is repeated by shifting 1 bit to the right in the row direction with reference to, and assigning 1 to the position shifted downward in the column direction at the second cycle number Q2 = 139 (139 bits). A submatrix C in the matrix H is constructed.

<Numerical coordinates hi-j (numerical value) for submatrix C of parity check matrix initial value table in Table 2>
First line: h1-4 (5671) to h1-13 (47570)
2nd line: h2-4 (6181) to h2-13 (51347)
3rd line: h3-4 (3988) to h3-13 (51728)
...
48th line: h48-4 (13092) to h48-13 (48057)

  In this way, the numerical values of 48 rows in the numerical coordinates hi-j (numerical value) for the submatrix C in Table 2 (each row of the 48 rows corresponds to the first column for every 360 columns of the submatrix C) is 1 column. Each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix C), and the second cycle number Q2 = 139 shift is repeated as shown in FIG. It is possible to designate the position of 1 of the submatrix C in the check matrix H corresponding to 48 = 17280 bits (columns). The number of rows of the submatrix C is 360 × Q2 = 50040, and the size of the submatrix C is 17280 bits in the row direction and 50040 bits in the column direction.

  Next, the partial matrix D (FIG. 18) will be described. In order to form the partial matrix D, the encoder (LDPC encoding unit 114) of the present embodiment forms a part of the parity check matrix initial value table shown in Table 2 above (in Table 2, from the 49th line to the 53rd line). A numerical value is read from (line), and the position of 1 in the region of the partial matrix D in the check matrix H is periodically arranged. However, the same number of cycles Q2 = 139 as that of the submatrix C is applied to the submatrix D. However, the difference from the submatrix C is that the first cycle number Q1 = By using a bit shift in the row direction corresponding to 5, parity interleaving is applied.

  As shown in FIG. 18, the encoder (LDPC encoding unit 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix D is arranged from the parity check matrix initial value table in Table 2. All of the 5 rows and j columns (11 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the specified submatrix D, and this first assigned position of 1 The first cycle number Q1 = 5 bits is shifted to the right in the row direction with reference to, and 1 is repeatedly assigned to the position shifted downward in the column direction with the second cycle number Q2 = 139 (139 bits). Thus, the partial matrix D in the check matrix H in FIG. 13 is configured.

<Numerical coordinates hi-j (numerical value) for submatrix D of parity check matrix initial value table in Table 2>
49th line: h49-1 (3009) to h49-11 (45590)
50th line: h50-1 (2479) to h50-11 (48243)
Line 51: h51-1 (6072) to h51-11 (44472)
52nd line: h52-1 (2164) to h52-11 (40143)
Line 53: h53-1 (4094) to h53-11 (49258)

  As described above, the parity check matrix initial value table reading method to which parity interleaving is applied is a different reading method from the partial matrices A and C, and is 5 in the numerical coordinates hi-j (numerical value) for the partial matrix D in Table 2. Read the numerical values of the rows (each row of these 5 rows corresponds to the first 5 columns of the submatrix D) for each column (the numerical value for each column corresponds to the row position of the first 5 columns of the submatrix D). The reading of one row of the numerical coordinates hi-j (numerical value) for the submatrix D in Table 2 is taken as one set. Then, as shown in FIG. 18, 360 right shifts by Q1 = 5 bits corresponding to the first cycle number and Q2 = 139 minutes downward shift corresponding to the second cycle number are repeated 360 times. It becomes possible to designate the position of 1 of the submatrix D in the check matrix H corresponding to x5 = 1800 bits (columns). The number of rows of the submatrix D is 360 × Q2 = 50040, and the size of the submatrix D is 1800 bits in the row direction and 50040 bits in the column direction.

That is, the relationship between the parity check matrix initial value table in the submatrix D shown in Table 2 and the column numbers in the parity check matrix H is shown below.
The numerical value in the 49th row of the parity check matrix initial value table is a value in the first parity check matrix H that repeats at the cycle number Q1 and Q2 of the 17281th column (that is, the first column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 50th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 17282th column (that is, the second column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 51st row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 17283th column (that is, the third column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 52nd row of the parity check matrix initial value table is the first position of 1 in the 17284th column (that is, the fourth column of the submatrix D) in the parity check matrix H (in the first parity check matrix H that repeats with the cycle numbers Q1 and Q2). Line position) is described.
The numerical value in the 53rd row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 17285th column (that is, the fifth column of the submatrix D) in the parity check matrix H. Line position) is described.

  In FIG. 18, the numerical value read from the 49th row of the parity check matrix initial value table is shifted by Q2 = 139 for every Q1 = 5 bits. By repeating this operation 360 times, the position of 1 in the submatrix D is determined for a total of 360 columns. Similarly, the numerical value read from the 50th row of the parity check matrix initial value table is also shifted by Q2 = 139 every Q1 = 5 bits, and the position of 1 in the submatrix D is determined for a total of 360 columns. . Thereafter, the same processing is repeated in the 51st, 52nd, and 53rd rows to determine the position of 1 in the submatrix D corresponding to 360 columns × 5 sets = 1800 bits. Therefore, the size of the submatrix D is 1800 bits in the row direction and 50040 bits in the column direction. In this way, by including in the check matrix H the partial matrix D to which the parity interleaving that shifts Q2 for each Q1 is applied, the generation of the cycle 4 that occurs between the partial matrix B and the partial matrix B that is connected to the higher rank with respect to the partial matrix D Thus, it is possible to improve the decoding performance of the LDPC code. That is, one of the causes of transmission characteristic deterioration in the LDPC code is the generation of an error floor. As the generation factor of this error floor, if one arrangement included in the check matrix H has many shape arrangements of cycle 4, for example, an error occurs. It has been found that floors are more likely to occur. Therefore, a check matrix H including a partial matrix D is used as a means for solving this problem.

  Using the parity check equation (3) described above using the parity check matrix H that is a set matrix of the partial matrices A, B, C, D, I, and O at the LDPC coding rate 4/16 obtained by the above processing, LDPC parity is calculated. In the case of a coding rate of 4/16, the information bit length is 17280 bits. Therefore, in the parity check equation, the parity calculation based on the LDGM structure is applied from the first row to the 1800th row of the parity check matrix H. The parity calculation based on the diagonal structure is applied from the 1801st line to the 51840th line.

  The encoder (LDPC encoder 114) of this embodiment has 69120 bits as a basic unit, and 69120 is a value divisible by the values 1, 2, 3, 4, 5, 6, 8, 10, 12. is there. Therefore, when applied as a functional block of the transmission apparatus 1 shown in FIG. 1, the encoder of the present embodiment can use a very wide variety of modulation multilevel numbers. For example, BPSK (π / 2 shift BPSK) ), QPSK, 8PSK, 16APSK (16QAM), 32APSK (32QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and the like. Therefore, the transmission apparatus 1 according to the present embodiment can perform signal transmission combining a very flexible modulation scheme and coding rate. Note that the parity check matrix initial value table for the parity check matrix used for LDPC encoding can be transmitted from the transmission apparatus 1 to the reception apparatus 2 as auxiliary information, or may be held in advance by the reception apparatus 2. . Alternatively, the check matrix itself can be transmitted from the transmission apparatus 1 to the reception apparatus 2, or the check matrix itself may be held in advance by the reception apparatus 2.

  Next, the process of the decoder (LDPC decoding unit 212) at the LDPC coding rate 4/16 of the present embodiment will be described.

(Processing of decoder at code length 69120 bits and LDPC code rate 4/16)
The decoder (LDPC decoding unit 212) of this embodiment performs decoding processing of an LDPC code using a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. . In the following description, for the sake of simplicity, the modulation method is assumed to be BPSK.

Decoder of the present embodiment (LDPC decoder 212) first calculates the log likelihood ratio lambda _n to (n = from 1 to 69120) on the basis of the transmitted symbols _{x n} and the received symbol _{y n.} It is a natural logarithm of the ratio of bits 0 and 1 of the probability that sends the log likelihood ratio lambda _n, represented by the formula (4) described above by using the transmission symbols x _n and the received symbol y _n.

  An LDPC decoding method such as a sum-product decoding method is performed using the log likelihood ratio obtained by Equation (4) and a parity check matrix H (corresponding to FIG. 13) corresponding to the coding rate of 4/16. The number of iteration decoding is an arbitrary value. In LDPC decoding, various means such as a min-sum decoding method have been proposed in addition to the sum-product decoding method. Various methods for maximizing the likelihood ratio using a parity check matrix are used in the present invention. This is applicable to such LDPC decoding.

FIG. 19 shows C / N versus BER characteristics (computer simulation) in QPSK modulation for an LDPC code rate of 4/16 according to the parity check matrix initial value table (Table 2). FIG. 19 shows the result after error correction by a BCH code (correction capability 12 bits) based on Non-Patent Document 2 (ARIB STD-B44). The decoding algorithm is a sum-product decoding method (for example, non-patent document 1). The number of decoding iterations of the sum-product decoding method is 50 times. FIG. 20 shows a comparison result of C / N that achieves the QPSK Shannon limit at a coding rate of 4/16 and C / N at BER = 1 × 10 ⁻⁷ points obtained from FIG. FIG. 20 shows that decoding performance approaching the Shannon limit can be obtained by applying an encoder, a decoder, a transmission apparatus 1 and a reception apparatus 2 based on this parity check matrix. Therefore, by using the check matrix H based on Table 2, it is possible to obtain a preferable transmission performance that is less than 1 dB with respect to the Shannon limit, which is difficult in the current digital terrestrial broadcasting.

(Transmission frame configuration with code length 69120 bits and LDPC coding rate 5/16)
FIGS. 21 (a) and 21 (b) show the structure of a transmission frame in an LDPC code rate 5/16 transmission system according to an embodiment of an LDPC code having a code length of 69120 bits according to the present invention. In particular, FIG. 21 (a) shows the configuration of a transmission frame when only an LDPC code with an LDPC code rate of 5/16 is used as an error correction code, and FIG. 3 (b) shows an error correction code as The structure of a transmission frame in the case of using a concatenated code composed of a BCH code as an outer code and an LDPC code with an LDPC code rate of 5/16 as an inner code is shown. The transmission frames shown in FIGS. 21A and 21B are assumed to be transmission frames based on LDPC codes used in the next-generation terrestrial broadcasting transmission system.

  First, the transmission frame shown in FIG. 21A is composed of information bits and LDPC parity satisfying the LDPC coding rate 5/16. The transmission apparatus 1 according to an embodiment of the present invention performs encoding and modulation by using the transmission frame configuration shown in FIG. The receiving device 2 according to an embodiment of the present invention performs demodulation and decoding of an error correction code based on this transmission frame configuration.

  The transmission frame shown in FIG. 21 (b) is composed of information bits, BCH parity, and LDPC parity as a modification of FIG. 21 (a), and is similar to the transmission frame shown in FIG. 21 (a). The present invention is applicable to the transmission device 1 and the reception device 2 according to the embodiment. In FIG. 21B, K_bch corresponds to the parity bit length of the BCH code. As an example of the outer code, a case where a BCH code that can be used in the advanced satellite broadcasting system is applied is shown, and K_bch is 192 bits. BCH parity is basically handled as a part of information bits and has a role of protecting minor bit errors that cannot be corrected by an LDPC code. When the LDPC parity length is equal, FIGS. 21A and 21B have the same LDPC code correction capability. However, since most of the error correction capability depends on the LDPC code, the description will mainly be made on the premise of the transmission frame shown in FIG.

  As shown in FIG. 21A, the transmission frame length assuming the next-generation terrestrial broadcast transmission system corresponds to 69120 bits which is the LDPC code length. The 69120 bits are composed of an integral multiple of 360 and can be divided by 360 × 192. Also, since the information bit length is 21600 bits and 21600/69120 = 5/16, this transmission frame satisfies the LDPC coding rate 5/16. Moreover, since the code length 69120 bits is sufficiently longer than the LDPC code length 44880 bits in the advanced satellite broadcasting system, an error correction capability closer to the Shannon limit can be expected.

  First, the process of the encoder (LDPC encoder 114) at an LDPC encoding rate of 5/16 according to an embodiment will be described.

(Processing of encoder at code length 69120 bits and LDPC code rate 5/16)
The encoder according to the present embodiment (LDPC encoding unit 114) generates a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. To generate LDPC code parity. FIG. 22 shows a basic configuration of parity check matrix H at LDPC coding rate 5/16. The length in the row direction of parity check matrix H corresponds to the LDPC code length, and LDPC code length N = 69120 is set. Since the coding rate of this parity check matrix is 5/16, the length in the column direction of parity check matrix H corresponds to the LDPC parity length, and the LDPC parity length P = 47520 bits.

  In FIG. 22, partial matrices A, C, and D are partial matrices configured using the parity check matrix initial value table shown in Table 3 above, and the LDGM structure (FIG. 23) is applied to partial matrix B. . The row weight of the LDGM structure (number of 1 in the row direction of the check matrix) is 1 for the first row, the remaining row weights are all 2, and the column weights are 2 for all columns (however, only the last column is 1). It is a matrix. The size of the submatrix B is 1800 bits in both the row direction and the column direction. In addition, a diagonal matrix (FIG. 24) is applied to the submatrix I. The row weights of the diagonal matrix are all 1. The size of the submatrix I is 45720 bits in both the row direction and the column direction. The submatrix O corresponds to a zero matrix.

  As shown in FIG. 25, the size of the submatrix A is 1800 bits (rows) × 21600 bits (columns).

  The size of the submatrix C is 45720 bits (rows) × 21600 bits (columns) as shown in FIG.

  Further, as shown in FIG. 27, the size of the submatrix D is 45720 bits (rows) × 1800 bits (columns).

  In any of the partial matrices A, C, and D, since the size of these partial matrices is finite, the position of 1 of the parity check matrix is calculated based on the above-described equation (1), and Q in equation (1) is , The number of cycles having a value determined for each coding rate, and Q is obtained by the above-described equation (2).

  Therefore, at the LDPC coding rate of 5/16 in the present embodiment, Q = 5 (first cycle number Q1) in the case of the submatrix A, Q = 127 (the second cycle number in the case of the submatrix C and the submatrix D). Cycle number Q2).

  Hereinafter, a method for generating a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O at an LDPC coding rate of 5/16 will be described in more detail.

  First, the submatrix A (FIG. 25) will be described. In order to form the partial matrix A, the encoder (LDPC encoding unit 114) of the present embodiment reads numerical values from a part of the parity check matrix initial value table shown in Table 3 above, and The position of 1 in the region of the matrix A is periodically arranged. In the parity check matrix initial value table shown in Table 3, numerical values of 65 in the column direction and 12 at the maximum in the row direction are described. This numerical value corresponds to the first position (initial value) of 1 of the parity check matrix used in the partial matrices A, C, and D. That is, the first position of 1 in the partial matrices A, C, and D in the check matrix H shown in FIG. 22 is designated by the numerical coordinates hi-j (numerical value) of the i-th row and j-th column in Table 3. As an example, in FIG. 25, h1-1 (754) corresponds to arranging 1 in the first column of the submatrix A in the 754th row in the check matrix H, and h1-2 (1583) is submatrix. This corresponds to arranging 1 in the first column of A in the 1583th row in the parity check matrix H. H2-1 (187) places 1 in the 361th column of the submatrix A in the 187th row of the check matrix H, and h2-2 (488) sets 1 in the 361th column of the submatrix A to the check matrix. This corresponds to the arrangement on the 488th line in H.

  Based on the above relationship, as shown in FIG. 25, the encoder (LDPC encoding unit 114) of this embodiment arranges 1 for every 360 columns of the submatrix A from the parity check matrix initial value table in Table 3. All of 60 rows and j columns (maximum 3 columns) of numerical coordinates hi-j (numerical values) for designating the row position to be read are read, and 1 is first assigned to the position in the designated submatrix A. 1 bit is shifted rightward in the row direction with reference to the position of 1 assigned first, and 1 is assigned to the position shifted downward in the column direction by the first cycle number Q1 = 5 (5 bits). By repeating, the submatrix A in the check matrix H is configured.

<Numerical coordinates hi-j (numerical value) for submatrix A of parity check matrix initial value table in Table 3>
First line: h1-1 (774) to h1-2 (1583)
2nd line: h2-1 (187) to h2-2 (488)
3rd line: h3-1 (886) to h3-2 (1010)
Fourth line: h4-1 (1101) to h4-2 (1183)
5th line: h5-1 (283) to h5-2 (460)
6th line: h6-1 (111) to h6-3 (1265)
...
60th line: h60-1 (761) to h60-3 (1242)

  In this way, the numerical values of 60 rows in the numerical coordinates hi-j (numerical value) for the submatrix A in Table 3 (each row of the 60 rows corresponds to the first column for every 360 columns of the submatrix A) is 1 column. By reading out each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix A) and repeating the first cycle number Q1 = 5 shift as shown in FIG. 25, 360 × It is possible to designate the position of 1 of the submatrix A in the check matrix H corresponding to 60 = 21600 bits (columns). The number of rows of the submatrix A is 360 × Q1 = 1800, and the size of the submatrix A is 21600 bits in the row direction and 1800 bits in the column direction.

  Next, the partial matrix C (FIG. 26) will be described. In order to form the partial matrix C, the encoder (LDPC encoding unit 114) of the present embodiment reads a numerical value from a part of the parity check matrix initial value table shown in Table 3 above, and The position of 1 in the region of the matrix C is periodically arranged. In the parity check matrix initial value table shown in Table 3, numerical values of 65 in the column direction and 12 at the maximum in the row direction are described. The difference between the submatrix C and the submatrix A is the read position in the parity check matrix initial value table and the number of cycles.

  As shown in FIG. 26, the encoder (LDPC encoding unit 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix C is arranged from the parity check matrix initial value table in Table 3. All of the numerical coordinates hi-j (numerical value) of 60 rows and j columns (maximum 10 columns) are read out, and 1 is first assigned to the position in the designated submatrix C, and the first assigned 1 22 by shifting 1 bit to the right in the row direction with respect to the position and assigning 1 to the position shifted downward in the column direction at the second cycle number Q2 = 127 (127 bits). A submatrix C in the check matrix H is constructed.

<Numerical coordinates hi-j (numerical value) for submatrix C of parity check matrix initial value table in Table 3>
First line: h1-3 (7200) to h1-12 (44894)
2nd line: h2-3 (2727) to h2-12 (46671)
3rd line: h3-3 (13409) to h3-10 (47450)
Fourth line: h4-3 (2141) to h4-10 (37652)
5th line: h5-3 (4362) to h5-10 (46201)
6th line: h6-4 (8144) to h6-11 (43231)
...
60th line: h60-4 (2808) to h60-11 (40215)

  In this way, 60 columns in the numerical coordinates hi-j (numerical value) for the submatrix C in Table 3 (each row of the 60 rows corresponds to the first column for every 360 columns of the submatrix C) is 1 column. By reading out every time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix C), and repeating the second cycle number Q2 = 127 shift as shown in FIG. 26, 360 × It is possible to designate the position of 1 of the submatrix C in the check matrix H corresponding to 60 = 21600 bits (columns). The number of rows of the submatrix C is 360 × Q2 = 45720, and the size of the submatrix C is 21600 bits in the row direction and 45720 bits in the column direction.

  Next, the partial matrix D (FIG. 27) will be described. In order to form the partial matrix D, the encoder (LDPC encoding unit 114) of the present embodiment uses a part of the parity check matrix initial value table shown in Table 3 (from the 61st row to the 65th row in Table 3). A numerical value is read from (line), and the position of 1 in the region of the partial matrix D in the check matrix H is periodically arranged. However, the same number of cycles Q2 = 127 as that of the submatrix C is applied to the submatrix D. However, the difference from the submatrix C is that the first cycle number Q1 = By using a bit shift in the row direction corresponding to 5, parity interleaving is applied.

  As shown in FIG. 27, the encoder (LDPC encoding unit 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix D is arranged from the parity check matrix initial value table in Table 3. All of the 5 rows and j columns (9 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the specified submatrix D, and this first assigned position of 1 The first cycle number Q1 = 5 bits is shifted to the right in the row direction with reference to, and 1 is assigned to the position shifted downward in the column direction with the second cycle number Q2 = 127 (127 bits). Thus, the partial matrix D in the check matrix H in FIG. 22 is configured.

<Numerical coordinates hi-j (numerical value) for submatrix D of parity check matrix initial value table in Table 3>
61st line: h61-1 (7173) to h61-9 (40288)
62nd line: h62-1 (4656) to h62-9 (45395)
63rd line: h63-1 (8410) to h63-9 (46251)
64th line: h64-1 (8401) to h64-9 (45997)
65th line: h65-1 (6188) to h65-9 (30935)

  As described above, the parity check matrix initial value table reading method to which parity interleaving is applied is a different reading method from the partial matrices A and C, and is 5 in the numerical coordinates hi-j (numerical value) for the partial matrix D in Table 3. Read the numerical values of the rows (each row of these 5 rows corresponds to the first 5 columns of the submatrix D) for each column (the numerical value for each column corresponds to the row position of the first 5 columns of the submatrix D). In Table 3, one row of numerical coordinates hi-j (numerical value) for the submatrix D is read as one set. Then, as shown in FIG. 27, 3601 is repeated 360 times by shifting a right shift of Q1 = 5 bits corresponding to the first cycle number and a downward shift of Q2 = 127 corresponding to the second cycle number. It becomes possible to designate the position of 1 of the submatrix D in the check matrix H corresponding to x5 = 1800 bits (columns). The number of rows of the submatrix D is 360 × Q2 = 45720, and the size of the submatrix D is 1800 bits in the row direction and 45720 bits in the column direction.

That is, the relationship between the parity check matrix initial value table in the partial matrix D shown in Table 3 and the column numbers in the parity check matrix H is shown below.
The numerical value in the 61st row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 21601st column (that is, the first column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 62nd row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 21602th column (that is, the second column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value of the 63rd row of the parity check matrix initial value table is the first position of the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 21603rd column (that is, the third column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 64th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 21604th column (that is, the fourth column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 65th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 in the 21605th column (that is, the fifth column of the submatrix D) in the parity check matrix H. Line position) is described.

  In FIG. 27, the numerical value read from the 61st row of the parity check matrix initial value table is shifted by Q2 = 127 every Q1 = 5 bits. By repeating this operation 360 times, the position of 1 in the submatrix D is determined for a total of 360 columns. Similarly, the numerical value read from the 62nd row of the parity check matrix initial value table is also shifted by Q2 = 127 every Q1 = 5 bits, and the position of 1 in the submatrix D is determined for a total of 360 columns. . Thereafter, the same process is repeated in the 63rd, 64th, and 65th rows, thereby determining the position of 1 in the submatrix D corresponding to 360 columns × 5 sets = 1800 bits. Therefore, the size of the submatrix D is 1800 bits in the row direction and 45720 bits in the column direction. In this way, by including in the check matrix H the partial matrix D to which the parity interleaving that shifts Q2 for each Q1 is applied, the generation of the cycle 4 that occurs between the partial matrix B and the partial matrix B that is connected to the higher rank with respect to the partial matrix D Thus, it is possible to improve the decoding performance of the LDPC code. That is, one of the causes of transmission characteristic deterioration in the LDPC code is the generation of an error floor. As the generation factor of this error floor, if one arrangement included in the check matrix H has many shape arrangements of cycle 4, for example, an error occurs. It has been found that floors are more likely to occur. Therefore, a check matrix H including a partial matrix D is used as a means for solving this problem.

  Using the parity check equation (3) described above using the parity check matrix H, which is a set matrix of the partial matrices A, B, C, D, I, and O at the LDPC coding rate 5/16 obtained by the above processing, LDPC parity is calculated. In the case of a coding rate of 5/16, since the information bit length is 21600 bits, in the parity check equation, parity calculation based on the LDGM structure is applied from the first row to the 1800th row of the check matrix H. The parity calculation based on the diagonal structure is applied from the 1801st line to the 47520th line.

  The encoder (LDPC encoder 114) of this embodiment has 69120 bits as a basic unit, and 69120 is a value divisible by the values 1, 2, 3, 4, 5, 6, 8, 10, 12. is there. Therefore, when applied as a functional block of the transmission apparatus 1 shown in FIG. 1, the encoder of the present embodiment can use a very wide variety of modulation multilevel numbers. For example, BPSK (π / 2 shift BPSK) ), QPSK, 8PSK, 16APSK (16QAM), 32APSK (32QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and the like. Therefore, the transmission apparatus 1 according to the present embodiment can perform signal transmission combining a very flexible modulation scheme and coding rate. Note that the parity check matrix initial value table for the parity check matrix used for LDPC encoding can be transmitted from the transmission apparatus 1 to the reception apparatus 2 as auxiliary information, or may be held in advance by the reception apparatus 2. . Alternatively, the check matrix itself can be transmitted from the transmission apparatus 1 to the reception apparatus 2, or the check matrix itself may be held in advance by the reception apparatus 2.

  Next, the process of the decoder (LDPC decoding unit 212) at the LDPC coding rate 5/16 of this embodiment will be described.

(Processing of decoder at code length 69120 bits and LDPC coding rate 5/16)
The decoder (LDPC decoding unit 212) of this embodiment performs decoding processing of an LDPC code using a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. . In the following description, for the sake of simplicity, the modulation method is assumed to be BPSK.

Decoder of the present embodiment (LDPC decoder 212) first calculates the log likelihood ratio lambda _n to (n = from 1 to 69120) on the basis of the transmitted symbols _{x n} and the received symbol _{y n.} It is a natural logarithm of the ratio of bits 0 and 1 of the probability that sends the log likelihood ratio lambda _n, represented by the formula (4) described above by using the transmission symbols x _n and the received symbol y _n.

  An LDPC decoding method such as a sum-product decoding method is performed using the log likelihood ratio obtained by Expression (4) and a check matrix H (corresponding to FIG. 22) corresponding to the above-described coding rate of 5/16. The number of iteration decoding is an arbitrary value. In LDPC decoding, various means such as a min-sum decoding method have been proposed in addition to the sum-product decoding method. Various methods for maximizing the likelihood ratio using a parity check matrix are used in the present invention. This is applicable to such LDPC decoding.

FIG. 28 shows C / N versus BER characteristics (computer simulation) in QPSK modulation for an LDPC coding rate of 5/16 according to the parity check matrix initial value table (Table 3). FIG. 28 shows the result after error correction by the BCH code (correction capability 12 bits) based on Non-Patent Document 2 (ARIB STD-B44), and the decoding algorithm is the sum-product decoding method (for example, Non-Patent Document 1). The number of decoding iterations of the sum-product decoding method is 50 times. FIG. 29 shows a comparison result between C / N that achieves the Shannon limit of QPSK at a coding rate of 5/16 and C / N at BER = 1 × 10 ⁻⁷ points obtained from FIG. From FIG. 29, it can be seen that decoding performance approaching the Shannon limit can be obtained by configuring the encoder, decoder, transmitter 1 and receiver 2 based on this parity check matrix. Therefore, the adoption of the check matrix H based on Table 3 makes it possible to obtain a preferable transmission performance that is less than 1 dB with respect to the Shannon limit, which was difficult in the current digital terrestrial broadcasting.

(Transmission frame configuration of code length 69120 bits, LDPC coding rate 6/16)
FIGS. 30 (a) and 30 (b) show the structure of a transmission frame in an LDPC code rate 6/16 transmission system according to an embodiment of an LDPC code having a code length of 69120 bits according to the present invention. In particular, FIG. 30A shows a transmission frame configuration when only an LDPC code having an LDPC code rate of 6/16 is used as an error correction code, and FIG. 3B shows an error correction code as an error correction code. The configuration of a transmission frame in the case of using a concatenated code consisting of a BCH code as an outer code and an LDPC code having an LDPC code rate of 6/16 as an inner code is shown. The transmission frames shown in FIGS. 30A and 30B are assumed to be transmission frames based on LDPC codes used in the next-generation terrestrial broadcasting transmission system.

  First, the transmission frame shown in FIG. 30A is composed of information bits and LDPC parity satisfying the LDPC coding rate 6/16. The transmission apparatus 1 according to an embodiment of the present invention performs encoding and modulation by using the transmission frame configuration shown in FIG. The receiving device 2 according to an embodiment of the present invention performs demodulation and decoding of an error correction code based on this transmission frame configuration.

  The transmission frame shown in FIG. 30 (b) is composed of information bits, BCH parity, and LDPC parity as a modification of FIG. 30 (a), and is similar to the transmission frame shown in FIG. 30 (a). The present invention is applicable to the transmission device 1 and the reception device 2 according to the embodiment. In FIG. 30B, K_bch corresponds to the parity bit length of the BCH code. As an example of the outer code, a case where a BCH code that can be used in the advanced satellite broadcasting system is applied is shown, and K_bch is 192 bits. BCH parity is basically handled as a part of information bits and has a role of protecting minor bit errors that cannot be corrected by an LDPC code. When LDPC parity lengths are equal, FIGS. 30A and 30B have the same LDPC code correction capability. However, since most of the error correction capability depends on the LDPC code, the description will mainly be made on the assumption of the transmission frame shown in FIG.

  As shown in FIG. 30A, the transmission frame length assuming the next-generation terrestrial broadcast transmission system corresponds to 69120 bits which is the LDPC code length. The 69120 bits are composed of an integral multiple of 360 and can be divided by 360 × 192. Further, since the information bit length is 25920 bits and 25920/69120 = 6/16, this transmission frame satisfies the LDPC coding rate 6/16. Moreover, since the code length 69120 bits is sufficiently longer than the LDPC code length 44880 bits in the advanced satellite broadcasting system, an error correction capability closer to the Shannon limit can be expected.

  First, the process of the encoder (LDPC encoder 114) at an LDPC encoding rate of 6/16 according to an embodiment will be described.

(Processing of encoder at code length 69120 bits and LDPC code rate 6/16)
The encoder according to the present embodiment (LDPC encoding unit 114) generates a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. To generate LDPC code parity. FIG. 31 shows a basic configuration of parity check matrix H at LDPC coding rate 6/16. The length in the row direction of parity check matrix H corresponds to the LDPC code length, and LDPC code length N = 69120 is set. Since the coding rate of this parity check matrix is 6/16, the length in the column direction of parity check matrix H corresponds to the LDPC parity length, and LDPC parity length P = 43200 bits.

  In FIG. 31, partial matrices A, C, and D are partial matrices configured using the parity check matrix initial value table shown in Table 4 above, and the LDGM structure (FIG. 32) is applied to the partial matrix B. . The row weight of the LDGM structure (number of 1 in the row direction of the check matrix) is 1 for the first row, the remaining row weights are all 2, and the column weights are 2 for all columns (however, only the last column is 1). It is a matrix. The size of the submatrix B is 1800 bits in both the row direction and the column direction. In addition, a diagonal matrix (FIG. 33) is applied to the submatrix I. The row weights of the diagonal matrix are all 1. The size of the submatrix I is 41400 bits in both the row direction and the column direction. The submatrix O corresponds to a zero matrix.

  The size of the submatrix A is 1800 bits (rows) × 25920 bits (columns) as shown in FIG.

  Further, as shown in FIG. 35, the size of the submatrix C is composed of 41400 bits (rows) × 25920 bits (columns).

  The size of the submatrix D is 41400 bits (rows) × 1800 bits (columns), as shown in FIG.

  In any of the partial matrices A, C, and D, since the size of these partial matrices is finite, the position of 1 of the parity check matrix is calculated based on the above-described equation (1), and Q in equation (1) is , The number of cycles having a value determined for each coding rate, and Q is obtained by the above-described equation (2).

  Therefore, in the LDPC coding rate 6/16 of the present embodiment, in the case of the submatrix A, Q = 5 (first cycle number Q1), the submatrix C, and the submatrix D, Q = 115 (second Cycle number Q2).

  Hereinafter, generation of a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O at an LDPC coding rate of 6/16 will be described more specifically.

  First, the submatrix A (FIG. 34) will be described. In order to form the partial matrix A, the encoder (LDPC encoding unit 114) of the present embodiment reads a numerical value from a part of the parity check matrix initial value table shown in Table 4 above, and The position of 1 in the region of the matrix A is periodically arranged. In the parity check matrix initial value table shown in Table 4, numerical values of 77 in the column direction and 12 at the maximum in the row direction are described. This numerical value corresponds to the first position (initial value) of 1 of the parity check matrix used in the partial matrices A, C, and D. That is, the first position of 1 in the partial matrices A, C, and D in the check matrix H shown in FIG. 31 is designated by the numerical coordinates hi-j (numerical value) of the i-th row and j-th column in Table 4. As an example, in FIG. 34, h1-1 (910) corresponds to placing 1 of the first column of the submatrix A in the 910th row of the check matrix H, and h1-2 (1224) is the submatrix. This corresponds to arranging 1 in the first column of A in the 1224th row in the check matrix H. H2-1 (602) places 1 in the 361th column of the submatrix A in the 602nd row of the check matrix H, and h2-2 (1599) sets 1 in the 361th column of the submatrix A to the check matrix. This corresponds to the arrangement in the 1599th line in H.

  Based on the above relationship, as shown in FIG. 34, the encoder (LDPC encoding unit 114) of this embodiment arranges 1 for every 360 columns of the submatrix A from the parity check matrix initial value table in Table 4. All of the 72 rows and j columns (maximum 3 columns) of numerical coordinates hi-j (numerical values) for designating the row position to be read are read, and 1 is first assigned to the position in the designated submatrix A. 1 bit is shifted rightward in the row direction with reference to the position of 1 assigned first, and 1 is assigned to the position shifted downward in the column direction by the first cycle number Q1 = 5 (5 bits). By repeating, the submatrix A in the check matrix H is configured.

<Numerical coordinates hi-j (numerical value) for submatrix A of parity check matrix initial value table in Table 4>
First line: h1-1 (910) to h1-2 (1224)
...
25th line: h25-1 (209) to h25-2 (1725)
26th line: h26-1 (201) to h26-3 (1643)
...
72nd line: h72-1 (473) to h72-3 (1374)

  In this way, the numerical values of 72 rows in the numerical coordinates hi-j (numerical values) for the submatrix A in Table 4 (each row of the 72 rows corresponds to the first column for every 360 columns of the submatrix A) are 1 column. By reading out each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix A) and repeating the first cycle number Q1 = 5 shift as shown in FIG. 34, 360 × It becomes possible to designate the position of 1 of the submatrix A in the parity check matrix H corresponding to 72 = 25920 bits (columns). The number of rows of the submatrix A is 360 × Q1 = 1800, and the size of the submatrix A is 25920 bits in the row direction and 1800 bits in the column direction.

  Next, the partial matrix C (FIG. 35) will be described. In order to form the partial matrix C, the encoder (LDPC encoding unit 114) of the present embodiment reads a numerical value from a part of the parity check matrix initial value table shown in Table 4 above, and The position of 1 in the region of the matrix C is periodically arranged. In the parity check matrix initial value table shown in Table 4, numerical values of 77 in the column direction and 12 at the maximum in the row direction are described. The difference between the submatrix C and the submatrix A is the read position in the parity check matrix initial value table and the number of cycles.

  As shown in FIG. 35, the encoder (LDPC encoder 114) of the present embodiment designates the row position where 1 is assigned for every 360 columns of the submatrix C from the parity check matrix initial value table in Table 4. All of the 72 rows and j columns (up to 10 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the designated submatrix C, and the first assigned 1 By repeatedly assigning 1 to the position shifted by 1 bit to the right in the row direction with respect to the position and shifted downward in the column direction by the second cycle number Q2 = 115 (115 bits), FIG. A submatrix C in the check matrix H is constructed.

<Numerical coordinates hi-j (numerical value) for submatrix C of parity check matrix initial value table in Table 4>
First line: h1-3 (9915) to h1-12 (35296)
...
22nd line: h22-3 (2244) to h22-12 (35420)
23rd line: h23-3 (10233) to h23-8 (41986)
...
25th line: h25-3 (2098) to h25-8 (35854)
26th line: h26-4 (2745) to h26-9 (29478)
...
72nd line: h26-4 (6781) to h72-9 (16858)

  In this way, the numerical values of 72 rows in the numerical coordinates hi-j (numerical values) for the submatrix C in Table 4 (each row of the 72 rows corresponds to the first column for every 360 columns of the submatrix C) are 1 column. Each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix C), and the second cycle number Q2 = 115 shift is repeated as shown in FIG. It is possible to designate the position of 1 in the submatrix C in the check matrix H corresponding to 72 = 25920 bits (columns). The number of rows of the submatrix C is 360 × Q2 = 41400, and the size of the submatrix C is 25920 bits in the row direction and 41400 bits in the column direction.

  Next, the partial matrix D (FIG. 36) will be described. In order to form the partial matrix D, the encoder (LDPC encoding unit 114) of the present embodiment forms part of the parity check matrix initial value table shown in Table 4 above (from Table 73 to 77th line 77). A numerical value is read from (line), and the position of 1 in the region of the partial matrix D in the check matrix H is periodically arranged. However, the same number of cycles Q2 = 115 as that of the submatrix C is applied to the submatrix D. However, the difference from the submatrix C is that the first cycle number Q1 = By using a bit shift in the row direction corresponding to 5, parity interleaving is applied.

  As shown in FIG. 36, the encoder (LDPC encoder 114) of the present embodiment designates the row position where 1 is assigned for every 360 columns of the submatrix D from the parity check matrix initial value table in Table 4. All of the 5 rows and j columns (7 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the specified submatrix D, and this first assigned position of 1 The first cycle number Q1 = 5 bits is shifted to the right in the row direction with reference to, and 1 is repeatedly assigned to the position shifted downward in the column direction at the second cycle number Q2 = 115 (115 bits). Thus, the partial matrix D in the check matrix H in FIG. 31 is configured.

<Numerical coordinates hi-j (numerical value) for submatrix D of parity check matrix initial value table in Table 4>
Line 73: h73-1 (12796) to h73-7 (25584)
74th line: h74-1 (9420) to h74-7 (36703)
75th line: h75-1 (26267) to h75-7 (42550)
76th line: h76-1 (5004) to h76-7 (39968)
Line 77: h77-1 (17764) to h77-7 (41091)

  As described above, the parity check matrix initial value table reading method to which parity interleaving is applied is a different reading method from the partial matrices A and C, and is 5 in the numerical coordinates hi-j (numerical value) for the partial matrix D in Table 4. Read the numerical values of the rows (each row of these 5 rows corresponds to the first 5 columns of the submatrix D) for each column (the numerical value for each column corresponds to the row position of the first 5 columns of the submatrix D). The reading of one row of the numerical coordinates hi-j (numerical value) for the submatrix D in Table 4 is taken as one set. Then, as shown in FIG. 36, 3601 is repeated 360 times by shifting a right shift of Q1 = 5 bits corresponding to the first cycle number and a downward shift of Q2 = 115 minutes corresponding to the second cycle number. It becomes possible to designate the position of 1 of the submatrix D in the check matrix H corresponding to x5 = 1800 bits (columns). The number of rows of the submatrix D is 360 × Q2 = 41400, and the size of the submatrix D is 1800 bits in the row direction and 41400 bits in the column direction.

That is, the relationship between the parity check matrix initial value table in the submatrix D shown in Table 4 and the column numbers in the parity check matrix H is shown below.
The numerical value in the 73rd row of the parity check matrix initial value table is a value in the first parity check matrix H that repeats at the cycle number Q1, Q2 in the 25921st column (that is, the first column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 74th row of the parity check matrix initial value table is the value in the first parity check matrix H repeated at the first position (number of cycles Q1 and Q2) of 25922 in the parity check matrix H (that is, the second column of the submatrix D). Line position) is described.
The numerical value in the 75th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 25923th column (that is, the third column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value in the 76th row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats at the number of cycles Q1 and Q2 of the 25924th column in the parity check matrix H (that is, the fourth column of the submatrix D). Line position) is described.
The numerical value in the 77th row of the parity check matrix initial value table is the first position of 1 in the 25925th column (that is, the fifth column of the submatrix D) in the parity check matrix H (in the first parity check matrix H that repeats with the cycle numbers Q1 and Q2). Line position) is described.

  In FIG. 36, the numerical value read from the 73rd row of the parity check matrix initial value table is shifted by Q2 = 115 every Q1 = 5 bits. By repeating this operation 360 times, the position of 1 in the submatrix D is determined for a total of 360 columns. Similarly, the numerical value read from the 74th row of the parity check matrix initial value table is also shifted by Q2 = 115 every Q1 = 5 bits, and the position of 1 in the submatrix D is determined for a total of 360 columns. . Thereafter, the same processing is repeated in the 75th, 76th, and 77th rows to determine the position of 1 in the submatrix D corresponding to 360 columns × 5 sets = 1800 bits. Therefore, the size of the submatrix D is 1800 bits in the row direction and 41400 bits in the column direction. In this way, by including in the check matrix H the partial matrix D to which the parity interleaving that shifts Q2 for each Q1 is applied, the generation of the cycle 4 that occurs between the partial matrix B and the partial matrix B that is connected to the higher rank with respect to the partial matrix D Thus, it is possible to improve the decoding performance of the LDPC code. That is, one of the causes of transmission characteristic deterioration in the LDPC code is the generation of an error floor. As the generation factor of this error floor, if one arrangement included in the check matrix H has many shape arrangements of cycle 4, for example, an error occurs. It has been found that floors are more likely to occur. Therefore, a check matrix H including a partial matrix D is used as a means for solving this problem.

  Using the parity check equation (3) described above using the parity check matrix H that is a set matrix of the partial matrices A, B, C, D, I, and O at the LDPC coding rate 6/16 obtained by the above processing, LDPC parity is calculated. In the case of a coding rate of 6/16, the information bit length is 25920 bits. Therefore, in the parity check equation, the parity calculation based on the LDGM structure is applied from the first row to the 1800th row of the check matrix H. The parity calculation based on the diagonal structure is applied from the 1801st line to the 43200th line.

  The encoder (LDPC encoder 114) of this embodiment has 69120 bits as a basic unit, and 69120 is a value divisible by the values 1, 2, 3, 4, 5, 6, 8, 10, 12. is there. Therefore, when applied as a functional block of the transmission apparatus 1 shown in FIG. 1, the encoder of the present embodiment can use a very wide variety of modulation multilevel numbers. For example, BPSK (π / 2 shift BPSK) ), QPSK, 8PSK, 16APSK (16QAM), 32APSK (32QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and the like. Therefore, the transmission apparatus 1 according to the present embodiment can perform signal transmission combining a very flexible modulation scheme and coding rate. Note that the parity check matrix initial value table for the parity check matrix used for LDPC encoding can be transmitted from the transmission apparatus 1 to the reception apparatus 2 as auxiliary information, or may be held in advance by the reception apparatus 2. . Alternatively, the check matrix itself can be transmitted from the transmission apparatus 1 to the reception apparatus 2, or the check matrix itself may be held in advance by the reception apparatus 2.

  Next, the process of the decoder (LDPC decoding unit 212) at the LDPC coding rate 6/16 of this embodiment will be described.

(Processing of decoder at code length 69120 bits and LDPC coding rate 6/16)
The decoder (LDPC decoding unit 212) of this embodiment performs decoding processing of an LDPC code using a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. . In the following description, for the sake of simplicity, the modulation method is assumed to be BPSK.

Decoder of the present embodiment (LDPC decoder 212) first calculates the log likelihood ratio lambda _n to (n = from 1 to 69120) on the basis of the transmitted symbols _{x n} and the received symbol _{y n.} It is a natural logarithm of the ratio of bits 0 and 1 of the probability that sends the log likelihood ratio lambda _n, represented by the formula (4) described above by using the transmission symbols x _n and the received symbol y _n.

  An LDPC decoding method such as a sum-product decoding method is performed using the log-likelihood ratio obtained by Expression (4) and a check matrix H (corresponding to FIG. 31) corresponding to the coding rate of 6/16. The number of iteration decoding is an arbitrary value. In LDPC decoding, various means such as a min-sum decoding method have been proposed in addition to the sum-product decoding method. Various methods for maximizing the likelihood ratio using a parity check matrix are used in the present invention. This is applicable to such LDPC decoding.

FIG. 37 shows C / N versus BER characteristics (computer simulation) in QPSK modulation for an LDPC coding rate of 6/16 according to the parity check matrix initial value table (Table 4). FIG. 37 shows the result after error correction by a BCH code (correction capability 12 bits) based on Non-Patent Document 2 (ARIB STD-B44). The decoding algorithm is a sum-product decoding method (for example, non-patent document 1). The number of decoding iterations of the sum-product decoding method is 50 times. FIG. 38 shows a comparison result between C / N that achieves the Shannon limit of QPSK at a coding rate of 6/16 and C / N at BER = 1 × 10 ⁻⁷ obtained from FIG. From FIG. 38, it can be seen that decoding performance approaching the Shannon limit can be obtained by configuring the encoder, decoder, transmitter 1 and receiver 2 based on this parity check matrix. Therefore, by adopting the check matrix H based on Table 4, it is possible to obtain a preferable transmission performance that is less than 1 dB with respect to the Shannon limit that is difficult in the current digital terrestrial broadcasting.

[LDPC code with a code length of 17280 bits]
Next, referring to FIG. 39 to FIG. 52, encoders for LDPC code rates 2/16, 3/16, 4/16, 5/16, and 6/16 in an LDPC code having a code length of 17280 bits. The (LDPC encoding unit 114) and the decoder (LDPC decoding unit 212) will be described. The configuration of a transmission apparatus 1 including an LDPC code encoder (LDPC encoding unit 114) having a code length of 17280 bits and a reception apparatus 2 including an LDPC code decoder (LDPC decoding unit 212) having a code length of 17280 bits. Is configured similarly to that shown in FIGS. 1 and 2 described above.

(Code length 17280 bits, LDPC code rate 2/16 transmission frame configuration)
FIGS. 39 (a) and 39 (b) respectively show transmission frame configurations in an LDPC code rate 2/16 transmission system according to an embodiment relating to the code length N = 17280 bits of the LDPC code according to the present invention. In particular, FIG. 39 (a) shows the configuration of a transmission frame when only an LDPC code having an LDPC coding rate of 2/16 is used as an error correction code, and FIG. 39 (b) shows an error correction code as The structure of a transmission frame in the case of using a concatenated code including a BCH code as an outer code and an LDPC code having an LDPC code rate of 2/16 as an inner code is shown. 39A and 39B are assumed to be transmission frames based on LDPC codes used in the next-generation terrestrial broadcast transmission method.

  First, the transmission frame shown in FIG. 39A is composed of information bits and LDPC parity that satisfy the LDPC coding rate 2/16. The transmission apparatus 1 according to an embodiment of the present invention performs encoding and modulation by using the transmission frame configuration shown in FIG. The receiving device 2 according to an embodiment of the present invention performs demodulation and decoding of an error correction code based on this transmission frame configuration.

  The transmission frame shown in FIG. 39 (b) is composed of information bits, BCH parity, and LDPC parity as a modification of FIG. 39 (a), and is similar to the transmission frame shown in FIG. 39 (a). The present invention is applicable to the transmission device 1 and the reception device 2 according to the embodiment. In FIG. 39B, K_bch corresponds to the parity bit length of the BCH code. As an example of the outer code, it is possible to apply a BCH code that can be used in the advanced satellite broadcasting system, but in addition, a 168-bit BCH code can be applied as K_bch. BCH parity is basically handled as a part of information bits and has a role of protecting minor bit errors that cannot be corrected by an LDPC code. When the LDPC parity lengths are equal, FIGS. 39A and 39B have the same LDPC code correction capability. However, since most of the error correction capability depends on the LDPC code, the description will mainly be made on the premise of the transmission frame shown in FIG.

  As shown in FIG. 39 (a), in the case of LDPC coding rate 2/16, the transmission frame length assuming the next-generation terrestrial broadcasting transmission system corresponds to N = 17280 bits which is the LDPC code length. The 17280 bits are composed of an integer multiple of M = 360, and can be divided by 360 × 48. Further, since the information bit length J = 2160 bits and 2160/17280 = 2/16, this transmission frame satisfies the LDPC coding rate 2/16. Also, the code length of 17280 bits is shorter than the LDPC code length of 44880 bits in the advanced satellite broadcasting system, which is disadvantageous as an error correction capability, but as a simple transmission system, error correction closer to the Shannon limit than the current terrestrial digital broadcasting Ability can be expected.

(Processing of encoder at code length 17280 bits, LDPC code rate 2/16)
The encoder according to the present embodiment (LDPC encoding unit 114) generates a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. To generate LDPC code parity. FIG. 40 shows the basic configuration of parity check matrix H at the LDPC coding rate 2/16. The length in the row direction of parity check matrix H corresponds to the LDPC code length, and LDPC code length N = 17280 is set. Since the coding rate of this parity check matrix is 2/16, the length in the column direction of parity check matrix H corresponds to the LDPC parity length, and LDPC parity length P = 15120 bits.

  In FIG. 40, partial matrices A, C, and D are partial matrices configured using the parity check matrix initial value table shown in Table 5 above, and the LDGM structure (FIG. 41) is applied to the partial matrix B. . The row weight of the LDGM structure (number of 1 in the row direction of the check matrix) is 1 for the first row, the remaining row weights are all 2, and the column weights are 2 for all columns (however, only the last column is 1). It is a matrix. The size of the submatrix B is 1440 bits in both the row direction and the column direction. In addition, a diagonal matrix (FIG. 42) is applied to the submatrix I. The row weights of the diagonal matrix are all 1. The size of the submatrix I is 13680 bits in both the row direction and the column direction. The submatrix O corresponds to a zero matrix.

  As shown in FIG. 43, the size of the submatrix A is composed of M1 × J = 1440 bits (rows) × 2160 bits (columns).

  Further, as shown in FIG. 44, the size of the submatrix C is configured by M2 × J = 13680 bits (rows) × 2160 bits (columns).

  Further, as shown in FIG. 45, the size of the submatrix D is composed of M2 × M1 = 13680 bits (rows) × 1440 bits (columns).

  In any of the partial matrices A, C, and D, since the size of these partial matrices is finite, the position of 1 of the parity check matrix is calculated based on the above-described equation (1), and Q in equation (1) is , The number of cycles having a value determined for each coding rate, and Q is obtained by the above-described equation (2).

  Therefore, in the LDPC coding rate 2/16 of the present embodiment, in the case of the partial matrix A, Q = 4 (first cycle number Q1 = M1 / M = 1440/360), the partial matrix C, and the partial matrix D. In this case, Q = 38 (second cycle number Q2 = M2 / M = 13680/360).

  Hereinafter, a method for generating a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O at LDPC coding rate 2/16 will be described in more detail.

  First, the submatrix A (FIG. 43) will be described. In order to form the partial matrix A, the encoder (LDPC encoding unit 114) of the present embodiment reads numerical values from a part of the parity check matrix initial value table shown in Table 5 above, and The position of 1 in the region of the matrix A is periodically arranged. In the parity check matrix initial value table shown in Table 5, numerical values of 10 in the column direction and 11 at the maximum in the row direction are described. This numerical value corresponds to the first position (initial value) of 1 of the parity check matrix used in the partial matrices A, C, and D. That is, the first position of 1 in the partial matrices A, C, and D in the check matrix H shown in FIG. 40 is designated by the numerical coordinates hi-j (numerical values) in the i-th row and j-th column in Table 5. As an example, in FIG. 43, h1-1 (698) corresponds to placing 1 of the first column of the submatrix A on the 698th row in the check matrix H, and h1-2 (964) is the submatrix. This corresponds to arranging 1 in the first column of A in the 964th row in the parity check matrix H. H2-1 (534) places 1 in the 361th column of the submatrix A in the 534th row of the check matrix H, and h2-2 (595) sets 1 in the 361th column of the submatrix A to the check matrix. This corresponds to the arrangement in the 595th line in H.

  Based on the above relationship, as shown in FIG. 43, the encoder (LDPC encoder 114) of this embodiment arranges 1 for every 360 columns of the submatrix A from the parity check matrix initial value table in Table 5. All the 6 rows and j columns (3 columns) of numerical coordinates hi-j (numerical values) for specifying the row position to be read are read out, and 1 is first assigned to the position in the designated submatrix A. 1 is assigned to the position shifted rightward in the row direction with respect to the position of 1 assigned to 1 and shifted downward in the column direction at the first cycle number Q1 = 4 (4 bits). Thus, the partial matrix A in the check matrix H is configured.

<Numerical Coordinates hi-j (Numeric Value) for Submatrix A in Check Matrix Initial Value Table in Table 5>
First line: h1-1 (698) to h1-3 (1335)
2nd line: h2-1 (534) to h2-3 (1325)
3rd line: h3-1 (262) to h3-3 (1336)
Fourth line: h4-1 (884) to h4-3 (1301)
5th line: h5-1 (8) to h5-3 (853)
6th line: h6-1 (73) to h6-3 (816)

  In this way, the numerical values of 6 rows in the numerical coordinates hi-j (numerical values) for the submatrix A in Table 5 (each row of these 6 rows corresponds to the first column for every 360 columns of the submatrix A) are 1 column. By reading out each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix A) and repeating the first cycle number Q1 = 4 shifts as shown in FIG. It becomes possible to specify the position of 1 of the submatrix A in the check matrix H corresponding to 6 = 2160 bits (columns). The number of rows of the submatrix A is 360 × Q1 = 1440, and the size of the submatrix A is 2160 bits in the row direction and 1440 bits in the column direction.

  Next, the partial matrix C (FIG. 44) will be described. In order to form the partial matrix C, the encoder (LDPC encoding unit 114) of the present embodiment reads numerical values from a part of the parity check matrix initial value table shown in Table 2 above, and The position of 1 in the region of the matrix C is periodically arranged. In the parity check matrix initial value table shown in Table 5, numerical values of 10 in the column direction and 11 at the maximum in the row direction are described. The difference between the submatrix C and the submatrix A is the read position in the parity check matrix initial value table and the number of cycles.

  As shown in FIG. 44, the encoder (LDPC encoding unit 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix C is arranged from the parity check matrix initial value table in Table 5. All of the numerical coordinates hi-j (numerical values) of 6 rows and j columns (maximum 8 columns) are read out, and 1 is first assigned to the position in the designated submatrix C, and the first assigned 1 40 by shifting 1 bit rightward in the row direction with respect to the position and assigning 1 to the position shifted downward in the column direction at the second cycle number Q2 = 38 (38 bits). A submatrix C in the check matrix H is constructed.

<Numerical Coordinates hi-j (Numeric Value) for Submatrix C of Check Matrix Initial Value Table in Table 5>
First line: h1-4 (3209) to h1-10 (13592)
2nd line: h2-4 (1970) to h2-11 (15025)
3rd line: h3-4 (2307) to h3-11 (10902)
Fourth line: h4-4 (6441) to h4-11 (11622)
5th line: h5-4 (3911) to h5-11 (10034)
6th line: h6-4 (3957) to h6-11 (14862)

  Thus, the numerical values of 6 rows in the numerical coordinates hi-j (numerical values) for the submatrix C in Table 5 (each row of these 6 rows corresponds to the first column for every 360 columns of the submatrix C) is 1 column. By reading out each time (the numerical value for each column corresponds to the first row position for every 360 columns of the submatrix C) and repeating the second cycle number Q2 = 38 shift as shown in FIG. It is possible to designate the position of 1 in the submatrix C in the parity check matrix H corresponding to 6 = 2160 bits (columns). Further, the number of rows of the submatrix C is 360 × Q2 = 13680, and the size of the submatrix C is 2160 bits in the row direction and 13680 bits in the column direction.

  Next, the partial matrix D (FIG. 45) will be described. In order to form the partial matrix D, the encoder (LDPC encoding unit 114) of the present embodiment forms a part of the parity check matrix initial value table shown in Table 5 (from the seventh row to 10th row in Table 5). A numerical value is read from (line), and the position of 1 in the region of the partial matrix D in the check matrix H is periodically arranged. However, the same number of cycles Q2 = 38 as that of the submatrix C is applied to the submatrix D. However, the submatrix D differs from the submatrix C in the read cycle in the parity check matrix initial value table in the first cycle number Q1 = By using a bit shift in the row direction corresponding to 4, parity interleaving is applied.

  As shown in FIG. 45, the encoder (LDPC encoding unit 114) of the present embodiment designates the row position where 1 for every 360 columns of the submatrix D is arranged from the parity check matrix initial value table in Table 2. All of the four rows and j columns (10 columns) of numerical coordinates hi-j (numerical values) are read out, and 1 is first assigned to the position in the designated submatrix D, and this first assigned position of 1 The first cycle number Q1 = 4 bits is shifted to the right in the row direction with reference to, and 1 is repeatedly assigned to the position shifted downward in the column direction at the second cycle number Q2 = 38 (38 bits). Thus, the partial matrix D in the check matrix H in FIG. 45 is configured.

<Numerical coordinates hi-j (numerical value) for submatrix D of parity check matrix initial value table in Table 5>
7th line: h7-1 (5621) to h7-10 (14217)
8th line: h8-1 (2433) to h8-10 (12608)
9th line: h9-1 (3411) to h9-10 (14822)
10th line: h10-1 (1525) to h10-10 (13529)

  As described above, the parity check matrix initial value table reading method to which parity interleaving is applied is a different reading method from the partial matrices A and C, and 4 in the numerical coordinates hi-j (numerical value) for the partial matrix D in Table 5. Read the numerical value of each row (each row of the four rows corresponds to the first four columns of the submatrix D) for each column (the numerical value for each column corresponds to the row position for each of the first four columns of the submatrix D). In Table 5, one row of the numerical coordinates hi-j (numerical value) for the submatrix D is read as one set. Then, as shown in FIG. 45, 3601 is repeated 360 times by shifting a right shift of Q1 = 4 bits corresponding to the first cycle number and a downward shift of Q2 = 38 minutes corresponding to the second cycle number. It becomes possible to designate the position of 1 of the submatrix D in the check matrix H corresponding to x4 = 1440 bits (columns). Further, the number of rows of the submatrix D is 360 × Q2 = 13680, and the size of the submatrix D is 1440 bits in the row direction and 13680 bits in the column direction.

That is, the relationship between the parity check matrix initial value table in the partial matrix D shown in Table 5 and the column numbers in the parity check matrix H is shown below.
The numerical value in the seventh row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 2161th column (that is, the first column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value of the 8th row of the parity check matrix initial value table is the first position of 1 in the 2162th column (that is, the second column of the partial matrix D) in the parity check matrix H. Line position) is described.
The numerical value in the ninth row of the parity check matrix initial value table is the first position in the first parity check matrix H that repeats with the number of cycles Q1 and Q2 in the 2163rd column (that is, the third column of the submatrix D) in the parity check matrix H. Line position) is described.
The numerical value of the 10th row of the parity check matrix initial value table is the first position of 1 in the 2164th column (that is, the fourth column of the submatrix D) in the parity check matrix H (the first parity check matrix H that repeats with the cycle numbers Q1 and Q2). Line position) is described.

  In FIG. 45, the numerical value read from the seventh row of the parity check matrix initial value table is shifted by Q2 = 38 every Q1 = 4 bits. By repeating this operation 360 times, the position of 1 in the submatrix D is determined for a total of 360 columns. Similarly, the numerical value read from the 8th row of the parity check matrix initial value table is also shifted by Q2 = 38 every Q1 = 4 bits, and the position of 1 in the submatrix D is determined for a total of 360 columns. . Thereafter, the same process is repeated in the 9th and 10th rows to determine the position of 1 in the submatrix D corresponding to 360 columns × 4 sets = 1440 bits. Therefore, the size of the submatrix D is 1440 bits in the row direction and 13680 bits in the column direction. In this way, by including in the check matrix H the partial matrix D to which the parity interleaving that shifts Q2 for each Q1 is applied, the generation of the cycle 4 that occurs between the partial matrix B and the partial matrix B that is connected to the higher rank with respect to the partial matrix D Thus, it is possible to improve the decoding performance of the LDPC code. That is, one of the causes of transmission characteristic deterioration in the LDPC code is the generation of an error floor. As the generation factor of this error floor, if one arrangement included in the check matrix H has many shape arrangements of cycle 4, for example, an error occurs. It has been found that floors are more likely to occur. Therefore, a check matrix H including a partial matrix D is used as a means for solving this problem.

  Using the parity check equation (3) described above using the parity check matrix H that is a set matrix of the partial matrices A, B, C, D, I, and O at the LDPC coding rate 2/16 obtained by the above processing, LDPC parity is calculated. In the case of coding rate 2/16, since the information bit length is 2160 bits, the parity check based on the LDGM structure is applied from the first row to the 1440th row of the parity check matrix H in the parity check equation. The parity calculation based on the diagonal structure is applied from the 1441st line to the 15120th line.

  The encoder (LDPC encoding unit 114) of this embodiment uses 17280 bits as a basic unit, and 17280 is a value divisible by the values 1, 2, 3, 4, 5, 6, 8, 10, 12. is there. Therefore, when applied as a functional block of the transmission apparatus 1 shown in FIG. 1, the encoder of the present embodiment can use a very wide variety of modulation multilevel numbers. For example, BPSK (π / 2 shift BPSK) ), QPSK, 8PSK, 16APSK (16QAM), 32APSK (32QAM), 64QAM, 256QAM, 1024QAM, 4096QAM, and the like. Therefore, the transmission apparatus 1 according to the present embodiment can perform signal transmission combining a very flexible modulation scheme and coding rate. Note that the parity check matrix initial value table for the parity check matrix used for LDPC encoding can be transmitted from the transmission apparatus 1 to the reception apparatus 2 as auxiliary information, or may be held in advance by the reception apparatus 2. . Alternatively, the check matrix itself can be transmitted from the transmission apparatus 1 to the reception apparatus 2, or the check matrix itself may be held in advance by the reception apparatus 2.

  Next, the process of the decoder (LDPC decoding unit 212) at the LDPC coding rate 2/16 of this embodiment will be described.

(Processing of decoder at code length 17280 bits and LDPC code rate 2/16)
The decoder (LDPC decoding unit 212) of this embodiment performs decoding processing of an LDPC code using a check matrix H divided into six regions by partial matrices A, B, C, D, I, and O. . In the following description, for the sake of simplicity, the modulation method is assumed to be BPSK.

Decoder of the present embodiment (LDPC decoder 212) first calculates the log likelihood ratio lambda _n to (n = 1 to 17280) on the basis of the transmitted symbols _{x n} and the received symbol _{y n.} It is a natural logarithm of the ratio of bits 0 and 1 of the probability that sends the log likelihood ratio lambda _n, represented by the formula (4) described above by using the transmission symbols x _n and the received symbol y _n.

  An LDPC decoding method such as a sum-product decoding method is performed using the log likelihood ratio obtained by Expression (4) and a parity check matrix H (corresponding to FIG. 13) corresponding to the coding rate 2/16 described above. The number of iteration decoding is an arbitrary value. In LDPC decoding, various means such as a min-sum decoding method have been proposed in addition to the sum-product decoding method. Various methods for maximizing the likelihood ratio using a parity check matrix are used in the present invention. This is applicable to such LDPC decoding.

(Code length 17280 bits, encoder and decoder at other LDPC code rates 3/16, 4/16, 5/16, 6/16)
Encoder (LDPC encoder 114) and decoder (LDPC decoder 212) for LDPC code rates 3/16, 4/16, 5/16, and 6/16 in an LDPC code having a code length of 17280 bits Also, based on the respective parity check matrix initial value tables (Tables 6 to 9), the same method as in the case of the LDPC coding rate 2/16 related to the LDPC code having a code length of 17280 bits shown in FIGS. A check matrix H can be constructed. FIG. 46 shows parameters N, P, J for LDPC coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 according to the LDPC code having a code length of 17280 bits according to the present invention. , M1, M2, Q1, Q2, P / M, and J / M are shown in comparison (M = 360).

47 to 51 show QPSK modulation for LDPC coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 according to the parity check matrix initial value tables (Tables 5 to 9). C / N vs. BER characteristics (computer simulation) are shown. 47 to 51 show the results before error correction by the BCH code (correction capability 12 bits), and the decoding algorithm uses the sum-product decoding method (for example, see Non-Patent Document 1). The number of decoding iterations of the sum-product decoding method is 50 times. FIG. 52 shows C / N for achieving the Shannon limit of QPSK at each of coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 at a code length of 17280 bits, and FIGS. The comparison result of C / N in BER = 1 * 10 < ^-7 > point acquired from 51 is shown. From FIG. 52, it is understood that decoding performance approaching the Shannon limit can be obtained by applying the encoder, the decoder, the transmission apparatus 1 and the reception apparatus 2 based on this parity check matrix. Therefore, the adoption of the check matrix H based on Tables 5 to 9 makes it possible to obtain a preferable transmission performance that is less than 2 dB with respect to the Shannon limit, which was difficult in the current digital terrestrial broadcasting.

  With respect to the above-described embodiment, a computer that functions as an encoder and a decoder, and a transmission device 1 and a reception device 2 is configured, and the respective units of the encoder and the decoder and the transmission device 1 and the reception device 2 are made to function. The program for this can be used suitably. Specifically, the control unit for controlling each means can be constituted by a central processing unit (CPU) in the computer, and at least a storage part for appropriately storing a program necessary for operating each means. A single memory can be used. In other words, the functions of the respective means described above can be realized by causing such a computer to execute the program by the CPU. Furthermore, a program for realizing the function of each unit can be stored in a predetermined area of the storage unit (memory). Such a storage unit can be constituted by a RAM or a ROM inside the apparatus, or can be constituted by an external storage device (for example, a hard disk). Further, such a program can be constituted by a part of software (stored in a ROM or an external storage device) on an OS used in a computer. Furthermore, a program for causing such a computer to function as each means can be recorded on a computer-readable recording medium. Moreover, each means mentioned above can be comprised as a part of hardware or software, and can also be implement | achieved combining each.

  Although the above embodiments have been described as representative examples, it will be apparent to those skilled in the art that many changes and substitutions can be made within the spirit and scope of the invention. For example, as other error correction coding when combined with LDPC coding, besides BCH coding, not only block coding such as Reed-Solomon coding but also convolutional coding, or other LDPC encoding may be combined. Accordingly, the invention should not be construed as limited by the embodiments described above, but only by the claims.

  The encoder and decoder, the transmitter, and the receiver according to the present invention are useful in a transmission system that time-division-multiplexes a plurality of types of digital modulation schemes when the code lengths of LDPC codes are different in various transmission schemes.

DESCRIPTION OF SYMBOLS 1 Transmitter 11 Main signal processor 111 Transmission frame generator 112 Energy spreader 113 BCH encoder 114 LDPC encoder 115 Modulator 12 TMCC generator 2 Receiver 21 Main signal processor 211 Demodulator 212 LDPC decoder 213 BCH decoding unit 214 Energy despreading unit 22 TMCC demodulation / decoding unit

Claims (9)

An encoder that performs LDPC encoding of digital data using a check matrix unique to each coding rate,
An information length corresponding to each of coding rates 2/16, 4/16, 5/16, and 6/16, with a parity check matrix initial value table predetermined for each coding rate having a code length of 69120 bits as an initial value. Comprising: means for performing LDPC encoding using a parity check matrix including a partial matrix configured by periodically arranging one element of a partial matrix corresponding to 1 in a column direction with a plurality of types of cycles. Encoder.   The parity check matrix based on the parity check matrix initial value table of each of the coding rates 2/16, 4/16, 5/16, and 6/16 is an element of 1 periodically in the first cycle number as the partial matrix. Including a first submatrix arranged in the column direction, and a second submatrix that periodically arranges one element in the column direction at a second cycle number different from the first cycle number. The encoder of claim 1, characterized in that:   The parity check matrix based on the parity check matrix initial value table of each of the coding rates 2/16, 4/16, 5/16, and 6/16 is shifted in the row direction for each of the first cycle numbers, and the second matrix The encoder according to claim 2, further comprising a third submatrix that is parity-interleaved by arranging elements of 1 periodically in the column direction. An encoder that performs LDPC encoding of digital data using a check matrix unique to each coding rate,
A check matrix initial value table predetermined for each coding rate with a code length of 17280 bits is used as an initial value for each of coding rates 2/16, 3/16, 4/16, 5/16, and 6/16. A means for performing LDPC encoding using a parity check matrix including a partial matrix in which one element of a partial matrix corresponding to a corresponding information length is periodically arranged with a plurality of types of cycles in the column direction; An encoder characterized by.   The parity check matrix based on the parity check matrix initial value table of each of the coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 is periodically the first cycle number as the partial matrix. A first submatrix in which one element is arranged in the column direction, and a second submatrix in which one element is periodically arranged in the column direction at a second cycle number different from the first cycle number, The encoder according to claim 4, comprising:   The parity check matrix based on the parity check matrix initial value table of each of the coding rates 2/16, 3/16, 4/16, 5/16, and 6/16 is shifted in the row direction for each first cycle number. 6. The encoder according to claim 5, further comprising a third submatrix subjected to parity interleaving by arranging elements of 1 periodically in the column direction in the second cycle number.   7. A decoder, wherein the data encoded by the encoder according to claim 1 is subjected to LDPC decoding based on the check matrix.   A transmission apparatus comprising the encoder according to any one of claims 1 to 6.   A receiving apparatus comprising the decoder according to claim 7.