JP2019012642A - Organic el display panel and manufacturing method of organic el display panel - Google Patents

Abstract

To provide an organic EL display panel having a high pixel opening rate.SOLUTION: An organic EL display panel comprises: a substrate; a thin film semiconductor layer disposed on the substrate; a lower insulation layer disposed on the thin film semiconductor layer; an auxiliary electrode that is partially disposed on the lower insulation layer, that has a recessed part recessing to a substrate side, and that is for supplying power; an upper insulation layer disposed above the lower insulation layer and the auxiliary electrode; and an EL element disposed on the upper insulation layer. A contact hole that reaches the recessed part of the auxiliary electrode is provided in the upper insulation layer. The EL element comprises a pixel electrode that is disposed on a part where the contact hole in the upper insulation layer is not provided, a luminescent layer disposed on the pixel electrode, and a common electrode layer disposed on the luminescent layer and in the contact hole. In the contact hole, the common electrode layer is formed along a hole inner wall and an auxiliary electrode surface.SELECTED DRAWING: Figure 13

Description

  The present disclosure relates to an organic EL display panel using an organic EL (Electro Luminescence) element using an electroluminescence phenomenon of an organic material, and a manufacturing method thereof.

In recent years, an organic EL display panel in which a plurality of organic EL elements are arranged in a matrix on a substrate has been put into practical use as a display panel used in a display device such as a digital television.
In the organic EL display panel, the light emitting layer of each organic EL element and the adjacent organic EL element are generally partitioned by an insulating layer made of an insulating material. In an organic EL display panel for color display, an organic EL element forms subpixels that emit light in RGB colors, and unit pixels in color display are formed by combining adjacent RGB subpixels.

An organic EL element has a basic structure in which a light emitting layer containing an organic light emitting material is disposed between a pair of electrodes, and when driven, a hole is injected into the light emitting layer by applying a voltage between the pair of electrodes. Emits light upon recombination of electrons with electrons.
The top emission type organic EL element has an element structure in which a pixel electrode, an organic layer (including a light emitting layer), and a common electrode layer are sequentially provided on a substrate. The light from the light emitting layer is reflected by the pixel electrode made of a light reflective material and emitted upward from the common electrode layer made of a light transmissive material.

The above common electrode layer is often formed over the entire surface of the substrate, and when the electric resistance of the common electrode layer is large, the luminous efficiency is lowered without sufficient current being supplied due to a voltage drop at a portion far from the power feeding unit, Due to this, luminance unevenness may occur.
Therefore, a method of providing an auxiliary electrode for reducing the resistance of the common electrode layer has been proposed (for example, Patent Document 1). According to Patent Document 1, the auxiliary electrode is formed in the same layer as the pixel electrode, and the auxiliary electrode is electrically connected to the common electrode layer while being electrically insulated from the pixel electrode.

JP 2002-318556 A JP-A-5-163488

  However, when the auxiliary electrode is formed in the same layer as the pixel electrode, there is a problem in that the area of the pixel electrode on the substrate is reduced and the pixel aperture ratio is reduced. Further, depending on the manufacturing process of the organic EL display panel, a layer having a relatively high electrical resistance may be formed between the auxiliary electrode and the common electrode layer. In that case, the electric current between the auxiliary electrode and the common electrode layer is formed. There is a problem that resistance increases.

  The present disclosure solves the above-described problems, and does not reduce the pixel aperture ratio, and in the case where an organic layer having a relatively high electrical resistance is formed between the auxiliary electrode and the common electrode layer, An object of the present invention is to provide an organic EL display panel capable of reducing electrical resistance in electrical connection between the two and a manufacturing method suitable for manufacturing the organic EL display panel.

  An organic EL display panel according to an aspect of the present disclosure is partially disposed on a substrate, a thin film semiconductor layer disposed on the substrate, a lower insulating layer disposed on the thin film semiconductor layer, and a lower insulating layer. And a power supply auxiliary electrode having a recess recessed in the substrate side, a lower insulating layer, an upper insulating layer disposed above the auxiliary electrode, and an EL element disposed on the upper insulating layer. A contact hole reaching the concave portion of the auxiliary electrode is formed in the upper insulating layer. The EL element includes a pixel electrode disposed in a portion where no contact hole is formed on the upper insulating layer, a light emitting layer disposed on the pixel electrode, and a common electrode layer disposed on the light emitting layer and in the contact hole. And including. In the contact hole, the common electrode layer is formed along the hole inner wall and the auxiliary electrode surface.

  In the organic EL display panel according to one embodiment of the present disclosure, the auxiliary electrode is formed in a layer different from the pixel electrode, so that the area of the pixel electrode can be reduced, and as a result, the decrease in the pixel aperture ratio can be suppressed. Further, since the auxiliary electrode is formed in a dedicated layer, the resistance of the common electrode layer can be reduced by increasing the area of the auxiliary electrode. Further, even when an organic layer having a relatively high electrical resistance is formed between the auxiliary electrode and the common electrode layer due to the concave portion on the surface of the auxiliary electrode, the organic layer forming method and the common electrode layer forming method are not used. By using film formation methods having different step coverage, it is possible to easily realize a reduction in resistance of electrical connection between the auxiliary electrode and the common electrode layer.

3 is a schematic diagram showing a configuration of a display device 1. FIG. 3 is a schematic diagram showing a circuit configuration at 10a in each pixel of the display panel 10. FIG. 3 is a schematic diagram showing a circuit configuration of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 4 is a schematic diagram for explaining a manufacturing process of the display panel 10. FIG. 4 is a schematic diagram for explaining a manufacturing process of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 4 is a schematic diagram for explaining a manufacturing process of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 4 is a schematic diagram for explaining a manufacturing process of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG. 4 is a schematic diagram for explaining a manufacturing process of the display panel 10. FIG. 4 is a schematic diagram for explaining a cross-sectional configuration of the display panel 10. FIG. 3 is a schematic diagram showing a cross-sectional configuration of the display panel 10. FIG.

(Embodiment 1)
1.1 Configuration 1.1.1 Configuration of Display Device 1 The configuration of the display device 1 according to Embodiment 1 will be described with reference to FIG.
As illustrated in FIG. 1, the display device 1 includes a display panel 10 and a drive control circuit unit 20 connected to the display panel 10.

The display panel 10 is an organic EL (Electro Luminescence) panel using an electroluminescence phenomenon of an organic material, and a plurality of organic EL elements are arranged in a matrix, for example. The drive control circuit unit 20 includes four drive circuits 21 to 24 and a control circuit 25.
In the display device 1, the arrangement form of each circuit of the drive control circuit unit 20 with respect to the display panel 10 is not limited to the form shown in FIG. 1.

1.1.2 Circuit Configuration of Each Pixel 10a of Display Panel 10 In the display panel 10, a plurality of pixels 10a are arranged in a matrix to form a display area. The circuit configuration of each pixel 10a will be described with reference to FIG.
As shown in FIG. 2, in the display panel 10 according to the present embodiment, each pixel 10a has two transistors Tr ₁ and Tr ₂ , one capacitor C, and an organic EL element portion EL as a light emitting portion. It is configured. The transistor Tr ₁ is a drive transistor, and the transistor Tr ₂ is a switching transistor.

The gate G ₂ of the switching transistor Tr ₂ is connected to the scanning line Vscn, the source S ₂ is connected to the data line Vdat. The drain D ₂ of the switching transistor Tr ₂ is connected to the gate G ₁ of the driving transistor Tr _1.
The drain D ₁ of the driving transistor Tr ₁ is connected to the power line Va, source S ₁ is connected to the organic EL element portions EL of the pixel electrode (anode). The common electrode layer (cathode) in the organic EL element part EL is connected to the ground line Vcat.

The first terminal of the capacitor C is connected to the gate G ₁ of the drain D ₂ and the driving transistor Tr ₁ of the switching transistor Tr _2, the second end of the capacitor C is connected to the power supply line Va.
1.1.3 Circuit Configuration of Display Panel 10 The circuit configuration of the display panel 10 will be described with reference to FIG. In the display panel 10, pixels 10a having a circuit configuration as shown in FIG. 2 are arranged in a matrix as shown in FIG. 3 to form a display area 10A.

Gate lines GL-1 to n from the gate G ₂ of each pixel 10a arranged in a matrix is drawn, the connecting portion 10b which lies outside the display area 10A, the external connection terminal via the wiring connection portion CNscn-1~n It is connected to TMscn-1 to n and connected to the scanning lines Vscn-1 to n.
Similarly, source lines SL- ₁ to SL-m are drawn from the source S2 of each pixel 10a arranged in a matrix, and in the connection portion 10b, the external connection terminals TMdat-1 are connected via the wiring connection portions CNdat-1 to m. To m and to data lines Vdat-1 to m.

In addition, the power supply lines Va of the respective pixels are aggregated and connected to the external connection terminal TMa via the wiring connection portion CNa in the connection portion 10b.
In the display device 1 that performs color display, a plurality of adjacent pixels 10a (for example, three pixels 10a of red (R), green (G), and blue (B) emission colors) are used as sub-pixels, respectively. A plurality of subpixels may be combined to form one pixel.

1.1.4 Cross-sectional Configuration of Display Panel 10 The display panel 10 is a top emission type organic EL display panel, in which a TFT layer is formed below the Z-axis direction, and a planarization layer is formed thereon, and An EL layer is formed thereon.
(TFT layer)
The TFT layer will be described with reference to FIG. FIG. 4 is a diagram showing an example of a cross-sectional configuration of the display panel 10 on the YZ plane.

On the substrate 100, gate electrodes 101 and 102 are formed with a space therebetween. A gate insulating layer 103 is formed so as to cover the gate electrodes 101 and 102 and the surface of the substrate 100.
On the gate insulating layer 103, channel layers 104 and 105 are formed corresponding to the gate electrodes 101 and 102, respectively. A channel protective layer 106 is formed so as to cover the surfaces of the channel layers 104 and 105 and the gate insulating layer 103.

  A source electrode 107 and a drain electrode 108 are formed on the channel protective layer 106 so as to correspond to the gate electrode 101 and the channel layer 104 and are spaced apart from each other. Similarly, a source electrode 110 and a drain electrode 109 are formed at intervals from each other corresponding to the gate electrode 102 and the channel layer 105. Then, a passivation layer 112 is formed so as to cover the surfaces of the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106.

A contact hole is provided in the gate insulating layer 103 and the channel protective layer 106 above the contact region 102a of the gate electrode 102, and the drain electrode 108 is in contact with the gate electrode 102 at the bottom of the contact hole.
The channel protective layer 106 is provided with a contact hole above the contact region 104 a of the channel layer 104, and the source electrode 107 is in contact with the channel layer 104 at the bottom of the contact hole. Similarly, a contact hole is provided in the channel protective layer 106 above the contact region 104b of the channel layer 104, and the drain electrode 108 is in contact with the channel layer 104 at the bottom of the contact hole.

  The channel protective layer 106 is provided with a contact hole above the contact region 105 a of the channel layer 105, and the drain electrode 109 is in contact with the channel layer 105 at the bottom of the contact hole. Similarly, a contact hole is provided in the channel protective layer 106 above the contact region 105 b of the channel layer 105, and the source electrode 110 is in contact with the channel layer 105 at the bottom of the contact hole.

In addition, a contact hole is provided in the passivation layer 112 above the contact region 110a of the source electrode 110, and a pixel electrode 116 described later is in contact with the source electrode 110 at the bottom of the contact hole.
Note that the gate electrode 101 corresponds to the gate G ₂ in FIG. 2, the source electrode 107 corresponds to the source S ₂ in FIG. 2, and the drain electrode 108 corresponds to the drain D ₂ in FIG. Similarly, the gate electrode 102 corresponds to the gate G ₁ in FIG. 2, the source electrode 110 corresponds to the source S ₁ in FIG. 2, and the drain electrode 109 corresponds to the drain D ₁ in FIG.

(Flattening layer)
The planarization layer will be described with reference to FIGS. FIG. 5 is a diagram illustrating an example of a cross-sectional configuration of the XZ plane of the display panel 10.
A lower interlayer insulating layer 113 is formed on the passivation layer 112, and an auxiliary electrode 114 is formed on the lower interlayer insulating layer 113. An upper interlayer insulating layer 115 is formed so as to cover the surfaces of the auxiliary electrode 114 and the lower interlayer insulating layer 113.

As shown in FIG. 4, the lower interlayer insulating layer 113 and the upper interlayer insulating layer 115 are provided with contact holes above the contact region 110 a of the source electrode 110.
As shown in FIG. 5, the upper interlayer insulating layer 115 is provided with a contact hole above the contact region 114 a of the auxiliary electrode 114, and a common electrode layer 119 (described later) is provided at the bottom of the contact hole. Touching.

The auxiliary electrode 114 is provided to extend in the X-axis direction and the Y-axis direction, avoiding a contact hole above the contact region 110a of the source electrode 110 provided in the lower interlayer insulating layer 113 and the upper interlayer insulating layer 115. ing. The contact region 114a of the auxiliary electrode 114 is provided extending in the Y-axis direction every plural pixels (for example, three pixels) in the X-axis direction.
(EL layer)
The EL layer will be described with reference to FIG.

  On the upper interlayer insulating layer 115, pixel electrodes 116 are provided in units of pixels 10a in portions where no contact holes are formed above the contact regions 114a of the auxiliary electrodes 114. The pixel electrode 116 is connected to the source electrode through a contact hole formed above the contact region 110 a of the source electrode 110 of the passivation layer 112, the lower interlayer insulating layer 113, and the upper interlayer insulating layer 115.

A bank 117 is formed on the pixel electrode 116 so as to cover the edge of the pixel electrode 116. Openings corresponding to the respective pixels 10 a are formed by surrounding the banks 117.
A light emitting layer 118 is formed in the opening defined by the bank 117 on the pixel electrode 116.
A common electrode layer 119 is formed so as to cover the light emitting layer 118, the bank 117, and the upper interlayer insulating layer 115. The common electrode layer 119 is formed continuously in the entire display panel, and is connected to the auxiliary electrode through a contact hole in the upper interlayer insulating layer 115 provided above the contact region 114a of the auxiliary electrode 114.

1.2 Constituent materials The constituent materials of each part will be described.
(1) Substrate 100
Examples of the substrates 100 and 130 include glass substrates, quartz substrates, silicon substrates, molybdenum sulfide, copper, zinc, aluminum, stainless steel, magnesium, iron, nickel, gold, silver and other metal substrates, and semiconductor substrates such as gallium arsenide groups. A plastic substrate or the like can be used.

  As the plastic material, either a thermoplastic resin or a thermosetting resin may be used. For example, polyolefin such as polyethylene, polypropylene, ethylene-propylene copolymer, ethylene-vinyl acetate copolymer (EVA), cyclic polyolefin, modified polyolefin, polyvinyl chloride, polyvinylidene chloride, polystyrene, polyamide, polyimide (PI), Polyamideimide, polycarbonate, poly- (4-methylbenten-1), ionomer, acrylic resin, polymethyl methacrylate, acrylic-styrene copolymer (AS resin), butadiene-styrene copolymer, polio copolymer (EVOH) ), Polyesters such as polyethylene terephthalate (PET), polybutylene terephthalate, polyethylene naphthalate (PEN), precyclohexane terephthalate (PCT), polyethers, polyether ketones Polyethersulfone (PES), polyetherimide, polyacetal, polyphenylene oxide, modified polyphenylene oxide, polyarylate, aromatic polyester (liquid crystal polymer), polytetrafluoroethylene, polyvinylidene fluoride, other fluororesins, styrene, polyolefin Various types of thermoplastic elastomers such as polyvinyl chloride, polyurethane, fluororubber, chlorinated polyethylene, epoxy resin, phenol resin, urea resin, melamine resin, unsaturated polyester, silicone resin, polyurethane, etc. Copolymers, blends, polymer alloys and the like are mentioned, and a laminate obtained by laminating one or more of these can be used.

(2) Gate electrodes 101 and 102
As the gate electrodes 101 and 102, for example, a molybdenum-tungsten alloy (MoW) is employed. The configuration of the gate electrodes 101 and 102 is not limited to this, and for example, a laminated body (Ti / Al (or Al alloy) / Ti) of titanium (Ti) and aluminum (Al) can be employed. It is also possible to adopt the following materials.

  Materials that can be adopted include molybdenum (Mo), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), tantalum (Ta), niobium (Nb), silver (Ag), Metals such as gold (Au), platinum (Pt), palladium (Pd), indium (In), nickel (Ni), neodymium (Nd) or their alloys, or zinc oxide, tin oxide, indium oxide, gallium oxide Conductive metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO), or polyaniline, polypyrrole, Conductive polymers such as polythiophene, polyacetylene or the like, hydrochloric acid, sulfuric acid, sulfonic acid, etc. Acids, phosphorus hexafluoride, arsenic pentafluoride, Lewis acids such as iron chloride, halogen atoms such as iodine, metal atoms such as sodium and potassium added, or carbon black and metal particles dispersed Examples include conductive composite materials. Alternatively, a polymer mixture containing fine metal particles and conductive particles such as graphite may be used. These may be used alone or in combination of two or more.

(3) Gate insulating layer 103
As the gate insulating layer 103, for example, a stacked body of silicon oxide (SiO ₂ ) and silicon nitride (SiN _x ) is employed. However, the structure of the gate insulating layer 103 is not limited to this, and as a constituent material of the gate insulating layer, for example, any known organic material or inorganic material may be used as long as it has an electrical insulating property. Can be used.

As the organic material, for example, an acrylic resin, a phenol resin, a fluorine resin, an epoxy resin, an imide resin, a novolac resin, or the like can be used.
Examples of inorganic materials include silicon oxide, aluminum oxide, tantalum oxide, zirconium oxide, cerium oxide, zinc oxide, cobalt oxide and other metal oxides, silicon nitride, aluminum nitride, zirconium nitride, cerium nitride, zinc nitride, Examples thereof include metal nitrides such as cobalt nitride, titanium nitride, and tantalum nitride, and metal composite oxides such as barium strontium titanate and lead zirconium titanate. These can be used alone or in combination of two or more.

Furthermore, what processed the surface with the surface treating agent (ODTS OTS HMDS (beta) PTS) etc. is also contained.
(4) Channel layers 104 and 105
As the channel layers 104 and 105, for example, layers made of amorphous indium gallium zinc oxide (IGZO) are employed. The constituent material of the channel layers 104 and 105 is not limited to this, and an oxide semiconductor containing at least one selected from indium (In), gallium (Ga), and zinc (Zn) can be used. .
Further, low temperature polysilicon (LTPS) can be used as a constituent material of the channel layers 104 and 105.

(5) Channel protective layer 106
As the channel protective layer 106, for example, a layer made of silicon oxide (SiO ₂ ) is employed. The constituent material of the channel protective layer 106 is not limited to this. For example, silicon oxynitride (SiON), silicon nitride (SiN), or aluminum oxide (AlO _x ) can be used. Alternatively, a plurality of layers using the above materials can be stacked.

(6) Source electrodes 107 and 110, drain electrodes 108 and 109
As the source electrodes 107 and 110 and the drain electrodes 108 and 109, a laminate (Ti / Al (or Al alloy) / Ti) of titanium (Ti) and aluminum (Al) is employed. As the source electrodes 107 and 110 and the drain electrodes 108 and 109, a stacked body of copper manganese (CuMn), copper (Cu), and molybdenum (Mo) can be used.

(7) Passivation layer 112
As the passivation layer 112, for example, a layer made of silicon oxide (SiO ₂ ) is employed. The constituent material of the passivation layer is not limited to this. For example, silicon oxynitride (SiON), silicon nitride (SiN), or aluminum oxide (AlO _x ) can be used. Alternatively, a plurality of layers using the above materials can be stacked.

(8) Lower interlayer insulating layer 113
The lower interlayer insulating layer 113 is formed using, for example, an organic compound such as polyimide, polyamide, or acrylic resin material. The constituent material of the lower interlayer insulating layer 113 is not limited to this, and may be formed using an inorganic material such as silicon oxide (SiO ₂ ), silicon oxynitride (SiON), or silicon nitride (SiN).

(9) Auxiliary electrode 114
The auxiliary electrode 114 is made of a metal material such as tungsten, for example. The constituent material of the auxiliary electrode 114 is not limited to this, and a single layer of a metal layer, an alloy layer, or a transparent conductive layer can also be employed. Moreover, the structure which laminated | stacked the some film selected from a metal layer, an alloy layer, and a transparent conductive film may be sufficient. The metal layer can be made of, for example, a metal material containing tungsten oxide (WOx), molybdenum (Mo), silver (Ag), or aluminum (Al) in addition to tungsten (W). As the alloy layer, for example, APC (alloy of silver, palladium, copper), ARA (alloy of silver, rubidium, gold), MoCr (alloy of molybdenum and chromium), NiCr (alloy of nickel and chromium), etc. are used. Can do. As a constituent material of the transparent conductive layer, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like can be used.

(10) Upper interlayer insulating layer 115
The upper interlayer insulating layer 115 is formed using an organic compound such as polyimide, polyamide, or acrylic resin material. The constituent material of the lower interlayer insulating layer 113 is not limited to this, and may be formed using an inorganic material such as silicon oxide (SiO ₂ ), silicon oxynitride (SiON), or silicon nitride (SiN).

(11) Pixel electrode 116
The pixel electrode 116 is composed of a laminate of tungsten (W) and aluminum (Al) or an aluminum alloy. In the case of the top emission type display panel 10, the surface portion thereof preferably has high reflectivity.
Note that the pixel electrode 116 may employ not only the above-described configuration but also a single layer of a metal layer, an alloy layer, or a transparent conductive layer. Moreover, the structure which laminated | stacked the some film selected from a metal layer, an alloy layer, and a transparent conductive film may be sufficient. The metal layer can be made of a metal material including, for example, tungsten (W), tungsten oxide (WOx), silver (Ag), or aluminum (Al). As the alloy layer, for example, APC (alloy of silver, palladium, copper), ARA (alloy of silver, rubidium, gold), MoCr (alloy of molybdenum and chromium), NiCr (alloy of nickel and chromium), etc. are used. Can do. As a constituent material of the transparent conductive layer, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like can be used. For example, the pixel electrode 116 may be a stacked body of a WOx / Al alloy, an IZO / Al alloy, an ITO / Al alloy, or the like.

(12) Bank 117
The bank 117 is formed using an organic material such as a resin and has an insulating property. Examples of the organic material used for forming the bank 117 include acrylic resin, polyimide resin, and novolac type phenol resin. The bank 117 preferably has organic solvent resistance. Furthermore, since the bank 117 may be subjected to an etching process, a baking process, or the like during the manufacturing process, the bank 117 should be formed of a highly resistant material that does not excessively deform or alter the process. Is preferred. Moreover, in order to give the surface water repellency, the surface can be treated with fluorine.

Furthermore, as for the structure of the bank 117, not only a single layer structure as shown in FIG. 4 but also a multilayer structure of two or more layers can be adopted. In this case, the above materials can be combined for each layer, and an inorganic material and an organic material can be used for each layer.
(13) Light emitting layer 118
As described above, the light emitting layer 118 has a function of emitting light by generating an excited state by injecting and recombining holes and electrons. As a material used for forming the light-emitting layer 118, it is necessary to use a light-emitting organic material that can be formed by a wet printing method.

  Specifically, for example, the oxinoid compound, perylene compound, coumarin compound, azacoumarin compound, oxazole compound, oxadiazole compound, perinone compound, pyrrolopyrrole compound, naphthalene compound, anthracene compound, fluorene compound, fluoranthene described in Patent Document 2 Compound, tetracene compound, pyrene compound, coronene compound, quinolone compound and azaquinolone compound, pyrazoline derivative and pyrazolone derivative, rhodamine compound, chrysene compound, phenanthrene compound, cyclopentadiene compound, stilbene compound, diphenylquinone compound, styryl compound, butadiene compound, dicyano Methylenepyran compounds, dicyanomethylenethiopyran compounds, fluorescein compounds, pyrylium compounds, thiapyril Compounds, selenapyrylium compounds, telluropyrylium compounds, aromatic aldadiene compounds, oligophenylene compounds, thioxanthene compounds, anthracene compounds, cyanine compounds, acridine compounds, metal complexes of 8-hydroxyquinoline compounds, metal complexes of 2-bipyridine compounds, It is preferably formed of a fluorescent material such as a complex of a Schiff salt and a group III metal, an oxine metal complex, or a rare earth complex. As a constituent material of the transparent conductive layer, for example, indium tin oxide (ITO), indium zinc oxide (IZO), or the like can be used.

(14) Common electrode layer 119
The common electrode layer 119 is formed using, for example, indium tin oxide (ITO) or indium zinc oxide (IZO). As in this embodiment, in the case of the display panel 10 according to this embodiment of the top emission type, it is necessary to be formed of a light transmissive material. About light transmittance, it is preferable that the transmittance | permeability shall be 80 [%] or more.

1.3 Manufacturing Method A manufacturing method of the display panel 10 will be described with reference to FIGS.
(1) Formation of gate electrodes 101 and 102 and gate insulating layer 103 Gate electrodes 101 and 102 spaced apart from each other are formed on the upper surface of the substrate 100 in the Z-axis direction, for example, as shown in FIG. . The gate electrodes 101 and 102 are formed, for example, by forming a metal thin film made of MoW on the surface of the substrate 100 using a metal sputtering method and forming a resist pattern on the metal thin film using a photolithography method. Next, after performing wet etching, the resist pattern is removed. Thereby, the gate electrodes 101 and 102 are formed.

Note that the wiring 101a illustrated in FIG. 6A corresponds to the gate lines GL-1 to GLn in FIG.
A gate insulating layer 103 is formed so as to cover the surfaces of the gate electrodes 101 and 102 and the substrate 100. The gate insulating layer 103 is formed using a plasma CVD (Chemical Vapor Deposition) method or a sputtering method.

(2) Formation of Channel Layers 104 and 105 and Channel Protection Layer 106 Channel layers 104 and 105 spaced apart from each other are formed on the surface of the gate insulating layer 103 as shown in FIG. 6B, for example. The channel layers 104 and 105 are formed by, for example, forming an oxide semiconductor film using a sputtering method and patterning the film using a photolithography method and a wet etching method.

A channel protective layer 106 is stacked so as to cover the surfaces of the channel layers 104 and 105 and the gate insulating layer 103. The channel protective layer 106 is formed by stacking layers made of SiO using a plasma CVD method or a sputtering method, and performing an annealing process at a temperature equal to or higher than the film formation temperature in a dry air or oxygen atmosphere after the film formation. Made.
(3) Formation of source electrodes 107 and 110, drain electrodes 108 and 109, formation of passivation layer 112 On the surface of the channel protective layer 106, for example, as shown in FIG. 6C, the source electrodes 107 and 110 and the drain electrode 108 and 109 are formed.

  First, contact holes are formed in corresponding portions of the gate insulating layer 103 and the channel protective layer 106 (portions above the contact regions 102a, 104a, 104b, 105a, and 105b of the gate electrode 102 and the channel layers 104 and 105). The contact hole is formed by patterning using a photolithography method and then performing etching using a dry etching method. Next, using a sputtering method, for example, a metal thin film made of Ti, a metal thin film made of Al, and a metal thin film made of Ti are sequentially laminated. Then, the source electrodes 107 and 110 and the drain electrodes 108 and 109 are formed by patterning using a photolithography method and a wet etching method.

Note that the wiring 107a illustrated in FIG. 6C corresponds to the source lines SL-1 to n in FIG. A wiring 109a shown in FIG. 6C corresponds to the power supply line Va in FIG.
A passivation layer 112 is formed so as to cover the source electrodes 107 and 110, the drain electrodes 108 and 109, and the channel protective layer 106. The passivation layer 112 is formed by using a plasma CVD method, an ALD (Atomic Layer Deposition) method, or a sputtering method.

(4) Formation of Lower Interlayer Insulating Layer 113, Auxiliary Electrode 114, and Upper Interlayer Insulating Layer 115 The lower interlayer insulating layer 113 is laminated so as to cover the passivation layer 112. The lower interlayer insulating layer 113 is formed by applying the organic material described above and planarizing the surface.
The auxiliary electrode 114 is formed by forming a metal film made of tungsten (W) using a sputtering method or a vacuum evaporation method, and then patterning using a photolithography method and an etching method. For example, as shown in FIG. 6D, a region 114H extending in the X-axis direction and a region 114V extending in the Y-axis direction are provided so as to avoid a portion located above the contact region 110a of the source electrode 110. Next, the auxiliary electrode 114 is patterned. The region 114H is provided to extend over a plurality of pixels in the X-axis direction, and the region 114V is provided to extend over a plurality of pixels in the Y-axis direction. A contact region 114a of the auxiliary electrode 114 is provided in the region 114V.

An upper interlayer insulating layer 115 is laminated so as to cover the lower interlayer insulating layer 113 and the auxiliary electrode 114. The upper interlayer insulating layer 115 is formed by applying the organic material described above and planarizing the surface.
(5) Formation of Pixel Electrode 116 A contact hole is formed on the contact region 110a of the source electrode 110 in the lower interlayer insulating layer 113 and the upper interlayer insulating layer 115, and the pixel electrode 116 is formed.

  The contact hole is formed by patterning using a photolithography method and then performing etching using a dry etching method. The pixel electrode 116 is formed by using a sputtering method, a vacuum deposition method, or the like to form a metal film by sequentially laminating a thin film made of tungsten (W) and a thin film made of aluminum (Al) or an aluminum alloy. Lithography and etching are used, for example, by patterning as shown in FIG. By patterning the plurality of pixel electrodes 116 in an array, a plurality of pixel electrodes 116 are formed on the upper interlayer insulating layer 115 as shown in FIG.

Note that the pixel electrode 116 is in contact with the contact region of the source electrode 110 through the contact hole and is electrically connected to the source electrode 110.
Further, on the contact region 114a of the auxiliary electrode 114 in the upper interlayer insulating layer 115, a procedure similar to that for forming a contact hole on the contact region 110a of the source electrode 110 in the lower interlayer insulating layer 113 and the upper interlayer insulating layer 115 is used. Open a contact hole.

(6) Formation of Bank 117 The bank 117 is formed so as to cover the edge of the pixel electrode 116. The bank 117 surrounds the opening that defines each pixel, and is provided so that the surface of the pixel electrode 116 is exposed at the bottom.
In forming the bank 117, the row bank 117H is formed as shown in FIG. 7B, and then the column bank 117V is formed as shown in FIG. 7C.

  In forming the bank 117, first, a film made of a constituent material of the bank 117 (for example, a photosensitive resin material) is formed on the pixel electrode 116 and the upper interlayer insulating layer 115 by using a spin coat method or the like. Then, the resin film is patterned to form the row bank 117H and the column bank 117V in this order, thereby forming an opening through which the pixel electrode 116 is exposed. The patterning of the row bank 117H and the column bank 117V is performed by performing exposure using a photomask above the resin film, and performing a development process and a baking process.

(7) Formation of Light-Emitting Layer 118 The light-emitting layer 118 is formed by applying an ink containing a constituent material in the opening defined by the bank 117 using an ink jet method, and then baking it. Specifically, in this step, the pixel electrode 116 exposed in the opening is filled with ink containing a material for any one of R, G, and B by an inkjet method, and the filled ink is dried under reduced pressure. Then, by baking, a light emitting layer 118 is formed as shown in FIG. At this time, in the ink application of the light emitting layer 118, first, a solution for forming the light emitting layer 118 is applied using a droplet discharge device. When the application of the ink for forming any one of the red light emitting layer, the green light emitting layer, and the blue light emitting layer is completed, the process of applying another color ink and then applying the third color ink is repeated. The three colors of ink are applied sequentially. Thereby, a red light emitting layer, a green light emitting layer, and a blue light emitting layer are repeatedly formed side by side.

(8) Formation of Common Electrode Layer 119 After forming the light emitting layer 123, the common electrode layer is formed over the entire surface of the display panel 10 by CVD (Chemical Vapor Deposition), sputtering, or the like as shown in FIG. 119 is formed.
The common electrode layer 119 is also formed on the contact hole where the contact region 114a of the auxiliary electrode 114 on the upper interlayer insulating layer 115 is exposed. The common electrode layer 119 is in contact with the contact region 114a of the auxiliary electrode 114 through the contact hole and is electrically connected to the auxiliary electrode 114.

1.4 Effect Since the display panel 10 forms the auxiliary electrode 114 in a layer different from the pixel electrode 116, the area of the pixel electrode 116 can be reduced, and as a result, the decrease in the pixel aperture ratio can be suppressed.
Further, since the auxiliary electrode 114 is formed in a dedicated layer, the degree of freedom of wiring of the auxiliary electrode 114 is high. Specifically, if the restriction that the auxiliary electrode 114 is patterned on the lower interlayer insulating layer 113 while avoiding the contact hole for electrically connecting the pixel electrode 116 and the source electrode 110 is observed, the upper interlayer insulating layer 113 may be formed. In addition, the auxiliary electrode 114 can be freely patterned. Thereby, the area of the auxiliary electrode 114 can be easily increased, and as a result, the resistance of the common electrode layer can be reduced.

2 Modification Although the display panel 10 according to Embodiment 1 has been described, the present disclosure is not limited to the above-described embodiment except for essential characteristic components. For example, embodiments obtained by subjecting the embodiments to various modifications conceived by those skilled in the art, and embodiments realized by arbitrarily combining the components and functions in each embodiment without departing from the spirit of the present invention Are also included in this disclosure. Below, the modification of the display panel 10 is demonstrated as an example of such a form.

(1) In the first embodiment, the auxiliary electrode 114 is formed between the lower interlayer insulating layer 113 and the upper interlayer insulating layer constituting the planarization layer. However, the formation position of the auxiliary electrode is not limited to this. Absent. The auxiliary electrode can also be formed on the TFT layer.
Hereinafter, as a display panel according to Modification Example 1, a display panel in which auxiliary electrodes are formed in a TFT layer will be described. Note that the description of the same configuration, constituent materials, and manufacturing method as those in Embodiment 1 is omitted.

(1-1. Configuration)
A configuration of the display panel according to the first modification will be described with reference to FIGS. FIG. 8 is a diagram illustrating an example of a cross-sectional configuration of the display panel along the YZ plane, and FIG. 9 is a diagram illustrating an example of a cross-sectional configuration of the display panel along the XZ plane.
As shown in FIG. 9, an auxiliary electrode 111 is formed on the channel protective layer 106 at a distance from the source electrodes 107 and 110 and the drain electrodes 108 and 109. Then, a passivation layer 112 is formed so as to cover the surfaces of the source electrodes 107 and 110, the drain electrodes 108 and 109, the auxiliary electrode 111 and the channel protective layer 106.

A lower interlayer insulating layer 113 is formed on the passivation layer 112. In the passivation layer 112 and the lower interlayer insulating layer 113, a contact hole is provided above the contact region 111a of the auxiliary electrode 111, and the common electrode layer 119 is in contact with the auxiliary electrode 111 at the bottom of the contact hole. .
Unlike the first embodiment described above, as shown in FIGS. 8 and 9, the auxiliary electrode 114 and the upper interlayer insulating layer 115 are not formed on the lower interlayer insulating layer 113, but the pixel electrode 116, the bank 117, and the common electrode layer. 119 is formed.

Although not shown, the auxiliary electrode 111 is continuously provided in a plurality of pixels by extending in the X axis direction and / or the Y axis direction, avoiding the source electrodes 107 and 110 and the drain electrodes 108 and 109. It has been. Note that the contact region 111a of the auxiliary electrode 111 is provided extending in the Y-axis direction every plurality of pixels in the X-axis direction.
(1-2. Constituent materials)
As the auxiliary electrode 111, the same constituent material as the source electrodes 107 and 110 and the drain electrodes 108 and 109, that is, a laminate (Ti / Al (or Al alloy) / Ti) of titanium (Ti) and aluminum (Al), A laminate of copper manganese (CuMn), copper (Cu), and molybdenum (Mo) can be used.

(1-3. Manufacturing method)
A method for manufacturing a display panel according to Modification 1 will be described.
An auxiliary electrode 111 is formed on the surface of the channel protective layer 106. The auxiliary electrode 111 is formed by using a sputtering method, in which a metal thin film made of Ti, a metal thin film made of Al, and a metal thin film made of Ti are sequentially laminated. Then, by using a photolithography method and a wet etching method, the auxiliary electrode 111 is formed by patterning as shown in FIG. Note that the auxiliary electrode 111 can be formed at the same time as the formation of the source electrodes 107 and 110 and the drain electrodes 108 and 109.

The opening of the contact hole on the contact region 111a of the auxiliary electrode 111 in the lower interlayer insulating layer 113 is the same as the opening of the contact hole on the contact region 114a of the auxiliary electrode 114 in the upper interlayer insulating layer 115 in the first embodiment. It can be done with the procedure.
(1-4. Effects)
In the display panel 10 according to the first modification, the auxiliary electrode 114 is formed in a layer different from the pixel electrode 116, so that the area of the pixel electrode 116 can be suppressed, and as a result, the decrease in the pixel aperture ratio can be suppressed.

In addition, since the auxiliary electrode 111 is formed of the same constituent material in the same layer as the source electrodes 107 and 110 and the drain electrodes 108 and 109, the manufacturing process can be simplified.
(2) In the display panel according to Modification 1, the auxiliary electrode is formed on the TFT layer and the auxiliary electrode is not formed on the planarizing layer. However, the auxiliary electrode is formed on both the TFT layer and the planarizing layer. Also good.
Hereinafter, as a display panel according to Modification 2, a display panel in which auxiliary electrodes for both the TFT layer and the planarization layer are formed will be described. In addition, description is abbreviate | omitted about the same structure, constituent material, and manufacturing method as Embodiment 1 and the modification 1. FIG.

(2-1) Configuration A configuration of a display panel according to Modification 2 will be described with reference to FIG.
As shown in FIG. 11, the auxiliary electrode 111 is formed on the channel protective layer 106 at a distance from the source electrodes 107 and 110 and the drain electrodes 108 and 109 as in the first modification.

Similarly to the first embodiment, the auxiliary electrode 114 and the upper interlayer insulating layer 115 are formed on the lower interlayer insulating layer 113.
In the passivation layer 112 and the lower interlayer insulating layer 113, a contact hole is provided above the contact region 111a of the auxiliary electrode 111, and the auxiliary electrode 114 is in contact with the auxiliary electrode 111 at the bottom of the contact hole.

(2-2) Manufacturing Method A display panel manufacturing method according to Modification 2 will be described.
As in the first modification, the auxiliary electrode 111 is formed on the surface of the channel protective layer 106, and then a contact hole is opened above the contact region 111 a of the auxiliary electrode 111 in the lower interlayer insulating layer 113.

  After opening a contact hole in the lower interlayer insulating layer 113, an auxiliary electrode 114 is formed. The auxiliary electrode 114 is formed by using a sputtering method, a vacuum deposition method, or the like, forming a metal film made of tungsten (W), and then patterning using a photolithography method and an etching method, for example, as shown in FIG. That is done. The auxiliary electrode 114 and the auxiliary electrode 111 are in contact with each other at the bottom of the contact hole formed in the lower interlayer insulating layer 113 above the contact region 111a of the auxiliary electrode 111. Then, in the contact region 114 a provided in the auxiliary electrode 114, the common electrode layer 119 and the auxiliary electrode 114 are in contact with each other.

(2-3) Effect Since the display panel 10 according to the modification 2 forms the auxiliary electrode 114 in a layer different from the pixel electrode 116, the area of the pixel electrode 116 can be suppressed, and as a result, the pixel aperture ratio decreases. Can be suppressed.
Further, since the auxiliary electrode 114 is formed in a dedicated layer, the degree of freedom of wiring of the auxiliary electrode 114 is high. Thereby, the area of the auxiliary electrode 114 can be easily increased, and as a result, the resistance of the common electrode layer can be reduced.

In addition, since the auxiliary electrode 111 is formed of the same constituent material in the same layer as the source electrodes 107 and 110 and the drain electrodes 108 and 109, the manufacturing process can be simplified.
(3) In the manufacturing process of the organic EL display panel, an electron transport layer having a function of transporting electrons injected from the common electrode layer to the light emitting layer between the light emitting layer and the common electrode layer in order to improve luminous efficiency. It is possible to form an organic layer such as After the light emitting layer is formed, when an organic layer is formed on the front surface of the display panel using a film forming method such as a vacuum evaporation method, an organic layer having a relatively high electrical resistance is also formed between the auxiliary electrode and the common electrode layer. There is a problem that the electrical resistance between the auxiliary electrode and the common electrode layer is increased. On the other hand, by using a mask to avoid the contact portion between the auxiliary electrode and the common electrode layer, an organic layer is formed to prevent the electrical resistance between the auxiliary electrode and the common electrode layer from increasing. Can do. Further, by devising the shape of the contact portion of the auxiliary electrode with the common electrode layer, it is possible to prevent an increase in electrical resistance between the auxiliary electrode and the common electrode layer without performing mask vapor deposition.

In the case where an organic layer such as an electron transport layer is formed between the light-emitting layer and the common electrode layer as a display panel according to the modification 3, the electric power between the auxiliary electrode and the common electrode layer is not performed without performing mask vapor deposition. A display panel capable of preventing an increase in resistance will be described. In addition, description is abbreviate | omitted about the same structure, constituent material, and manufacturing method as Embodiment 1, the modification 1, and the modification 2. FIG.
(3-1. Configuration)
A configuration of a display panel according to Modification 3 will be described with reference to FIG. FIG. 13 is a diagram illustrating an example of a cross-sectional configuration of the XZ plane of the display panel.

  In the display panel according to the third modification, the electron transport layer 120 is formed between the light emitting layer 118 and the common electrode layer 119. The electron transport layer 120 is formed continuously in the entire display panel 10. That is, the electron transport layer 120 is also formed above the auxiliary electrode 114 exposed at the bottom of the contact hole formed in the upper interlayer insulating layer 115, and the common electrode layer 119 is further formed thereabove.

A connection portion between the auxiliary electrode 114 and the common electrode layer 119 in the display panel according to Modification 3 will be described with reference to FIG. 14 is a schematic cross-sectional view of a connection portion between the auxiliary electrode 114 and the common electrode layer 119 in the display panel according to the third modification, corresponding to the portion denoted by reference numeral 200 in FIG. 13 in the display panel of the first embodiment. .
As shown in FIG. 14, a contact hole is formed in a part of the lower interlayer insulating layer 113 located below the auxiliary electrode 114, and the passivation layer 112 is exposed at the bottom. Along the contact hole, a recess is formed in the auxiliary electrode 114 that is recessed into the passivation layer 112 side (substrate 100 side).

An upper interlayer insulating layer 115 is formed above the auxiliary electrode 114, and a contact hole is formed in the upper interlayer insulating layer 115 to expose the contact region 114 a including the concave portion of the auxiliary electrode 114.
An electron transport layer 120 is formed above the upper interlayer insulating layer 115 and the auxiliary electrode 114 exposed by the contact hole. The electron transport layer 120 is completely or partially missing (between the end portions 120a and 120b or between the end portions 120c and 120d in the drawing) in the concave portion of the auxiliary electrode 114. The contact surface 114c is exposed.

A common electrode layer 119 is formed above the electron transport layer 120. The common electrode layer 119 is formed so as to be in direct contact with the contact surface 114c of the auxiliary electrode 114 exposed at the missing portion (between the end portions 120a and 120b or between the end portions 120c and 120d) of the electron transport layer 120. ing.
(3-2. Constituent materials)
The electron transport layer 120 is made of an organic material having a high electron transport property. Examples of the organic material used for the electron transport layer 120 include π-electron low molecular weight organic materials such as an oxadiazole derivative (OXD), a triazole derivative (TAZ), and a phenanthroline derivative (BCP, Bphen). The electron transport layer 120 may include a layer formed by doping an organic material having a high electron transport property with a doped metal selected from an alkali metal or an alkaline earth metal. Further, the electron transport layer 120 may include a layer formed of sodium fluoride. Specifically, the alkali metal is Li (lithium), Na (sodium), K (potassium), Rb (rubidium), Cs (cesium), or Fr (francium). The alkaline earth metal is specifically Ca (calcium), Sr (strontium), Ba (barium), or Ra (radium).

(3-3. Manufacturing method)
A method for manufacturing a display panel according to Modification 3 will be described with reference to FIG.
FIG. 15 is a diagram for explaining a method for manufacturing a connection portion between the auxiliary electrode 114 and the common electrode layer 119 in the display panel according to the third modification.
First, a lower interlayer insulating layer 113 is formed on the passivation layer 112 (FIG. 15A), and a pattern is formed on the formed lower interlayer insulating layer 113 using a photolithography method, and then etching is performed using a dry etching method. By executing this, a contact hole is opened (FIG. 15B).

  After opening a contact hole in the lower interlayer insulating layer 113, a metal film made of tungsten (W) is formed using a sputtering method or a vacuum evaporation method, and patterned by using a photolithography method and an etching method, The auxiliary electrode 114 is formed (FIG. 15C). At this time, the concave portion of the auxiliary electrode 114 is formed by forming a metal film along the inner wall of the contact hole.

After the auxiliary electrode 114 is formed, an upper interlayer insulating layer is formed so as to cover the lower interlayer insulating layer 113 and the auxiliary electrode 114 (FIG. 15D), and a photolithography method is applied to the formed upper interlayer insulating layer 115. After the pattern is used, contact holes are formed by performing etching using a dry etching method (FIG. 15E).
After opening a contact hole in the lower interlayer insulating layer 113, the electron transport layer 120 is formed by vacuum deposition or the like (FIG. 15 (f)). At this time, the film is formed such that a contact surface 114c of the concave portion of the auxiliary electrode 114 is intentionally missing (stepped) and the contact surface 114c of the concave portion of the auxiliary electrode 114 is exposed in the missing portion.

  After the electron transport layer 120 is formed, the common electrode layer 119 is formed by a CVD (Chemical Vapor Deposition) method, a sputtering method, or the like so as to cover the electron transport layer 120 (FIG. 15G). At this time, the common electrode layer 119 is formed so as to go around the missing portion of the electron transport layer 120 and directly contact the contact surface 114 c of the concave portion of the auxiliary electrode 114 exposed at the missing portion of the electron transport layer 120.

(3-4. Configuration in which auxiliary electrode 114 and common electrode layer 119 are in direct contact)
In the auxiliary electrode 114, it is desirable that the inclination angle of the contact surface 114c be 60 degrees or more and 120 degrees or less. If it is less than 60 [degrees], the electron transport layer 120 will not be disconnected, and it will be difficult to ensure electrical connection with the common electrode layer 119. On the other hand, when the angle exceeds 120 degrees, the common electrode layer 119 is also cut off at the inner wall of the concave portion of the auxiliary electrode 114, and the auxiliary electrode 114 is less likely to contact the common electrode layer 119. Since this inclination angle coincides with the inclination angle of the side surface of the contact hole formed in the lower interlayer insulating layer 113, it can be controlled by the exposure amount when the contact hole is formed in the lower interlayer insulating layer 113. The depth of the concave portion of the auxiliary electrode 114 is, for example, in the range of 1 [μm] to 7 [μm]. The width of the concave portion of the auxiliary electrode 114 is, for example, in the range of 2 [μm] to 10 [μm].

  With such a shape, the electron transport layer 120 formed on the auxiliary electrode 114 is formed to be interrupted (disconnected) in the concave portion of the auxiliary electrode 114. Specifically, in the electron transport layer 120, the end portions 120a and 120b (or between the end portions 120c and d) are spaced apart so that the contact surface 114c of the auxiliary electrode 114 is exposed. On the other hand, the common electrode layer 119 is formed in contact with the contact surface 114c of the auxiliary electrode 114 so as to go around between the end portions 120a and 120b (or between the end portions 120c and 120d) of the electron transport layer 120.

  The auxiliary electrode 114 is desirably formed by a film formation method (for example, a sputtering method or a CVD method) with excellent step coverage so as not to be disconnected at the side surface of the contact hole of the lower interlayer insulating layer 113. Further, even if the film thickness of the auxiliary electrode 114 is excessively thin even by a film formation method having excellent step coverage, a step breakage may occur. Therefore, the film thickness is preferably 25 [nm] or more. .

  The electron transport layer 120 is desirably formed by a film formation method (for example, a vacuum evaporation method) having relatively inferior step coverage so that the contact surface 114c is exposed at the concave portion of the auxiliary electrode 114 to be exposed. In addition, when the thickness of the electron transport layer 120 is excessively thin, electrons move directly from the common electrode layer 119 to the light emitting layer 118, and the function of limiting the injection of electrons into the light emitting layer 118 cannot be achieved. Therefore, it is desirable that the thickness of the electron transport layer 120 be 3 nm or more. On the other hand, increasing the thickness of the electron transport layer 120 reduces the transmittance of the electron transport layer 120 and inhibits the occurrence of step breakage. In order not to excessively attenuate the light passing through the electron transport layer 120 and to intentionally generate a step break in the concave portion of the auxiliary electrode 114, the thickness of the electron transport layer 120 is formed to 40 nm or less. Is preferred.

  The common electrode layer 119 is desirably formed by a film formation method (for example, a sputtering method or a CVD method) with excellent step coverage so that the common electrode layer 119 is formed around the stepped portion of the electron transport layer 120. If the common electrode layer 119 is excessively thin, it may cause a step breakage. Therefore, it is desirable to form the common electrode layer 119 with a film thickness of 25 [nm] or more. On the other hand, since increasing the thickness of the common electrode layer 119 decreases the transmittance of the common electrode layer 119, it is desirable to form the common electrode layer 119 with a thickness of 300 [nm] or less.

(3-5. Effect)
In the display panel according to Modification 3, the electron transport layer 120 is disconnected by providing a recess in the auxiliary electrode 114, and the contact surface 114c of the auxiliary electrode 114 exposed by the disconnection and the common electrode layer 119 are in direct contact with each other. It is a configuration. With such a configuration, when forming the electron transport layer 120, it is not necessary to perform mask vapor deposition in order to avoid the auxiliary electrode 114, and it is possible to avoid a decrease in productivity due to high-precision alignment of the precision mask. it can.

In addition, when the auxiliary electrode is formed on the TFT layer and the planarization layer as in the display panel according to the modified example 2, the same effect can be obtained by forming the auxiliary electrode as shown in FIGS.
(4) In the display panel according to Modification 3, the electron transport layer 120 is missing so that the contact surface 114c is exposed in the recess of the auxiliary electrode 114. However, the common electrode layer 119, the auxiliary electrode 114, If the electrical resistance in the electrical connection can be reduced, the contact surface 114c may not be completely exposed without being lost. For example, in the electron transport layer 120, the portion in contact with the contact surface 114 c in the recess of the auxiliary electrode 114 is thinned to a thickness of, for example, 1 [nm] or less. The common electrode layer 119 may be electrically connected to the auxiliary electrode 114 with an electric resistance lower than that of the layer 120.

(5) In the above-described embodiment, a hole injection layer may be formed between the pixel electrode 116 and the light emitting layer 118.
The hole injection layer has a function of assisting hole generation and stably injecting and transporting holes to the light emitting layer 118. The hole injection layer may be formed of, for example, an oxide such as silver (Ag), molybdenum (Mo), chromium (Cr), vanadium (V), tungsten (W), nickel (Ni), iridium (Ir), or PEDOT ( It is a layer made of a conductive polymer material such as a mixture of polythiophene and polystyrenesulfonic acid.

  (6) Each of the embodiments described above shows a preferred specific example of the present invention. The numerical values, shapes, materials, constituent elements, arrangement positions and connection forms of the constituent elements, steps, order of steps, and the like shown in the embodiments are merely examples, and are not intended to limit the present invention. In addition, among the constituent elements in the embodiment, steps that are not described in the independent claims indicating the highest concept of the present invention are described as arbitrary constituent elements constituting a more preferable form.

In addition, the order in which the above steps are performed is for illustration in order to specifically describe the present invention, and may be in an order other than the above. Moreover, a part of said process may be performed simultaneously with another process (parallel).
Further, for easy understanding of the invention, the scales of the components shown in the above-described embodiments may be different from actual ones. The present invention is not limited by the description of each of the above embodiments, and can be appropriately changed without departing from the gist of the present invention.

Moreover, you may combine at least one part among the functions of each embodiment and its modification.
Furthermore, various modifications in which the present embodiment is modified within the range conceivable by those skilled in the art are also included in the present invention.
3 Supplement The configuration of the present disclosure will be further described below.

  (1) An organic EL display panel according to a first aspect of the present disclosure includes a substrate, a thin film semiconductor layer disposed on the substrate, a lower insulating layer disposed on the thin film semiconductor layer, and a portion on the lower insulating layer An auxiliary electrode for power feeding having a recess recessed into the substrate side, an upper insulating layer disposed above the lower insulating layer and the auxiliary electrode, an EL element disposed on the upper insulating layer, Is provided. A contact hole reaching the concave portion of the auxiliary electrode is formed in the upper insulating layer. The EL element includes a pixel electrode disposed in a portion where no contact hole is formed on the upper insulating layer, a light emitting layer disposed on the pixel electrode, and a common electrode layer disposed on the light emitting layer and in the contact hole. And including. In the contact hole, the common electrode layer is formed along the hole inner wall and the auxiliary electrode surface.

  (2) The organic EL display panel according to the second aspect of the present disclosure is the organic EL display panel according to the first aspect. The EL element is further disposed on the light emitting layer, in the contact hole, and below the common electrode layer. Functional layer. In the contact hole, the functional layer is formed along the inner wall of the hole and the surface of the auxiliary electrode, the portion located on the inner wall of the concave portion of the auxiliary electrode is missing or thinned, and the common electrode layer is the functional layer It is in direct contact with the exposed auxiliary electrode due to the lack of, and is electrically connected to the auxiliary electrode at a portion where the functional layer is thinned with a resistance lower than that of the other functional layer portions.

  (3) The organic EL display panel according to the third aspect of the present disclosure is a thin film semiconductor when the auxiliary electrode is defined as the first auxiliary electrode and the contact hole is defined as the first contact hole in the organic EL display panel according to the first aspect. The layer includes a gate electrode disposed on the substrate, a source electrode and a drain electrode disposed above the gate electrode, and a second auxiliary electrode disposed in the same layer as the source electrode and the drain electrode. A second auxiliary electrode disposed in a portion located below the auxiliary electrode. A second contact hole reaching the second auxiliary electrode is formed in the lower insulating layer. In the second contact hole, the first auxiliary electrode is formed along the inner wall of the hole and the surface of the second auxiliary electrode.

  (4) A method of manufacturing an organic EL display panel according to a fourth aspect of the present disclosure includes a step of forming a thin film semiconductor layer on a substrate, a step of forming a lower insulating layer on the thin film semiconductor layer, Forming a power supply auxiliary electrode having a recess recessed into the substrate side, forming a lower insulating layer and an upper insulating layer above the auxiliary electrode, and forming an auxiliary electrode on the upper insulating layer. And a step of forming an EL element on the upper insulating layer. The step of forming the EL element includes a step of forming a pixel electrode in a portion where the contact hole on the upper insulating layer is not opened, a step of forming a light emitting layer on the pixel electrode, a step on the light emitting layer and in the contact hole Forming a common electrode layer. In the step of forming the common electrode layer, the common electrode layer is formed in the contact hole along the inner wall of the hole and the surface of the auxiliary electrode.

  (5) The method for manufacturing an organic EL display panel according to the fifth aspect of the present disclosure is the method for manufacturing an organic EL display panel according to the fourth aspect. Forming a functional layer in the hole and below the common electrode layer. In the step of forming the functional layer, in the contact hole, along the inner wall of the hole and the surface of the auxiliary electrode, the functional layer is formed by vacuum deposition so as to be lost or thinned at a portion located on the inner wall of the concave portion of the auxiliary electrode. Form. The step of forming the common electrode layer has a lower resistance in the thinned portion of the functional layer than in the other functional layers so that it is in direct contact with the auxiliary electrode exposed due to the lack of the functional layer. The common electrode layer is formed by a sputtering method or a CVD (Chemical Vapor Deposition) method so as to be electrically connected to the auxiliary electrode.

  (6) The method for manufacturing an organic EL display panel according to the sixth aspect of the present disclosure is the method for manufacturing the organic EL display panel according to the fourth aspect, wherein the auxiliary electrode is defined as the first auxiliary electrode and the contact hole is defined as the first contact hole. In this case, the step of forming the thin film semiconductor layer includes a step of forming a gate electrode on the substrate, a step of forming a source electrode and a drain electrode above the gate electrode, and a second layer in the same layer as the source electrode and the drain electrode. Forming an auxiliary electrode. Furthermore, the method for manufacturing the organic EL display panel further includes a step of opening a second contact hole reaching the second auxiliary electrode in the lower insulating layer. In the step of forming the first auxiliary electrode, the first auxiliary electrode is formed along the inner wall of the hole and the surface of the second auxiliary electrode in the second contact hole.

  (7) An organic EL display panel according to a seventh aspect of the present disclosure includes a substrate, a gate electrode disposed on the substrate, a source electrode and a drain electrode disposed above the gate electrode, and a source electrode and a drain electrode. A power supply auxiliary electrode disposed on the same layer, a source electrode, a drain electrode, an insulating layer disposed above the auxiliary electrode, and an EL element disposed above the insulating layer. A contact hole reaching the auxiliary electrode is opened in the insulating layer. The EL layer includes a pixel electrode disposed in a portion where no contact hole is formed on the insulating layer, a light emitting layer disposed on the pixel electrode, a common electrode layer disposed on the light emitting layer and in the contact hole, ,including. In the contact hole, the common electrode layer is formed along the hole inner wall and the auxiliary electrode surface.

  (8) The organic EL display panel according to the eighth aspect of the present disclosure includes a substrate, a gate electrode disposed on the substrate, a source electrode and a drain electrode disposed above the gate electrode, and a source electrode and a drain electrode. A first auxiliary electrode for power feeding arranged in the same layer as the first electrode, a source electrode, a drain electrode, a lower insulating layer arranged above the first auxiliary electrode, and a first auxiliary electrode on the lower insulating layer. A power supply second auxiliary electrode disposed in the position; a lower insulating layer; an upper insulating layer disposed above the second auxiliary electrode; and an EL element disposed on the upper insulating layer. A first contact hole reaching the first auxiliary electrode is formed in the lower insulating layer. The second auxiliary electrode is formed in the first contact hole along the inner wall of the first contact hole and the surface of the first auxiliary electrode. A second contact hole reaching the second auxiliary electrode is formed in the upper insulating layer. The EL element is disposed on the pixel electrode disposed in the portion where the second contact hole is not formed on the upper insulating layer, the light emitting layer disposed on the pixel electrode, the light emitting layer, and the second contact hole. A common electrode layer. In the second contact hole, the common electrode layer is formed along the hole inner wall and the second auxiliary electrode surface.

  The organic EL display panel and the organic EL display device according to the present invention can be widely used in various electronic devices having devices such as a television set, a personal computer, a mobile phone, and other display panels.

DESCRIPTION OF SYMBOLS 1 Display apparatus 10 Display panel 100 Substrate 101,102 Gate electrode 104,105 Channel layer 107,110 Source electrode 108,109 Drain electrode 111,114 Auxiliary electrode 116 Pixel electrode 117 Bank 118 Light emitting layer 119 Common electrode layer

Claims (6)

An organic EL display panel,
A substrate,
A thin film semiconductor layer disposed on the substrate;
A lower insulating layer disposed on the thin film semiconductor layer;
An auxiliary electrode for power feeding, which is partially disposed on the lower insulating layer and has a recess recessed into the substrate side;
An upper insulating layer disposed above the lower insulating layer and the auxiliary electrode;
An EL element disposed on the upper insulating layer,
In the upper insulating layer, a contact hole reaching the concave portion of the auxiliary electrode is opened,
The EL element includes a pixel electrode disposed on a portion of the upper insulating layer where the contact hole is not formed, a light emitting layer disposed on the pixel electrode, and on the light emitting layer and in the contact hole. A common electrode layer disposed,
In the contact hole, the common electrode layer is formed along the inner wall of the hole and the surface of the auxiliary electrode. The EL element further includes a functional layer disposed on the light emitting layer, in the contact hole, and below the common electrode layer,
In the contact hole, the functional layer is formed along the inner wall of the hole and the surface of the auxiliary electrode, a portion located on the inner wall of the concave portion of the auxiliary electrode is missing or thinned,
The common electrode layer is in direct contact with the auxiliary electrode exposed due to the lack of the functional layer, and has a lower resistance than the other functional layer portions in the portion where the functional layer is thinned. The organic EL display panel according to claim 1, wherein the organic EL display panel is electrically connected to the auxiliary electrode. When the auxiliary electrode is defined as a first auxiliary electrode and the contact hole is defined as a first contact hole,
The thin film semiconductor layer includes a gate electrode disposed on the substrate, a source electrode and a drain electrode disposed above the gate electrode, and the source disposed on a portion located below the first auxiliary electrode. An electrode and a second auxiliary electrode in the same layer as the drain electrode,
A second contact hole reaching the second auxiliary electrode is opened in the lower insulating layer,
The organic EL display panel according to claim 1, wherein the first auxiliary electrode is formed along the inner wall of the hole and the surface of the second auxiliary electrode in the second contact hole. A method of manufacturing an organic EL display panel,
Forming a thin film semiconductor layer on the substrate;
Forming a lower insulating layer on the thin film semiconductor layer;
Forming a power supply auxiliary electrode having a recess recessed into the substrate side, partially on the lower insulating layer;
Forming an upper insulating layer above the lower insulating layer and the auxiliary electrode;
Opening a contact hole reaching the concave portion of the auxiliary electrode in the upper insulating layer;
Forming an EL element on the upper insulating layer,
The step of forming the EL element includes:
Forming a pixel electrode in a portion where the contact hole on the upper insulating layer is not opened;
Forming a light emitting layer on the pixel electrode;
Forming a common electrode layer on the light emitting layer and in the contact hole,
The step of forming the common electrode layer includes forming the common electrode layer along the inner wall of the hole and the surface of the auxiliary electrode in the contact hole. The step of forming the EL element further includes a step of forming a functional layer above the light emitting layer, in the contact hole, and below the common electrode layer,
The step of forming the functional layer is a vacuum in the contact hole so as to be missing or thinned at a portion located on the inner wall of the concave portion of the auxiliary electrode layer along the inner wall of the hole and the surface of the auxiliary electrode. Forming the functional layer by vapor deposition;
In the step of forming the common electrode layer, in the portion where the functional layer is thinned so as to be in direct contact with the auxiliary electrode exposed due to the lack of the functional layer, the portion of the functional layer other than that The method of manufacturing an organic EL display panel according to claim 4, wherein the common electrode layer is formed by a sputtering method or a CVD (Chemical Vapor Deposition) method so as to be electrically connected to the auxiliary electrode with a low resistance. When the auxiliary electrode is defined as a first auxiliary electrode and the contact hole is defined as a first contact hole,
The step of forming the thin film semiconductor layer includes:
Forming a gate electrode on the substrate;
Forming a source electrode and a drain electrode above the gate electrode;
Forming a second auxiliary electrode in the same layer as the source electrode and the drain electrode,
A step of opening a second contact hole reaching the second auxiliary electrode in the lower insulating layer;
5. The organic EL display panel according to claim 4, wherein in the step of forming the first auxiliary electrode, the first auxiliary electrode is formed in the second contact hole along the inner wall of the hole and the surface of the second auxiliary electrode. Method.

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