JP2019009357A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To enhance performance of a semiconductor device including a power transistor arranged by use of silicon carbide by reducing a leak current in the power transistor.SOLUTION: A semiconductor device comprises: a power transistor formed on an epitaxial layer EPI including silicon carbide as a primary component. In the semiconductor device, the power transistor comprises: an insulation film OXF formed over a side wall of a gate electrode GE; and an interlayer insulation film IL formed so as to cover the gate electrode GE and the insulation film OXF. The insulation film OXF is higher, in density, than the interlayer insulation film IL. The insulation film OXF includes conductive type impurities at an impurity density no more than 1/100 of a maximum impurity density of a conductive type impurity included in the gate electrode GE.SELECTED DRAWING: Figure 13

Description

  The present invention relates to a semiconductor device using, for example, silicon carbide (SiC) and a technology effective when applied to a manufacturing technology thereof.

  Japanese Patent Laid-Open No. 2010-212636 (Patent Document 1) discloses that when a positive bias is applied to the gate electrode by introducing a conductive impurity only in the central portion of the gate electrode made of a polysilicon film, A technique is described in which a depletion layer generated at an end portion is extended to relax an electric field in the vicinity of the end portion of the gate electrode.

JP 2010-212636 A

  The most important issues in realizing a sustainable society are the depletion of energy resources and excessive emissions of greenhouse gases such as carbon dioxide. For this reason, the power converter device which is excellent in energy efficiency and has little carbon dioxide emission has become important. Many of the power conversion devices are composed of semiconductor devices including power transistors that are switching elements. For this reason, the loss reduction of the semiconductor device is directly linked to the energy saving of the power conversion device.

  Here, as a technique for reducing the loss of a semiconductor device, a method of forming a power transistor with 4H-type silicon carbide (4H—SiC, hereinafter referred to as SiC) has attracted attention. However, as a result of studies by the present inventors, it has been found that in current power transistors using silicon carbide, reduction of leakage current becomes apparent as room for improvement. For this reason, in a power transistor using silicon carbide, it is desired to reduce leakage current.

  An object of the present invention is to improve the performance of a semiconductor device including a power transistor by reducing leakage current in the power transistor using silicon carbide.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A semiconductor device in one embodiment includes a power transistor formed on an epitaxial layer mainly composed of silicon carbide. At this time, the power transistor includes a gate insulating film formed on the epitaxial layer, a gate electrode formed on the gate insulating film and containing a conductive impurity, and a first insulation formed on the sidewall of the gate electrode. A film, and a second insulating film formed to cover the gate electrode and the first insulating film. The density of the first insulating film is higher than the density of the second insulating film. The first insulating film contains the conductive impurity at an impurity concentration of 1/100 or less of the maximum impurity concentration of the conductive impurity contained in the gate electrode.

  According to one embodiment, it is possible to improve the performance of a semiconductor device including a power transistor using silicon carbide.

It is a block diagram which shows an example of the three-phase motor system (power converter device) applied to a railway vehicle. It is a circuit diagram which shows the circuit structure of the converter and inverter shown in FIG. It is the figure which took out some 3 phase inverters. It is a figure explaining the mechanism of "false point arc". It is a figure explaining "false point arc". It is a figure explaining the short by "false point arc". It is a figure explaining the preventive measure of "false point arc". It is a figure explaining the preventive measure of "false point arc". It is a figure explaining the room for improvement which this inventor discovered. It is a figure which shows typically the potential barrier by a gate insulating film, when the electric field strength in a gate insulating film is small. It is a figure which shows typically the potential barrier by a gate insulating film, when the electric field strength in a gate insulating film becomes large. It is a figure which shows the device structure which suppresses the increase in the leakage current in the edge part of a gate electrode in the power transistor which uses silicon carbide. It is principal part sectional drawing of SiC power MOSFET in embodiment. It is sectional drawing which shows the manufacturing process of SiC power MOSFET. FIG. 15 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 14. FIG. 16 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 15. FIG. 17 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 16. FIG. 18 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 17. FIG. 19 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 18. FIG. 20 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 19. FIG. 21 is a cross-sectional view showing a manufacturing step of the SiC power MOSFET following FIG. 20. It is a figure explaining the modification 1. FIG. It is a figure explaining the modification 2. FIG.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

  In this specification, the wide band gap semiconductor material refers to a semiconductor material having a band gap larger than that of silicon (1.12 eV), for example, silicon carbide (2.20 to 3.02 eV), Examples include gallium nitride (3.39 eV) and diamond (5.47 eV). The wide band gap semiconductor device refers to a semiconductor device using such a wide band gap semiconductor material as a substrate.

<Configuration example of three-phase motor system>
FIG. 1 is a block diagram illustrating an example of a three-phase motor system (power converter) applied to, for example, a railway vehicle. As shown in FIG. 1, electric power is supplied to the railway vehicle from the overhead line RT via the pantograph PG. At this time, the high-voltage AC voltage supplied from the overhead line RT is, for example, 25 kV or 15 kV. The high-voltage AC voltage supplied to the railway vehicle from the overhead line RT via the pantograph PG is stepped down to an AC voltage of, for example, 3.3 kV by the insulating main transformer MTR. The stepped-down AC voltage is forward converted to a DC voltage (3.3 kV) by the converter CON. Thereafter, the DC voltage converted by the converter CON is converted into a three-phase AC voltage whose phase is shifted by 120 degrees by the inverter INV via the capacitor CL. The three-phase AC voltage converted by the inverter INV is supplied to the three-phase motor MT. As a result, when the three-phase motor MT is driven, the wheel WHL can be rotated, and thereby the railway vehicle can be run.

  As described above, the three-phase motor system of the railway vehicle includes the converter CON and the inverter INV. FIG. 2 is a circuit diagram showing a circuit configuration of converter CON and inverter INV shown in FIG. As shown in FIG. 2, each of the converter CON and the inverter INV includes six power transistors Q and six free wheel diodes FRD. For example, paying attention to the inverter INV, an upper arm (high side switch) and a lower arm (low side switch) are provided corresponding to each of three phases (U phase, V phase, W phase). Each of the lower arms is composed of one power transistor Q and one freewheel diode FRD connected in parallel to each other. At this time, the power transistor Q functions as a switching element, while the free wheel diode FRD functions as a rectifying element that flows a reflux current caused by an inductance included in the three-phase motor MT, for example.

  As described above, in power conversion devices such as the inverter INV and the converter CON, power semiconductor elements such as the power transistor Q and the free wheel diode FRD are used as main components having a switching function and a rectifying function. . For example, an IGBT (Insulated Gate Bipolar Transistor) using silicon (Si) as a substrate material is used as the power transistor Q, and a pn junction diode using silicon as a substrate material is used as the free wheel diode FRD. Yes.

  In this regard, in recent years, the use of a wide band gap semiconductor material having a larger band gap than silicon as a substrate material for power semiconductor elements has been studied, and the development of power semiconductor elements using such wide band gap semiconductor materials has been studied. It is being advanced. This is because a wide band gap semiconductor material has a higher breakdown field strength than silicon due to a larger band gap than silicon. In other words, a power semiconductor element using a wide bandgap semiconductor material has a higher dielectric breakdown field strength than silicon, so the drift layer (epitaxial layer) is thinner than a power semiconductor element using silicon as a substrate material. Even with this, the breakdown voltage can be secured. Furthermore, in a power semiconductor element using a wide band gap semiconductor material, the on-resistance can be reduced by reducing the thickness of the drift layer. That is, in a power semiconductor element using a wide band gap semiconductor material as a substrate material, there can be obtained an advantage that it is possible to achieve both the ensuring of the breakdown voltage and the reduction of the on-resistance in a trade-off relationship.

  For example, examples of the wide band gap semiconductor material include silicon carbide (SiC), gallium nitride (GaN), diamond, and the like. In the following, description will be given with particular attention to SiC.

  SiC, which is a wide band gap semiconductor material, has a dielectric breakdown electric field strength that is about an order of magnitude higher than that of silicon, so that the on-resistance of the power semiconductor element can be reduced. This is because, as described above, if the dielectric breakdown electric field strength is high, the breakdown voltage can be ensured even with a thin drift layer (epitaxial layer), and the on-resistance can be reduced by making the drift layer thin. Furthermore, the thermal conductivity of SiC is about three times the thermal conductivity of silicon and is excellent in semiconductor physical properties even at high temperatures, so that it is suitable for use at high temperatures.

  Therefore, in recent years, it has been studied to replace a power semiconductor element using silicon as a substrate material with a power semiconductor element using SiC as a substrate material. Specifically, taking the inverter INV as an example, among the switching element and the rectifying element that are the components of the inverter INV, as a free wheel diode FRD that is a rectifying element, a pn junction diode that uses silicon as a substrate material is used as an SiC. Development has been advanced to replace pn junction diodes (hereinafter referred to as SiC-pn junction diodes) using as a substrate material.

  Furthermore, as a power transistor Q that is a switching element, replacement of the Si-IGBT with a power MOSFET using SiC as a substrate material (hereinafter referred to as SiC-MOSFET) is also under study. This is because the SiC-MOSFET has a higher breakdown voltage per device than the Si-IGBT, so that the number of components can be reduced. As a result, the size (volume) of the three-phase motor system can be reduced. For example, the floor of the railway vehicle can be lowered by downsizing the underfloor parts including the three-phase motor system. In addition, by downsizing the underfloor parts, it is possible to secure a space where a storage battery SB (see FIG. 1) can be newly installed in a part of the railway vehicle. Therefore, when the railway vehicle is not traveling, the wheel WHL is used. Thus, the electric power can be stored in the storage battery SB without returning the electric power to the overhead line RT. As a result, the regeneration efficiency of the railway vehicle can be improved. In other words, the life cycle cost of the railway system can be reduced.

  In the present embodiment, in particular, on the premise that the power transistor is composed of SiC-MOSFET, by improving the performance of the SiC-MOSFET, the performance of the power converter represented by the inverter INV is improved. The purpose is to plan. Below, the technical idea in this Embodiment which devised the SiC-MOSFET will be described. First, the room for improvement, which is a premise for reaching the technical idea in the present embodiment, will be described, and then the technical idea in the present embodiment will be described.

<Examination of improvement>
FIG. 3 is a diagram showing a part of the three-phase inverter. In FIG. 3, a power transistor Q1 constituting a high-side switch (upper arm) and a power transistor Q2 constituting a low-side switch (lower arm) are connected in series between a power supply terminal VT and a ground terminal GT. One leg is shown. FIG. 3 also shows a second leg in which a power transistor Q3 constituting a high-side switch (upper arm) and a power transistor Q4 constituting a low-side switch (lower arm) are connected in series.

  In FIG. 3, for example, the power transistor Q1 and the power transistor Q4 are turned on, while the power transistor Q2 and the power transistor Q3 are turned off. As a result, as indicated by a thick arrow, a current can flow through the path of the power supply terminal VT → the turned on power transistor Q1 → the load motor MT → the turned on power transistor Q4 → the ground terminal GT. A certain motor MT can be driven.

  At this time, as shown in FIG. 3, in order to turn on the power transistor Q1, “+15 V” is applied to the gate electrode of the power transistor Q1. Similarly, in order to turn on the power transistor Q4, “+15 V” is applied to the gate electrode of the power transistor Q4. On the other hand, as shown in FIG. 3, in order to turn off the power transistor Q2, "-8V" is applied to the gate electrode of the power transistor Q2. Similarly, in order to turn off the power transistor Q3, “−8 V” is applied to the gate electrode of the power transistor Q3.

  Here, as shown in FIG. 4, since “1500 V” is supplied to the power supply terminal VT and the power transistor Q1 is turned on, the potential of the node V1 becomes “1500 V”. On the other hand, in the power transistor Q2, since the parasitic capacitance CP exists between the drain and the gate electrode, when the potential of the node V1 becomes “1500 V”, the gate voltage V2 of the gate electrode becomes “1500 V” due to the parasitic capacitance CP. It rises from "-8V". Specifically, as shown in FIG. 5, when the potential of the node V1 becomes “1500 V”, the gate voltage V2 of the power transistor Q2 increases from “−8 V” due to capacitive coupling by the parasitic capacitance CP. At this time, as shown in FIG. 5, when the gate voltage V2 of the power transistor Q2 exceeds the threshold voltage of the power transistor Q2, the power transistor Q2 that is turned off is erroneously turned on. As described above, the phenomenon in which the power transistor Q2 that should be turned off is turned on is called “false point arc”. That is, in the configuration in which the gate voltage V2 of the power transistor Q2 is set to “−8 V” in order to turn off the power transistor Q2, the above-mentioned “false spot” tends to occur. Then, when “false point” occurs in the power transistor Q2 to be turned off, the power transistor Q1 and the power transistor Q2 are turned on simultaneously as shown in FIG. As a result, the power supply terminal VT and the ground terminal GT are short-circuited, whereby a large current indicated by a thick arrow flows between the power supply terminal VT and the ground terminal GT. Then, when a large current flows between the power supply terminal VT and the ground terminal GT, the power conversion device including the three-phase inverter generates heat and is destroyed. From the above, from the viewpoint of improving the reliability of the power conversion device constituted by the three-phase inverter, a measure for suppressing “false point arc” is required.

  In this regard, for example, as shown in FIG. 7, a measure is taken to change the gate voltage V2 of the power transistor Q2 to be turned off from “−8V” to “−15V”. That is, measures are taken to increase the absolute value of the negative voltage applied to the gate electrode of the power transistor Q to be turned off. In this case, as shown in FIG. 8, even when the gate voltage V2 of the power transistor Q2 to be turned off increases due to capacitive coupling due to parasitic capacitance, the margin until the threshold voltage is reached increases. This makes it difficult for the power transistor Q2 to have a “false point” and suppress a short circuit between the power supply terminal VT and the ground terminal GT. Therefore, a measure for increasing the absolute value of the negative voltage applied to the gate electrode of the power transistor Q2 to be turned off is useful from the viewpoint of suppressing the “false point” and improving the reliability of the power converter. However, the present inventor has found that there is room for new improvement in the measure for increasing the absolute value of the negative voltage applied to the gate electrode of the power transistor Q2 to be turned off in order to suppress the “false point”. Therefore, this point will be described below.

  FIG. 9 is a diagram for explaining the room for improvement found by the present inventors. FIG. 9 shows a schematic cross-sectional structure of a so-called vertical power transistor. In FIG. 9, the power transistor is formed in an epitaxial layer EPI made of an n-type semiconductor layer.

  Specifically, as shown in FIG. 9, a well region WL made of a p-type semiconductor layer is formed in the epitaxial layer EPI, and a source region SR and a body contact region BC are formed on the surface of the well region WL. Is formed. The source region is composed of an n-type semiconductor region, while the body contact region BC is composed of a p-type semiconductor region having a higher impurity concentration than the well region WL.

  As shown in FIG. 9, a gate insulating film GOX is formed over the surface of the epitaxial layer EPI, the surface of the well region WL, and the surface of the source region SR. Further, the gate electrode GE is formed on the gate insulating film GOX, and the interlayer insulating film IL is formed over the gate insulating film GOX and over the gate insulating film GOX.

  Here, as shown in FIG. 9, when a negative voltage is applied to the gate electrode GE, electrons are accumulated in the gate electrode GE. Thereby, positive charges (holes) are induced on the surface of the epitaxial layer EPI (inversion layer), the surface of the channel layer (accumulation layer), and the surface of the source region SR (inversion layer). As a result, an electric field indicated by an arrow in FIG. 9 is generated. In particular, as shown in FIG. 9, at the end of the gate electrode GE, electric field concentration occurs and the electric field strength increases. When a negative voltage is applied to the gate electrode GE in this way, the electric field strength increases at the end of the gate electrode GE, resulting in an increase in leakage current generated between the gate electrode GE and the semiconductor substrate.

  In particular, when a negative voltage is applied to the gate electrode GE, an increase in leakage current at the end of the gate electrode GE becomes obvious. For example, when a positive voltage is applied to the gate electrode GE, considering that the gate electrode GE is composed of a polysilicon film into which an n-type impurity is introduced, the interface between the gate electrode GE and the gate insulating film GOX is used. A depletion layer formed on the gate electrode GE side extends. In consideration of the function of the depletion layer itself as an insulating layer, when a positive voltage is applied to the gate electrode GE, it means that the thickness of the gate insulating film GOX is substantially increased. As a result, when a positive voltage is applied to the gate electrode GE, the electric field concentration at the end of the gate electrode GE is alleviated, and an increase in leakage current due to the electric field concentration becomes difficult to manifest. On the other hand, when a negative voltage is applied to the gate electrode GE, a depletion layer as in the case where a positive voltage is applied to the gate electrode GE does not occur, and therefore the effect of reducing the electric field concentration by the depletion layer cannot be expected. Therefore, the leakage current between the gate electrode GE and the semiconductor substrate becomes apparent particularly when a negative voltage is applied to the gate electrode GE. Further, if the absolute value of the negative voltage applied to the gate electrode GE is increased in order to suppress the “false spot”, electric field concentration at the end of the gate electrode GE is more likely to occur, An increase in leakage current with the semiconductor substrate becomes apparent. In other words, as a measure for suppressing the “false point” and improving the reliability of the power converter, if a measure for increasing the absolute value of the negative voltage applied to the gate electrode of the power transistor to be turned off is adopted, the gate electrode GE The side effect of increasing the electric field concentration at the edge of the surface becomes obvious.

  Therefore, in the following, a mechanism in which a leakage current flowing between the gate electrode GE and the semiconductor substrate increases when the electric field strength increases due to electric field concentration will be described.

<< Mechanism of leakage current increase due to electric field concentration >>
FIG. 10 is a diagram schematically showing a potential barrier due to the gate insulating film when the electric field strength in the gate insulating film is small. In FIG. 10, when a negative voltage is applied to the gate electrode, electrons are accumulated in the gate electrode. When electrons existing in the gate electrode escape to the substrate side, a leakage current is generated. In this case, electrons existing in the gate electrode need to tunnel through the potential barrier having the width “L1”. However, the slope of the potential barrier due to the gate insulating film is gentle when the electric field strength is small. Therefore, the potential barrier width “L1” is large, and the probability that electrons existing in the gate electrode tunnel through the potential barrier formed by the gate insulating film is low. This means that the electron current (FN tunnel current) flowing from the gate electrode to the substrate decreases, in other words, the leak current flowing from the substrate to the gate electrode decreases.

  On the other hand, FIG. 11 is a diagram schematically showing a potential barrier due to the gate insulating film when the electric field strength in the gate insulating film increases. In FIG. 11, when electrons existing in the gate electrode escape to the substrate side, a leakage current is generated. In this case, electrons existing in the gate electrode need to tunnel through a potential barrier having a width of “L2”. is there. Here, the gradient of the potential barrier due to the gate insulating film becomes steep when the electric field strength increases. Therefore, the potential barrier width “L2” is smaller than the potential barrier width “L1” in FIG. As a result, the probability that electrons existing in the gate electrode tunnel through the potential barrier formed by the gate insulating film is increased. This means that the electron current (FN tunnel current) flowing from the gate electrode to the substrate increases, in other words, the leak current flowing from the substrate to the gate electrode increases.

  With the above mechanism, when the electric field strength existing inside the gate insulating film increases, the leak current flowing from the substrate to the gate electrode increases. In other words, as a measure to suppress “false spot”, increasing the absolute value of the negative voltage applied to the gate electrode of the power transistor to be turned off increases the electric field strength at the end of the gate electrode, resulting in an increase in leakage current. It will be done.

<< Situations peculiar to power transistors using silicon carbide >>
As described above, when the electric field strength at the end of the gate electrode increases, the leakage current increases. In this regard, in a power transistor using silicon carbide, an increase in leakage current is more likely to be manifested as a result of an increase in electric field strength at the end of the gate electrode than in a power transistor using silicon. This point will be described below.

  First, since an epitaxial layer made of silicon carbide is difficult to be oxidized, there is a situation in which it is difficult to use light oxidation after forming a gate electrode. For example, in an epitaxial layer made of silicon, a gate insulating film is formed on the epitaxial layer, and then light oxidation is performed after forming a gate electrode on the gate insulating film. This light oxidation forms a silicon oxide film at the edge of the gate electrode, resulting in a substantial increase in the thickness of the gate insulating film at the edge of the gate electrode, thereby suppressing electric field concentration at the edge of the gate electrode. it can. This light oxidation increases the substantial thickness of the gate insulating film at the end of the gate electrode because oxygen molecules and oxygen-containing molecules pass through the gate insulating film, and the epitaxial layer made of silicon is oxidized. Because. However, when an epitaxial layer made of silicon carbide is used, even if oxygen molecules or molecules containing oxygen pass through the gate insulating film by light oxidation, the epitaxial layer made of silicon carbide is not oxidized. Therefore, the substantial thickness of the gate insulating film in the portion does not increase. That is, in the power transistor using silicon, by performing the light oxidation, the substantial thickness of the gate insulating film at the end portion of the gate electrode can be increased, so that electric field concentration at the end portion of the gate electrode can be suppressed. On the other hand, in a power transistor using silicon carbide, even if light oxidation is performed, silicon carbide is not easily oxidized. As a result, it is difficult to suppress electric field concentration at the end of the gate electrode. Therefore, in a power transistor using silicon carbide, there is a situation where the countermeasure of using light oxidation is not effective in order to suppress electric field concentration at the end of the gate electrode.

  Next, in a power transistor using silicon carbide, leakage current at the intersection of this “step bunching” and the end of the gate electrode due to “step bunching” existing on the surface of the epitaxial layer made of silicon carbide. There is a circumstance that increases. Here, “step bunching” refers to a step generated when silicon carbide is epitaxially grown. Specifically, a step flow growth method is used as an epitaxial growth technique for silicon carbide. With this step flow growth method, in order to realize good epitaxial growth, for example, with respect to a surface into which an offset angle (off angle) of several degrees (for example, 4 degrees or 8 degrees) is introduced from the {0001} plane, This is a method of performing epitaxial growth. The epitaxial layer formed using the step flow growth method has an off-angle in principle, and the {0001} plane has a left-right asymmetric crystal structure inclined by the off-angle with respect to the horizontal plane. doing. As a result, a step due to the off-angle exists on the surface of the epitaxial layer, and this step is called “step bunching”. As a result of the study by the present inventor, it was found that in the power transistor using silicon carbide, the leakage current increases at the intersection of “step bunching” and the end of the gate electrode. Therefore, from the viewpoint of improving the reliability of the power transistor, it is extremely important for the power transistor using silicon carbide to suppress the leakage current at the end of the gate electrode as compared with the power transistor using silicon. There are circumstances.

  Furthermore, in a power transistor using silicon carbide, the thickness of the gate insulating film tends to be thinner than that of a power transistor using silicon, and the electric field strength applied to the inside of the gate insulating film is reduced by thinning the gate insulating film. growing. For example, on the surface of the epitaxial layer made of silicon carbide, there is a fine step called “step bunching” and silicon carbide is used due to dangling bonds and carbon atoms remaining in the gate insulating film. In the power transistor, the electron mobility of the channel is lower than that of a power transistor using silicon. Therefore, a power transistor using silicon carbide has a higher channel resistance than a power transistor using silicon. Therefore, in a power transistor using silicon carbide, the channel resistance can be reduced by increasing the gate capacitance and increasing the electron density generated in the channel by reducing the thickness of the gate insulating film. Has been done. For this reason, the power transistor using silicon carbide tends to have a thinner gate insulating film than the power transistor using silicon. As a result, the electric field strength inside the gate insulating film increases, and in particular, an increase in leakage current at the end of the gate electrode becomes apparent.

  From the above, due to a plurality of circumstances described above, in a power transistor using silicon carbide, an increase in leakage current at the end of the gate electrode is more likely to be manifested as a problem than in a power transistor using silicon. .

<< New knowledge discovered by the inventor >>
Therefore, in power transistors using silicon carbide, measures are taken to suppress an increase in leakage current at the end of the gate electrode. Specifically, FIG. 12 is a diagram showing a device structure that suppresses an increase in leakage current at the end of the gate electrode in a power transistor using silicon carbide. In FIG. 12, an insulating film OXF is provided so as to cover the gate electrode GE. This insulating film OXF is made of, for example, a silicon oxide film formed by a thermal oxidation method, and is formed by CVD (Chemical Vapor Deposition). ) Film having a higher density than the interlayer insulating film IL made of a silicon oxide film formed by the method. By forming such an insulating film OXF on the side wall of the gate electrode GE, it is possible to suppress the occurrence of leakage current at the end of the gate electrode GE. That is, as a result of forming the dense insulating film OXF having high insulation resistance on the side wall of the gate electrode GE, it is considered that the generation of leakage current at the end of the gate electrode GE can be suppressed.

  However, the present inventor has found that it is not sufficient to form a dense insulating film OXF having high insulation resistance on the side wall of the gate electrode GE in order to reduce the leakage current at the end of the gate electrode GE. . That is, the present inventor newly found that the leakage current when a negative voltage is applied to the gate electrode GE strongly depends on the film quality of the insulating film OXF formed on the side wall of the gate electrode GE. Specifically, if the insulating film OXF formed on the side wall of the gate electrode GE contains phosphorus as an n-type impurity in a high concentration, the insulating film OXF is formed on the side wall of the gate electrode GE. The present inventor has found a new finding that the leakage current at the end of the gate electrode GE cannot be sufficiently reduced.

  Here, the reason why the n-type impurity is introduced into the insulating film OXF is as follows. That is, although the gate electrode GE is formed of a polysilicon film, a high concentration n-type impurity is introduced into the polysilicon film in order to reduce the resistance of the gate electrode GE. Therefore, for example, the n-type impurity diffuses from the inside of the polysilicon film into the insulating film OXF formed on the side wall of the gate electrode GE by the heat treatment for activating the n-type impurity introduced into the polysilicon film. To do. As a result, n-type impurities are also introduced into the insulating film OXF.

  In this regard, if phosphorus, which is an n-type impurity, is contained in the insulating film OXF in a high concentration, even if the insulating film OXF is formed on the sidewall of the gate electrode GE, the leakage current at the end of the gate electrode GE A mechanism that cannot sufficiently reduce the above will be described. Specifically, even if the insulating film OXF is formed on the side wall of the gate electrode GE by the following two mechanisms, the leakage current at the end portion of the gate electrode GE increases.

  First, the first mechanism will be described. For example, when an n-type impurity is introduced into silicon, a donor level due to the n-type impurity is formed immediately below the conduction band of silicon. On the other hand, even when an n-type impurity is introduced into the insulating film OXF, a trap level (midgap level) caused by the n-type impurity is formed at the same energy level as the above-described donor level. Because the band gap of the insulating film OXF is much larger than the band gap of silicon, the energy level formed in the vicinity of the conduction band in silicon is near the center of the band gap in the insulating film OXF. This is because the energy level becomes. As a result, when an n-type impurity is introduced at a high concentration inside the insulating film OXF, a large amount of trap levels are formed near the middle of the band gap of the insulating film OXF. Also in the film OXF, electrons can be excited from the valence band to the conduction band. As a result, the electrons excited in the conduction band recombine with the holes in the valence band, thereby increasing the leakage current in the insulating film OXF.

  Next, the second mechanism will be described. For example, the n-type impurity introduced into the insulating film OXF may be ionized. In this case, since the n-type impurity has a positive charge and electrons are accumulated by applying a negative voltage to the gate electrode GE, the interface between the gate electrode GE and the insulating film OXF is For example, a steep potential barrier is generated as in the gate insulating film shown in FIG. In such a steep potential barrier, for example, as shown in FIG. 11, since the potential barrier width “L2” becomes small, an FN tunnel current easily flows, and this FN tunnel current becomes a leak current. . In particular, a high concentration of n-type impurities contained in the insulating film OXF means that the number of ionized n-type impurities increases accordingly. Therefore, when an n-type impurity is introduced into the insulating film OXF at a high concentration, a steeper potential barrier is generated at the interface between the gate electrode GE and the insulating film OXF, and thereby the FN tunnel current ( (Leakage current) increases.

  From the above, the n-type impurity is formed inside the insulating film OXF formed on the side wall of the gate electrode GE by the first mechanism caused by the energy level of the n-type impurity and the second mechanism caused by ionization of the n-type impurity. If phosphorus, which is an impurity, is contained in a high concentration, it becomes impossible to reduce the leakage current at the end of the gate electrode GE.

  Therefore, in the present embodiment, a device for reducing the leakage current at the end portion of the gate electrode GE is taken based on the new knowledge described above. In the following, the technical idea in the present embodiment in which this device is applied will be described.

<Configuration of SiC power MOSFET>
The structure of an n-channel SiC power MOSFET constituting the wide band gap semiconductor device according to the present embodiment will be described with reference to FIG.

FIG. 13 is a cross-sectional view of a main part of the SiC power MOSFET in the present embodiment. As shown in FIG. 13, on the surface (first main surface) of a substrate 1S made of n ⁺ type SiC containing silicon carbide (SiC) as a main component, from the substrate 1S containing n ⁺ type SiC as a main component. An n ⁻ type epitaxial layer EPI (drift layer) mainly composed of silicon carbide (SiC) having a low impurity concentration is also formed. The thickness of the n ⁻ type epitaxial layer EPI is, for example, about 5 μm to 20 μm, and has an offset angle (off angle) of 4 degrees or 8 degrees, for example.

  Here, the “main component” as used in the present specification refers to a material component that is contained most among the constituent materials constituting the member. For example, “epitaxial layer containing silicon carbide as a main component”. The term “epitaxial layer” means that the epitaxial layer contains the most silicon carbide. The intent of using the term “main component” in this specification is to express that, for example, the epitaxial layer is basically composed of silicon carbide, but does not exclude the case where impurities are included. It is used for.

the n ^- -type epitaxial layer EPI, n ^- -type p-type well region (body region) WL having a predetermined depth from the surface of the epitaxial layer EPI is formed. Further, in the p-type well region WL, the n ⁺ -type source region has a predetermined depth from the surface of the n ⁻ -type epitaxial layer EPI and is separated from the end of the p-type well region WL. SR is formed. This source region SR has a structure different from the LDD structure. The depth of the p-type well region WL from the surface of the epitaxial layer EPI is, for example, about 0.5 μm to 2.0 μm. In addition, the depth of the n ⁺ -type source region SR from the surface of the epitaxial layer EPI is, for example, about 0.1 μm to 0.4 μm.

Further, the p ⁺⁺ type body contact region BC has a predetermined depth from the surface of the n ⁻ type epitaxial layer EPI and fixes the potential of the p type well region WL in the p type well region WL. Is formed. The depth of the p ⁺⁺ type body contact region BC from the surface of the epitaxial layer EPI is, for example, about 0.05 μm to 0.2 μm.

  Further, a back surface silicide layer BSL is formed on the back surface (second main surface) of the substrate 1S, and a back electrode BE is formed so as to be in contact with the back surface silicide layer BSL.

Note that “ ⁻ ” and “ ⁺ ” are signs representing the relative impurity concentration of the n-type or p-type conductivity, for example, “n ⁻ ”, “n”, “n ⁺ ”, “n ⁺⁺ ”. ”Indicates that the impurity concentration of the n-type impurity increases.

The preferable range of the impurity concentration of the substrate 1S made of n ⁺ type SiC is, for example, 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the preferable range of the impurity concentration of the n ⁻ type epitaxial layer EPI is For example, it is 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The preferable range of the impurity concentration of the p ⁺⁺ type body contact region BC is, for example, 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ , and the preferable range of the impurity concentration of the p-type well region WL is For example, it is 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . A preferable range of the impurity concentration of the n ⁺ -type source region SR is, for example, 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ . Further, the n-type impurity (phosphorus) contained in the gate electrode GE has an impurity concentration of 10 ²⁰ / cm ³ or more.

A gate insulating film GOX is formed on the surface of the substrate 1S in a region continuing from the source region SR to the epitaxial layer EPI through the well region WL, and a gate made of a polysilicon film is in contact with the gate insulating film GOX. An electrode GE is formed. The conductivity type of the polysilicon film constituting the gate electrode GE is, for example, n ⁺ type. The gate electrode GE is covered with an insulating film OXF made of, for example, a silicon oxide film formed by a thermal oxidation method. Then, an interlayer insulating film IL made of, for example, a silicon oxide film formed by a CVD method is formed so as to be in contact with the insulating film OXF. At this time, the density of the insulating film OXF is higher than the density of the interlayer insulating film IL. The insulating film OXF is thinner than the interlayer insulating film IL. The insulating film OXF is formed on the side wall of the gate electrode GE, but this insulating film OXF is not a side wall spacer for making the source region SR a so-called LDD structure, and reduces the leakage current at the end of the gate electrode GE. It is a film | membrane which has a function to do. In particular, in the SiC power MOSFET in the present embodiment, the source region SR does not have an LDD structure, and therefore no sidewall spacer is provided. The insulating film OXF in the present embodiment is a dense film having higher insulation resistance than a general sidewall spacer. Specifically, the insulating film OXF in this embodiment is a silicon oxide film formed by a thermal oxidation method, whereas a general sidewall spacer is a silicon oxide film formed by a CVD method, for example. There are some differences. The insulating film OXF is thicker than the gate insulating film GOX. In the SiC power MOSFET in the present embodiment, the thickness of the gate insulating film GOX is 80 nm or less.

Further, at the bottom surface of the opening OP formed in the interlayer insulating film IL, a part of the n ⁺ -type source region SR and the p ^{+ +} -type body contact region BC are exposed, and the metal silicide layer SL is formed on these surfaces. Is formed. A part of the n ⁺ type source region SR and the p ^{+ +} type body contact region BC are electrically connected to the source electrode SE through the metal silicide layer SL. The substrate 1S is electrically connected to the back electrode (drain electrode) BE via the back silicide layer BSL.

  Here, the gate potential is applied to the gate electrode GE from the outside, the source potential is applied to the source electrode SE from the outside, and the drain potential is applied to the drain electrode DE from the outside.

  The SiC power MOSFET configured as described above is used, for example, as power transistors Q1 to Q4 shown in FIG. As shown in FIG. 7, when the SiC power MOSFET is turned on, a first voltage (+15 V) equal to or higher than the threshold voltage is applied to the gate electrode of the SiC power MOSFET. On the other hand, when turning off the SiC power MOSFET, a second voltage (−15V) having the same absolute value as that of the first voltage and opposite in polarity to the first voltage is applied to the gate electrode of the SiC power MOSFET. Is done.

  The semiconductor device in the present embodiment includes a SiC power MOSFET formed on an epitaxial layer EPI mainly composed of silicon carbide (SiC). At this time, the SiC power transistor includes a gate insulating film GOX formed on the epitaxial layer EPI, a gate electrode GE formed on the gate insulating film GOX and containing an n-type impurity (conductive impurity), a gate An insulating film OXF formed on the side wall of the electrode GE and an interlayer insulating film IL formed so as to cover the gate electrode GE and the insulating film OXF are provided. Here, the density of the insulating film OXF is higher than the density of the interlayer insulating film IL. The insulating film OXF contains an n-type impurity (conductivity type impurity) at an impurity concentration of 1/100 or less of the maximum impurity concentration of the n-type impurity (conductivity type impurity) contained in the gate electrode GE.

<Structural Features in Embodiment>
Next, structural features in the present embodiment will be described. The structural feature of the present embodiment is that, for example, in FIG. 13, the impurity concentration of the n-type impurity (phosphorus) introduced into the insulating film OXF formed on the side wall of the gate electrode GE is different from that of the gate electrode GE. Is 1/100 or less of the maximum impurity concentration of the n-type impurity (phosphorus) contained in. Specifically, the maximum impurity concentration of the n-type impurity contained in the gate electrode GE is on the order of 10 ²⁰ / cm ³ or more, whereas the n-type impurity (phosphorus) contained in the insulating film OXF is The impurity concentration is on the order of 10 ¹⁸ / cm ³ or less. Thereby, according to the SiC power MOSFET in the present embodiment, it is possible to reduce the leakage current at the end of the gate electrode GE which is a critical point. As a result, the reliability of the power conversion device using the SiC power MOSFET in the present embodiment can be improved.

  In particular, the insulating film OXF in the present embodiment is composed of a silicon oxide film formed by a thermal oxidation method. For example, the insulating film OXF is more densely insulated than the interlayer insulating film IL which is a silicon oxide film formed by a CVD method. It is a highly resistant film. For this reason, according to the SiC power MOSFET in the present embodiment, it is considered that the leakage current at the end of the gate electrode GE can be reduced. However, there is an n-type impurity in the insulating film OXF formed on the side wall of the gate electrode GE by the first mechanism caused by the energy level of the n-type impurity and the second mechanism caused by ionization of the n-type impurity. When phosphorus is contained in a high concentration, it becomes impossible to reduce the leakage current at the end of the gate electrode GE. In this regard, according to the structural feature in the present embodiment, the impurity concentration of the n-type impurity (phosphorus) introduced into the insulating film OXF formed on the side wall of the gate electrode GE is equal to the gate electrode GE. 1/100 or less of the maximum impurity concentration of the n-type impurity (phosphorus) contained in. Thereby, according to the SiC power MOSFET in the present embodiment, since the impurity concentration of the n-type impurity (phosphorus) introduced into the insulating film OXF formed on the side wall of the gate electrode GE is low, it is dense and has insulation resistance. The advantages of a silicon oxide film formed by a thermal oxidation method, which is an excellent film, can be maximized. Therefore, according to the SiC power MOSFET in the present embodiment, the leakage current at the end of gate electrode GE can be reduced.

On the other hand, in the SiC power MOSFET in the present embodiment, since the maximum impurity concentration of the n-type impurity contained in the gate electrode GE is on the order of 10 ²⁰ / cm ³ or more, the resistance of the gate electrode GE is reduced. Can be planned. Therefore, according to the SiC power MOSFET in the present embodiment, the impurity concentration of the n-type impurity (phosphorus) introduced into the insulating film OXF formed on the side wall of the gate electrode GE is contained in the gate electrode GE. Due to the feature that it is 1/100 or less of the maximum impurity concentration of the n-type impurity (phosphorus), it is possible to reduce the leakage current at the end of the gate electrode GE while ensuring the low resistance of the gate electrode GE. it can. That is, it can be seen that the feature point in the present embodiment is an excellent technical idea in that both reduction in resistance in the gate electrode GE and reduction in leakage current at the end of the gate electrode GE can be achieved. Thus, according to the structural features in the present embodiment, it has great utility in that it is possible to achieve both improved reliability and improved performance of the power conversion device.

<Manufacturing method of SiC power MOSFET>
The SiC power MOSFET in the present embodiment is configured as described above, and the manufacturing method thereof will be described below with reference to the drawings.

First, as illustrated in FIG. 14, a substrate 1 ^</ b ^> S mainly including an n ⁺ -type 4H—SiC substrate is prepared. An n-type impurity is introduced into the substrate 1S. The n-type impurity is, for example, nitrogen (N), and the impurity concentration of the n-type impurity is, for example, 1 × 10 ¹⁸ cm ⁻³ to 1 × 10. The range is ²¹ cm ⁻³ . The substrate 1S made of an n ⁺ -type SiC substrate has both a Si surface and a C surface, but the surface of the substrate 1S may be either the Si surface or the C surface.

Next, an n ⁻ type epitaxial layer EPI mainly composed of silicon carbide is formed on the surface (first main surface) of the substrate 1S by an epitaxial growth method. At this time, the n ⁻ -type epitaxial layer EPI may be formed by ion implantation instead of the epitaxial growth method. An n-type impurity lower than the impurity concentration of the substrate 1S is introduced into the n ⁻ type epitaxial layer EPI. The impurity concentration of the n ⁻ -type epitaxial layer EPI depends on the element rating of the SiC power MOSFET, but is, for example, in the range of 1 × 10 ¹⁴ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . The thickness of the n ⁻ type epitaxial layer EPI is, for example, 5 μm to 20 μm.

Subsequently, a first resist pattern is formed on the surface of the n ⁻ type epitaxial layer EPI. Then, the first resist pattern as a mask, n ^- -type epitaxial layer p-type impurities in EPI, for example, by aluminum atoms to (Al) ion implantation, n ^- p-type well region -type epitaxial layer EPI WL is formed. The depth of the p-type well region WL from the surface of the epitaxial layer EPI is, for example, about 0.5 μm to 2.0 μm. The impurity concentration of the p-type well region WL is, for example, in the range of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ . Next, after removing the first resist pattern, a second resist pattern is formed on the surface of the n ⁻ type epitaxial layer EPI. Subsequently, by using the second resist pattern as a mask, an n-type impurity, for example, a nitrogen atom (N) or a phosphorus atom (P) is ion-implanted into the p-type well region WL, whereby the p-type well region WL is implanted. An n ⁺ type source region SR is formed. The depth of the n ⁺ -type source region SR from the surface of the epitaxial layer EPI is, for example, about 0.1 μm to 0.4 μm.

Nitrogen atoms (N) or phosphorus atoms (P) are exemplified as n-type impurities ion-implanted into the p-type well region WL. However, the depth from the surface of the epitaxial layer EPI of the n ⁺ -type source region SR is set as follows. In order to make it shallow, any n-type impurity that can easily form a shallow junction may be used. For example, nitrogen molecule (N ₂ ), nitrogen fluoride (NF), nitrogen difluoride (NF ₂ ), nitrogen trifluoride (NF ₃ ), phosphorus molecule (P ₂ ), phosphine (PH ₃ ), phosphorus fluoride (PF), phosphorus difluoride (PF ₂ ), phosphorus trifluoride (PF ₃ ), or a mixed gas of the above gas species may be used. Note that the impurity concentration of the n ⁺ -type source region SR is, for example, in the range of 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

Subsequently, after removing the second resist pattern, a third resist pattern is formed on the surface of the n ⁻ -type epitaxial layer EPI. In the third resist pattern, an opening region is provided only in a region where the p ⁺⁺ type body contact region BC is formed in the subsequent process. Then, using the third resist pattern as a mask, a p-type impurity, for example, an aluminum atom (Al) is ion-implanted into the p-type well region WL, whereby a p ^++- type body contact region is formed in the p-type well region WL. BC is formed.

The depth of the p ⁺⁺ type body contact region BC from the surface of the epitaxial layer EPI is, for example, about 0.05 to 0.2 μm. The impurity concentration of the p ⁺⁺ type body contact region BC is, for example, in the range of 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ .

Next, after removing the third resist pattern, a gate insulating film GOX is formed on the surface of the n ⁻ type epitaxial layer EPI. The gate insulating film GOX is, for example, a silicon oxide film (SiO ₂ film) formed by thermally oxidizing the substrate 1S, a silicon oxide film formed by a thermal CVD (Chemical Vapor Deposition) method, or silicon nitride It consists of a film (SiN film) and a silicon oxynitride film (SiON film). The thickness of the gate insulating film GOX is, for example, about 0.01 μm to 0.10 μm.

  Thereafter, as shown in FIG. 15, a non-doped polysilicon film PF into which no conductivity type impurity is introduced is formed on the gate insulating film GOX. The polysilicon film PF is formed by CVD in a polycrystalline state or by CVD in an amorphous state, and this film is annealed at a temperature of about 700 to 900 ° C. and crystallized. To do.

  Next, as shown in FIG. 16, a fourth resist pattern is formed on the polysilicon film PF. Then, by using the fourth resist pattern as a mask, the polysilicon film PF is processed by a dry etching method, thereby forming the gate electrode GE made of the polysilicon film PF.

  Subsequently, as shown in FIG. 17, an insulating film OXF made of a silicon oxide film is formed on the surface of the gate electrode GE made of a polysilicon film, for example, by a thermal oxidation method in which the substrate 1S is heated at about 1000 ° C. Then, as shown in FIG. 18, a partial region of the insulating film OXF that covers the end portion of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE and is formed on the upper portion of the gate electrode GE. A resist pattern PR having an opening OP that opens is formed. Thereafter, an n-type impurity (phosphorus) is introduced into the gate electrode GE by ion implantation using the resist pattern PR as a mask. Thereafter, the substrate 1S is heated to about 800 ° C. to activate the n-type impurity (phosphorus) introduced into the gate electrode GE.

Thereafter, as shown in FIG. 19, after removing the resist pattern PR, the surface of the n ⁻ type epitaxial layer EPI is oxidized by, for example, plasma CVD so as to cover the gate insulating film GOX and the insulating film OXF. An interlayer insulating film IL made of a silicon film is formed.

Subsequently, as shown in FIG. 20, a fifth resist pattern is formed on the interlayer insulating film IL. Then, using the fifth resist pattern as a mask, the interlayer insulating film IL and the gate insulating film GOX are processed by the dry etching method, and a contact reaching a part of the n ⁺ type source region SR and the p ^{+ +} type body contact region BC. Hole CNT is formed.

Next, as shown in FIG. 21, after removing the fifth resist pattern, a part of the n ⁺ -type source region SR and the p ⁺⁺ -type body contact region BC exposed on the bottom surface of the contact hole CNT, respectively. A metal silicide layer SL is formed on the surface.

In the step of forming the metal silicide layer SL, first, although not shown, for example, the interlayer insulating film IL and the inside of the contact hole CNT (side surface and bottom surface) are covered on the surface of the n ⁻ type epitaxial layer EPI, for example A first metal film made of, for example, a nickel film (Ni film) is deposited by sputtering. The thickness of the first metal film is, for example, about 0.05 μm. Thereafter, by performing a heat treatment at 500 to 900 ° C., the first metal film and the n ⁻ type epitaxial layer EPI are reacted at the bottom surface of the contact hole CNT, for example, a metal made of a nickel silicide layer (NiSi layer). Silicide layer SL is formed on a part of n ⁺ type source region SR exposed on the bottom surface of contact hole CNT and on the surface of p ⁺⁺ type body contact region BC. Then, the unreacted first metal film is removed by a wet etching method. In the wet etching method, for example, sulfuric acid / hydrogen peroxide is used.

  Subsequently, although not shown, a second metal film is deposited on the back surface of the substrate 1S by, for example, a sputtering method. The thickness of the second metal film is, for example, about 0.1 μm.

  And as shown in FIG. 13, the 2nd metal film and the board | substrate 1S are made to react by performing heat processing at 800-1200 degreeC, and the back surface silicide layer BSL is formed in the back surface side of the board | substrate 1S. Thereafter, a back electrode BE (drain electrode) is formed so as to cover the back silicide layer BSL. The thickness of the back electrode BE is, for example, about 0.4 μm.

  Next, although not shown, the interlayer insulating film IL is processed by a dry etching method using a resist pattern as a mask to form an opening reaching the gate electrode GE.

Then, as shown in FIG. 13, a contact hole CNT reaching a metal silicide layer SL formed on the surface of a part of the n ⁺ -type source region SR and the p ^{+ +} -type body contact region BC, and the gate electrode A third metal film is deposited on the interlayer insulating film IL including the inside of the opening (not shown) reaching the GE. The third metal film is composed of, for example, a laminated film of a titanium film (Ti film), a titanium nitride film (TiN film), and an aluminum film (Al film). The thickness of the aluminum film is desirably 2.0 μm or more, for example. Subsequently, the third metal film is processed to be electrically connected to the source electrode SE and the gate electrode GE that are electrically connected to a part of the n ⁺ -type source region SR via the metal silicide layer SL. Gate electrode wiring (not shown) is formed. Thereafter, external wirings are electrically connected to the gate electrode GE, the source electrode SE, and the back electrode BE (drain electrode), respectively. As described above, the SiC power MIOSFET in the present embodiment can be manufactured.

<Characteristics of the manufacturing method in the embodiment>
Next, feature points on the manufacturing method in the present embodiment will be described. The first feature point in the manufacturing method according to the present embodiment is that, for example, in FIG. 17, by using a thermal oxidation method, the surface of the non-doped polysilicon film into which the n-type impurity constituting the gate electrode GE is not introduced In addition, an insulating film OXF made of a silicon oxide film is formed. Thereby, in the present embodiment, since a non-doped polysilicon film is used, n-type impurities are not introduced into the insulating film OXF formed by the thermal oxidation method. As a result, according to the first feature point in the manufacturing method of the present embodiment, it is possible to prevent high-concentration n-type impurities from being mixed into the insulating film OXF, which causes an increase in leakage current at the end of the gate electrode GE. .

  For example, in FIG. 15, when the polysilicon film PF is formed on the gate insulating film GOX, it may be possible to form the polysilicon film PF into which an n-type impurity is introduced. In this case, n-type impurities have already been introduced into the gate electrode GE shown in FIG. 16 at this high impurity concentration. Therefore, the n-type impurity can be introduced into the gate electrode GE at a high impurity concentration without newly adding a process for introducing the n-type impurity into the gate electrode GE. The resistance of the electrode GE can be reduced. However, in this case, the n-type impurity introduced into the gate electrode GE is diffused into the insulating film OXF by the high-temperature heat treatment performed when the insulating film OXF is formed on the sidewall of the gate electrode GE. Resulting in. As a result, high-concentration n-type impurities are introduced into the insulating film OXF, thereby increasing the leakage current at the end of the gate electrode GE.

  On the other hand, in the present embodiment, in FIG. 15, a polysilicon film PF into which n-type impurities are not introduced is not formed, but a non-doped polysilicon film PF into which n-type impurities are not introduced is formed. ing. In this embodiment, the insulating film OXF made of a silicon oxide film is formed on the surface of the non-doped polysilicon film PF by high-temperature heat treatment using a thermal oxidation method. In this case, since the n-type impurity is not introduced into the non-doped polysilicon film PF in the first place, the n-type impurity is diffused from the polysilicon film PF by the subsequent high-temperature heat treatment, so that the insulating film OXF It is possible to effectively suppress the introduction of n-type impurities into the inside. As a result, in the present embodiment, it is possible to prevent high-concentration n-type impurities from being mixed into the insulating film OXF, which causes an increase in leakage current at the end of the gate electrode GE. However, in this case, since the n-type impurity is not introduced into the gate electrode GE, the resistance of the gate electrode GE becomes high as it is. Therefore, in the present embodiment, n-type impurities are introduced into the gate electrode GE with a high impurity concentration in an ion implantation process different from the polysilicon film forming process. At this time, when an n-type impurity is introduced into the entire gate electrode GE, a heat treatment for activating the n-type impurity is performed to form an insulating film OXF formed on the side wall of the gate electrode GE from the gate electrode GE. The n-type impurities are easily diffused, and accordingly, the n-type impurities are mixed in the insulating film OXF with a high impurity concentration. For this reason, in the present embodiment, a contrivance is made to suppress the mixing of n-type impurities into the insulating film OXF, and this contrivance point is the second feature point in the manufacturing method in the present embodiment. . Below, the 2nd feature point on the manufacturing method in this Embodiment is demonstrated.

  The second feature point in the manufacturing method according to the present embodiment is, for example, as shown in FIG. 18, covering the end portion of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE, and the gate electrode An n-type impurity is introduced into the gate electrode GE by an ion implantation method using a mask (resist pattern PR) having an opening OP that opens a partial region of the insulating film OXF formed above the GE. is there. Thereby, according to the present embodiment, the portion of the gate electrode GE into which the n-type impurity is introduced is separated from the insulating film OXF formed on the side wall of the gate electrode GE. In this case, the introduction of n-type impurities into the insulating film OXF can be suppressed. Since the portion of the gate electrode GE into which the n-type impurity is introduced is separated from the insulating film OXF formed on the side wall of the gate electrode GE, the n-type impurity performed after the ion implantation step is activated. Even if the n-type impurity is diffused by the heat treatment for forming the n-type impurity, mixing of the n-type impurity at a high impurity concentration into the insulating film OXF formed on the sidewall of the gate electrode GE is suppressed. Therefore, according to the second feature point in the manufacturing method in the present embodiment, the impurity concentration of the n-type impurity introduced into the insulating film OXF formed on the side wall of the gate electrode GE is set to the n-type impurity contained in the gate electrode GE. The maximum impurity concentration of impurities can be reduced to 1/100 or less. As a result, according to the second feature point in the manufacturing method according to the present embodiment, the n-type impurity can be introduced into the gate electrode GE at a sufficient impurity concentration in order to reduce the resistance of the gate electrode GE. On the other hand, mixing of n-type impurities at a high impurity concentration into the insulating film OXF formed on the sidewall of the gate electrode GE can be suppressed. Therefore, according to the present embodiment, it is possible to achieve both reduction in resistance of the gate electrode GE and suppression of leakage current at the end of the gate electrode GE. Thus, according to the present embodiment, it is possible to obtain a remarkable effect that the reliability of the semiconductor device can be improved while improving the performance of the semiconductor device.

<Modification 1>
In the above-described embodiment, for example, as shown in FIG. 18, the insulating film OXF formed on the gate electrode GE and covering the end portion of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE is formed. The example in which the resist pattern PR is used as the mask having the opening OP that opens a partial region of the film OXF has been described. However, the technical idea in the above embodiment is not limited to this. For example, as shown in FIG. 22, the edge of the gate electrode GE and the insulating film OXF formed on the side wall of the gate electrode GE are covered. A hard mask HM made of a silicon oxide film may be used as a mask having an opening OP that opens a partial region of the upper surface of the gate electrode GE. In this case, since the insulating film OXF exposed from the opening OP is formed of the same silicon oxide film as the hard mask HM, when the opening OP is formed in the hard mask HM, as shown in FIG. The insulating film OXF exposed from the bottom surface of OP is also removed.

<Modification 2>
In the first modification, the example in which the n-type impurity is introduced into the gate electrode GE by the ion implantation method using the hard mask HM has been described. However, the technical idea in the embodiment is not limited to this. For example, as shown in FIG. 23, after forming the hard mask HM having the opening OP, the gate electrode GE exposed from the hard mask HM The PSG film, which is a film containing n-type impurity pure material, is brought into contact, and thereafter, for example, heat treatment may be performed to diffuse the n-type impurity from the BPSG film into the gate electrode. The heat treatment in this case is at a lower temperature than the activation annealing performed after ion implantation. Therefore, it is useful in that phosphorus (P) can be prevented from diffusing into the insulating film OXF formed on the side wall of the gate electrode GE.

<Modification 3>
In the above embodiment, for example, as shown in FIGS. 15 to 17, after processing the non-doped polysilicon film PF into which n-type impurities are not introduced to form the gate electrode GE, the non-doped polysilicon film PF is formed. The example in which the insulating film OXF is formed on the surface of the gate electrode GE made of has been described. However, the technical idea in the embodiment is not limited to this. For example, after forming the gate electrode GE by processing the polysilicon film PF into which the n-type impurity is introduced at a low impurity concentration, the gate is formed. An insulating film OXF may be formed on the surface of the electrode GE. Even in this case, it is not possible to use the non-doped polysilicon film PF, but compared to the case where the polysilicon film PF into which n-type impurities are introduced at a high impurity concentration is used, the insulating film OXF. N-type impurities can be prevented from being mixed in.

  When the non-doped polysilicon film PF is used, the formation rate of the insulating film OXF on the surface of the gate electrode GE by the thermal oxidation method is reduced, whereas the n-type impurity is introduced at a low impurity concentration. When the polysilicon film PF is used, the formation rate of the insulating film OXF on the surface of the gate electrode GE by the thermal oxidation method can be increased. However, in the case of Modification 3, for example, in order to reduce the resistance of the gate electrode GE by adding a process shown in FIG. 18, for example, it is necessary to introduce an n-type impurity into the gate electrode GE. is there.

<Modification 4>
Furthermore, in addition to the structure of the SiC power MOSFET in the above embodiment, the corner of the gate electrode GE may be configured to have a round shape. Thereby, the electric field concentration at the end of the gate electrode GE can be relaxed. Therefore, according to the fourth modification, the impurity concentration of the n-type impurity introduced into the insulating film OXF formed on the sidewall of the gate electrode GE is set to the maximum impurity concentration of the n-type impurity contained in the gate electrode GE. A synergistic effect between the configuration of 1/100 or less and the configuration in which the corners of the gate electrode GE have a round shape can suppress an increase in leakage current at the end of the gate electrode GE.

<Modification 5>
In the embodiment described above, phosphorus (P) is taken as an example of the n-type impurity, and the technical idea in the embodiment has been described. However, the technical idea in the embodiment is not limited to this, and n Widely applicable to type impurities. For example, n-type impurities other than phosphorus can include arsenic (As). In particular, since arsenic is heavier than phosphorus and difficult to diffuse, applying the technical idea in the above embodiment further reduces the impurity concentration of n-type impurities (arsenic) mixed in the insulating film OXF. Can do. That is, adopting arsenic as the n-type impurity reduces the amount of n-type impurity mixed in the insulating film OXF formed on the side wall of the gate electrode GE, thereby reducing leakage current at the end of the gate electrode GE. It is useful from the viewpoint of suppression.

<Modification 6>
In the above-described embodiment, an embodiment in which an n-type impurity typified by phosphorus is introduced into the gate electrode GE of the SiC power MOSFET has been described. However, the technical idea in the above-described embodiment is not limited thereto, and the SiC power MOSFET is not limited thereto. The present invention can also be applied to a mode in which a p-type impurity typified by boron (B) is introduced into the gate electrode GE.

  In particular, in an n-channel SiC power MOSFET, the threshold voltage can be increased by introducing a p-type impurity into the gate electrode GE. This means that "false point" can be suppressed. This is because, for example, as can be seen from FIG. 5, when the gate voltage V2 of the SiC power transistor to be turned off exceeds the threshold voltage due to capacitive coupling, a “false point arc” occurs. This is because if it is high, the gate voltage V2 of the SiC power transistor to be turned off hardly exceeds the threshold voltage.

  In a configuration in which a p-type impurity is introduced into the gate electrode GE in the n-channel SiC power MOSFET, when a negative voltage is applied to the gate electrode GE, the gate electrode GE in the vicinity of the interface between the gate electrode GE and the gate insulating film GOX. A depletion layer is formed. Considering that this depletion layer functions as an insulating layer, the thickness of the gate insulating film GOX is substantially increased at the end of the gate electrode GE. This means that the electric field strength at the end of the gate electrode GE is relaxed. As a result, in the configuration of Modification 6, when a negative voltage is applied to the gate electrode GE, an increase in leakage current at the end of the gate electrode GE can be suppressed.

  On the other hand, in a configuration in which a p-type impurity is introduced into the gate electrode GE in the n-channel SiC power MOSFET, a depletion layer cannot be formed in the gate electrode GE when a positive voltage is applied to the gate electrode GE. It is considered that the effect of reducing the leakage current due to the increase in the thickness of the gate insulating film GOX cannot be obtained as in the case of applying a negative voltage to. In addition, by analogy with the above embodiment, there is a concern about increase in leakage current at the end of the gate electrode GE due to p-type impurities mixed in the insulating film OXF formed on the sidewall of the gate electrode GE.

  In this regard, it is surmised that the first mechanism described in the column of “<< new knowledge found by the inventor >>” is shown below. That is, the p-type impurity level (acceptor level) is lower than the n-type impurity level (donor level). This means that in the band gap of the insulating film OXF, a trap level caused by the p-type impurity is formed at a position lower in energy level than the trap level caused by the n-type impurity. This is because the structure in which the p-type impurity is mixed in the insulating film OXF is conducted from the valence band through the trap level than the structure in which the n-type impurity is mixed in the insulating film OXF. This means that the excitation of electrons to the band is less likely to occur. Therefore, it is considered that the increase in leakage current due to the first mechanism described above is less obvious in the configuration in which the p-type impurity is mixed in the insulating film OXF than in the configuration in which the n-type impurity is mixed in the insulating film OXF. .

  Furthermore, it is speculated that the first mechanism described in the column of “<< the new knowledge found by the inventor >>” is shown below. That is, since the n-type impurity has a positive charge and electrons are accumulated by applying a negative voltage to the gate electrode GE, the interface between the gate electrode GE and the insulating film OXF is, for example, As with the gate insulating film shown in FIG. 11, a steep potential barrier is generated. In such a steep potential barrier, for example, as shown in FIG. 11, since the potential barrier width “L2” becomes small, an FN tunnel current easily flows, and this FN tunnel current becomes a leak current. .

  On the other hand, unlike the n-type impurity, the p-type impurity has a negative charge, so that the slope of the potential barrier formed at the interface between the gate electrode GE and the insulating film OXF becomes gentler. Further, since electrons are not accumulated by applying a positive voltage to the gate electrode GE, it is difficult for the FN tunnel current to flow.

  From the above, the increase in leakage current due to the first mechanism and the second mechanism described above is a configuration in which the p-type impurity is mixed in the insulating film OXF rather than the configuration in which the n-type impurity is mixed in the insulating film OXF. Then, it becomes difficult to manifest. Therefore, for example, in the configuration of Modification 6 in which the p-type impurity is mixed into the insulating film OXF, the impurity concentration of the p-type impurity contained in the insulating film OXF is the maximum impurity concentration of the p-type impurity contained in the gate electrode GE. Even in the configuration of 1/10 or less, it is possible to sufficiently suppress an increase in leakage current at the end of the gate electrode GE.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

(Appendix 1)
Including a power transistor formed on an epitaxial layer mainly composed of silicon carbide;
The power transistor is
A gate insulating film formed on the epitaxial layer;
A gate electrode formed on the gate insulating film and containing a p-type impurity;
A first insulating film formed on a sidewall of the gate electrode;
A second insulating film formed to cover the gate electrode and the first insulating film;
With
The density of the first insulating film is higher than the density of the second insulating film,
The semiconductor device, wherein the first insulating film contains a p-type impurity at an impurity concentration of 1/10 or less of a maximum impurity concentration of the p-type impurity contained in the gate electrode.

(Appendix 2)
In the semiconductor device according to attachment 1,
The semiconductor device, wherein the p-type impurity is boron.

EPI epitaxial layer GE gate electrode GOX gate insulating film IL interlayer insulating film OXF insulating film SR source region

Claims (14)

Including a power transistor formed on an epitaxial layer mainly composed of silicon carbide;
The power transistor is
A gate insulating film formed on the epitaxial layer;
A gate electrode formed on the gate insulating film and containing a conductive impurity;
A first insulating film formed on a sidewall of the gate electrode;
A second insulating film formed to cover the gate electrode and the first insulating film;
With
The density of the first insulating film is higher than the density of the second insulating film,
The first insulating film contains a conductive impurity at an impurity concentration of 1/100 or less of the maximum impurity concentration of the conductive impurity contained in the gate electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the first insulating film is a silicon oxide film. The semiconductor device according to claim 1,
The semiconductor device, wherein an impurity concentration of the conductive impurity contained in the gate electrode is 10 ²⁰ / cm ³ or more. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first insulating film is thicker than the gate insulating film. The semiconductor device according to claim 1,
The gate insulating film has a thickness of 80 nm or less. The semiconductor device according to claim 1,
The power transistor is a semiconductor device having a source region different from the LDD structure. The semiconductor device according to claim 1,
The epitaxial device has a semiconductor device having an off angle. The semiconductor device according to claim 1,
The semiconductor device, wherein the first insulating film is thinner than the second insulating film. The semiconductor device according to claim 1,
The corner of the gate electrode is a semiconductor device having a round shape. The semiconductor device according to claim 1,
When turning on the power transistor, a first voltage equal to or higher than a threshold voltage is applied to the gate electrode;
The semiconductor device, wherein when the power transistor is turned off, a second voltage having the same absolute value as the first voltage and opposite in polarity to the first voltage is applied to the gate electrode. A method of manufacturing a semiconductor device including a power transistor formed in an epitaxial layer mainly composed of silicon carbide,
(A) forming a gate insulating film;
(B) forming a polysilicon film on the gate insulating film;
(C) patterning the polysilicon film to form a gate electrode;
(D) forming a first insulating film on the surface of the gate electrode using a thermal oxidation method;
(E) introducing a conductive impurity into the gate electrode;
With
In the step (e), a semiconductor device manufacturing method using a mask that covers an end portion of the gate electrode and the first insulating film formed on a side wall of the gate electrode. In the manufacturing method of the semiconductor device according to claim 11,
In the step (b), the non-doped polysilicon film into which the conductive impurity is not introduced is formed. In the manufacturing method of the semiconductor device according to claim 11,
In the step (e), a semiconductor device manufacturing method using an ion implantation method. In the manufacturing method of the semiconductor device according to claim 11,
The step (e)
(E1) contacting the gate electrode exposed from the mask with a film containing a conductive impurity;
(E2) diffusing the conductive impurities from the film into the gate electrode;
A method for manufacturing a semiconductor device, comprising:

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