JP2018536344A5 - - Google Patents

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JP2018536344A5
JP2018536344A5 JP2018521657A JP2018521657A JP2018536344A5 JP 2018536344 A5 JP2018536344 A5 JP 2018536344A5 JP 2018521657 A JP2018521657 A JP 2018521657A JP 2018521657 A JP2018521657 A JP 2018521657A JP 2018536344 A5 JP2018536344 A5 JP 2018536344A5
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Japan
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JP2018521657A
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Japanese (ja)
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JP2018536344A (ja
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Priority claimed from US14/925,761 external-priority patent/US10419772B2/en
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Publication of JP2018536344A5 publication Critical patent/JP2018536344A5/ja
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JP2018521657A 2015-10-28 2016-08-23 並列算術コーディング技法 Pending JP2018536344A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/925,761 US10419772B2 (en) 2015-10-28 2015-10-28 Parallel arithmetic coding techniques
US14/925,761 2015-10-28
PCT/US2016/048244 WO2017074539A1 (en) 2015-10-28 2016-08-23 Parallel arithmetic coding techniques

Publications (2)

Publication Number Publication Date
JP2018536344A JP2018536344A (ja) 2018-12-06
JP2018536344A5 true JP2018536344A5 (https=) 2019-09-12

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ID=56990948

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Application Number Title Priority Date Filing Date
JP2018521657A Pending JP2018536344A (ja) 2015-10-28 2016-08-23 並列算術コーディング技法

Country Status (7)

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US (1) US10419772B2 (https=)
EP (1) EP3369250A1 (https=)
JP (1) JP2018536344A (https=)
KR (1) KR20180075523A (https=)
CN (1) CN108353174A (https=)
TW (1) TW201724852A (https=)
WO (1) WO2017074539A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10924591B2 (en) * 2018-06-21 2021-02-16 Intel Corporation Low-latency link compression schemes
JP7040629B2 (ja) * 2018-09-20 2022-03-23 富士通株式会社 符号化装置、符号化方法、符号化プログラム、復号装置、復号方法及び復号プログラム
US11487544B2 (en) * 2020-01-15 2022-11-01 Western Digital Technologies, Inc. Method and device for simultaneously decoding data in parallel to improve quality of service
KR102574824B1 (ko) * 2021-04-26 2023-09-06 주식회사 모르미 가변 비트 수를 지원하는 병렬 처리 장치
FR3157037A1 (fr) * 2023-12-19 2025-06-20 Stmicroelectronics International N.V. Système informatique et procédé de décodage arithmétique

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045852A (en) * 1990-03-30 1991-09-03 International Business Machines Corporation Dynamic model selection during data compression
GB2306868B (en) 1994-09-30 1997-10-22 Ricoh Kk Apparatus for decoding data
JP3350482B2 (ja) * 1999-06-04 2002-11-25 松下電送システム株式会社 算術符号化装置および算術復号化装置
CN1364341A (zh) 2000-03-07 2002-08-14 皇家菲利浦电子有限公司 算术编码信息信号的算术译码
KR100694098B1 (ko) 2005-04-04 2007-03-12 한국과학기술원 산술 복호 방법 및 그 장치
US8306125B2 (en) 2006-06-21 2012-11-06 Digital Video Systems, Inc. 2-bin parallel decoder for advanced video processing
US8542727B2 (en) * 2007-12-31 2013-09-24 Intel Corporation Systems and apparatuses for performing CABAC parallel encoding and decoding
US8761240B2 (en) 2010-07-13 2014-06-24 Blackberry Limited Methods and devices for data compression using context-based coding order
US8696620B2 (en) * 2010-07-30 2014-04-15 St. Jude Medical, Atrial Fibrillation Division, Inc. Catheter with a mechanism for omni-directional deflection of a catheter shaft
US8604951B2 (en) * 2010-10-05 2013-12-10 Massachusetts Institute Of Technology System and method for optimizing context-adaptive binary arithmetic coding
WO2012135442A1 (en) 2011-03-30 2012-10-04 Amazon Technologies, Inc. Frameworks and interfaces for offload device-based packet processing
TWI487295B (zh) 2011-05-17 2015-06-01 Univ Nat Cheng Kung 高產出平行化ａｖｃ／ｈ.２６４前後文適應性二位元算數解碼器之方法

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