JP2018514868A - 改良された命令セットを有する中央処理ユニット - Google Patents

改良された命令セットを有する中央処理ユニット Download PDF

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Publication number
JP2018514868A
JP2018514868A JP2017554326A JP2017554326A JP2018514868A JP 2018514868 A JP2018514868 A JP 2018514868A JP 2017554326 A JP2017554326 A JP 2017554326A JP 2017554326 A JP2017554326 A JP 2017554326A JP 2018514868 A JP2018514868 A JP 2018514868A
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JP
Japan
Prior art keywords
volatile memory
integrated circuit
segment
protection
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017554326A
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English (en)
Japanese (ja)
Other versions
JP2018514868A5 (enExample
Inventor
マイケル キャサーウッド，
マイケル キャサーウッド，
デイビッド ミッキー，
デイビッド ミッキー，
ブライアン クリス，
ブライアン クリス，
カラム ウィルキー，
カラム ウィルキー，
ジェイソン サックス，
ジェイソン サックス，
アンドレアス ライター，
アンドレアス ライター，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of JP2018514868A publication Critical patent/JP2018514868A/ja
Publication of JP2018514868A5 publication Critical patent/JP2018514868A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Executing Machine-Instructions (AREA)
  • Storage Device Security (AREA)
  • Advance Control (AREA)
JP2017554326A 2015-04-30 2016-04-29 改良された命令セットを有する中央処理ユニット Pending JP2018514868A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562154927P 2015-04-30 2015-04-30
US62/154,927 2015-04-30
US201562195692P 2015-07-22 2015-07-22
US62/195,692 2015-07-22
PCT/US2016/030159 WO2016176593A1 (en) 2015-04-30 2016-04-29 Central processing unit with enhanced instruction set

Publications (2)

Publication Number Publication Date
JP2018514868A true JP2018514868A (ja) 2018-06-07
JP2018514868A5 JP2018514868A5 (enExample) 2019-05-23

Family

ID=55963480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017554326A Pending JP2018514868A (ja) 2015-04-30 2016-04-29 改良された命令セットを有する中央処理ユニット

Country Status (7)

Country Link
US (2) US10983931B2 (enExample)
EP (1) EP3289442B1 (enExample)
JP (1) JP2018514868A (enExample)
KR (1) KR20170140225A (enExample)
CN (1) CN107548492B (enExample)
TW (1) TW201706856A (enExample)
WO (1) WO2016176593A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11872623B2 (en) 2016-11-04 2024-01-16 Lg Chem, Ltd. Thermosetting composition

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111679787B (zh) 2016-04-27 2023-07-18 慧荣科技股份有限公司 闪存装置、闪存控制器及闪存存储管理方法
US10019314B2 (en) 2016-04-27 2018-07-10 Silicon Motion Inc. Flash memory apparatus and storage management method for flash memory
JP2020510951A (ja) * 2017-06-12 2020-04-09 サンディスク テクノロジーズ エルエルシー マルチコアオンダイメモリマイクロコントローラ
KR102032146B1 (ko) 2018-04-11 2019-10-15 경희대학교 산학협력단 소자 결점을 보완하기 위한 구간 선형 정류 유닛을 사용하는 인공신경망 시스템
CN111382429B (zh) * 2018-12-27 2022-12-27 华为技术有限公司 指令的执行方法、装置及存储介质
CN109886416A (zh) * 2019-02-01 2019-06-14 京微齐力(北京)科技有限公司 集成人工智能模块的系统芯片及机器学习方法
CN109870921B (zh) * 2019-03-26 2022-04-01 广东美的制冷设备有限公司 驱动控制电路与家电设备
TWI715371B (zh) * 2019-12-25 2021-01-01 新唐科技股份有限公司 一次性可編程記憶體裝置及其容錯方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5167028A (en) * 1989-11-13 1992-11-24 Lucid Corporation System for controlling task operation of slave processor by switching access to shared memory banks by master processor
US5226138A (en) * 1990-11-27 1993-07-06 Sun Microsystems, Inc. Method for selectively transferring data instructions to a cache memory
US6327648B1 (en) * 1994-12-09 2001-12-04 Cirrus Logic, Inc. Multiprocessor system for digital signal processing
US7272703B2 (en) * 1997-08-01 2007-09-18 Micron Technology, Inc. Program controlled embedded-DRAM-DSP architecture and methods
ITMI981564A1 (it) * 1998-07-09 2000-01-09 St Microelectronics Srl Memoria non volatile in grado di eseguire un programma autonomamente
US6260082B1 (en) * 1998-12-23 2001-07-10 Bops, Inc. Methods and apparatus for providing data transfer control
GB2365545B (en) * 1999-12-23 2004-06-02 Ibm Data processing system with master and slave processors
US6691216B2 (en) 2000-11-08 2004-02-10 Texas Instruments Incorporated Shared program memory for use in multicore DSP devices
US6895479B2 (en) 2000-11-15 2005-05-17 Texas Instruments Incorporated Multicore DSP device having shared program memory with conditional write protection
JP2002185430A (ja) * 2000-12-13 2002-06-28 Sony Corp 受信装置及び方法
US6349056B1 (en) 2000-12-28 2002-02-19 Sandisk Corporation Method and structure for efficient data verification operation for non-volatile memories
US7007172B2 (en) * 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US7571287B2 (en) * 2003-03-13 2009-08-04 Marvell World Trade Ltd. Multiport memory architecture, devices and systems including the same, and methods of using the same
CN1301473C (zh) * 2003-09-17 2007-02-21 中兴通讯股份有限公司 多处理器系统共享引导模块的方法
US7325122B2 (en) * 2004-02-20 2008-01-29 International Business Machines Corporation Facilitating inter-DSP data communications
JP4575059B2 (ja) * 2004-07-21 2010-11-04 株式会社日立製作所 ストレージ装置
US7917753B2 (en) * 2005-05-16 2011-03-29 Texas Instruments Incorporated Transferring control between programs of different security levels
CN101366004A (zh) 2005-12-06 2009-02-11 波士顿电路公司 用于带有专用线程管理的多核处理的方法和设备
US20080235493A1 (en) 2007-03-23 2008-09-25 Qualcomm Incorporated Instruction communication techniques for multi-processor system
GB2466695B (en) * 2007-06-18 2011-11-23 Fujitsu Ltd Processor and prefetch support program
WO2009090502A1 (en) * 2008-01-16 2009-07-23 Freescale Semiconductor, Inc. Processor based system having ecc based check and access validation information means
US20110087922A1 (en) * 2009-10-09 2011-04-14 National Tsing Hua University Test method and tool for master-slave systems on multicore processors
US8478974B2 (en) 2010-06-23 2013-07-02 Assured Information Security, Inc. Method and system for reducing an impact of malware during a booting sequence
US8904190B2 (en) 2010-10-20 2014-12-02 Advanced Micro Devices, Inc. Method and apparatus including architecture for protecting sensitive code and data
US9021170B2 (en) * 2011-06-29 2015-04-28 Texas Instruments Incorporated System and method for improving ECC enabled memory timing
US9195581B2 (en) * 2011-07-01 2015-11-24 Apple Inc. Techniques for moving data between memory types
GB2503470B (en) * 2012-06-27 2014-08-13 Nordic Semiconductor Asa Memory protection
US9858229B2 (en) 2014-09-30 2018-01-02 International Business Machines Corporation Data access protection for computer systems
RU2580016C1 (ru) * 2014-10-17 2016-04-10 Закрытое акционерное общество "Лаборатория Касперского" Способ передачи управления между областями памяти

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11872623B2 (en) 2016-11-04 2024-01-16 Lg Chem, Ltd. Thermosetting composition

Also Published As

Publication number Publication date
US20190188163A1 (en) 2019-06-20
US10983931B2 (en) 2021-04-20
US20160321202A1 (en) 2016-11-03
TW201706856A (zh) 2017-02-16
EP3289442B1 (en) 2023-04-19
CN107548492A (zh) 2018-01-05
US10776292B2 (en) 2020-09-15
EP3289442A1 (en) 2018-03-07
WO2016176593A1 (en) 2016-11-03
CN107548492B (zh) 2021-10-01
KR20170140225A (ko) 2017-12-20

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