JP2018506776A5 - - Google Patents

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JP2018506776A5
JP2018506776A5 JP2017533975A JP2017533975A JP2018506776A5 JP 2018506776 A5 JP2018506776 A5 JP 2018506776A5 JP 2017533975 A JP2017533975 A JP 2017533975A JP 2017533975 A JP2017533975 A JP 2017533975A JP 2018506776 A5 JP2018506776 A5 JP 2018506776A5
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JP
Japan
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address
translation
cache
address translation
memory
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JP2017533975A
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Japanese (ja)
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JP2018506776A (ja
JP6718454B2 (ja
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Priority claimed from US14/579,654 external-priority patent/US9514059B2/en
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JP2017533975A 2014-12-22 2015-12-22 選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと Active JP6718454B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/579,654 2014-12-22
US14/579,654 US9514059B2 (en) 2014-12-22 2014-12-22 Hiding page translation miss latency in program memory controller by selective page miss translation prefetch
PCT/US2015/067525 WO2016106392A1 (en) 2014-12-22 2015-12-22 Hiding page translation miss latency in program memory controller by selective page miss translation prefetch

Publications (3)

Publication Number Publication Date
JP2018506776A JP2018506776A (ja) 2018-03-08
JP2018506776A5 true JP2018506776A5 (https=) 2019-01-31
JP6718454B2 JP6718454B2 (ja) 2020-07-08

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JP2017533975A Active JP6718454B2 (ja) 2014-12-22 2015-12-22 選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと

Country Status (5)

Country Link
US (1) US9514059B2 (https=)
EP (1) EP3238073B1 (https=)
JP (1) JP6718454B2 (https=)
CN (1) CN107111550B (https=)
WO (1) WO2016106392A1 (https=)

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KR102701812B1 (ko) * 2016-07-27 2024-09-03 에스케이하이닉스 주식회사 휘발성 메모리를 캐쉬로 사용하는 비휘발성 메모리 시스템
US9673977B1 (en) 2016-09-15 2017-06-06 ISARA Corporation Refreshing public parameters in lattice-based cryptographic protocols
US10719451B2 (en) * 2017-01-13 2020-07-21 Optimum Semiconductor Technologies Inc. Variable translation-lookaside buffer (TLB) indexing
US10565115B2 (en) * 2017-03-30 2020-02-18 Western Digital Technologies, Inc. Calculating the optimal number of LBNS to prefetch per CPU
US10929296B2 (en) * 2017-10-12 2021-02-23 Texas Instruments Incorporated Zero latency prefetching in caches
KR102151180B1 (ko) * 2017-11-20 2020-09-02 삼성전자주식회사 효율적인 가상 캐시 구현을 위한 시스템 및 방법
US10642742B2 (en) * 2018-08-14 2020-05-05 Texas Instruments Incorporated Prefetch management in a hierarchical cache system
US10489305B1 (en) * 2018-08-14 2019-11-26 Texas Instruments Incorporated Prefetch kill and revival in an instruction cache
CN111984318B (zh) 2019-05-22 2025-10-03 德克萨斯仪器股份有限公司 伪先进先出（fifo）标签线替换
US11113208B2 (en) 2019-05-22 2021-09-07 Texas Instruments Incorporated Pseudo-first in, first out (FIFO) tag line replacement
US10977184B2 (en) * 2019-06-20 2021-04-13 Apical Limited and Arm Limited Managing memory access for convolutional neural networks
US11403110B2 (en) * 2019-10-23 2022-08-02 Texas Instruments Incorporated Storing a result of a first instruction of an execute packet in a holding register prior to completion of a second instruction of the execute packet
US11704253B2 (en) * 2021-02-17 2023-07-18 Microsoft Technology Licensing, Llc Performing speculative address translation in processor-based devices

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JPH05298185A (ja) * 1992-04-17 1993-11-12 Fujitsu Ltd 仮想記憶方式および装置
US5778434A (en) 1995-06-07 1998-07-07 Seiko Epson Corporation System and method for processing multiple requests and out of order returns
JPH1040171A (ja) * 1996-07-24 1998-02-13 Sony Corp アドレス変換装置および方法
US6487640B1 (en) 1999-01-19 2002-11-26 International Business Machines Corporation Memory access request reordering to reduce memory access latency
EP1182569B8 (en) 2000-08-21 2011-07-06 Texas Instruments Incorporated TLB lock and unlock operation
US7054927B2 (en) * 2001-01-29 2006-05-30 Adaptec, Inc. File system metadata describing server directory information
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