JP2018207078A - Power semiconductor device - Google Patents

Abstract

To provide a small power semiconductor device in which the number of wirings directly connected to a semiconductor chip is reduced to ensure the protecting effect of the surface of a semiconductor chip and improvement effect of the electrical stability.SOLUTION: A power semiconductor device includes a conductive base plate 1, a lower metal plate 3 thereon, a power semiconductor chip 4 thereon, an upper metal plate 6 thereon, a support member 7 thereon, a conductive cover plate 8 thereon, a conductive member 9, and a signal terminal 10. The conductive member 9 and the signal terminal 10 are disposed so as to penetrate through the supporting member 7 from the upper metal plate 6 side to the conductive cover plate 8 side. The signal terminal 10 passes through both the support member 7 and the upper metal plate 6.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device including a pressure contact type power semiconductor core module.

  In recent years, various power semiconductor devices have been proposed in which electrical connection between a control terminal and a control circuit board is made by pressure contact using elastic force instead of solder from the viewpoint of reducing environmental load and increasing output. ing. For example, Japanese translations of PCT publication No. 2004-528724 (patent document 1) discloses a high-power semiconductor module in which a plurality of semiconductor chips and a cover plate directly above them are electrically connected by spring-like contact elements. ing. In the high-power semiconductor module disclosed in JP-T-2004-528724, a plurality of pre-tested submodules are arranged in parallel in one module housing element. A gate electrode of an IGBT (Insulated Gate Bipolar Transistor) which is a semiconductor chip is connected to a gate runner disposed on the side of the semiconductor chip via a bonding wire. Thereby, each of the plurality of semiconductor chips is collected on one common gate signal conductor.

  However, in such a structure, the gate electrode of the semiconductor chip is connected to a gate runner disposed outside in a plan view of the semiconductor chip via a bonding wire. For this reason, the plane area of the entire high-power semiconductor module is increased by the area where the bonding wires and the gate runner are arranged. Therefore, it is considered that such a configuration is not suitable for downsizing the entire high-power semiconductor module.

  On the other hand, for example, the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 11-3395 (Patent Document 2) has a configuration in which the gate electrode of the semiconductor chip is connected to the gate terminal via a contact probe extending directly above the semiconductor chip. ing. For this reason, the connection path from the semiconductor chip to the gate terminal is not arranged outside in the plan view of the semiconductor chip, and the semiconductor device is downsized.

JP-T-2004-528724 JP-A-11-3395

  However, in the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 11-3395, the tips of a plurality of contact probes directly contact the surface of the semiconductor chip, which may damage the surface of the semiconductor chip. That is, from the viewpoint of reducing the damage on the surface of the semiconductor chip, the wiring other than the contact probe connected to the gate electrode is preferably connected to a member of a conductive material other than the surface of the semiconductor chip.

  Also, as disclosed in Japanese Patent Application Laid-Open No. 11-3395, a configuration in which a plurality of contact probes are directly connected to the surface of a semiconductor chip and an electric signal is output therefrom is such that the contact probes are brought into contact with each other on the surface of the semiconductor chip and externally energized. This will narrow the possible range. For this reason, there is a possibility that the electrical stability of the input / output of the electric signal by the contact probe is poor.

  The present invention has been made in view of the above problems, and the object thereof is to reduce the number of wirings directly connected to the semiconductor chip, to ensure the protective effect of the surface of the semiconductor chip and the electrical stability improving effect, and It is an object to provide a miniaturized power semiconductor device.

  The power semiconductor device of the present invention includes a conductive base plate, a lower metal plate thereon, a power semiconductor chip thereon, an upper metal plate thereon, a supporting member thereon, A conductive cover plate, a conductive member, and a signal terminal are provided. The conductive member and the signal terminal are disposed so as to penetrate through the support member from the upper metal plate side to the conductive cover plate side. The signal terminal penetrates both the support member and the upper metal plate.

  According to the present invention, since the conductive member is disposed so as to contact the upper metal plate, the number of the conductive members that directly contact the surface of the power semiconductor chip is reduced, thereby protecting the surface of the semiconductor chip and An effect of improving electrical stability is obtained. In addition, since the signal terminal extends right above the member on the semiconductor chip, the power semiconductor device is reduced in size.

It is a schematic plan view of a partial region of the power semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view of one self-extinguishing semiconductor element region along the line AA in FIG. 1 according to a first example of the first embodiment. FIG. 3 is a schematic plan view showing a configuration of a part of a self-extinguishing semiconductor element along the line III-III in FIG. 2. It is a schematic plan view which shows the structure of the part of an upper metal plate which follows the IV-IV line in FIG. FIG. 5 is a schematic plan view illustrating a configuration of a support member according to a first example of the first embodiment, taken along line VV in FIG. 2. FIG. 4 is a schematic cross-sectional view of one self-extinguishing semiconductor element region along the line AA in FIG. 1 according to a second example of the first embodiment. FIG. 7 is a schematic cross-sectional view of one self-extinguishing semiconductor element region along the line AA in FIG. 1 according to a third example of the first embodiment. It is a schematic plan view which shows the aspect in the planar view of the board | substrate for emitters along the VIII-VIII line in FIG. It is a schematic plan view which shows the aspect in the planar view of the board | substrate for gates along the IX-IX line in FIG. FIG. 6 is a schematic cross-sectional view of a region of one self-extinguishing semiconductor element along the line AA in FIG. 1 according to a fourth example of the first embodiment. It is a schematic plan view which shows the structure of the supporting member which concerns on the 4th example of Embodiment 1 along the XI-XI line in FIG. 6 is a schematic plan view showing a configuration of a support member according to a fifth example of Embodiment 1. FIG. 6 is a schematic plan view showing a configuration of a support member according to Embodiment 2. FIG. It is a schematic sectional drawing which shows the structure of the area | region of one signal terminal contained in the self-extinguishing type semiconductor element area | region of Embodiment 2 along the XIV-XIV line | wire in FIG. It is a schematic sectional drawing which shows the structure of the area | region of the other signal terminal contained in the self-extinguishing type | mold semiconductor element area | region of Embodiment 2 along the XV-XV line | wire in FIG. FIG. 6 is a schematic cross-sectional view of a region of one self-extinguishing semiconductor element along the AA line in FIG. 1 according to the third embodiment. It is the schematic which shows the structure of the signal terminal in the area | region XVII enclosed with the dotted line in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
First, the configuration of the power semiconductor device of the first example of the present embodiment will be described with reference to FIGS. 1 to 9 (excluding FIGS. 6 and 7). For convenience of explanation, an X direction, a Y direction, and a Z direction are introduced. In the schematic plan view of the power semiconductor device 101 in FIG. 1, the X direction corresponds to the left-right direction in the drawing, the Y direction corresponds to the up-down direction in the drawing, and the Z direction corresponds to a direction perpendicular to the drawing sheet. FIG. 1 shows a plan view of a partial region of the power semiconductor device 101.

  Referring to FIG. 1, a power semiconductor device 101 according to the present invention has a power semiconductor core module 102. The power semiconductor device 101 has a planar form in which a configuration in which, for example, four power semiconductor core modules 102A, 102B, 102C, and 102D are gathered as one unit of the power semiconductor core module 102 is provided. The power semiconductor core module 102A is disposed on the X direction negative side and the Y direction positive side (upper left side) of FIG. 1 in the power semiconductor core module 102. The power semiconductor core module 102B is disposed on the X direction positive side and the Y direction positive side (upper right side) of FIG. 1 in the power semiconductor core module 102. The power semiconductor core module 102 </ b> C is disposed on the X direction negative side and the Y direction negative side (lower left side) of FIG. 1 in the power semiconductor core module 102. The power semiconductor core module 102D is arranged on the positive side in the X direction and the negative side in the Y direction (lower right side) in FIG. 1 in the power semiconductor core module 102. The power semiconductor device 101 includes a plurality of units each including four power semiconductor core modules 102A to 102D in the planar form shown in FIG. 1 in both the X direction and the Y direction at intervals. It is preferable to have a repeated configuration so as to be arranged in a matrix at intervals.

  Each of the power semiconductor core modules 102A to 102D has a plurality of self-extinguishing semiconductor element regions MT and a plurality of diode regions DI. That is, as shown in FIG. 1, each of the power semiconductor core modules 102A to 102D has, for example, five self-extinguishing semiconductor element regions MT and four diode regions DI. In each of the power semiconductor core modules 102 </ b> A to 102 </ b> D, the self-extinguishing semiconductor element region MT is disposed so as to surround the outermost part of the entire unit of the power semiconductor core module 102. That is, in the power semiconductor core module 102A, on the left and upper sides of FIG. 1, in the power semiconductor core module 102B, on the right and upper sides, in the power semiconductor core module 102C, on the left and lower sides, the power semiconductor core module 102D. In FIG. 2, self-extinguishing type semiconductor element regions MT are arranged on the right side and the lower side. On the other hand, in each of the power semiconductor core modules 102A to 102D, four diode regions DI are arranged so as to be gathered inside so as to be surrounded by the self-extinguishing semiconductor element region MT.

  The planar form of the power semiconductor device 101 and the power semiconductor core module 102 shown in FIG. 1 is an example, and is not limited to this. For example, in FIG. 1, four power semiconductor core modules 102A to 102D are arranged in a matrix. However, the present invention is not limited to this, and the number of power semiconductor core modules arranged in the power semiconductor device 101 is arbitrary two or more. In FIG. 1, each of the power semiconductor core modules 102A to 102D has a square planar shape, and the power semiconductor device 101 in which these are arranged in a matrix also has a square planar shape. However, the present invention is not limited to this. For example, each of the power semiconductor core modules 102A to 102D may have a circular or elliptical planar shape. Further, the self-extinguishing semiconductor element region MT and the diode region DI also have a rectangular shape in FIG. 1, but may have a circular or elliptical planar shape. Furthermore, in FIG. 1, each of the power semiconductor core modules 102A to 102D has a total of nine rows of five self-extinguishing semiconductor element regions MT and four diode regions DI, three in each of the X and Y directions. They are arranged in a matrix. However, the present invention is not limited to this, and the number of self-extinguishing semiconductor element regions MT and diode regions DI arranged in each of the power semiconductor core modules 102A to 102D is arbitrary.

  In the self-extinguishing semiconductor element region MT, semiconductor elements such as MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and IGBT are mounted. In the diode region DI, for example, an SBD (Schottky Barrier Diode) and a PN diode are mounted.

  FIG. 2 shows a cross-sectional aspect of a self-extinguishing semiconductor element region MT1 as one of a plurality of self-extinguishing semiconductor element regions MT arranged in FIG. 1 according to the first example of the present embodiment. Referring to FIG. 2, self-extinguishing semiconductor element region MT1 of the first example of the present embodiment includes base plate 1, lower metal plate 3, power semiconductor chip 4, upper metal plate 6, A support member 7, a cover plate 8, a conductive member 9, and a signal terminal 10 are mainly provided.

  The base plate 1 is a flat plate-like member that is disposed at the bottom in the Z direction that serves as the foundation of the entire self-extinguishing semiconductor element region MT1. Base plate 1 is preferably formed of a conductive material having a relatively low coefficient of thermal expansion, such as molybdenum. However, the present invention is not limited thereto, and may be a generally known metal material such as one selected from the group consisting of copper, SUS, and aluminum. If the base plate 1 is made of a conductive material in this way, there is no need for wiring for taking out the connection terminal from the lower metal plate 3 in contact with the lower part of the power semiconductor chip 4 in the Z direction to the outside of the power semiconductor core module 102. It can be.

  The lower metal plate 3 is a member disposed on the base plate 1, that is, in contact with the main surface on the upper side in the Z direction of the base plate 1. The lower metal plate 3 has a substantially flat plate shape in FIG. 2, but is not limited thereto, and may have, for example, a prismatic shape. Here, the flat plate shape means a rectangular parallelepiped shape in which a rectangular main surface is arranged along the XY plane, and the thickness in the Z direction intersecting the main surface is smaller than the dimensions in the X direction and the Y direction. Here, the prismatic shape means a rectangular parallelepiped shape in which a rectangular main surface is arranged along the XY plane, and the thickness in the Z direction intersecting the main surface is larger than the dimensions in the X direction and the Y direction.

  The power semiconductor chip 4 is a member disposed on the lower metal plate 3, that is, in contact with the main surface on the upper side in the Z direction of the lower metal plate 3. The power semiconductor chip 4 is a semiconductor chip as a self-extinguishing semiconductor element, and is made of, for example, silicon. As described above, semiconductor elements such as MOSFETs and IGBTs are mounted on the power semiconductor chip 4.

  FIG. 3 shows an aspect in plan view of the power 4 along the line III-III in FIG. Referring to FIG. 3, power semiconductor chip 4 has electrode 4 </ b> E disposed on a chip having a rectangular shape, particularly a square planar shape, that is, in contact with the main surface on the upper side in the Z direction of the chip. A gate pad 4P is formed inside thereof. An electric signal can be input and output from a MOSFET or the like mounted on the power semiconductor chip 4 via the electrode 4E and the gate pad 4P. The electrode 4E and the gate pad 4P are preferably thin films made of a generally known metal material such as aluminum or copper.

  Referring to FIG. 2 again, upper metal plate 6 is a member disposed on power semiconductor chip 4, that is, in contact with the main surface on the upper side in the Z direction of power semiconductor chip 4. Therefore, upper metal plate 6 is arranged such that the main surface on the lower side in the Z direction is in contact with electrode 4E. The upper metal plate 6 has a generally flat plate shape in FIG. 2, but is not limited thereto, and may have, for example, a prismatic shape. The lower metal plate 3 and the upper metal plate 6 are preferably formed of a metal material such as copper.

  FIG. 4 shows an aspect in plan view of the upper metal plate 6 along the line IV-IV in FIG. Referring to FIGS. 2 and 4, the upper metal plate 6 has a through hole 11 penetrating therethrough from one main surface, ie, the main surface on the lower side in the Z direction, to the other main surface, ie, the main surface on the upper side in the Z direction. Is formed. In FIG. 4, the through hole 11 is formed to have a circular (or elliptical) planar shape. However, the present invention is not limited to this. For example, the through hole 11 may have a rectangular (square) planar shape. Good. The through hole 11 is a hole through which a signal terminal 10 to be described later passes. Therefore, the size of the through hole 11 in a plan view is a size in which the signal terminal 10 can be inserted. An insulating coating film 12 is formed on the wall surface of the through-hole 11, that is, the wall surface inside the through-hole 11 as a hole extending along the Z direction. The insulating coating film 12 is provided to suppress a short circuit between the signal terminal 10 and the upper metal plate 6.

  The insulating coating film 12 is one selected from the group consisting of a silicone resin, an epoxy resin, and an imide resin in consideration of easy electrical supply and easy supply to the wall surface of the through hole 11. Preferably one is used. The thickness of the insulating coating film 12 is preferably 5 μm or more and 2 mm or less, but is not limited thereto.

  Referring to FIG. 2 again, support member 7 is, for example, a flat plate-shaped member disposed on upper metal plate 6, that is, in contact with the main surface on the upper side in the Z direction of upper metal plate 6. However, the support member 7 may have a prismatic shape or a cylindrical shape.

  The support member 7 is preferably made of any one metal material selected from the group consisting of copper, aluminum, and molybdenum. However, the support member 7 is not limited to this, and may be made of any one insulating material selected from the group consisting of a thermosetting resin, a thermoplastic resin molding, and ceramic. By using a metal as the support member 7, it is possible to integrally mold with the upper metal plate 6 and to reduce the cost. Further, by using a thermosetting resin or a thermoplastic resin molding as the support member 7, the cost can be reduced. Furthermore, since the dimensional accuracy with respect to temperature is superior to the thermosetting resin and the thermoplastic resin molding by using a ceramic plate processed product as the support member 7, the conductive member 9 and the signal terminal for the power semiconductor chip 4 are used. The positional accuracy of 10 is improved.

  FIG. 5 shows an aspect in plan view of the support member 7 in the first example of the present embodiment along the line VV in FIG. Referring to FIG. 5, like the upper metal plate 6, the support member 7 penetrates from one main surface thereof, ie, the main surface on the lower side in the Z direction, to the other main surface, ie, the main surface on the upper side in the Z direction. A through-hole 11 is formed. This through-hole 11 is also a hole for allowing a signal terminal 10 to be described later to penetrate therethrough. Accordingly, the through hole 11 extends from the main surface on the lower side in the Z direction of the upper metal plate 6 to the main surface on the upper side in the Z direction of the support member 7 so as to penetrate both the upper metal plate 6 and the support member 7.

  When the support member 7 is made of a metal material, as shown in FIG. 5, the through hole of the support member 7 is used from the viewpoint of suppressing a short circuit between the signal terminal 10 passing through the through hole 11 of the support member 7 and the support member 7. An insulating coating film 12 is formed on the wall surface of 11, that is, the wall surface inside the through hole 11 as a hole extending along the Z direction. With this insulating coating film 12, the support member 7 and the signal terminal 10 are electrically insulated from each other. This insulating coating film 12 is the same as the insulating coating film 12 on the inner wall surface of the through hole 11 of the upper metal plate 6. On the other hand, when the support member 7 is made of any one insulating material selected from the group consisting of a thermosetting resin, a thermoplastic resin molding, and ceramic, unlike FIG. 5, the inside of the through hole 11 of the support member 7 The insulating coating film 12 may not be formed on the wall surface. That is, the insulating coating film 12 is disposed on the wall surface of the through hole 11 that is a hole that penetrates both the support member 7 and the upper metal plate 6.

  Referring again to FIG. 2, here, the dimensions, that is, the thicknesses of the lower metal plate 3 and the upper metal plate 6 in the Z direction are much larger than those of the power semiconductor chip 4. However, the present invention is not limited to this. For example, the lower metal plate 3 and the upper metal plate 6 may have the same thickness as the power semiconductor chip 4 or may be thinner than the power semiconductor chip 4. In FIG. 2, the lower metal plate 3, the upper metal plate 6, and the support member 7 have the same thickness. However, the present invention is not limited to this, and for example, the support member 7 is more than the lower metal plate 3 and the upper metal plate 6. It can be thicker or thinner. The lower metal plate 3 may be thicker or thinner than the upper metal plate 6.

  In FIG. 2, the lower metal plate 3 is larger than the upper metal plate 6 in plan view, and the support member 7 is larger than the upper metal plate 6 in plan view. However, the present invention is not limited to this. For example, the sizes of the lower metal plate 3, the upper metal plate 6, and the support member 7 may all be equal, or the lower metal plate 3 may be smaller than the upper metal plate 6, The plate 6 may be larger than the support member 7. Further, in FIG. 2, the lower metal plate 3 is larger than the support member 7 in plan view, but conversely, the support member 7 may be larger than the lower metal plate 3.

  The cover plate 8 is a member disposed on the support member 7, that is, in contact with the main surface on the upper side in the Z direction of the support member 7. The cover plate 8 is a flat plate-like member disposed at the top in the Z direction of the entire self-extinguishing semiconductor element region MT1. The cover plate 8 is preferably formed of an insulating material.

  FIG. 6 shows a cross-sectional aspect of a self-extinguishing semiconductor element region as one of a plurality of self-extinguishing semiconductor element regions MT arranged in FIG. 1 according to the second example of the present embodiment. FIG. 7 shows a cross-sectional aspect of a self-extinguishing semiconductor element region as one of a plurality of self-extinguishing semiconductor element regions MT arranged in FIG. 1 according to the third example of the present embodiment. Referring to FIG. 6, the self-extinguishing type semiconductor device region shown here is basically the same as the self-extinguishing type semiconductor device region shown in FIG. However, the self-extinguishing semiconductor element region of FIG. 6 is different from the self-extinguishing semiconductor element region of FIG. 2 in that it has a conductive material 15 electrically connected to an emitter substrate 21 described later. The conductive material 15 is disposed on the cover plate 8, that is, in contact with the main surface on the upper side in the Z direction of the cover plate 8. The conductive material 15 is a flat member made of a conductive material.

  FIG. 7 is basically the same as FIG. 6 except that two or more self-extinguishing semiconductor element regions in FIG. 6 are stacked in the Z direction, that is, multi-layered. Referring to FIG. 7, when power semiconductor core modules 102 </ b> A to 102 </ b> D are configured by stacking a plurality of (for example, two) self-extinguishing semiconductor element regions MT <b> 1, individual self-extinguishing semiconductor element regions are provided. A conductive material 15 as shown in FIG. 6 is preferably disposed on the uppermost surface of the cover plate 8 of MT1. In this way, the stacked self-extinguishing semiconductor element regions MT1 can be easily electrically connected to each other.

  The conductive member 9 is a member arranged so as to penetrate through the support member 7 from the upper metal plate 6 side, that is, the main surface at the bottom in the Z direction, to the cover plate 8 side, that is, the main surface at the top in the Z direction. In other words, the conductive member 9 is disposed between the upper metal plate 6 and the cover plate 8 in the Z direction. 2 and 5, the support member 7 has a plurality of cylindrical holes spaced from each other so as to penetrate from the main surface at the bottom in the Z direction to the main surface at the top in the Z direction. Open and formed. The conductive member 9 is disposed so as to pass through the inside of each of the cylindrical holes. Therefore, a plurality of conductive members 9 are installed in the self-extinguishing semiconductor element region MT1. As shown in FIG. 5, for example, the support member 7 is formed with seven rows of cylindrical holes (except for the center) in each of the X direction and the Y direction, but is not limited thereto. The number of columns to be played is arbitrary.

  The signal terminal 10 is a member arranged so as to penetrate through the support member 7 from the upper metal plate 6 side, that is, the main surface at the bottom in the Z direction, to the cover plate 8 side, that is, the main surface at the top in the Z direction. In other words, the conductive member 9 is disposed between the upper metal plate 6 and the cover plate 8 in the Z direction. In this respect, the signal terminal 10 is the same as the conductive member 9. However, the signal terminal 10 penetrates both the support member 7 and the upper metal plate 6. That is, the signal terminal 10 is disposed so as to pass through the through hole 11 formed in both the support member 7 and the upper metal plate 6 as described above. For this reason, the signal terminal 10 extends from the uppermost portion in the Z direction of the support member 7 to the lowermost portion in the Z direction of the upper metal plate 6. The signal terminal 10 passes through both the inside of the through hole 11 of the support member 7 and the inside of the through hole 11 of the upper metal plate 6 connected so as to overlap each other in a planar manner. In this respect, the signal terminal 10 is different from the conductive member 9 penetrating only the support member 7.

  Since the through hole 11 is formed in both the support member 7 and the upper metal plate 6 and the signal terminal 10 penetrates the inside of the through hole 11, the through hole 11 is formed in the signal terminal 10 when the power semiconductor device 101 is manufactured. It can be used as a guide for placement location and extension direction. For this reason, the signal terminal 10 can be easily positioned.

  The material which comprises the electroconductive member 9 and the signal terminal 10 is not specifically limited, It can be set as arbitrary electroconductive materials. In addition, the shapes of the conductive member 9 and the signal terminal 10 are not particularly limited, and can be various shapes such as a spring shape and a rod shape as long as they have elasticity. In FIG. 2, a conductive member 9 and a signal terminal 10 having a spring shape are shown as an example. When coil springs or ring springs are used as the conductive member 9 and the signal terminal 10, members that contact the upper side and the lower side of the conductive member 9 and the signal terminal 10 (power semiconductor chip 4, cover plate 8, etc.) Can be made uniform. As a result, the conductive member 9 and the signal terminal 10 can electrically stabilize the input / output of an electric signal between the conductive member 9 and the signal terminal 10.

  Referring to FIG. 2 again, in addition to these, an emitter substrate 21 and a gate substrate 22 are disposed in the self-extinguishing semiconductor element region MT1. The emitter substrate 21 is a flat plate-like member that is disposed under the cover plate 8, that is, in contact with the main surface of the cover plate 8 on the lower side in the Z direction. That is, the emitter substrate 21 is disposed between the support member 7 and the cover plate 8, and has a main surface along the XY plane, like the support member 7 and the cover plate 8, and the support member 7 and the cover plate 8. It is arranged so as to include a region that overlaps with the plane.

  FIG. 8 shows an aspect in plan view of the emitter substrate 21 along the line VIII-VIII in FIG. Referring to FIG. 8, emitter substrate 21 has a plane size larger than that of power semiconductor chip 4 or the like that extends along the XY plane so as to overlap the entire power semiconductor core modules 102A to 102D in plan view. It is a big member. In FIG. 8, the emitter substrate 21 included in the power semiconductor core module 102D is shown as an example, but the same emitter substrate 21 is also disposed in the other power semiconductor core modules 102A to 102C. The emitter substrate 21 is a plate-like member in plan view, which is made of a conductive material that is electrically connected to the emitter terminal as a whole.

  The emitter substrate 21 has an emitter substrate hole 21H penetrating therethrough from the lower main surface to the upper main surface. The emitter substrate hole 21H is planar with both the through hole 11 of the support member 7 and the through hole 11 of the upper metal plate 6 in each of the plurality of self-extinguishing semiconductor element regions MT1 included in the power semiconductor core module 102D. It is preferable to arrange so that it may overlap. Therefore, the emitter substrate hole 21H has, for example, a circular plane shape, like the through hole 11. In FIG. 8, the support members 7 included in the self-extinguishing semiconductor element region MT1 (represented by three rows in each of the X direction and the Y direction as shown in FIG. 1) are represented by dotted rectangles. Yes. Since the support members 7 are arranged in the same number as the self-extinguishing semiconductor element regions MT, in FIG. 8, they are arranged at the same positions as the self-extinguishing semiconductor element regions MT of FIG.

  Of a plurality (five) of self-extinguishing semiconductor element regions MT included in the power semiconductor core module 102D, a region adjacent to the supporting member 7A as the supporting member 7 of the self-extinguishing semiconductor element region MT in the upper right of the figure. The emitter substrate terminal 21T as a terminal of the emitter substrate 21 extends rightward in the X direction in FIG. This corresponds to the emitter substrate terminal 21T in which the emitter substrate 21 extends to the right of the cover plate 8 in FIG. An electrical signal can be input / output to / from the power semiconductor device 101 from the emitter substrate terminal 21T.

  The lower end of the conductive member 9 in the Z direction is in contact with the uppermost surface of the upper metal plate 6, but the lowermost surface of the upper metal plate 6 is the emitter (electrode 4 E) of the semiconductor element included in the power semiconductor chip 4. It is connected to the. Therefore, the lower end portion of the conductive member 9 in the Z direction is connected to the emitter (electrode 4E) of the semiconductor element included in the power semiconductor chip 4. The conductive member 9 penetrating through the support member 7 so as to extend in the Z direction is electrically connected to the uppermost portion in the Z direction in contact with the conductive emitter substrate 21. Is electrically connected to the upper metal plate 6 by being in contact therewith. Accordingly, each of the plurality of conductive members 9 is in contact with both the upper metal plate 6 (the gate of the semiconductor element included in the power semiconductor chip 4) and the emitter substrate 21 in a state of extending in the vertical direction. ing.

  The gate substrate 22 is a flat plate-like member that has a main surface along the XY plane so as to be along the main surface of the cover plate 8 and is partially buried in the cover plate 8. . Most of the gate substrate 22 is a region having a main surface along the XY plane as described above, but additionally includes a gate substrate signal wiring portion 22L and a gate substrate terminal 22T. The gate substrate signal wiring portion 22L extends from the top in the Z direction of the signal terminal 10 to the inside of the cover plate 8 through the emitter substrate hole 21H of the emitter substrate 21, and extends in the Z direction. It is mechanically and electrically connected to a region extending in the XY plane. On the other hand, the gate substrate terminal 22T is a region exposed to the outside of the cover plate 8 from the region of the gate substrate 22 along the main surface of the cover plate 8 buried in the cover plate 8. For this reason, the gate substrate terminal 22T extends rightward in the X direction in FIG. 8 in the same manner as the emitter substrate terminal 21T. The gate substrate terminal 22T is also mechanically and electrically connected to a region extending in the XY plane of the gate substrate 22.

  FIG. 9 shows an aspect in plan view of the gate substrate 22 along the line IX-IX in FIG. Referring to FIG. 9, the gate substrate 22 includes the gate substrate signal wiring portion 22 </ b> L and the gate substrate terminal 22 </ b> T, and is entirely made of a conductive material that is electrically connected to the gate terminal. The gate substrate 22 is connected so as to connect the signal terminals 10 penetrating through the support members 7 of the plurality of self-extinguishing semiconductor element regions MT1 constituting the power semiconductor core module 102 (102D) in plan view, for example. A linear (polygonal) planar shape as shown in FIG. Alternatively, although not shown, the gate substrate 22 may be plate-like as the emitter substrate 21 is. Then, a part of the gate substrate 22 protrudes from the cover plate 8, thereby forming a gate substrate terminal 22 </ b> T that protrudes from a region overlapping the power semiconductor core module 102 in a plane.

  However, if the gate substrate terminal 22T extends from a region adjacent to the support member 7A on the upper right side of the figure, like the emitter substrate terminal 21T, the gate substrate 22T may be short-circuited with the emitter substrate terminal 21T. This is because the gate substrate terminal 22T and the emitter substrate terminal 21T are close to each other. Therefore, from the viewpoint of avoiding this, as indicated by a dotted line in FIG. 9, for example, the gate substrate terminal 22T may extend from a region adjacent to the other support member 7B adjacent to the support member 7A. . When the gate substrate terminal 22T extends from a region adjacent to the other support member 7B, the gate substrate terminal 22T does not appear in the cross-sectional view of FIG. From the gate substrate terminal 22T extending as described above, an electric signal can be input and output to the outside of the power semiconductor device 101.

  The lower end of the signal terminal 10 in the Z direction is directly connected to the gate (gate pad 4P) of the semiconductor element included in the power semiconductor chip 4. The signal terminal 10 penetrating through the support member 7 so as to extend in the Z direction is electrically connected to the Z-direction uppermost portion in contact with the gate substrate signal wiring portion 22L. By being in contact with the gate (gate pad 4P) of the power semiconductor chip 4, it is electrically connected thereto. Therefore, the signal terminal 10 is in contact with both the gate pad 4P of the power semiconductor chip 4 and the gate substrate 22 in a state of extending in the vertical direction.

  Each self-extinguishing semiconductor element region MT of the power semiconductor device 101 having the above-described members is housed in the resin case 13. That is, the main body portion of the resin case 13 is disposed so as to connect the base plate 1 and the cover plate 8.

Gas for the purpose of electrical insulation between the respective members may be enclosed in the power semiconductor device 101 described above, that is, in the power semiconductor core module 102 (inside the resin case 13). As a kind of gas, it is preferable to use any one selected from the group consisting of sulfur hexafluoride (SF ₆ ), nitrogen (N ₂ ), carbon dioxide (CO ₂ ), and dry air. In particular, since sulfur hexafluoride gas has good insulation performance, it is desirable to use sulfur hexafluoride gas when high insulation performance is required. Further, for the purpose of electrical insulation inside the resin case 13 of the power semiconductor core module 102, a sealing resin may be enclosed instead of the gas. As the kind of the sealing resin, silicone gel or epoxy resin can be used.

Next, the effect of the 1st example of this Embodiment is demonstrated.
In the present embodiment, the signal terminal 10 penetrates both the support member 7 and the upper metal plate 6, and the upper metal plate 6 is disposed on the power semiconductor chip 4. Thereby, the signal terminal 10 is directly electrically connected to the gate pad 4P of the power semiconductor chip 4. In contrast, the conductive member 9 passes through the support member 7 from the upper metal plate 6 side to the cover plate 8 side, and the upper metal plate 6 is disposed on the power semiconductor chip 4. Therefore, when the conductive member 9 is in contact with the uppermost surface of the upper metal plate 6, the conductive member 9 is electrically connected to the emitter electrode 4 </ b> E of the power semiconductor chip 4.

  By having such a configuration, in this embodiment, a terminal in contact with the surface of the power semiconductor chip 4 including the electrode 4E and the gate pad 4P serves as one signal terminal 10. The conductive member 9 connected to the emitter substrate 21 is not directly connected to the power semiconductor chip 4, but is connected to the upper metal plate 6, thereby being electrically connected to the power semiconductor chip 4 via the upper metal plate 6. Connected. For this reason, the number of terminals in contact with the surface of the power semiconductor chip 4 can be reduced, and the protective effect of the surface of the power semiconductor chip 4 can be enhanced. Further, the conductive member 9 can be connected to any position on the main surface of the wide upper metal plate 6, and a necessary distance can be maintained between the plurality of conductive members 9. For this reason, compared with the case where the electroconductive member 9 is connected on the narrow electrode of the semiconductor chip 4 for electric power, for example, it can be connected so that it may be electrically stabilized with the semiconductor chip 4 for electric power.

  Further, in the present embodiment, an electrical signal of the gate is taken out by the signal terminal 10 extending right above the gate pad 4P of the power semiconductor chip 4. For this reason, for example, compared with the case where the gate electrode of the semiconductor chip is connected to the gate runner arranged outside in the plan view of the semiconductor chip via the bonding wire, the plane area of the entire power semiconductor device 101 is reduced. Thus, the power semiconductor device 101 can be reduced in size.

  Further, since the signal terminal 10 is inserted into the through holes 11 of both the support member 7 and the upper metal plate 6, the position thereof is guided by the through holes 11. Therefore, the signal terminal 10 can be easily positioned.

  Referring again to FIG. 5, in the first example of the present embodiment, in support member 7, a plurality of conductive members 9 are arranged symmetrically with respect to signal terminal 10 in plan view. That is, when the support member 7 is viewed in plan, the signal terminal 10 is arranged at the center thereof, and the plurality of conductive members 9 are arranged in a line-symmetrical and point-symmetrical positional relationship with respect to the signal terminal 10. Has been placed. In this way, the plurality of conductive members 9 are evenly arranged so as to surround the signal terminal 10. On the other hand, the signal terminal 10 is in contact with and electrically connected to the gate substrate 22 in the cover plate 8, and the conductive member 9 is in contact with the emitter substrate 21 in contact with the main surface on the lower side of the cover plate 8 in the Z direction. Connected. Therefore, the force that the signal terminal 10 holds the gate substrate 22 by the elastic force and the force that the conductive member 9 holds the emitter substrate 21 by the elastic force become uniform. Also from this, the electrical stability of the connection between the signal terminal 10 and the gate substrate 22 and the connection between the conductive member 9 and the emitter substrate 21 can be improved.

  Next, FIG. 10 shows a cross-sectional aspect of a self-extinguishing semiconductor element region MT2 as one of a plurality of self-extinguishing semiconductor element regions MT arranged in FIG. 1 according to the fourth example of the present embodiment. ing. Moreover, FIG. 11 has shown the aspect in planar view of the supporting member 7 in the 4th example of this Embodiment so that the XI-XI line in FIG. 10 may be met. Referring to FIG. 10 and FIG. 11, the self-extinguishing semiconductor element region MT2 of the fourth example of the present embodiment has basically the same configuration as the self-extinguishing semiconductor element region MT1, and therefore the same The same reference numerals are given to the constituent elements, and the description thereof will not be repeated. However, in the self-extinguishing semiconductor element region MT2, the positional relationship between the signal terminal 10 and the plurality of conductive members 9 is different from that in the self-extinguishing semiconductor element region MT1. Specifically, in the self-extinguishing semiconductor element region MT2, the signal terminals 10 are arranged in the rightmost column in the X direction among a plurality of columns (here, seven columns) arranged in the X direction of the conductive member 9. A plurality of conductive members 9 are arranged so as to surround this from the left side in the X direction and the upper and lower sides in the Y direction. That is, the conductive member 9 is not disposed on the right side in the X direction of the signal terminal 10 in the self-extinguishing semiconductor element region MT2. In this respect, the self-extinguishing semiconductor element region MT2 is different from the self-extinguishing semiconductor element region MT1 in which the signal terminal 10 is disposed at the center of the plurality of conductive members 9 in the X direction and the Y direction. As shown in FIG. 11, the signal terminals 10 are arranged in the rightmost column in the X direction of the conductive members 9 arranged in a plurality of columns in the X direction, but the same as the self-extinguishing semiconductor element region MT1 in the Y direction. Are arranged in the central row of the conductive members 9 arranged in a plurality of rows.

  As shown in FIGS. 10 and 11, the signal terminal 10 is a central portion of the matrix-like arrangement of the conductive members 9 in plan view (in other words, the conductive members 9 are symmetrical with respect to the signal terminal 10 in plan view). It does not need to be arranged in this way. The position of the signal terminal 10 with respect to the conductive member 9 can be appropriately determined in consideration of the structure of the self-extinguishing semiconductor element region MT. Although not shown, for example, the signal terminals 10 may be disposed in the leftmost column in the X direction of the plurality of conductive members 9 arranged, or the signal terminals may be arranged in the row in the front or back side in the Y direction of the plurality of conductive members 9 arranged. 10 may be arranged.

  FIG. 12 shows a cross-sectional aspect of a self-extinguishing semiconductor element region MT2 as one of a plurality of self-extinguishing semiconductor element regions MT arranged in FIG. 1 according to the fifth example of the present embodiment. Referring to FIG. 12, support member 7 in the self-extinguishing semiconductor element region of the fifth example of the present embodiment basically has the same configuration as support member 7 in FIG. Are denoted by the same reference numerals and the description thereof will not be repeated. However, in FIG. 12, the through hole 11 has a rectangular (square) planar shape, and in this respect, the through hole 11 is different from the support member 7 of FIG. 5 having a circular planar shape. Thus, the planar shape of the through hole 11 is arbitrary. In the case of the configuration of FIG. 12, the through hole 11 of the upper metal plate 6 immediately below the through hole 11 of the support member 7 has a rectangular shape as well.

Embodiment 2. FIG.
The structure of the power semiconductor device of this embodiment will be described with reference to FIGS. FIG. 13 shows an aspect in plan view of the support member 7 in the present embodiment. FIG. 14 shows a cross-sectional aspect of a portion including the signal terminal 10A of the present embodiment along the line XIV-XIV in FIG. FIG. 15 shows a cross-sectional aspect of a portion including another signal terminal 10B of the present embodiment along the XV-XV line of FIG.

  Referring to FIGS. 13 to 15, in power semiconductor device 101 (see FIG. 1) of the present embodiment, as one of self-extinguishing semiconductor element regions MT included in a plurality of power semiconductor core modules 102. The self-extinguishing semiconductor element region MT3 is disposed. Since the self-extinguishing semiconductor element region MT3 basically has the same configuration as the self-extinguishing semiconductor element region MT1, the same components are denoted by the same reference numerals and description thereof will not be repeated. However, the self-extinguishing semiconductor element region MT3 has one signal terminal 10A and the other signal terminal 10B as the two signal terminals 10. As described above, the self-extinguishing semiconductor element region MT3 according to the present embodiment has only a single signal terminal 10 in that it has a plurality of signal terminals 10. This is different from the regions MT1 and MT2.

  Referring to FIGS. 13 and 14, one signal terminal 10A in self-extinguishing semiconductor element region MT3 has a lower end in the Z direction of power semiconductor chip 4 as a self-extinguishing semiconductor element. It is directly connected to the gate pad 4P. One signal terminal 10A has its upper end in the Z direction connected to the gate substrate signal wiring portion 22L. Accordingly, one signal terminal 10A is in contact with both the gate pad 4P of the power semiconductor chip 4 and the gate substrate 22 in a state of extending in the vertical direction, like the signal terminal 10 of the first embodiment. ing. Referring to FIGS. 13 and 15, the other signal terminal 10B in the self-extinguishing semiconductor element region MT3 is electrically connected to the top of the Z direction in contact with the emitter substrate 21, The lowermost portion in the Z direction is directly connected to the emitter pad 4EP of the power semiconductor chip 4. Therefore, the other signal terminal 10B is in contact with both the emitter pad 4EP of the power semiconductor chip 4 and the emitter substrate 21.

  That is, in this embodiment, as shown in FIG. 15, in addition to the conductive member 9, another signal terminal 10B is used in combination as a member for taking out the emitter terminal to the emitter substrate 21 side. In this way, the emitter terminal may be extracted using the signal terminal 10. The self-extinguishing type semiconductor element region MT is configured to have only one signal terminal 10 like the self-extinguishing type semiconductor element regions MT1 and MT2 in the first embodiment, or the self-extinguishing type in this embodiment. Whether to have a plurality of signal terminals 10 as in the semiconductor element region MT3 can be determined as appropriate depending on the structure of the self-extinguishing semiconductor element region MT.

  As described above, since the present embodiment has a plurality (two) of signal terminals 10, a plurality (two) of through holes 11 through which the signal terminals 10 are inserted are formed in both the upper metal plate 6 and the support member 7. Yes. Three or more through holes 11 may be formed.

  14 and 15, the signal terminals 10 </ b> A and 10 </ b> B are both arranged on the outer edge of the matrix arrangement of the plurality of conductive members 9 on the support member 7, that is, on the right side in the X direction. However, the present invention is not limited to this. For example, one signal terminal 10A may be arranged at the center of the matrix arrangement of the plurality of conductive members 9, and the other signal terminal 10B may be arranged at the outer edge of the matrix arrangement. Or vice versa. Alternatively, the signal terminals 10 </ b> A and 10 </ b> B may be arranged at positions relatively closer to the center of the matrix arrangement of the plurality of conductive members 9 with a space therebetween. The arrangement of these signal terminals 10A can be appropriately determined depending on the structure of the self-extinguishing semiconductor element region MT.

  Since the effect of this Embodiment is the same as the effect of the 1st example of Embodiment 1, the description is not repeated.

Embodiment 3 FIG.
FIG. 16 shows a cross-sectional aspect of a self-extinguishing semiconductor element region MT4 as one of a plurality of self-extinguishing semiconductor element regions MT arranged in FIG. 1 according to the present embodiment. FIG. 17 shows a mode of signal terminals arranged in a region XVII surrounded by a dotted line in FIG. Referring to FIGS. 16 and 17, self-extinguishing semiconductor element region MT4 of the present embodiment basically has the same configuration as self-extinguishing semiconductor element region MT1, and therefore the same components are The same reference numerals are given and the description thereof is not repeated. However, the self-extinguishing type semiconductor element region MT4 is different from the self-extinguishing type semiconductor element region MT1 in that a signal terminal 17 with an insulating coating film is arranged instead of the signal terminal 10.

  As shown in FIG. 17, the signal terminal 17 with the insulating coating film has a configuration in which the surface of the signal terminal 10 made of the same conductive material as that of the first embodiment is covered with the insulating coating film 12. ing. That is, the signal terminal 17 with the insulating coating film has a configuration in which the surface of the signal terminal 10 is covered with the insulating coating film 12. The insulating coating film 12 here is made of a silicone resin, an epoxy resin, or an imide resin, similarly to the insulating coating film 12 covering the inner wall surface of the through hole 11 through which the signal terminal 10 is inserted in the first embodiment. Any one selected from the group is preferably used.

  The effect of this Embodiment is demonstrated. In the present embodiment, the insulating coating film 12 is formed so as to cover the surface of the signal terminal 10. In this case, since the surface of the signal terminal 10 is covered with the insulating coating film 12 in advance, it is not necessary to provide the insulating coating film 12 on the inner wall surface of the through hole 11 of the upper metal plate 6 and the support member 7, and the manufacturing process is reduced. It can be simplified.

  You may apply so that the characteristic described in each embodiment described above (each example contained in) may be combined suitably in the range with no technical contradiction.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1 base plate, 3 lower metal plate, 4 power semiconductor chip, 4E electrode, 4P gate pad, 6 upper metal plate, 7 support member, 8 cover plate, 9 conductive member, 10 signal terminal, 10A one signal terminal, 10B Other signal terminal, 11 Through hole, 12 Insulating coating film, 13 Resin case, 15 Conductive material, 17 Signal terminal with insulating coating film, 21 Emitter substrate, 21H Emitter substrate hole, 21T Emitter substrate terminal, 22 gate substrate, 22L gate substrate signal wiring section, 22T gate substrate terminal, 101 power semiconductor device, 102, 102A, 102B, 102C, 102D power semiconductor core module, DI diode region, MT, MT1, MT2, MT3, MT4 Self-extinguishing semiconductor element region.

Claims (7)

A base plate;
A lower metal plate disposed on the base plate;
A power semiconductor chip disposed on the lower metal plate;
An upper metal plate disposed on the power semiconductor chip;
A support member disposed on the upper metal plate;
A cover plate disposed on the support member;
A conductive member and a signal terminal arranged so as to penetrate the support member from the upper metal plate side to the cover plate side;
The power semiconductor device, wherein the signal terminal penetrates both the support member and the upper metal plate.   The power semiconductor device according to claim 1, wherein the support member and the signal terminal are electrically insulated from each other by an insulating coating film.   The power semiconductor device according to claim 2, wherein the insulating coating film is disposed on a wall surface of a hole that penetrates both the support member and the upper metal plate.   The power semiconductor device according to claim 2, wherein a surface of the signal terminal is covered with the insulating coating film.   5. The power semiconductor device according to claim 2, wherein the insulating coating film is any one selected from the group consisting of a silicone resin, an epoxy resin, and an imide resin.   The power semiconductor device according to claim 1, wherein the conductive member is disposed symmetrically with respect to the signal terminal in a plan view. The power semiconductor device according to claim 1, wherein at least one of the conductive member and the signal terminal has a spring structure.

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