JP2018200979A - Capacitor - Google Patents

Abstract

To provide a capacitor having high electrostatic capacitance and high withstand voltage.SOLUTION: A capacitor includes a capacitor body 1 in which a plurality of dielectric layers 5 and internal electrode layers 7 are alternately laminated, and the dielectric layer 5 includes a plurality of metal particles 13a which are spaced apart from the surface of the dielectric layer 5 and have a metal particle row 13 arranged along the surface 5a. The metal particle 13a has a particle diameter of 0.2 μm or more and 0.4 μm or less, and the metal particle row 13 is separated from the surface 5a of the dielectric layer 5 by 0.4 μm or more.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a multilayer capacitor.

  In recent years, multilayer capacitors (hereinafter referred to as “capacitors”) have been made thinner in dielectric layers and internal electrode layers in order to reduce size and increase capacity (for example, see Patent Document 1). reference).

JP 2011-132056 A

  The capacitor according to the present disclosure is a capacitor including a capacitor body in which a plurality of dielectric layers and internal electrode layers are alternately stacked, and the dielectric layer includes a plurality of metal particles. The metal particles have metal particle rows forming rows along the surface at positions away from the surface of the dielectric layer.

1 shows the structure of a capacitor according to the present embodiment, wherein (a) is a perspective view of the appearance, (b) is a cross-sectional view taken along line AA in (a), and (c) is a cross-sectional view taken along line BB in (a). FIG. It is sectional drawing to which the P section of FIG.1 (c) was expanded. It is a cross-sectional schematic diagram showing a part of the manufacturing process of the capacitor of the present embodiment and showing a change in state when a conductor paste is printed on the surface of a ceramic green sheet.

  Conventionally, the thinning of the dielectric layer in a capacitor has been one of the important means for increasing the capacitance of the capacitor. However, when the thickness of the dielectric layer is reduced, the withstand voltage of the capacitor is likely to decrease with a decrease in insulation. The present disclosure addresses such problems, and an object thereof is to provide a capacitor having a high capacitance and a high withstand voltage.

  Hereinafter, the capacitor of the present disclosure will be described with reference to FIGS. 1 and 2. 1A and 1B show the structure of a capacitor according to the present embodiment, in which FIG. 1A is a perspective view of an appearance, FIG. 1B is a cross-sectional view taken along the line AA in FIG. 1A, and FIG. FIG. FIG. 2 is an enlarged cross-sectional view of a portion P in FIG.

  The capacitor of the present embodiment includes a capacitor body 1 and an external electrode 3 provided on the end surface thereof. The capacitor body 1 is formed by alternately laminating a plurality of dielectric layers 5 and internal electrode layers 7. In this case, the capacitor main body 1 includes a capacitance portion 9 that develops an electrostatic capacitance, and a non-capacitance portion 11 that is disposed so as to surround the capacitance portion 9 and does not develop an electrostatic capacitance.

Here, the capacitor of this embodiment has the metal particle row | line | column 13 arrange | positioned in the dielectric material layer 5 so that the some metal particle 13a may comprise a row | line | column. The metal particle row 13 is formed at a position away from the surface 5 a (main surface) of the dielectric layer 5. The metal particle rows 13 are arranged along the surface 5 a of the dielectric layer 5. The metal particle row 13 refers to a state in which the metal particles 13a are arranged at intervals of 1 μm or less between adjacent metal particles 13a.

  A capacitor in which the metal particle rows 13 are formed in the dielectric layer 5 with the above configuration can have a higher capacitance than a capacitor in which the metal particle rows 13 are not formed. This is due to the presence of the metal particle rows 13 in the dielectric layer 5, in addition to the capacitance generated between the two internal electrode layers 7 provided across the one dielectric layer 5, This is considered to be due to the addition of the capacitance generated between the metal particle array 13 in the dielectric layer 5 and the internal electrode layer 7.

  In this case, the metal particle rows 13 present in the dielectric layer 5 are formed in the dielectric layer 5 without contacting the internal electrode layer 7. For this reason, the distance between the two internal electrode layers 7 that are insulated with the dielectric layer 5 interposed therebetween is almost the same as the case where the metal particle row 13 is not provided. Therefore, even when the metal particle row 13 is formed in the dielectric layer 5, a withstand voltage equivalent to that of the capacitor in which the metal particle row 13 is not formed can be obtained. Thus, a capacitor having a high capacitance can be obtained while maintaining the withstand voltage. As a capacitor having such characteristics, the ratio of the number of the dielectric layers 5 having the metal particle rows 13 may be 10% or more.

  As described above, the metal particle rows 13 are preferably formed in a state along the surface 5 a of the dielectric layer 5. When the metal particle row 13 is formed in a state along the surface 5a of the dielectric layer 5, the distance from the two internal electrode layers 7 provided on both surfaces 5a via the dielectric layer 5 to the metal particle 13a. Becomes uniform. For this reason, the density distribution of the electric lines of force formed inside the dielectric layer 5 can be made uniform. Thereby, the dispersion | variation in the electrical property (electrostatic capacity and withstand voltage) output by applying an electric field can be made small. In this case, the state in which the metal particle rows 13 are along the surface 5 a of the dielectric layer 5 is a state in which the metal particle rows 13 are arranged so as to be placed on a straight line along the surface 5 a of the dielectric layer 5. say. Specifically, for example, when the dielectric layer 5 is viewed in cross section, the maximum difference in distance between the closest position and the farthest position from the surface 5a of the dielectric layer 5 in the metal particle array 13 is within 0.3 μm. Say what is in. In this evaluation, a plurality of locations in the metal particle array 13 having a length in the range of 50 μm are evaluated. For example, the number of locations to be measured in one dielectric layer 5 is 3 to 5, and such evaluation is extracted from each region obtained by dividing the capacitor body 1 into three equal parts in the stacking direction. Do about.

  When the metal particle row 13 is present in the dielectric layer 5, the thermal expansion coefficient of the dielectric layer 5 is originally smaller than the thermal expansion coefficient of the internal electrode layer 7. The expansion coefficient can be brought close to the thermal expansion coefficient of the internal electrode layer 7. Thereby, the thermal stress between the dielectric layer 5 and the internal electrode layer 7 can be reduced. As a result, even when the capacitor is placed in an environment where it undergoes a rapid temperature change, cracks and the like are less likely to occur, and the thermal shock resistance can be improved.

As a condition of the metal particle row 13, the average particle diameter D of the metal particles 13a is preferably 0.2 to 0.4 μm. The distance W ₁ between the metal particle row 13 and the surface 5a of the dielectric layer 5 is preferably 0.4 μm or more. The distance W ₁ is maximized is when the metal particles 13a is positioned at the center in the thickness direction of the dielectric layer 5. Further, the metal particles columns 13, to the diameter D of the metal particles 13a, spacing ratio _{w 2 (W 2} / D) of the metal particles 13a each other adjacent good in the range of 0.5-2.

The particle diameter D of the metal particles 13a, the distance W ₁ between the metal particle array 13 and the surface 5a of the dielectric layer 5, the interval w ₂ between the metal particles 13a and W ₂ / D scan the cross section of the capacitor body 1. Measure using a photograph taken with an electron microscope. The particle diameter D of the metal particles 13a is obtained by extracting the metal particle row 13 with a length of, for example, 50 μm from the cross section of the capacitor body 1, and measuring the maximum diameter of each metal particle 13a included in the metal particle row 13 And obtain the average value. Such measurement may be performed by extracting 3 to 5 metal particle rows 13 having the same length and obtaining an average value thereof. As for the distance W ₁ between the metal particle array 13 and the surface 5a of the dielectric layer 5, the interval W ₂ between the metal particles 13a and W ₂ / D, the metal particle array 13 obtained by measuring the particle diameter D of the metal particles 13a is used. .

  The metal particle array 13 is preferably formed in a region corresponding to the same area as the region where the internal electrode layer 7 is formed when the dielectric layer 5 is viewed in plan. In this case, the metal particle row 13 does not express the capacitance as well as the portion of the capacitance portion 9 where the capacitance is expressed by the two internal electrode layers 7 sandwiching the dielectric layer 5 in the capacitor. It is preferable that the dielectric layer 5 is also formed in the region of the non-capacitance portion 11. Thereby, also in the non-capacitance part 11, the thermal expansion coefficient of the dielectric layer 5 can be made close to the thermal expansion coefficient of the internal electrode layer 7. As a result, it is possible to reduce the thermal stress in the region of the non-capacitance part 11 and to further improve the thermal shock resistance.

  The metal particle array 13 can be applied to the dielectric layer 5 having any thickness t. In particular, the average thickness of the dielectric layer 5 is 0.5 to 3 μm, and the internal electrode layer 7 This is suitable for capacitors having an average thickness of 0.5 to 2 μm. Further, it is suitable for a multi-layer capacitor in which the number of layers is 100 or more when one unit of the dielectric layer 5 and the internal electrode layer 7 is one layer.

  As a material for forming the dielectric layer 5, for example, a dielectric material mainly composed of barium titanate exhibiting ferroelectricity is suitable, but not limited thereto, titanium oxide, strontium titanate. Similar effects can be obtained with dielectric materials exhibiting paraelectric properties such as calcium titanate. The main component described above may be used by including, for example, magnesium, rare earth element and manganese oxides in accordance with desired dielectric characteristics.

  Suitable materials for the internal electrode layer 7 and the external electrode 3 include base metal materials such as nickel and copper, as well as noble metal materials such as silver and palladium.

  Next, a method for manufacturing the capacitor of this embodiment will be described. The capacitor of this embodiment can be manufactured by a conventional method for manufacturing a capacitor, except that the conductor paste shown below is used as a conductor paste for forming the internal electrode pattern. In the production of the capacitor of the present embodiment, when the internal electrode pattern is formed on the surface of the ceramic green sheet as the conductor paste, the solvent contained in the conductor paste is high in a specific thickness region of the ceramic green sheet. A material that generates a sheet attack is used. Taking an example to be described later as an example, when a butyral resin is used as the resin to be included in the ceramic green sheet 21, it is preferable to use a conductive paste containing butyl cellosolve.

FIG. 3 shows a part of the manufacturing process of the capacitor of this embodiment, and is a schematic cross-sectional view showing a state change when a conductor paste is printed on the surface of the ceramic green sheet. As shown in FIG. 3, when manufacturing the capacitor of the present embodiment, a conductive paste is printed on the surface of the ceramic green sheet 21 to form the internal electrode pattern 23, and then a predetermined amount is applied from the surface of the ceramic green sheet 21. An intrusion portion 25 in which a part of the conductor paste intrudes into the depth is formed near the surface of the ceramic green sheet 21. By utilizing this, the metal particle row 13 in which the metal particles 13a are arranged in the dielectric layer 5 can be formed. In this case, the metal particles 13a are derived from the metal powder contained in the internal electrode pattern. The capacitor of this embodiment adjusts the content of the solvent with respect to the metal powder constituting the conductor paste, the combination of the solvent included in the conductor paste, the combination of the resin included in the ceramic green sheet 21 and the solvent included in the conductor paste, and the like. Can be obtained. Depending on the combination of solvents contained in the conductor paste or the content of the solvent, the ceramic green sheet 21 may be excessively dissolved and the shape of the ceramic green sheet 21 may be maintained. Since the ceramic green sheet 21 is difficult to dissolve, the intrusion portion 15 may not be formed in the ceramic green sheet 21. The metal particles 13a are in a state where the metal powder is heated as it is alone, together with sintered particles obtained by sintering two or more metal powders included in the conductor paste. Hereinafter, the embodiment will be described in detail.

Hereinafter, the capacitor was specifically produced and the characteristics were evaluated. First, as raw material powder for preparing dielectric powder, barium titanate powder (BaTiO ₃ ), magnesium carbonate powder (Mg ₂ CO ₃ ), dysprosium oxide powder (Dy ₂ O ₃ ), manganese carbonate powder (MnCO) ₃ ) and glass powder (SiO ₂ = 55, BaO = 20, CaO = 15, Li ₂ O ₃ = 10 (mol%)) and were prepared. The dielectric powder is 0.8 mol of magnesium oxide powder (MgO) in terms of MgO, 0.8 mol of dysprosium oxide powder (Dy ₂ O ₃ ), and MnCO ₃ powder with respect to 100 mol of barium titanate powder. Was added in an amount of 0.3 mol in terms of MnO, and 1 part by mass of a glass component (SiO ₂ —BaO—CaO-based glass powder) was added to 100 parts by mass of the barium titanate powder.

  A ceramic green sheet was prepared by a doctor blade method using a slurry prepared by mixing an organic vehicle with the above-described dielectric powder. A butyral resin was used as the resin to be included in the organic vehicle when preparing the ceramic green sheet. The amount of butyral resin added was 10 parts by mass with respect to 100 parts by mass of the dielectric powder. As the solvent, a solvent in which ethyl alcohol and toluene were mixed at a ratio of 1: 1 was used.

  Nickel powder was used as the metal for the conductor paste for forming the internal electrode pattern. Ethyl cellulose was used as the resin for preparing the conductor paste. The amount of ethyl cellulose added was 5 parts by mass with respect to 100 parts by mass of nickel powder. As the solvent, a dihydroterpineol solvent and butyl cellosolve were mixed and used. Table 1 shows the ratio (parts by mass) of the dihydroterpineol solvent and butyl cellosolve.

  Next, a conductive paste was printed on the produced ceramic green sheet to produce a pattern sheet. Table 1 shows the position of the pattern sheet having the intrusion portion derived from the conductor paste. In the table, the middle region refers to an intrusion portion in the middle region (90 layers) in the stacking direction when the 270 dielectric layers of the capacitor section are equally divided into the upper region, the middle region, and the lower region in the stacking direction. A pattern sheet having the above is applied. Sample No. is included in the pattern sheet having no intrusion portion. The pattern sheet used for sample preparation 1 was used.

  Next, 270 layers of the produced pattern sheets were laminated to produce a core laminate. Next, the ceramic green sheets were respectively stacked on the upper surface side and the lower surface side of the core laminated body to produce a mother laminated body. Thereafter, the base laminate was cut to produce a capacitor body molded body.

  Next, the capacitor body was produced by firing the produced body of the capacitor body. The main baking was carried out in hydrogen-nitrogen under the conditions that the temperature rising rate was 900 ° C./h and the maximum temperature was set to 1080 ° C. A roller hearth kiln was used for this baking.

  Next, reoxidation treatment was performed on the manufactured capacitor body. The conditions for the reoxidation treatment were set to a maximum temperature of 1000 ° C. and a holding time of 5 hours in a nitrogen atmosphere.

The size of the obtained capacitor body was 3.2 mm × 1.6 mm × 1.6 mm, and the average thickness of the dielectric layer was 2.8 μm. The average thickness of the internal electrode layer was 0.8 μm. The design value of the capacitance of the produced capacitor was set to 10 μF.

  Next, after barrel-polishing the capacitor body, an external electrode paste was applied to both ends of the capacitor body and baked at a temperature of 800 ° C. to form external electrodes. The external electrode paste used was added with Cu powder and glass. Thereafter, using an electrolytic barrel machine, Ni plating and Sn plating were sequentially formed on the surface of the external electrode to obtain a capacitor.

Next, the following evaluation was performed on the fabricated capacitor. First, the capacitor was mirror-polished to expose a cross section as shown in FIG. 1B, and the state of the metal particle rows present in the dielectric layer was observed. Table 1 shows each value. Each value shown in Table 1 is an average value of values measured by observing three ranges of 20 μm × 20 μm in the central portion in the stacking direction of the cross section of the capacitor body and the central portion in the longitudinal direction (L-shaped cross section). The particle size D of the metal particles was obtained by extracting a metal particle array with a length of 50 μm from the cross section of the capacitor body, measuring the maximum diameter of each metal particle contained in the metal particle array, and obtaining an average value. . The metal particle array 13 in which the particle diameter D of the metal particles was measured was also used for the distance W ₁ between the metal particle array and the surface of the dielectric layer, the interval W ₂ between the metal particles 13a, and W ₂ / D. When measuring the entire cross section of the capacitor body, the same area (20 μm × 20 μm) is extracted from each region obtained by dividing the cross section of the capacitor body into three equal parts, and measured using the same method as above. did.

  Among the produced capacitors, metal particle arrays are formed in any dielectric layer produced using a pattern sheet prepared so that the intrusion portion derived from the conductive paste is formed near the surface of the ceramic green sheet. It was. Moreover, the metal particle row was present on the non-capacity part side as well as the capacity part side.

  Next, with respect to the dielectric characteristics, the capacitance was measured under the condition that no DC voltage was applied (AC voltage 0.5 V, frequency 1 kHz). The number of samples was 30 and the average value was obtained.

  The withstand voltage was measured at a boosting speed of 5 V / sec (boost 1). The number of samples was 30 and the average value was obtained.

  The thermal shock test was performed under the condition that the capacitor was immersed for 1 second using a solder bath whose temperature was set to 305 ° C. (ΔT = 280 ° C.). The sample after the test was observed using a stereomicroscope to evaluate the presence or absence of cracks. The number of samples was 100. The number ratio of cracks is shown in Table 1.

  As is clear from Table 1, the samples (sample Nos. 2 to 6) in which the metal particle rows are present in the dielectric layer have a capacitance of 10.2 to 12 when the withstand voltage is 368 to 375 V. 3 μF. Further, these samples had a defective rate of 1/100 or less in the thermal shock test.

  Among these samples, sample No. 3 to 6 had a capacitance of 11.8 to 12.3 μF when the withstand voltage was 368 to 370 V. Further, no defect was found in the thermal shock test.

  In contrast, the sample (sample No. 1) having no metal particle array in the dielectric layer had a withstand voltage of 380 V, but had a capacitance of 9.8 μF.

1... Capacitor body 3... External electrode 5... Dielectric layer 7.・ Internal electrode layer 9... Capacitance part 11... Non-capacitance part 13. .... Metal particles 21 ..... Ceramic green sheet 23 ..... Internal electrode pattern 25 ..... Intrusion part

Claims (6)

  A capacitor comprising a capacitor body in which a plurality of dielectric layers and internal electrode layers are alternately laminated, wherein the dielectric layer includes a plurality of metal particles, and the plurality of metal particles are the dielectric material. A capacitor having a row of metal particles forming a row along the surface at a position away from the surface of the layer.   The capacitor according to claim 1, wherein the metal particles have a particle size of 0.2 μm or more and 0.4 μm or less. 3. The capacitor according to claim 1, wherein the metal particle array has a distance W ₁ to the surface of the dielectric layer of 0.4 μm or more. 4. The metal particle array according to claim 1, wherein a ratio (W ₂ / D) between the metal particle diameter D and a distance W ₂ between adjacent metal particles is 0.5 or more and 2 or less. Capacitor according to the above.   The capacitor body 1 is composed of the dielectric layer and the internal electrode layer, and has a capacitance portion that expresses capacitance, and a non-capacitance portion that is arranged so as to surround the capacitance portion and does not express capacitance. 5. The capacitor according to claim 1, wherein the metal particle row is also present in the dielectric layer constituting the non-capacitance portion.   The capacitor according to claim 1, wherein the metal particle row is present in all the dielectric layers sandwiched between the internal electrode layers.

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