JP2018196455A - Game machine - Google Patents

Abstract

To provide a game machine having a plurality of lottery states on an advantageous state capable of improving an interest in the game.SOLUTION: There is a case in which a state is controlled to a favored state (e.g., specific mode), in which shift control of a plurality of lottery states (e.g., ordinary mode) on an advantageous state (e.g., ART state) advantageous for a player is favored. In the favored state, the shift control of the lottery states is not only favored, but also whether or not an advantageous state is granted is determined based on a present lottery state as in a non-favored state (e.g., non-specific mode). In the favored state, there is a case where the lottery state becomes more advantageous, but there is no case where the lottery state becomes more disadvantageous.SELECTED DRAWING: Figure 32

Description

  The present invention relates to a gaming machine.

  Conventionally, a game called pachi-slot, comprising a plurality of reels each having a plurality of symbols provided on the surface, a start switch, a stop switch, a stepping motor provided for each reel, and a control unit. The machine is known. The start switch detects that the start lever has been operated by the player (hereinafter also referred to as “start operation”) after a game medium such as a medal or coin has been inserted into the gaming machine, and the rotation of all reels is detected. Outputs a signal requesting start. The stop switch detects that a stop button provided for each reel has been pressed by the player (hereinafter also referred to as “stop operation”), and outputs a signal requesting the rotation of the corresponding reel to stop. To do. The stepping motor transmits the driving force to the corresponding reel. Further, the control unit controls the operation of the stepping motor based on the signals output from the start switch and the stop switch, and performs the rotation operation and stop operation of each reel.

  In such a gaming machine, when a start operation is detected, lottery processing using random numbers (hereinafter referred to as “internal lottery processing”) is performed on the program, and the result of the lottery (hereinafter referred to as “internal winning combination”). And the rotation of the reel is stopped based on the timing of the stop operation. Then, when the rotation of all the reels is stopped and a symbol combination (display combination) related to the winning of the winning is displayed, a privilege corresponding to the symbol combination is given to the player. As an example of a privilege granted to a player, a replay (hereinafter also referred to as “replay”) in which an internal lottery process is performed again without paying out game media (medals, etc.) or consuming the game media. An operation of a special game state (bonus game) in which a game medium payout opportunity increases can be cited.

  Also, in such a gaming machine, a function for navigating establishment of a predetermined combination (for example, a predetermined small combination which is a combination related to payout of game media) with a ramp, that is, an assist time (hereinafter referred to as “AT”). ). In addition, in such a gaming machine, when a specific operating condition is satisfied, a gaming state having a higher replay winning probability than normal is activated, that is, a replay time (hereinafter referred to as “RT”) function. There is also. In addition, there is also an assist replay time (hereinafter referred to as “ART”) function in which AT and RT operate simultaneously.

  In recent years, such gaming machines have been known that have a plurality of modes with different transition probabilities of advantageous states (for example, bonus games) advantageous to the player (see, for example, Patent Document 1).

JP 2005-287880 A

  However, it is considered that there is room for further improvement in the playability using such a plurality of modes (lottery states).

  The present invention was made based on such a background, and it is an object of the present invention to provide a gaming machine having a plurality of lottery states related to an advantageous state and capable of improving the fun of the game. To do.

  To achieve the above object, according to the gaming machine of the present embodiment, the gaming machine of the following invention can be provided.

The gaming machine of the present invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A lottery state control having a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition Means (for example, main CPU 101);
A preferential state in which the lottery state transition control by the lottery state control means is preferential (for example, a specific mode) and a non-preferential state that is not the preferential state (for example, a non-specific mode), and a specific transition condition Preferential state control means (for example, the main CPU 101) capable of transition control between the preferential state and the non-preferential state based on
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means And determining means (for example, the main CPU 101).

  In the gaming machine having the above-described configuration, it is controlled to a preferential state (for example, a specific mode) in which transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

In addition, the gaming machine of the present invention,
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A lottery state control having a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition Means (for example, main CPU 101);
A preferential state in which the lottery state transition control by the lottery state control means is preferential (for example, a specific mode) and a non-preferential state that is not the preferential state (for example, a non-specific mode), and a specific transition condition Preferential state control means (for example, the main CPU 101) capable of transition control between the preferential state and the non-preferential state based on
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means Determining means (for example, main CPU 101),
The advantageous state provision determining means includes:
When the lottery state transferred by the lottery state control means is the lower lottery state (for example, the normal mode “0” to “2”), the specific combination (for example, “F_RB”) is used as the internal winning combination. It is possible to decide to give said advantageous state if it is decided;
When the lottery state transferred by the lottery state control means is the upper lottery state (for example, the normal mode “3” and “4”), when the other than the specific combination is determined as the internal winning combination Can be characterized in that it can be determined to give the advantageous state.

  In the gaming machine having the above-described configuration, it is controlled to a preferential state (for example, a specific mode) in which transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. In the lower lottery state (for example, the normal mode “0” to “2”), the advantageous state is not given unless the specific combination (for example, “F_RB”) is won, but the upper lottery state (for example, the normal mode “ 3 ”and“ 4 ”) are configured such that an advantageous state may be given without winning the specific combination. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

In addition, the gaming machine of the present invention,
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A lottery state control having a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition Means (for example, main CPU 101);
A preferential state in which the lottery state transition control by the lottery state control means is preferential (for example, a specific mode) and a non-preferential state that is not the preferential state (for example, a non-specific mode), and a specific transition condition Preferential state control means (for example, the main CPU 101) capable of transition control between the preferential state and the non-preferential state based on
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means Determining means (for example, main CPU 101),
The lottery state control means includes
In the non-preferential state, it is possible to determine that the lottery state is shifted to the more advantageous lottery state, and it is also possible to determine that the lottery state is shifted to the more disadvantageous lottery state,
In the preferential state, it is possible to determine to shift the lottery state to the more advantageous lottery state, and it is not possible to determine to shift the lottery state to the more unfavorable lottery state. be able to.

  In the gaming machine having the above-described configuration, it is controlled to a preferential state (for example, a specific mode) in which transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. In the preferential state, the lottery state may be more advantageous but may not be more disadvantageous. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

In addition, the gaming machine of the present invention,
The preferential state control means is capable of determining whether or not to shift to the preferential state when the lottery state control means does not determine to shift the lottery state in the non-preferential state. can do.

  The gaming machine having the above configuration is configured to determine whether or not to shift to the preferential state when the lottery state shift control is not performed in the non-preferential state. Therefore, even if the lottery state does not shift, it can be suppressed that the interest of the game is lowered.

  According to the gaming machine of the present invention configured as described above, in the gaming machine having a plurality of lottery states relating to the advantageous state, the interest of the game can be improved.

It is a figure for demonstrating the function flow of the game machine in one Embodiment of this invention. It is a perspective view which shows the external appearance structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows the internal structure of the game machine in one Embodiment of this invention. It is a figure which shows schematic structure of the various display screens displayed on the sub display apparatus of one Embodiment of this invention. It is a figure which shows the example of a transition of the display screen of the sub display apparatus in one Embodiment of this invention. It is a block diagram which shows the whole circuit structure with which the game machine of one Embodiment of this invention is provided. It is a block diagram which shows the internal structure of the main control circuit in one Embodiment of this invention. It is a block diagram which shows the internal structure of the microprocessor in one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub control circuit in one Embodiment of this invention. It is a block diagram of the various registers | resistors which the main CPU in one Embodiment of this invention has. It is a figure which shows the memory map of the main control circuit in one Embodiment of this invention. It is a figure which shows the transition flow of the game state of a pachislot in one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement | positioning table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the internal lottery table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows an example of the symbol combination table in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination, stop operation order (batting order), display combination etc. in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination, stop operation order (batting order), display combination etc. in one Embodiment of this invention. It is a figure which shows the correspondence of the internal winning combination, stop operation order (batting order), display combination etc. in one Embodiment of this invention. It is a figure which shows the structure of the winning request flag storage area | region and winning operation flag storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the carryover combination storage area in one Embodiment of this invention. It is a figure which shows the structure of the game state flag storage area in one Embodiment of this invention. It is a figure which shows the structure of the operation | movement stop button storage area in one Embodiment of this invention. It is a figure which shows the structure of the pressing order storage area | region in one Embodiment of this invention. It is a figure which shows the structure of the symbol code storage area in one Embodiment of this invention. It is a figure explaining the flow of the game of the whole pachislot in one Embodiment of this invention. It is a figure explaining the flow of the game of the normal state of a pachislot in one embodiment of the present invention. It is a figure which shows an example of the lottery table used in the normal state in one Embodiment of this invention. It is a figure which shows an example of the lottery table used in the normal state in one Embodiment of this invention. It is a figure which shows an example of the lottery table used in the normal state in one Embodiment of this invention. It is a figure which shows an example of the lottery table used in the normal state in one Embodiment of this invention. It is a figure explaining the flow of the game of a pachislot sign state in one embodiment of the present invention. It is a figure which shows an example of the lottery table used in the precursor state in one Embodiment of this invention. It is a figure explaining the flow of the game of the RUSH preparation state of the pachislot in one Embodiment of this invention. It is a figure which shows an example of the lottery table used in the RUSH preparation state in one Embodiment of this invention. It is a figure which shows an example of the effect display in the RUSH preparation state in one Embodiment of this invention. It is a figure explaining the flow of the game of the normal RUSH state of the pachislot in one Embodiment of this invention. It is a figure explaining the flow of the game of the special RUSH state of a pachislot in one embodiment of the present invention. It is a figure which shows an example of the effect display in the RUSH state in one Embodiment of this invention. It is a figure explaining the flow of the game of an ART state of a pachislot in one embodiment of the present invention. It is a figure which shows an example of the lottery table used in ART state in one Embodiment of this invention. It is a figure which shows an example of the effect display in ART state in one Embodiment of this invention. It is a figure explaining the flow of the game of the battle state of a pachislot in one embodiment of the present invention. It is a figure which shows an example of the lottery table used in the battle state in one Embodiment of this invention. It is a figure which shows an example of the lottery table used in the battle state in one Embodiment of this invention. It is a figure which shows an example of the lottery table used in the battle state in one Embodiment of this invention. It is a figure which shows an example of the effect display in the battle state in one Embodiment of this invention. It is a figure which shows an example of the effect display in the battle state in one Embodiment of this invention. It is a figure explaining the flow of the game of the pulling back state of a pachislot in one embodiment of the present invention. It is a figure which shows an example of the lottery table used in the drawing-back state in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of power-on (reset interruption) performed by the main control circuit of the gaming machine in one embodiment of the present invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the process at the time of power-on in one Embodiment of this invention. It is a flowchart which shows the example of the game return process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the game return process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change confirmation process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the setting change confirmation process in one Embodiment of this invention. It is a flowchart which shows the example of the setting change command production | generation storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the setting change command production | generation storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the communication data storage process in one Embodiment of this invention. It is a flowchart which shows the example of the communication data pointer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the communication data pointer update process in one Embodiment of this invention. It is a flowchart which shows the example of the process at the time of a power failure (external) in one Embodiment of this invention. It is a flowchart which shows the example of the checksum production | generation process (non-regulation) in one Embodiment of this invention. An example of a source program for executing various processes in the flowchart of the checksum generation process according to an embodiment of the present invention, and an operation of updating a stack pointer and an operation of reading data from a register executed in the checksum generation process FIG. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a flowchart which shows the example of the sum check process (unregulated) in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the sum check process in one Embodiment of this invention. It is a flowchart which shows the example of the main process (main operation process) performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of the medal acceptance / start check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of a medal reception and start check process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal insertion process in one Embodiment of this invention. It is a flowchart which shows the example of the medal insertion check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal insertion check process in one Embodiment of this invention. It is a flowchart which shows the example of the error process in one Embodiment of this invention. It is a figure which shows an example of a structure of the error table actually referred on the source program of the error processing in one Embodiment of this invention. It is a flowchart which shows the example of the random number acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the internal lottery process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the internal lottery process in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board control process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the 2nd interface board output process in one Embodiment of this invention. It is a flowchart which shows the example of the attraction | saving priority order storage process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the drawing priority order storage process in one Embodiment of this invention. It is a flowchart which shows the example of the symbol code acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the symbol code acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the AND operation process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the drawing priority order acquisition process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the drawing priority order acquisition process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop control process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the reel stop control process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the reel stop control process in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal OFF process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the reel stop possible signal ON process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the non-regulation port output process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the non-regulated port output process in one Embodiment of this invention. It is a flowchart which shows the example of the winning search process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the winning search process in one Embodiment of this invention. It is a flowchart which shows the example of the illegal hit check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the illegal hit check process in one Embodiment of this invention. It is a flowchart which shows the example of a prize check and medal payout process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of a prize check and medal payout process in one Embodiment of this invention. It is a flowchart which shows the example of the medal payout number check process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the medal payout number check process in one Embodiment of this invention. It is a flowchart which shows the example of the bonus check process in one Embodiment of this invention. It is a flowchart which shows the example of the RT check process in one Embodiment of this invention. It is a flowchart which shows the example of the interruption process performed by the main control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment LED drive processing in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the 7 segment LED drive process in one Embodiment of this invention. It is a flowchart which shows the example of 7 segment display data generation processing in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of 7 segment display data generation process in one Embodiment of this invention. It is a figure which shows an example of a structure of the 7 segment cathode table actually referred on the source program of the 7 segment display data generation process in one Embodiment of this invention. It is a flowchart which shows the example of the timer update process in one Embodiment of this invention. It is a figure which shows an example of the source program for performing the various processes in the flowchart of the timer update process in one Embodiment of this invention. It is a flowchart which shows the example of the trial test signal control process (non-regulation) in one Embodiment of this invention. It is a flowchart which shows the example of the rotation brake signal generation process in one Embodiment of this invention. It is a flowchart which shows the example of the special prize signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the condition apparatus signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the condition apparatus signal control process in one Embodiment of this invention. It is a flowchart which shows the example of the power-on process of the sub CPU performed by the sub control circuit of the gaming machine in one embodiment of the present invention. It is a flowchart which shows the example of the interruption interruption process of the sub CPU performed by the sub control circuit of the game machine in one Embodiment of this invention. It is a flowchart which shows the example of a process of the main board | substrate communication task in one Embodiment of this invention. It is a flowchart which shows the example of the sub side navigation control process in one Embodiment of this invention. It is a flowchart which shows the example of the player registration process in one Embodiment of this invention. It is a flowchart which shows the example of the log | history management process in one Embodiment of this invention. It is a flowchart which shows the example of the presentation control process in one Embodiment of this invention.

  Hereinafter, a pachislot machine is taken as an example of a gaming machine according to an embodiment of the present invention, and the configuration and operation thereof will be described with reference to the drawings. In the present embodiment, a pachislot machine having a bonus operation function and an ART function will be described.

<Function flow>
First, the functional flow of the pachislot will be described with reference to FIG. In the pachislot machine of this embodiment, medals are used as game media for playing games. In addition to medals, for example, coins, game balls, game point data, tokens, or the like can be applied as game media. In addition, the game medium may be referred to as “game value” or “game value”.

  When a player inserts a medal into the pachislot and operates the start lever, one value (hereinafter referred to as a random value) is extracted from random numbers in a predetermined numerical range (for example, 0 to 65535).

  The internal lottery means performs lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is one of various processing means (processing functions) provided in a main control circuit described later. By determining the internal winning combination, a combination of symbols that permits (display is permitted) to display along an after-mentioned effective line (winning determination line) is determined. The types of symbol combinations include those related to “winning” in which benefits such as payout of medals, replay (replay) operation, bonus operation, etc. are given to the player, and so-called “out of” other than that. Such a thing is provided. In the following, a combination relating to the payout of medals is referred to as a “small combination”, and a combination relating to replay (replay) operation is referred to as a “replay combination”. Further, a combination related to the operation of the bonus (bonus game) is referred to as a “bonus combination”. In addition, a role that can be won internally (that is, a combination of symbols permitted to be established) may be simply referred to as a “role”, and the internal winning combination may be “winning role”, “predetermined result”, or Sometimes referred to as “derivative allowance”. Further, the internal lottery means may be referred to as “combination determining means”, “winning combination determining means”, “preliminary determining means”, or “derivative allowance condition determining means”.

  Further, when the start lever is operated, a plurality of reels are rotated. Thereafter, when the player presses the stop button corresponding to the predetermined reel, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing when the stop button is pressed. Do. The reel stop control means is one of various processing means (processing functions) provided in a main control circuit described later. Note that the operation means for performing the start operation is not limited to a lever shape like a start lever, and any operation means may be used as long as the player can perform the start operation. . The operation means for performing the stop operation is not limited to a button shape like a stop button, and any operation means may be used as long as the player can perform the stop operation. .

  In the pachislot, basically, a control for stopping the rotation of the corresponding reel is performed within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. In this embodiment, when the specified time is 190 msec, the maximum number of sliding symbols (maximum number of sliding symbols) is set to 4 symbols, and when the specified time is 75 msec, the maximum sliding symbols are set. Set the number to one symbol. The specified time is normally 190 msec, and the maximum number of sliding symbols is 4 symbols for each reel. However, during operation of a specific bonus (middle bonus: referred to as MB), the specified reel is specified. The time is 75 msec, and the maximum number of sliding symbols is one symbol.

  The reel stop control means, when an internal winning combination permitting display of a symbol combination related to winning is determined, normally, the symbol combination is an effective line within a specified time of 190 msec (four symbols). The rotation of the reel is stopped so as to display as much as possible. In addition, the reel stop control means stops the rotation of the reel using a specified time so that the combination of symbols that are not permitted to be displayed by the internal winning combination is not displayed along the active line. The symbol displayed when the rotation of the reel is stopped may be referred to as “stop display” or “display result”. In addition, displaying the symbol on the effective line when the reel rotation stops may be expressed as “derivation of stop display” or “derivation of display result”.

  In addition, the reel stop control means automatically stops each reel when a predetermined automatic stop time has elapsed after the reel rotates, even if the player has not performed a stop operation. Stop control may be performed. In this case, since the reels are stopped without the player's stop operation, even if any internal winning combination is determined, any combination of symbols related to winning is also valid. It is desirable to stop the rotation of the reels so that they are not displayed along the line.

  In this way, when all the rotations of the plurality of reels are stopped, the winning determination means determines that the combination of symbols displayed along the active line is related to winning (or other predetermined one). It is determined whether or not there is. That is, it is determined whether or not a combination of symbols related to winning (or other predetermined symbol combinations) has been established. This winning determination means is also one of various processing means (processing functions) provided in the main control circuit described later. The displayed symbol combinations are those related to winning by the winning determination means (or other predetermined symbols) (that is, combinations of symbols related to winning (or other predetermined symbol combinations). ) Has been established), the player is given a privilege such as a medal payout, or various controls are triggered by this. In the pachislot, a series of flows as described above is performed as one game (unit game).

  The winning determination means determines whether the symbol combination displayed along the active line corresponds to any one of a plurality of symbol combinations determined in advance. It may be determined whether it corresponds to the combination of symbols related to the internal winning combination determined by the internal lottery means. In other words, in the former case, it may be determined whether or not the winning combination is a combination of symbols related to winning. In this case, as long as the stop control is appropriately performed by the reel stop control means, it is possible to sufficiently prevent the occurrence of the erroneous winning a prize, and therefore it becomes possible to reduce the control burden related to the erroneous winning detection. On the other hand, in the latter case, it is possible to determine whether or not the combination of symbols related to winning is a combination of symbols for which winning has been permitted. Therefore, security can be improved.

  Also, in the pachislot, in the series of gaming operations described above, various effects can be achieved by displaying images on a display device, outputting light from various lamps, outputting sound from a speaker, or a combination thereof. Is done.

  Specifically, when the start lever is operated, a random number value for presentation is extracted separately from the random number value used for determining the internal winning combination described above. When the effect random number is extracted, the effect content determination means determines the effect to be executed this time from lots of effect contents associated with the internal winning combination by lottery. This effect content determination means is one of various processing means (processing functions) provided in a sub-control circuit described later. In addition, when the main control circuit described later determines the contents of the effect, the effect content determining means can be one of various processing means (processing functions) included in the main control circuit described later.

  Next, when the content of the effect is determined by the effect content determination means, the effect execution means responds in conjunction with each opportunity such as when the rotation of the reel starts, when the rotation of each reel stops, or when the presence or absence of a prize is determined. Execute. In this way, in the pachislot, for example, by executing the production contents associated with the internal winning combination, there is an opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to be aimed at) It is provided to the player and the player's interest can be improved.

<Pachislot structure>
Next, the structure of a pachislot machine according to an embodiment of the present invention will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachi-slot 1.

  As shown in FIG. 2, the pachislot 1 includes an exterior body (game machine main body) 2. The exterior body 2 includes a cabinet 2a that houses a reel, a circuit board, and the like, and a front door 2b that is attached so that the opening of the cabinet 2a can be opened and closed.

  Inside the cabinet 2a, three reels 3L, 3C, 3R (variable display means, display columns) are provided in a horizontal row. Hereinafter, the reels 3L, 3C, and 3R (main reels) are also referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each reel 3L, 3C, 3R has a reel body formed in a cylindrical shape and a translucent sheet material mounted on the peripheral surface of the reel body. A plurality of (for example, 20) symbols are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction (reel rotation direction). Each of the reels 3L, 3C, 3R may be expressed as “design display means”, “variable display means”, “variable display”, or the like. In addition, the symbol display area 4 described later may be included as these components. Further, the “symbol” may be information that can be identified by the player by visual recognition, and may be expressed as “identification information” in that sense.

  The front door 2 b includes a door body 9, a front panel 10, a waist panel 12, and a pedestal portion 13. The door body 9 is attached to the cabinet 2a so as to be openable and closable using a hinge (not shown). The hinge is provided at the left side end of the door body 9 when viewed from the front side (player side) of the pachi-slot 1. The cabinet 2a can be simply referred to as a “box”, and the front door 2b can be simply referred to as a “door” or a “front door”. Further, since the cabinet 2a functions as a frame that supports or fixes the front door 2b, it may be expressed as "support", "support frame", or "fixed frame". Further, the front door 2b may be constituted by a plurality of door members. For example, it may be constituted by an upper door member attached to the upper side of the opening of the cabinet 2a and a lower door member attached to the lower side of the opening of the cabinet 2a, as viewed from the front side of the gaming machine. The inner door member attached to the opening side of the cabinet 2a and the outer door member attached to the front side of the gaming machine may be used.

  The front panel 10 is provided on the upper portion of the door body 9. The front panel 10 is constituted by a frame-like member having an opening 10a. The opening 10a of the front panel 10 is closed by the display device cover 30, and the display device cover 30 is disposed to face a display device 11 described later disposed inside the cabinet 2a.

  The display device cover 30 is formed of a black translucent synthetic resin. Therefore, the player can visually recognize the video (image) displayed on the display device 11 described later via the display device cover 30. In the present embodiment, the display device cover 30 is formed of a black translucent synthetic resin, thereby suppressing the entry of external light into the cabinet 2a and the image (image) displayed by the display device 11. Is clearly visible.

  A lamp group 21 is provided on the front panel 10. The lamp group 21 includes, for example, lamps 21 a and 21 b provided on the upper portion of the front panel 10 when viewed from the player side. Each lamp constituting the lamp group 21 is configured by an LED (Light Emitting Diode) or the like (refer to an LED group 85 in FIG. 7 described later), and turns on and off the light in a pattern corresponding to the contents of effects.

  The waist panel 12 is provided at a substantially central portion of the door body 9. The waist panel 12 includes a decorative panel on which an arbitrary image is drawn, and a light source (LED included in an LED group 85 described later) that emits light for illuminating the decorative panel from the back side.

  The pedestal portion 13 is provided between the front panel 10 and the waist panel 12. The pedestal 13 includes a symbol display area 4 and various devices (medal slot 14, MAX bet button 15a, 1 bet button 15b, start lever 16, three stop buttons 17L, 17C, and the like to be operated by the player. 17R, a settlement button (not shown), and the like.

  The symbol display area 4 is an area that overlaps with the three reels 3L, 3C, and 3R when viewed from the front, and is arranged at a position closer to the player than the three reels 3L, 3C, and 3R. 3L, 3C, 3R has a size that enables visual recognition. The symbol display area 4 functions as a display window, and is configured so that each reel 3L, 3C, 3R provided behind the display window 4 can be visually recognized. Hereinafter, the symbol display area 4 is referred to as a reel display window 4.

  When the rotation of the three reels 3L, 3C, 3R provided behind the reel display window 4 is stopped, the reel display window 4 is continuously arranged among a plurality of symbols provided on the peripheral surface of each reel. Two symbols are displayed in the frame. That is, when the rotation of the three reels 3L, 3C, 3R is stopped, one symbol (three in total) is placed in each of the upper, middle, and lower regions for each reel within the frame of the reel display window 4. ) Is displayed (in the frame of the reel display window 4, symbols are displayed in the form of 3 rows × 3 columns). In this embodiment, a line (cross-down line) connecting the upper area of the left reel 3L, the middle area of the middle reel 3C, and the lower area of the right reel 3R within the frame of the reel display window 4 is a winning combination. It is defined as an active line for determining whether or not.

  In the present embodiment, other lines, for example, a line (top line) connecting the upper region of the left reel 3L, the upper region of the middle reel 3C, and the upper region of the right reel 3R, the middle region of the left reel 3L, A line (bottom line) connecting the middle region of the middle reel 3C and the middle region of the right reel 3R (center line), a lower region of the left reel 3L, a lower region of the middle reel 3C, and a line connecting the lower region of the right reel 3R (bottom line) Line) and a line (cross-up line) connecting the lower stage area of the left reel 3L, the middle stage area of the middle reel 3C, and the upper stage area of the right reel 3R (cross-up line). Good. Moreover, you may define a some line as an effective line among these lines including the said cross down line.

  The reel display window 4 is formed by an opening of a frame member 31 provided on the pedestal portion 13. A substantially horizontal plane base region is provided below the frame member 31 that defines the reel display window 4. When viewed from the player side, a medal slot 14 is provided on the right side of the pedestal area, and a MAX bet button 15a and a 1 bet button 15b are provided on the left side.

  The medal slot 14 is provided to accept a medal dropped on the pachislot 1 from the outside by the player. The medals accepted from the medal slot 14 are used for one game up to a predetermined number (for example, three) set in advance, and the number of medals exceeding the predetermined number are deposited inside the pachislot 1. (So-called credit function (game medium storage means)).

  The MAX bet button 15a and the 1 bet button 15b are provided for determining the number of coins used for one game from medals deposited in the cabinet 2a. Note that a bet button LED (not shown) that is lit when a medal can be inserted is provided inside the MAX bet button 15a. The checkout button is provided to draw out (discharge) medals deposited inside the pachislot machine 1 to the outside.

  When the player depresses the MAX bet button 15a, medals corresponding to the number of bets (3) in the unit game are inserted and the effective line is activated. On the other hand, each time the 1-bet button 15b is pressed, one medal is inserted. When the 1-bet button 15b is operated three times, medals for the number of bets (3) in the unit game are inserted and the active line is activated.

  Hereinafter, the operation of the MAX bet button 15a, the operation of the 1 bet button 15b, and the operation of inserting a medal into the medal insertion slot 14 (operation of inserting a medal for playing a game) are all referred to as “insertion operation”.

  The start lever 16 is provided to start rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, and 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are also referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  In addition, an information display 6 is provided in the approximate center of the pedestal region on a substantially horizontal plane below the reel display window 4. The information display 6 is covered with a transparent window cover (not shown).

  The information display 6 has a 2-digit 7-segment LED for digitally displaying (notifying) information on the number of medals to be paid out to the player as a privilege (hereinafter referred to as “paid-out number”). (Hereinafter referred to as “7-segment LED”) and information such as the number of medals deposited inside the pachislot machine 1 (hereinafter referred to as “credit number”) for digital display (notification) to the player A 2-digit 7-segment LED is provided. In this embodiment, the 2-digit 7-segment LED for displaying the number of paid-out medals is a 2-digit 7-segment LED for digitally displaying (notifying) information about the occurrence of an error and the error type to the player. Is also used. Therefore, when an error occurs, the display mode of the 2-digit 7-segment LED for displaying the number of paid-out medals is switched from the display mode of the paid-out number to the display mode of the error type information.

  Further, the information display 6 is provided with an instruction monitor (not shown) for notifying information on a stop operation necessary for displaying a symbol combination corresponding to the combination determined as the internal winning combination along the effective line. ing. The instruction monitor (instruction display) is composed of, for example, a two-digit 7-segment LED. The instruction monitor informs the player of necessary stop operation information by turning on, blinking, or turning off the 2-digit 7-segment LED in a manner that uniquely corresponds to the stop operation information to be notified. To do.

  Note that the aspect uniquely corresponding to the information of the stop operation to be notified here is, for example, in the case of informing the pressing order “1st (perform the first stop operation on the left reel 3L)”. When the numerical value “1” is displayed on the instruction monitor and the push order “2nd (perform the first stop operation on the middle reel 3C)” is notified, the numerical value “2” is displayed on the instruction monitor and the push order In a case where “3rd (perform the first stop operation on the right reel 3R)” is notified, a numerical value “3” is displayed on the instruction monitor. In addition, the notification mode (navigation data determined on the main side described later) of the stop operation information on the instruction monitor will be described in detail later with reference to FIGS. 22 to 24 described later.

  As shown in FIG. 7 to be described later, the information display 6 is electrically connected to the main control board 71 via a door relay terminal board 68 and a game operation display board 81. Control is performed by a later-described main control circuit 90 in the control board 71. Moreover, the control method of the various 7-segment LEDs described above is dynamic lighting control.

  In the pachislot machine 1 of this embodiment, in addition to the instruction monitor controlled by the main control board 71, a configuration for notifying the stop operation information using other means controlled by the sub control board 72 is provided. Specifically, information on a stop operation is notified by a display device 11 described later configured by a projector mechanism 211 and a display unit 212 (see FIG. 3 and FIG. 7 described later).

  When such a configuration is applied, the notification mode in the instruction monitor and the notification mode in other means controlled by the sub-control board 72 may be different from each other. That is, the instruction monitor may be notified in a manner that uniquely corresponds to the information on the stop operation to be notified, and does not necessarily need to notify the information on the stop operation directly (for example, the numerical value “1” in the instruction monitor). Even if is displayed, there is a possibility that the notification content cannot be specified depending on the player, which is not a direct notification). On the other hand, in the notification on the sub side (sub control board side) by other means such as the display device 11 described later, information on the stop operation may be directly notified. For example, when the push order “1st” is notified, the instruction monitor displays a numerical value “1” that uniquely corresponds to the push order to be notified, but other means (for example, the display device 11) displays the left reel 3L. The instruction information (navigation data) for performing the first stop operation may be directly notified.

  In the pachislot machine 1 configured as described above, not only the control of the sub-control board 72 but also the control of the main control board 71 can notify information on necessary stop operation according to the internal winning combination. The presence / absence of notification of such stop operation information may be controlled according to the gaming state (control state). For example, the stop operation information may be notified in the later-described ART state (see FIG. 31 described later) without being notified in the normal state (see FIG. 31 described later) described later. .

  Further, a sub display device 18 is provided on the left side of the reel display window 4 when viewed from the player side. As shown in FIG. 2, the sub display device 18 is provided so as to stand substantially vertically from a pedestal region in a substantially horizontal plane of the pedestal portion 13 in the front surface portion of the door body 9. The sub display device 18 includes a liquid crystal display or an organic EL (Electro-Luminescence) display, and displays various types of information.

  A touch sensor 19 is provided on the display surface of the sub display device 18 (see FIG. 7 described later). The touch sensor 19 operates in accordance with a predetermined operation principle such as a capacitance method, and when a player's operation is accepted, outputs a signal corresponding to the operation as touch input information. The pachislot machine 1 according to the present embodiment has a function that allows the display of the sub display device 18 to be switched in accordance with the player's operation received via the touch sensor 19 (touch input information output from the touch sensor 19). Have The sub display device 18 is controlled by a later-described sub control board 72 (see FIG. 7 described later) based on touch input information output from the touch sensor 19.

  In the lower part of the door body 9, a medal payout opening 24, a medal tray 25, two speaker holes 20L, 20R, and the like are provided. The medal payout port 24 guides medals discharged by driving a medal payout device 51 described later to the outside. The medal tray 25 stores medals discharged from the medal payout opening 24. Sounds such as sound effects and music corresponding to the contents of the effects are output from the two speaker holes 20L and 20R.

[Internal structure]
Next, the internal structure of the pachislot machine 1 will be described with reference to FIGS. FIG. 3 is a diagram showing the internal structure of the cabinet 2a, and FIG. 4 is a diagram showing the internal structure of the back side of the front door 2b.

  As shown in FIG. 3, the cabinet 2a includes a top plate 27a, a bottom plate 27b, left and right side plates 27c and 27d, and a back plate 27e. And the display apparatus 11 is arrange | positioned in the upper part in the cabinet 2a.

  The display device 11 includes a projector mechanism 211 and a box-shaped projection member 212a onto which the image light projected from the projector mechanism 211 is projected, and displays an image by projection mapping. Specifically, in the display device 11, image light is generated based on the position (projection distance, angle, etc.) and shape of the projection member 212a that is a three-dimensional object, and the image light is projected by the projector mechanism 211 to the projection member. Projected onto the surface of 212a. By providing such an effect function, an advanced and powerful effect can be performed. Although not shown in FIG. 3, another projected member with a curved display surface is provided on the back side of the box-shaped projected member 212 a, and either one of the projected members is provided depending on the gaming state. Used as a screen on which image light is projected. Therefore, the cabinet 2a is also provided with a function (not shown) for switching the projection target member in accordance with the gaming state.

  A medal payout device (hereinafter referred to as a hopper device) 51, a medal auxiliary storage 52, and a power supply device 53 are disposed in the lower part of the cabinet 2a.

  The hopper device 51 is attached to the central portion of the bottom plate 27b in the cabinet 2a. The hopper device 51 can store a large amount of medals and can discharge them one by one. The hopper device 51 pays out medals when the number of stored medals exceeds 50, for example, or when the settlement button is pressed and settlement of medals is executed. Then, the medals paid out by the hopper device 51 are discharged from the medal payout outlet 24 (see FIG. 2).

  The medal auxiliary storage 52 stores medals overflowing from the hopper device 51. The medal auxiliary storage 52 is disposed on the right side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front. The medal auxiliary storage 52 is detachably attached to the bottom plate 27b of the cabinet 2a.

  The power supply device 53 includes a power switch 53a and a power supply board 53b (power supply means) (see FIG. 7 described later). The power supply device 53 is disposed on the left side of the hopper device 51 when the inside of the cabinet 2a is viewed from the front, and is attached to the left side plate 27c. The power supply device 53 converts the power of the AC voltage 100V supplied from the sub power supply device (not shown) into the power of the DC voltage necessary for each part, and supplies the converted power to each part.

  Further, a sub control board case 57 that houses a sub control board 72 (see FIG. 7 described later) is disposed above the power supply device 53 in the cabinet 2a. A sub control circuit 72 (see FIG. 10 described later), which will be described later, is mounted on the sub control board 72 accommodated in the sub control board case 57. The sub-control circuit 200 is a circuit that controls the execution of effects by displaying images. A specific configuration of the sub control circuit 200 will be described later.

  A sub-relay board 61 is disposed above the sub-control board case 57 in the cabinet 2a. The sub relay board 61 is a relay board on which wiring for connecting the sub control board 72 and a main control board 71 described later is mounted. The sub-relay board 61 is a relay board on which wiring for connecting the sub-control board 72, a board disposed around the sub-control board 72, various devices (units), and the like is mounted.

  Although not shown in FIG. 3, a cabinet-side relay board 44 (see FIG. 7 described later) is disposed in the cabinet 2a. The cabinet-side relay board 44 includes a main control board 71 (see FIG. 7 described later), a hopper device 51, a medal auxiliary storage switch 75 (see FIG. 7 described later), and a medal payout count switch (not shown). Is a relay board on which wiring for connecting is mounted.

  As shown in FIG. 4, a middle door 41 is disposed at the center of the rear side of the front door 2b, and the reel display window 4 (see FIG. 2) is attached so as to be openable and closable from the back side. Although not shown in FIG. 4, three reels 3L, 3C, 3R are attached to the middle door 41 on the reel display window 4 side, and main control is provided on the opposite side of the middle door 41 from the reel display window 4 side. A main control board case 55 in which a board 71 (see FIG. 7 described later) is housed is attached. A stepping motor (not shown) is connected to the three reels 3L, 3C, and 3R through gears having a predetermined reduction ratio.

  The main control board 71 accommodated in the main control board case 55 has a main control circuit 90 (see FIG. 9 described later) described later. The main control circuit 90 (main control means) is a circuit that controls the main flow of the game in the pachislot 1 such as determination of an internal winning combination, rotation and stop of each of the reels 3L, 3C, 3R, and determination of the presence or absence of winning. . In the present embodiment, the main control circuit 90 also performs control such as lottery processing for determining whether ART is determined, processing for displaying navigation information on an instruction monitor, and processing for transmitting various test signals. The specific configuration of the main control circuit 90 will be described later.

  Speakers 65L and 65R are disposed below the middle door 41 on the back side of the front door 2b. The speakers 65L and 65R are disposed at positions facing the speaker holes 20L and 20R (see FIG. 2), respectively.

  A selector 66 and a door open / close monitoring switch 67 are disposed above the speaker 65L. The selector 66 is a device for selecting whether or not the medal material and shape are appropriate, and guides the appropriate medal inserted into the medal insertion slot 14 to the hopper device 51. A medal sensor (game medium detecting means: not shown) for detecting that an appropriate medal has passed is provided on the path through which the medal passes in the selector 66.

  The door open / close monitoring switch 67 is disposed diagonally to the left of the selector 66 when the front door 2b is viewed from the back side. The door opening / closing monitoring switch 67 outputs a security signal for notifying the opening / closing of the front door 2b to the outside of the pachislot 1.

  Although not shown in FIG. 4, a door relay terminal plate 68 is disposed in the area where the front door 2 b is opened and closed by the middle door 41 on the back surface and below the reel display window 4 (see below). 7). The door relay terminal board 68 includes a main control board 71 in the main control board case 55, various buttons and switches, a sub-relay board 61, a selector 66, a game operation display board 81, a first interface board 301 for a testing machine, This is a relay board on which wiring for connecting each of the second interface boards 302 for the testing machine is mounted. Examples of the various buttons and switches include a MAX bet button 15a, a 1 bet button 15b, a door open / close monitoring switch 67, a BET switch 77 described later, a start switch 79, and the like.

<Display example of sub display device>
Here, various display screens displayed on the sub display device 18 will be described with reference to FIGS. 5A to 5E. 5A is a diagram showing a top screen 221 displayed on the sub display device 18, and FIG. 5B is a diagram showing a menu screen 222 displayed on the sub display device 18. 5C to 5E are diagrams showing game information screens 223, 224, and 225 displayed on the sub display device 18. FIG.

  Various display screens are displayed on the sub display device 18 by a player's touch operation. As shown in FIGS. 5A to 5E, various display screens including a top screen 221, a menu screen 222, and game information screens 223, 224, and 225 are displayed. The display screen is displayed. These display screens are switched based on the player's operation signal received via the touch sensor 19.

  The top screen 221 is an initial screen among the display screens displayed on the sub display device 18, and on the top screen 221, a “MENU” button 221a and a summary game history 221b are displayed. The “MENU” button 221a is an operation button for calling the menu screen 222 shown in FIG. 5B. When a predetermined operation (for example, tapping) is performed by the player on the “MENU” button 221a, the menu screen 222 is called. It is. On the top screen 221, a part of the game history (outline game history) of the pachislot 1 is displayed as the summary game history 221b. In the present embodiment, for example, the number of bonuses, the number of ARTs, and the number of games (number of games) are displayed as the summary game history 221b.

  The menu screen 222 is a screen that displays a menu that can be displayed on the sub display device 18. In the menu screen 222, a "return" button 222a, a "registration" button 222b, an "explanation" button 222c, and an "array payout" button 222d. , A “reach eye” button 222e, a “WEB site” button 222f, and a “volume” button 222g are displayed. The “return” button 222a is an operation button for calling the top screen 221. When the player performs an operation on the “return” button 222a, the top screen 221 is called. The “Register” button 222b to “Volume” button 222g are operation buttons for calling up the display screen of the corresponding menu contents. When the player performs an operation on each button, the corresponding menu contents are displayed. The display screen is called up.

  For example, when the “Register” button 222 b is operated by the player on the menu screen 222, a registration screen (not shown) for registering the player who is playing the game is called up on the display screen of the sub display device 18. In recent pachislot machines, a service is widely used in which a player is registered for each model and various information such as the achievement status of a defined mission is managed based on the player's previous game history. The registration screen called by the “registration” button 222b is a display screen for registering a player when receiving the provision of this service.

  For example, when the “explain” button 222 c is operated by the player on the menu screen 222, an explanation screen (not shown) of the pachislot 1 is called up on the display screen of the sub display device 18. The information displayed on the explanation screen includes, for example, explanation of the specifications of the pachislot 1 such as a bonus winning probability and ART winning probability for each set value, and an introduction explanation of characters appearing in the production of the pachislot 1.

  For example, when the “array payout” button 222 d is operated by the player on the menu screen 222, the array payout screen (not shown) of the pachislot 1 is called on the display screen of the sub display device 18. On the array payout screen, for example, the correspondence (payout table) between the combination of symbols determined to win in the pachislot 1 and the privilege when determined to be a win, and the reels 3L, 3C, and 3R are drawn. A symbol row (reel arrangement) or the like is displayed.

  For example, when the “reach eye” button 222 e is operated by the player on the menu screen 222, the reach eye screen (not shown) of the pachi-slot 1 is called to the display screen of the sub display device 18. On the reach eye screen, information on symbol combinations called “reach eyes” set in the pachi slot 1 is displayed. It should be noted that the symbol combination referred to as “reach eyes” is clearly notified that a special privilege is granted (for example, bonus winning or RUSH state winning) by displaying the symbol combination along the active line. Is a symbol combination.

  Further, for example, when the “WEB site” button 222 f is operated by the player on the menu screen 222, the WEB introduction screen (not shown) of the pachislot 1 is called up on the display screen of the sub display device 18. On the WEB introduction screen, for example, a two-dimensional code (for example, QR code (registered trademark)) indicating a URL of an arbitrary WEB site such as a special WEB site provided for each model of the pachislot 1 or a WEB site of the manufacturer of the pachislot 1 Is displayed. The player can access the corresponding WEB site by reading the two-dimensional code displayed on the WEB introduction screen with a mobile phone or the like.

  Further, for example, when the “volume” button 222g is operated by the player on the menu screen 222, a volume adjustment screen (not shown) that can adjust the volume of the sound output from the speakers 65L and 65R is displayed on the sub display device. Called 18 display screen. The player can adjust the volume of the effect sound of the pachislot 1 via the volume adjustment screen.

  Since the sub display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212) described above, it can be controlled separately from the display device 11. Therefore, in the pachislot machine 1 of the present embodiment, the display screen of the sub display device 18 can be switched by the player's operation even during the game (during execution of the effect by the display device 11). As a result, for example, when the player wants to know the character appearing in the presentation on the display device 11, the player operates the “explain” button 222 c to call the explanation screen, thereby It is possible to grasp information such as the relationship of the game during the game. Also, for example, if a player wants to grasp the symbol that should be used as a guideline for winning a rare role during reel rotation when a so-called `` rare role '' is won during a game, By operating the “array payout” button 222d to call the array payout screen, the reel arrangement can be grasped.

  The game information screens 223, 224, and 225 are display screens that display detailed game history information including a summary game history displayed on the top screen 221 of the game history of the pachislot 1.

  On the game information screen 223, a “return” button 223a, a “MENU” button 223b, a “previous” button 223c, a “next” button 223d, and a game history 223e are displayed. The “return” button 223a and the “MENU” button 223b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 223c and the “Next” button 223d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 223c is operated by the player, the display screen Is switched from the game information screen 223 to the game information screen 225, and when the “next” button 223d is operated by the player, the display screen is switched from the game information screen 223 to the game information screen 224. As the game history 223e, as shown in FIG. 5C, the number of games (number of games), the number of bonuses, and the number of ARTs are displayed.

  On the game information screen 224, a “return” button 224a, a “MENU” button 224b, a “previous” button 224c, a “next” button 224d, and a game history 214e are displayed. The “return” button 224a and the “MENU” button 224b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 224c and the “Next” button 224d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 224c is operated by the player, the display screen is changed to the game. When the information screen 224 is switched to the game information screen 223 and the “next” button 224 d is operated by the player, the display screen is switched from the game information screen 224 to the game information screen 225. Further, as shown in FIG. 5D, the game history 224e displays the number of rushes and the number of successes in a later-described pull-back state, the number of rushes in a later-described normal RUSH state, the number of rushes in a later-described special RUSH state, and the like.

  On the game information screen 225, a “return” button 225a, a “MENU” button 225b, a “previous” button 225c, a “next” button 225d, and a game history 225e are displayed. The “return” button 225a and the “MENU” button 225b are operation buttons for calling the top screen 221 and the menu screen 222 to the display screen of the sub display device 18, respectively. The display screen to be called is called. The “Previous” button 225c and the “Next” button 225d are operation buttons for switching the game information screen in a predetermined order. When the “Previous” button 225c is operated by the player, the display screen is displayed. Is switched from the game information screen 225 to the game information screen 224, and when the “next” button 225d is operated by the player, the display screen is switched from the game information screen 225 to the game information screen 223. Further, as shown in FIG. 5E, the game history 225e includes the number of wins and the winning probability of a specific internal winning combination (for example, “F_RB” described later, “F_MB_L” described later, and “F_MB_S” described later). Numerator is a fraction of 1).

  In addition, as a switching method of the display screen displayed on the sub display device 18, for example, a switching method based on a tap operation on an operation button displayed on each display screen may be employed. You may employ | adopt the method of switching based on the swipe operation with respect to a display screen.

<Various display screen switching functions of the sub display device>
Next, various display screen switching functions of the sub display device 18 in the pachi-slot 1 of the present embodiment will be described.

[Transition example of the display screen of the sub display device]
First, with reference to FIG. 6A and 6B, the transition example (switching aspect) of the display screen of the sub display apparatus 18 in the pachislot 1 of this embodiment is demonstrated. 6A is a diagram showing an example of transition of the display screen of the sub display device 18 in a situation where the player registration state is not set, and FIG. 6B is a sub display in a situation where the player registration state is set. FIG. 10 is a diagram illustrating a transition example of a display screen of the device 18.

  In the situation where the player registration state is not set, the display screen of the sub display device 18 transitions between the top screen 221 and the menu screen 222 and from the menu screen 222 and the menu screen 222 as shown in FIG. 6A. Transition is possible only between various possible display screens, and transition between these display screens is controlled by a sub control board 72 (sub CPU 201 described later). For example, the sub-control board 72 is connected between the top screen 221 and the menu screen 222 based on a touch operation acquired via the touch sensor 19 (for example, a tap operation on a predetermined button or a swipe operation on the display screen). Switch the display screen. However, in a situation where the player registration state is not set, the sub-control board 72 performs control so that the display of the game information screens 223, 224, 225 is impossible. That is, in a situation where the player registration state is not set, the player cannot display the game information screens 223, 224, 225 on the sub display device 18.

  On the other hand, in the situation where the player registration state is set, as shown in FIG. 6B, the display screen of the sub display device 18 is between the top screen 221 and the menu screen 222, and between the menu screen 222 and the menu screen 222. In addition to the various display screens that can be shifted from, the transition between the menu screen 222 and the game information screens 223, 224, and 225 is also possible. CPU201). In other words, the sub-control board 72 is configured not only between the top screen 221 and the menu screen 222 but also on each of the top screen 221 and the menu screen 222 based on the touch operation acquired via the touch sensor 19 and the game information screen. The display screen can also be switched between 223, 224 and 225. Therefore, in this embodiment, when the player registration state is set, the player can display the game information screens 223, 224, and 225 on the sub display device 18.

  As shown in FIG. 6B, the display screen transition order among the top screen 221, the menu screen 222, and the game information screens 223, 224, and 225 is arbitrary. Therefore, for example, it may be configured such that the top screen 221 can directly transition to the game information screens 223, 224, 225, or the game information screens 223, 224, 225 can be changed only from the top screen 221 via the menu screen 222. You may make it the structure which can be changed.

  In the pachi-slot 1 of the present embodiment, a configuration that allows transition from the top screen 221 to the game information screens 223, 224, and 225 only via the menu screen 222 (configuration that cannot transition directly from the top screen 221 to the game information screens 223, 224, and 225) ) Is adopted. In the pachi-slot 1 of the present embodiment, when the player performs a swipe operation (not a menu selection operation) on the display screen on the menu screen 222, the display screen is changed from the menu screen 222 to the game information screens 223, 224. , 225.

  In the present embodiment, the game information screens 223, 224, and 225 are display screens provided completely independently of the menu screen 222. That is, in the pachislot machine 1 of the present embodiment, information indicating a game result that a player has a strong interest in the game, such as a game history, is independent as information that is not related to a game result such as a payout arrangement or volume control. And display. In the present embodiment, the game information screens 223, 224, and 225 can be displayed without the player performing a menu selection operation on the menu screen 222 in a situation where the player registration state is set. . Therefore, in this embodiment, when the player registration state is set, it is possible to easily access the information game history information desired by the player.

  In the present embodiment, the menu selection operation on the menu screen 222 cannot change the display screen to the game information screens 223, 224, and 225, and the swipe operation (specified in the menu display) is performed on the menu screen 222. If no operation is performed, the display screen cannot be changed to the game information screens 223, 224, 225. Therefore, in the pachi-slot 1 of the present embodiment, the swipe operation for changing the display screen to the game information screens 223, 224, 225 can be handled as a hidden command in the situation where the player registration state is set. In this case, since the player can see more detailed game history information that cannot be seen by other players with little knowledge due to his / her own knowledge of the pachislot 1, than the other players. The game can be advantageously performed, and as a result, it can be expected that the player actively plays the game.

[Display switching function from game information screen to top screen]
The pachi-slot 1 of the present embodiment has a function of changing the display screen of the sub display device 18 from the game information screens 223, 224, 225 to the top screen 221 manually or automatically by the player. Specifically, in this embodiment, when the “return” button is operated on the game information screens 223, 224, 225, the display screen transitions from the game information screens 223, 224, 225 to the top screen 221 (manual transition). function). In the present embodiment, when a predetermined condition is satisfied while the game information screens 223, 224, and 225 are displayed, the display screen automatically changes to the top screen 221 regardless of the player's operation. Transition (automatic transition function).

  More specifically, in the pachi-slot 1, in the state where the game information screens 223, 224, and 225 are displayed, the insertion operation (the operation to the MAX bet button 15a, the operation to the 1 bet button 15b and the medal insertion slot 14). When a medal insertion operation is performed, the display screen of the sub display device 18 automatically transitions to the top screen 221. In the gaming state (high lip state) where the probability that the replay role is determined as the internal winning combination is high, such as the ART gaming state, medals are automatically inserted due to the replaying action associated with the replay winning combination. As a result, in the high lip state, the opportunity to display the game information screens 223, 224, 225 may be limited. Therefore, in the pachi-slot 1 of the present embodiment, when a medal is automatically inserted by the re-game operation, the display screen is automatically displayed in response to the start operation instead of the medal insertion operation. , 224, 225 to the top screen 221.

  That is, in this embodiment, when the re-game is activated and the game information screens 223, 224, 225 are displayed, the display screen is automatically displayed on the game information screens 223, 224 in response to the start operation. , 225 to the top screen 221. On the other hand, when the re-game operation is not performed, the display screen automatically transitions from the game information screens 223, 224, 225 to the top screen 221 in response to the input operation.

[Display switching function from menu content display screen to top screen (or menu screen)]
The pachi-slot 1 of this embodiment has various menu content display screens (a registration screen, an explanation screen, an array payout screen, a reach eye screen, a WEB introduction) on which the display screen of the sub display device 18 can be changed by a menu selection operation on the menu screen 222. The screen has a function of shifting from the screen and the volume adjustment screen) to the top screen 221 (or the menu screen 222) manually or automatically by the player. Specifically, in this embodiment, when a predetermined button (for example, “Return to TOP” button) is operated on the menu content display screen, the display screen transitions from the menu content display screen to the top screen 221 ( Manual transition function). In this embodiment, when a specific button (for example, a “return” button) is operated on the menu content display screen, the display screen transits from the menu content display screen to the menu screen 222 (manual transition). function).

  Furthermore, in the present embodiment, when a predetermined time elapses while the menu content display screen is displayed, the display screen automatically changes to the top screen 221 (or the menu screen 222) regardless of the player's operation. Transition (automatic transition function). At this time, the predetermined time that triggers automatic transition to the top screen 221 (or the menu screen 222) varies depending on the type of the menu content display screen currently displayed. For example, if the volume adjustment screen for adjusting the volume output from the pachislot 1 is displayed for a long time, not only may the volume be adjusted to an unintended volume due to an erroneous operation, but other players may be caused by an erroneous operation. There is also a risk of discomfort. Therefore, the volume adjustment screen is set to automatically transition to the top screen 221 (or the menu screen 222) in a shorter time than other menu content display screens. On the other hand, the registration screen is set to automatically transition to the top screen 221 (or the menu screen 222) in a longer time than other menu content display screens in order to facilitate player registration. .

  That is, in each menu content display screen, an elapsed time (automatic transition time) that triggers automatic transition to the top screen 221 (or menu screen 222) is appropriately set according to the type of the menu content display screen. In the volume adjustment screen, an automatic transition time shorter than that of the other menu content display screen is set, and in the registration screen, an automatic transition time longer than that of the other menu content display screen is set.

[Function for selecting whether to operate the menu]
In the pachi-slot 1 of this embodiment, the display screen of the sub display device 18 is changed from the menu screen 222 to a registration screen, an explanation screen, an array payout screen, a reach eye screen, a WEB introduction screen, and a volume adjustment screen. A person can perform various operations according to these menu content display screens, and can confirm various information. It should be noted that a function (a function for selecting whether or not to operate the menu) may be provided so that such a function that allows the player to select a menu can be restricted according to the settings on the game store side.

  For example, the display screen may not be allowed to transition from the menu screen 222 to the volume adjustment screen (for example, the “volume” button 222g is not displayed on the menu screen 222) according to settings at the game store side. In this case, the volume adjustment by the player can be made impossible.

<Control system for pachislot>
Next, a control system provided in the pachislo 1 will be described with reference to FIG. FIG. 7 is a circuit block diagram showing the configuration of the control system of the pachislot 1.

  The pachi-slot 1 includes a main control board 71 provided on the middle door 41 and a sub-control board 72 provided on the front door 2b. The pachi-slot 1 includes a reel relay terminal board 74, a setting key switch 54 (setting switch), and a cabinet-side relay board 44 connected to the main control board 71. Further, the pachi-slot 1 includes an external concentration terminal board 47, a hopper device 51, a medal auxiliary storage switch 75, a reset switch 76, and a power supply device 53 connected to the main control board 71 via the cabinet-side relay board 44. In addition, since the structure of the hopper apparatus 51 was mentioned above, the description is abbreviate | omitted here.

  The reel relay terminal plate 74 is disposed inside the reel body of each reel 3L, 3C, 3R. The reel relay terminal board 74 is electrically connected to stepping motors (not shown) of the reels 3L, 3C, 3R, and relays signals output from the main control board 71 to the stepping motors.

  The setting key type switch 54 is provided on the main control board case 55. The setting key switch 54 is used when changing the setting (setting 1 to setting 6) of the pachi-slot 1 or when checking the setting of the pachi-slot 1.

  The cabinet-side relay board 44 is a relay board on which wiring for connecting the main control board 71, the external concentration terminal board 47, the hopper device 51, the medal auxiliary storage switch 75, the reset switch 76, and the power supply device 53 is mounted. It is. The external concentration terminal board 47 is provided for outputting signals such as a medal insertion signal, a medal payout signal, and a security signal to the outside of the pachislot machine 1. The medal auxiliary storage switch 75 is provided in the medal auxiliary storage 52 and detects whether or not the medal auxiliary storage 52 is full of medals. The reset switch 76 is used, for example, when changing the setting of the pachislot 1.

  The power supply device 53 includes a power supply board 53b and a power switch 53a connected to the power supply board 53b. The power switch 53a is pressed when supplying the necessary power to the pachi-slot 1. The power supply board 53 b is connected to the main control board 71 via the cabinet side relay board 44 and also connected to the sub control board 72 via the sub relay board 61.

  The pachislot machine 1 includes a door relay terminal plate 68, a selector 66, a door open / close monitoring switch 67, a BET switch 77, a checkout switch 78, which are connected to the main control board 71 via the door relay terminal plate 68. It has a start switch 79, a stop switch board 80, a game operation display board 81, a sub-relay board 61, a first testing machine interface board 301, and a second testing machine interface board 302. Since the selector 66, the door opening / closing monitoring switch 67, and the sub relay board 61 have been described above, the description thereof is omitted here.

  The BET switch 77 (insertion operation detecting means) detects that the MAX bet button 15a or the 1 bet button 15b has been pressed by the player. The settlement switch 78 detects that a settlement button (not shown) has been pressed by the player. The start switch 79 (start operation detecting means) detects that the start lever 16 has been operated by the player (start operation).

  The stop switch substrate 80 (stop operation detecting means) includes a circuit for stopping the rotating main reel and a circuit for displaying the stopable main reel by an LED or the like. The stop switch substrate 80 is provided with a stop switch (not shown). The stop switch detects that each stop button 17L, 17C, 17R has been pressed by the player (stop operation).

  The game operation display board 81 is connected to the information display (7-segment display) 6 and the LED 82. The LED 82 includes, for example, three LEDs for displaying the number of inserted medals (hereinafter referred to as “first LED” to “first LED”) that are turned on in correspondence with the number of medals inserted in the current game (hereinafter referred to as “inserted number”). LED for lighting a medal insertion mark, a game start mark, a replay mark, etc. based on a signal input from the game operation display board 81) Etc. are included. In the first to third LEDs (display means), when one medal is inserted, the first LED is turned on, and when two medals are inserted, the first and second LEDs are turned on, and three medals (game) When the startable number of sheets is inserted, the first to third LEDs are turned on. Since the information display device 6 has been described above, the description thereof is omitted here.

  Both the first interface board 301 for testing machine and the second interface board 302 for testing machine are relay boards used when various signals relating to games are output to the testing machine in the pachislot 1 certification test (trial test) ( Since these relay boards are not mounted on the pachislot machine 1 as a release product for sale, the main control circuit 90 of the main control board 71 for sale includes the first interface board 301 for testing machine and the testing machine. Various electronic components necessary for connecting to the second interface board 302 are also not mounted). For example, a test signal for controlling a main operation related to the game (for example, internal lottery, reel stop control, etc.) is output via the first interface board 301 for testing machine, and is determined by the main control board 71, for example. A test signal or the like related to the pushed push navigation is output via the second interface board 302 for the testing machine.

  The sub control board 72 is connected to the main control board 71 via the door relay terminal board 68 and the sub relay board 61. The pachislot machine 1 includes a speaker group 84, LED groups 85, a 24h door opening / closing monitoring unit 63, a touch sensor 19, and a display unit 212, which are connected to the sub control board 72 via the sub relay board 61. Since the touch sensor 19 has been described above, the description thereof is omitted here.

  The speaker group 84 includes speakers 65L and 65R and various speakers (not shown). The LED group 85 includes a lamp group 21 provided on the front panel 10 and a light source that emits light for illuminating the decorative panel of the waist panel 12 from the back side. The 24h door opening / closing monitoring unit 63 stores opening / closing history information of the middle door 41. Further, the 24h door opening / closing monitoring unit 63 outputs a signal for displaying an error by the display device 11 to the sub control board 72 (sub control circuit 200) when the middle door 41 is opened. The display unit 212 includes, for example, a projection target 212a constituting the display device 11, and another projection target with a curved display surface provided on the back side of the projection target 212a.

  The pachi-slot 1 also includes a ROM cartridge substrate 86 and a liquid crystal relay substrate 87 connected to the sub control substrate 72. The ROM cartridge substrate 86 and the liquid crystal relay substrate 87 are housed in the sub control board case 57 together with the sub control board 72.

  The ROM cartridge substrate 86 is a substrate for managing various control programs executed by the sub CPU 201, production images (video), sound (speaker group 84), light (LED group 85), and communication data. . The liquid crystal relay substrate 87 is a substrate that relays connection wiring between the sub control substrate 72, the projector mechanism 211 constituting the display device 11, and the sub display device 18. Since the projector mechanism 211 and the sub display device 18 have been described above, the description thereof is omitted here.

<Main control circuit>
Next, the configuration of the main control circuit 90 mounted on the main control board 71 will be described with reference to FIG. FIG. 8 is a block diagram illustrating a configuration example of the main control circuit 90 of the pachi-slot 1.

  The main control circuit 90 includes a microprocessor 91, a clock pulse generation circuit 92, a power management circuit 93, and a switching regulator 94 (power supply means).

  The microprocessor 91 is a microprocessor with a security function for gaming machines. In the microprocessor 91 of the present embodiment, as will be described later, various instruction codes specific to the microprocessor 91 that can be defined in the source program (for example, “LDQ” instruction described later, etc., hereinafter: “main CPU 101” A dedicated instruction code). In this embodiment, by using the instruction code dedicated to the main CPU 101, the processing efficiency and the program capacity are reduced. The internal configuration of the microprocessor 91 will be described in detail with reference to FIG. 9 described later, and the instruction code dedicated to the main CPU 101 provided in the microprocessor 91 will be described in detail in various processes executed by a main control circuit described later. To do.

  The clock pulse generation circuit 92 generates a clock pulse signal for operating the main CPU, and outputs the generated clock pulse signal to the microprocessor 91. The microprocessor 91 executes a control program based on the input clock pulse signal.

  The power management circuit 93 manages fluctuations in the DC 12V power supply voltage supplied from the power supply board 53b (see FIG. 7). The power management circuit 93 outputs a reset signal to the “XSRST” terminal of the microprocessor 91, for example, when the power is turned on (when the power supply voltage exceeds the startup voltage value (10V) from 0V). When a power interruption occurs (when the power supply voltage falls below the power failure voltage value (10.5 V) from 12 V), a power interruption detection signal is output to the “XINT” terminal of the microprocessor 91. That is, the power management circuit 93 outputs a reset signal (start signal) to the microprocessor 91 when the power is turned on, and a power failure detection signal (power failure signal) to the microprocessor 91 when a power failure occurs. Also serves as a means to output (power failure means).

  The switching regulator 94 is a DC / DC conversion circuit, generates a DC drive voltage (DC power supply voltage of 5 V DC) for the microprocessor 91, and outputs the generated DC drive voltage to the “VCC” terminal of the microprocessor 91.

<Microprocessor>
Next, the internal configuration of the microprocessor 91 will be described with reference to FIG. FIG. 9 is a block diagram showing the internal configuration of the microprocessor 91.

  The microprocessor 91 includes a main CPU 101, a main ROM 102 (first storage means), a main RAM 103 (second storage means), an external bus interface 104, a clock circuit 105, a reset controller 106, an arithmetic circuit 107, A random number circuit 110, a parallel port 111, an interrupt controller 112, a timer circuit 113, a first serial communication circuit 114, and a second serial communication circuit 115 are included. These units constituting the microprocessor 91 are connected to each other via a signal bus 116.

  The main CPU 101 executes various control programs based on the clock pulse generated by the clock circuit 105 and performs control related to the overall game operation. Here, reel stop control will be described as an example of the control operation of the main CPU 101.

  The main CPU 101 counts the number of times pulses are output to the stepping motors of the reels 3L, 3C, 3L (main reel) after detecting the reel index. Thereby, the main CPU 101 manages the rotation angle of each reel (mainly, how many symbols the reel has rotated). The reel index is information indicating that the reel has made one revolution. The reel index includes, for example, an optical sensor having a light emitting unit and a light receiving unit, and a detection piece provided at a predetermined position of each reel and interposed between the light emitting unit and the light receiving unit by the rotation of each main reel. It is detected by a provided reel position detector (not shown).

  Here, management of the rotation angle of each reel 3L, 3C, 3L (main reel) will be specifically described. The number of pulses output to the stepping motor is counted by a pulse counter provided in the main RAM 103. Each time the output of a predetermined number of pulses necessary for the rotation of one symbol is counted by the pulse counter, the symbol counter provided in the main RAM 103 is incremented by one. A symbol counter is provided for each reel. The value of the symbol counter is cleared when a reel index is detected by a reel position detector (not shown).

  In other words, in the present embodiment, by managing the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

  The main ROM 102 stores various control programs executed by the main CPU 101, various data tables, data for transmitting various control commands (commands) to the sub control circuit 200, and the like. The main RAM 103 is provided with a storage area for storing various data such as an internal winning combination determined by execution of the control program. The internal configuration (memory map) of the main ROM 102 and the main RAM 103 will be described in detail with reference to FIG.

  The external bus interface 104 is for electrically connecting an external signal bus (not shown) to which various components (for example, each reel) provided outside the microprocessor 91 are connected to the microprocessor 91. It is an interface circuit. The clock circuit 105 includes, for example, a frequency divider (not shown) and the like, and the clock pulse signal for CPU operation input from the clock pulse generation circuit 92 is received by other components (for example, the timer circuit 113). Convert to a clock pulse signal of the frequency used. Note that the clock pulse signal generated by the clock circuit 105 is also output to the reset controller 106.

  The reset controller 106 resets an IAT (Illegal Address Trap) or WDT (watchdog timer) based on the reset signal input from the power management circuit 93. The arithmetic circuit 107 includes a multiplication circuit and a division circuit. For example, when executing a “MUL (multiplication)” instruction (see FIG. 85B described later) on the source program, the arithmetic circuit 107 executes a multiplication process based on the “MUL” instruction.

  The random number circuit 110 generates a random number in a predetermined range (for example, 0 to 65535 or 0 to 255). Although not shown, the random number circuit 110 generates a random number register 0 for obtaining a 2-byte hard latch random number, random number registers 1 to 3 for obtaining a 2-byte soft latch random number, and a 1-byte soft latch random number. It is composed of random number registers 4 to 7 for obtaining. The main CPU 101 extracts one value from a predetermined range of random numbers generated by the random number circuit 110, for example, as a random value for internal lottery. The parallel port 111 is a port (memory map I / O) for signals input / output between the microprocessor 91 and various circuits (for example, the power management circuit 93) provided outside the microprocessor 91. . The parallel port 111 is also connected to the random number circuit 110 and the interrupt controller 112. The start switch 79 is connected to one of the input ports PI0 to PI4 of the parallel port 111, and the latch signal is sent from the parallel port 111 to the random number register 0 of the random number circuit 110 at a timing (on edge) when the start switch 79 is turned on. Is output. In the random number circuit 110, when the latch signal is input, the random number register 0 is latched, and a 2-byte hard latch random number is acquired.

  The interrupt controller 112 performs an interrupt process by the main CPU 101 based on a power interruption detection signal input from the power management circuit 93 via the parallel port 111 or a time-out signal input from the timer circuit 113 at a cycle of 1.1172 ms. Control the execution timing of. When a power failure detection signal is input from the power management circuit 93 or a time-out signal is input from the timer circuit 113, the interrupt controller 112 sends an interrupt request signal indicating an interrupt processing start command to the main CPU 101. Output to. The main CPU 101 performs input port check processing, reel control processing, communication data transmission processing, 7-segment LED drive processing, timer based on an interrupt request signal input from the interrupt controller 112 in response to a timeout signal from the timer circuit 103. Various interrupt processes such as an update process (see FIG. 113 described later) are performed.

  The timer circuit 113 (PTC) operates with a clock pulse signal generated by the clock circuit 105 (clock pulse signal having a frequency obtained by dividing a clock pulse signal for operating the main CPU by a frequency divider (not shown)). Count elapsed time). Then, the timer circuit 113 outputs a timeout signal (trigger signal) to the interrupt controller 112 at a cycle of 1.1172 msec.

  The first serial communication circuit 114 is a circuit that controls a serial transmission operation when data (various control commands (commands)) is transmitted from the main control board 71 to the sub-control board 72. The second serial communication circuit 115 is a circuit that controls a serial transmission operation when data is transmitted from the main control board 71 to the second interface board 302 for the testing machine.

<Sub control circuit>
Next, the configuration of the sub control circuit 200 (sub control means) mounted on the sub control board 72 will be described with reference to FIG. FIG. 10 is a block diagram illustrating a configuration example of the sub control circuit 200 of the pachislot 1.

  The sub control circuit 200 is electrically connected to the main control circuit 90 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 90. The sub control circuit 200 basically includes a sub CPU 201, a sub RAM 202, a rendering processor 203, a drawing RAM 204, and a driver 205.

  The sub CPU 201 is connected to the ROM cartridge substrate 86. The driver 205 is connected to the liquid crystal relay substrate 87. That is, the driver 205 is connected to the projector mechanism 211 and the sub display device 18 via the liquid crystal relay substrate 87.

  The sub CPU 201 controls the output of video, sound, and light according to the control program stored in the ROM cartridge substrate 86 in accordance with the command transmitted from the main control circuit 90. The ROM cartridge substrate 86 basically includes a program storage area and a data storage area.

  In the program storage area, a control program executed by the sub CPU 201 is stored. For example, in the control program, a main board communication task for controlling communication with the main control circuit 90 and a random number value for production are extracted, and production registration for determining and registering production contents (production data). Various programs for executing tasks are included. In addition, the control program includes an animation task for controlling the display of video by the display device 11 based on the determined content of the presentation, a lamp control task for controlling the output of light from a light source such as the LED group 85, and the sound of the speaker group 84. Various programs for executing a sound control task for controlling output are also included.

  The data storage area includes a storage area for storing various data tables, a storage area for storing effect data constituting each effect content, and a storage area for storing animation data related to creation of video. Further, the data storage area includes a storage area for storing sound data related to BGM and sound effects, a storage area for storing lamp data related to a light on / off pattern, and the like.

  The sub RAM 202 is provided with a storage area for registering the determined contents and effects data, and a storage area for storing various data such as an internal winning combination and navigation data transmitted from the main control circuit 90.

  The sub CPU 201, the rendering processor 203, the drawing RAM (including the frame buffer) 204, and the driver 205 create a video according to the animation data designated by the contents of the presentation, and display the created video on the display device 11 (projector mechanism 211) and / or Alternatively, it is displayed on the sub display device 18. The display device 11 (projector mechanism 211) and the sub display device 18 are individually controlled by the sub control board 72.

  Further, the sub CPU 201 causes the speaker group 84 to output a sound such as BGM according to the sound data specified by the contents of the effect. Further, the sub CPU 201 controls lighting and extinguishing of the LED group 85 according to the lamp data designated by the contents of the effect.

<Various registers of main CPU>
Next, various registers included in the main CPU 101 will be described with reference to FIG. FIG. 11 is a schematic configuration diagram of various registers included in the main CPU 101.

  The main CPU 101 includes, as main registers, an accumulator A (hereinafter referred to as “A register”), a flag register F (flag register), a general purpose register B (hereinafter referred to as “B register”), and a general purpose register C (hereinafter referred to as “register A”). General purpose register D (hereinafter referred to as “D register”), general purpose register E (hereinafter referred to as “E register”), general purpose register H (hereinafter referred to as “H register”) and general purpose register L (hereinafter referred to as “C register”). , Referred to as “L register”). Further, the main CPU 101 includes, as sub registers, an accumulator A ′, a flag register F ′, a general purpose register B ′, a general purpose register C ′, a general purpose register D ′, a general purpose register E ′, a general purpose register H ′, and a general purpose register L ′. As a general purpose register. Each register is composed of a 1-byte register.

  In this embodiment, the B register and the C register are used as a pair register (hereinafter referred to as “BC register”), and the D register and the E register are used as a pair register (hereinafter referred to as “DE register”). Furthermore, in this embodiment, the H register and the L register are used as a pair register (hereinafter referred to as “HL register”).

  As shown in FIG. 11, predetermined flag information indicating the result of the arithmetic processing is set in each bit of the flag registers F and F ′. For example, in bit 6 (D6), data (zero flag) indicating whether or not the calculation result is “0” in the calculation result determination process is set. Specifically, when the operation result is “0”, data “1” is set in bit 6, and when the operation result is not “0”, data “0” is set in bit 6. In the calculation result determination process, the main CPU 101 performs determination (YES / NO) with reference to the data “0” / “1” of bit 6.

  The main CPU 101 has an extension register Q (hereinafter referred to as “Q register”). The Q register is composed of a 1-byte register. In this embodiment, as will be described in the various processing flows described later, various instruction codes dedicated to the main CPU 101 for performing address designation using the Q register are provided on the source program. As a result, the processing efficiency and the capacity of the main ROM 102 are reduced. In various instruction codes dedicated to the main CPU 101 that perform address designation using the Q register, the address data (address value) on the upper side of the address is stored in the Q register. In the Q register, “F0H” is set as an initial value immediately after the main CPU 101 is reset. In addition, in the “LD Q, n (8-bit data)” instruction using the Q register, the value of the Q register is changed by setting arbitrary 1 byte data to “n” and executing the instruction. be able to.

  Further, the main CPU 101 includes an interrupt page address register I and a memory refresh register R configured by 1-byte registers, and an index register IX and an index register IY configured by 2-byte registers. The stack pointer SP and the program counter PC are provided as dedicated registers.

<Internal configuration of main ROM and main RAM (memory map)>
Next, the internal configuration of the main ROM 102 and the main RAM 103 (hereinafter referred to as “memory map”) included in the main control circuit 90 (microprocessor 91) will be described with reference to FIGS. 12A to 12C. 12A is a diagram showing a memory map of the entire memory, FIG. 12B is a diagram showing a memory map of the main ROM 102, and FIG. 12C is a diagram showing a memory map of the main RAM 103.

  In the memory map of the entire memory included in the main control circuit 90 (microprocessor 91), as shown in FIG. 12A, from the head (0000H) side of the address, the memory area of the main ROM 102, the memory area of the main RAM 103, the built-in register area, The XCS decode areas are arranged at predetermined addresses in this order with an unused area in between.

  In the memory map of the main ROM 102, as shown in FIG. 12B, from the head (0000H) side of the address of the main ROM 102, there are a program area, a data area, an unspecified area, a trademark recording area, a program management area, and a security setting area. In order, they are arranged at predetermined addresses.

  In the program area, control programs for various processes executed by the main CPU 101 in various control processes related to game playability performed by the player are stored. In the data area, various data used by the main CPU 101 (for example, a data table such as an internal lottery table, various sub-control circuits 200, etc.) in various control processes related to game playability performed by the player. Data for transmitting a control command (command), etc.) are stored. In other words, the game ROM area (game storage area) composed of a program area and a data area is necessary for control processing (game-related processing) related to game playability actually performed by the player at the game store. Various programs and various data are stored.

  The non-regulated area stores control programs and data for various processes (processes that do not affect the game characteristics) that are not directly related to the game performance of the game executed by the player. For example, a program and data used in a pachislot 1 certification test (trial test), a control program and data used in checksum generation processing at power interruption or sum check processing at power recovery, and a fraud countermeasure program In addition, data necessary for the data and the like are stored in an unspecified area.

  In the memory map of the main RAM 103, as shown in FIG. 12C, from the head (F000H) side of the address of the main RAM 103, a gaming RAM area (predetermined storage area, gaming temporary storage area) and an unspecified RAM area (unspecified temporary area). Storage areas) are arranged at predetermined addresses in this order.

  The game RAM area is provided with a work area and a stack area for temporarily storing various data such as an internal winning combination determined by the execution of a control program related to the game performance of the game executed by the player. . Each of the various data is stored in a work area at a predetermined address in the game RAM area.

  In addition, the non-specified RAM area is provided with a non-standard work area that is a work area for various processes that are not directly related to the game performance of the game executed by the player, and a non-standard stack. In the present embodiment, various processes that are not directly related to the game playability of the game executed by the player, such as a sum check process, are executed using the non-regulated RAM area.

  As described above, in the pachislot machine 1 of the present embodiment, various programs and various data (tables) used for various processes that are not directly related to the game performance of the game performed by the player are stored in the main ROM 102. The data is stored in a non-standard ROM area (non-standard storage area) arranged at an address different from the ROM area. In addition, various processes that are not directly related to game playability performed by such a player are performed in the main RAM 103 using an unspecified RAM area that is arranged at an address different from the game RAM area. .

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually played by the player are placed in the ROM area (non-specified ROM area) where it is impossible to place a program or the like according to the conventional rules. can do. Therefore, in this embodiment, compression of the capacity of the game ROM area can be avoided.

<Game state transition flow>
Next, with reference to FIG. 13, various gaming states managed by the main control circuit 90 (main CPU 101) of the pachi-slot 1 of this embodiment and the transition flow thereof will be described. FIG. 13 is a transition flow diagram of the basic gaming state of the pachislot 1.

[Basic game state transition flow]
In the pachi-slot 1 of the present embodiment, a regular bonus (hereinafter referred to as “RB”) and a middle bonus (hereinafter referred to as “MB”) are provided as bonus game types. RB is a gaming state advantageous to a player called a first type special feature, and MB continuously activates a challenge bonus called a second type special feature (hereinafter referred to as “CB”). This is a game state that is advantageous to the player, called a continuous accessory operating device related to the second type special accessory. In addition, as a gaming state advantageous to the player, for example, instead of “RB”, a big bonus called a continuous actuating device for a type 1 special feature that continuously operates a type 1 special feature ("BB") can also be employed.

  In the pachi-slot 1 of the present embodiment, the basic gaming state can be roughly divided into a bonus state and a non-bonus state. The bonus state is a state in which the RB described above is operating (RB gaming state, hereinafter simply referred to as “RB”), or a state in which the MB is operating (MB gaming state, hereinafter “MB”). In addition, the MB gaming state operated by the establishment of MB1 may be referred to as the MB1 gaming state, the MB gaming state operated by the establishment of MB2 may be referred to as the “MB2 state”, and hereinafter simply referred to as “MB1” and “MB2”, respectively. The non-bonus state refers to a state where BB and MB are not operating (may be referred to as a normal gaming state or a general gaming state). In addition, when winning the RB in the non-bonus state, the winning of the RB is carried over until the RB is activated (established). The state where the RB is carried over is the bonus winning state (in this embodiment, RT5 state to be described later, hereinafter also referred to as “between flags”). That is, the non-bonus state is further divided into a bonus winning state in which the RB has been won (carried over) and a bonus non-winning state in which the RB has not been won (not carried over). Can be distinguished.

  The RB gaming state (RB) is a gaming state in which the winning probability of a predetermined small combination (for example, “F_RB combination” described later) is higher than the non-bonus state (see FIGS. 15 and 16 described later), This is a gaming state that is advantageous for the player who can increase the medal.

  In addition, the MB gaming state (more specifically, the CB gaming state continuously operated) is the maximum for a specific reel (in this embodiment, the reel 3R) when a stop operation is performed by the player. The number of sliding symbols is reduced from 4 symbols (1st symbol number) to 1 symbol (2nd symbol number), and all of the small winning roles (specifically, internal winning combinations that can be determined) , NML1 to 136 described later) are game states determined as internal winning combinations (see FIG. 84 described later), and are advantageous game states for the player who can increase the medal. Even in the MB gaming state, for the replay combination, the winning probability of the RT state in the non-bonus state (see FIGS. 15 and 16 described later) is taken over and the internal lottery process is performed.

  Further, the non-bonus state is composed of a plurality of RT states in which a part or all of the winning probabilities of a plurality of types of replay combinations can be changed. In the present embodiment, the RT state is the RT0 state (RT0 gaming state, hereinafter simply referred to as “RT0”), RT1 state (RT1 gaming state, hereinafter simply referred to as “RT1”), RT2 State (RT2 gaming state, hereinafter simply referred to as “RT2”), RT3 state (RT3 gaming state, hereinafter simply referred to as “RT3”), RT4 state (RT4 gaming state, hereinafter simply “ RT4 ”) and RT5 state (RT5 gaming state, hereinafter simply referred to as“ RT5 ”).

  As shown in FIG. 13, in the pachislot machine 1 of this embodiment, when a setting value is changed (see FIG. 60 described later) (setting change), the RT state is shifted to the RT0 state (RT0). When other initialization conditions (for example, initialization of the main RAM 103 based on the occurrence of an error) are satisfied (initialization conditions are satisfied), the RT state is shifted to the RT0 state (RT0). In that sense, the RT0 state (RT0) can be said to be an initial gaming state. Also, when the RB gaming state ends, the RT state is shifted to the RT0 state (RT0).

  In the RT0 state (RT0), when “RT1 transition symbol” is displayed on the active line (RT1 transition symbol is established), the RT state is shifted to the RT1 state (RT1). The “RT1 transition symbol” indicates a combination of symbols “HZR1” to “HZR28” described later (see FIGS. 17 to 21 described later).

  In the RT1 state (RT1), when “RT2 transition lip” is displayed on the active line (RT2 transition lip established), the RT state is shifted to the RT2 state (RT2). “RT2 transition lip” indicates a combination of symbols of “REP34” to “REP65” described later (see FIGS. 17 to 21 described later).

  In the RT2 state (RT2), when “RT3 transition lip” is displayed on the active line (RT3 transition lip established), the RT state is shifted to the RT3 state (RT3). The “RT3 transition lip” indicates a combination of symbols “REP66” to “REP73” described later (see FIGS. 17 to 21 described later). In the RT2 state (RT2), when the above-mentioned “RT1 transition symbol” or “RT1 transition lip” is displayed on the active line (RT1 transition symbol, RT1 transition lip established), the RT state is changed to the RT1 state (RT1). Transition. “RT1 transition lip” indicates a combination of symbols of “REP9” to “REP33” described later (see FIGS. 17 to 21 described later).

  In the RT3 state (RT3), when “RT4 transition lip” is displayed on the active line (RT4 transition lip established), the RT state is shifted to the RT4 state (RT4). The “RT4 transition lip” indicates a combination of symbols of “REP74” described later (see FIGS. 17 to 21 described later). In the RT3 state (RT3), when the above-mentioned “RT1 transition symbol” or the above-mentioned “RT1 transition lip” is displayed on the active line (RT1 transition symbol, RT1 transition lip established), the RT state is changed to the RT1 state (RT1). ).

  When “F_RB” is determined as an internal winning combination in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), the RT3 state (RT3) and the RT4 state (RT4) (RB winning), The RT state is shifted to the RT5 state (RT5). This RT5 state (RT5) is the above-described bonus winning state (between RB flags), and is maintained until RB is activated (established).

  The bonus combination (in this embodiment, “F_RB”) is determined by whether or not a hit request flag storage area (refer to FIG. 25 described later) and a carryover combination storage area (refer to FIG. 26 described later) provided in the main RAM 103. ) Is managed based on the data stored. Each gaming state described above is managed based on data stored in a gaming state flag storage area (described later in FIG. 27) provided in the main RAM 103.

  In the RT5 state (RT5), when a combination of symbols of “RB” (see FIGS. 17 to 21 described later) is displayed on the active line (RB established), the gaming state is shifted to the RB gaming state, In this RB gaming state, the RB gaming state is controlled until a predetermined ending condition is satisfied (eight wins or eight games are performed), and this predetermined ending condition is satisfied. Then (RB end), the RB gaming state ends, and as described above, the state shifts to the RT0 state (RT0) in the non-bonus state.

  Also, in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), the RT3 state (RT3) and the RT4 state (RT4), “F_MB_L” is determined as an internal winning combination, and the symbol “MB1” When a combination (see FIGS. 17 to 21 described later) is displayed on the active line (MB1 established), the RT state does not change, the game state is shifted to the MB game state (MB1 game state), and this MB game In the state (MB1 gaming state), it is controlled to the MB gaming state (MB1 gaming state) until a predetermined ending condition is satisfied (there is a payout of more than 149 medals), and this predetermined ending condition is When established (MB1 end), the MB gaming state (MB1 gaming state) ends, and the state transitions to the original RT state in the non-bonus state. In this embodiment, the symbol arrangement (see FIG. 14 to be described later) and the combination of symbols (see FIGS. 17 to 21 to be described later) are defined so that “MB1” is always activated (established) in the winning game. Therefore, a gaming state as a bonus winning state is not defined. However, when “MB1” is configured not to be activated (established) in the winning game, it may be carried over in the same manner as “RB”.

  Also, in the RT0 state (RT0), the RT1 state (RT1), the RT2 state (RT2), the RT3 state (RT3) and the RT4 state (RT4), “F_MB_S” is determined as an internal winning combination, and the symbol “MB2” When a combination (see FIGS. 17 to 21 described later) is displayed on the active line (MB2 established), the RT state does not change, and the gaming state is shifted to the MB gaming state (MB2 gaming state). In the state (MB2 gaming state), the MB gaming state (MB2 gaming state) is controlled until a predetermined ending condition is satisfied (there is more than 9 medals paid out), and this predetermined ending condition is When established (end of MB2), the MB gaming state (MB2 gaming state) ends, and the state shifts to the original RT state in the non-bonus state. In this embodiment, the symbol arrangement (see FIG. 14 to be described later) and the combination of symbols (see FIGS. 17 to 21 to be described later) are defined so that “MB2” is always activated (established) in the winning game. Therefore, a gaming state as a bonus winning state is not defined. However, when “MB2” is configured not to be activated (established) in the winning game, it may be carried over in the same manner as “RB”.

  In the present embodiment, a bonus combination (“F_RB” in the present embodiment) can be determined as an internal winning combination in the MB gaming state (MB1 gaming state and / or MB2 gaming state). The bonus combination (in this embodiment, “F_RB”) may not be determined as an internal winning combination.

  For example, in the case of the former configuration, even in the MB gaming state, lottery numbers “70” and “71” in an internal lottery table (see FIG. 15 and FIG. 16) described later are lottery with the probability shown in FIG. Then, in the MB gaming state, when an internal winning combination including “F_RB” is determined, the MB gaming state may be immediately terminated to shift to the RT5 state (RT5). However, in the game in which the internal winning combination including “F_RB” is determined, stop control in the MB gaming state is performed.

  For example, in the case of the latter configuration, in the MB gaming state, only the replay combination (winning numbers “1” to “48”) in the internal lottery table (see FIGS. 15 and 16), which will be described later, is shown in FIG. The lottery may be lottered with the probability shown in FIG. 5 or, as in the non-bonus state, lottery numbers will be lottered with the probability shown in the figure. However, if an internal winning combination including “F_RB” is determined. However, the control may be performed so that the data indicating it is not stored in the carryover combination storage area (see FIG. 26 described later).

<Configuration of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 102 will be described with reference to FIGS. The configuration of various data tables related to the ART function will be described later.

[Design arrangement table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table includes the position of each symbol in the rotation direction of each of the left reel 3L, the middle reel 3C, and the right reel 3R, and data (hereinafter referred to as symbol code) specifying the type of symbol arranged at each position. Define the correspondence.

  In the symbol arrangement table, when the reel index is detected, the position of the symbol located in the middle area of each reel within the frame of the reel display window 4 is defined as “0”. In each reel, the symbol counter value “0” corresponds to the value of the symbol counter in the order of advance in the reel rotation direction (the direction from symbol position “19” in FIG. 14 toward symbol position “0”). “0” to “19” are assigned to the symbols as symbol positions.

  That is, by referring to the symbol counter values (“0” to “19”) and the symbol arrangement table, the symbols are displayed in the upper, middle, and lower regions of each reel within the frame of the reel display window 4. It is possible to specify the type of design. In this embodiment, the symbols “white 7-1”, “white 7-2”, “red BAR”, “replay 1”, “replay 2”, “replay 3”, “replay 4”, “ Ten patterns of “Bell”, “Cherry 1” and “Cherry 2” are used.

  In the present embodiment, for example, the symbol “white 7-1” (symbol code 1) is assigned as data as “00000001” and the symbol “white 7-2” (symbol code 2) is assigned as the symbol code. Is assigned "00000010" as data, "00000011" is assigned to data for symbol "red BAR" (symbol code 3), and "00000101" is assigned to data for symbol "Replay 1" (symbol code 4). Is assigned to the symbol “Replay 2” (symbol code 5), and “00000101” is assigned to the symbol “Replay 3” (symbol code 6). “0000011” is assigned as data to “Replay 4” (symbol code 7).

  The symbol “Bell” (symbol code 8) is assigned “00001000” as data, the symbol “Cherry 1” (symbol code 9) is assigned “00001001” as data, and the symbol “Cherry 2”. “00001010” is assigned as data to (symbol code 10). Note that the data relating to these symbol codes is merely an example, and any information can be appropriately assigned as long as it is information that can identify the symbol type.

[Internal lottery table]
Next, an internal lottery table referred to when determining an internal winning combination will be described with reference to FIGS. 15 and 16.

  The internal lottery table is provided for each gaming state, and defines the correspondence between various internal winning combinations and lottery values when each internal winning combination is determined. The lottery value is defined for each set value (set values 1 to 6) for adjusting the expected value of the internal winning such as bonus combination or small combination set in advance. This set value is changed using, for example, the reset switch 76 and the setting key switch 54 (see FIG. 7).

  In the internal lottery process of this embodiment, first, a random number value extracted from a predetermined numerical range (for example, 0 to 65535) by the random number register 0 of the random number circuit 110 is assigned to each internal winning combination. Sequentially add with the specified lottery value. Next, it is determined whether or not the lottery result (lottery value + random number value) exceeds 65535 (whether or not the lottery result has overflowed). When the lottery result exceeds 65535 in a predetermined internal winning combination, it is determined that the internal winning combination is won. In the internal lottery process of the present embodiment, the lottery value is added to the extracted random number value to perform the lottery process. May be determined by determining whether the subtraction result (lottery result) is below “0” (whether the lottery result has underflowed) or not.

  Therefore, in the internal lottery process of the present embodiment, the probability of being determined is higher for an internal winning combination having a larger numerical value defined as a lottery value. The winning probability of each internal winning combination can be expressed by “the lottery value specified for each winning number / the number of all random numbers that may be extracted (random number denominator: 65536)”.

  As shown in FIGS. 15 and 16, in the present embodiment, “F_7 Lip_ALL” (winning number “1”) to “F_RB + F_Normal Lip” (winning number “71”) are defined as internal winning combinations. . Among these, “F_7 Lip_ALL” (winning number “1”) to “F_Chance Lip_321” (winning number “48”) are replay roles, and “F_6 selection bell_123A” (winning number “49”) to “ “F_RB combination” (winning number “67”) is a small combination, “F_MB_L” (winning number “68”) to “F_RB” (winning number “70”) is a bonus combination, and “F_RB + F_normal lip” (winning) The number “71”) is a double combination of a bonus combination and a replay combination.

  In the present embodiment, the lottery values shown in FIGS. 15 and 16 are defined for these internal winning combinations in each gaming state or in common with each gaming state, and the above-described arithmetic processing using this lottery value As a result, the internal winning combination is determined.

  As described above, in the MB gaming state, for the replay role, the winning probability of the current RT state (that is, the lottery values shown in FIGS. 15 and 16) is inherited and the lottery is performed. All the small combinations can be determined as internal winning combinations without lottery (see FIG. 84 described later). As described above, for the bonus combination (in this embodiment, “F_RB”), lottery may be performed, or lottery may not be performed. Here, in the internal lottery table in the MB gaming state (in MB) shown in FIG. 16, “−” is written in the columns of the winning numbers “49” to “71”, indicating that no lottery is performed. However, “0” is defined as the lottery value corresponding to these winning numbers, and although it is not actually won, it may be a lottery process common to each gaming state.

  Further, the method of determining the internal winning combination in the MB gaming state is not limited to this. For example, in the MB gaming state, the internal lottery table corresponding to the current RT state is referred to (that is, the internal lottery table in the MB gaming state (in the MB) is not prescribed), and all the winning numbers described above are prescribed. It may be possible to determine whether or not the winning combination is based on the lottery value, and thereafter, all the small combinations may be further determined as internal winning combinations. At this time, for example, when “F_RB + F_normal lip” (winning number “71”) is won, only “F_normal lip” is determined as an internal winning combination for control purposes (that is, “F_RB” is a hit request) The flag storage area (see FIG. 25 described later) and the carryover combination storage area (see FIG. 26 described later) may not be stored. Thereby, the data capacity concerning an internal lottery table can be reduced.

  Also, in the MB gaming state, the internal winning combination in the MB gaming state can be determined by combining the internal winning combination that can be determined in the MB gaming state (that is, only all the small combinations or all the small combinations and each replay combination). The internal lottery table for the MB gaming state (in MB) may be provided by defining a lottery value corresponding to the RT state for each internal winning combination in the MB gaming state. That is, when an internal lottery table in the MB gaming state (in MB) is provided, an internal combination of all the small combinations and the replay combinations (winning numbers “1” to “49”) shown in FIG. 15 and FIG. A winning combination is defined, and for the internal winning combination, a lottery value that is the same as the lottery value defined for each replay combination is defined for each RT state, and the lottery value defined for each RT state from “65536”. What is necessary is just to prescribe | regulate the value which reduced the total value as a lottery value of the internal winning combination from which all the small combinations are determined.

  This eliminates the need for MB game state-specific control (S319 and S320, which will be described later) in the internal lottery process (see 84, which will be described later), thereby reducing the control burden in the internal lottery process. Since the processing procedure of the internal lottery process can be made common regardless of whether or not is provided, the number of man-hours for design can be reduced. In this case, as the winning number of the internal winning combination in the MB gaming state, the winning number following the winning number specified in the other gaming state can be specified, or the same winning number as the other gaming state is specified. You can also In the latter case, it is only necessary to separately define data that can identify that the “corresponding symbol combination” changes depending on the winning number between the MB gaming state and the other gaming states.

  In the present embodiment, when an internal winning combination is determined, it is permitted (allowed) to display a combination of one or more symbols on the active line. The combinations of symbols permitted to be displayed on the effective line are as shown in “corresponding symbol combinations” shown in FIGS. 15 and 16.

  For example, “F_7 Lip_ALL” is a combination of symbols of “REP95” (name: C_B_7REP) described later, and “REP98” (name: C_CU_7REP_A_1) to “REP101” (name: C_CU_7REP_B_2) (FIGS. 17 to 21 described later). Is an internal winning combination that is allowed to be displayed on the active line, and when the gaming state is the RT0 state, the RT4 state, and the RT5 state, it is not determined as the internal winning combination (that is, the lottery value is “0”). Is determined as an internal winning combination with the probability of “4/65536” when the gaming state is the RT1 state and the RT2 state, and with the probability of “8/65536” when the gaming state is the RT3 state. It is determined as an internal winning combination, and the gaming state is RB gaming state (in RB). Also, as described above, in the MB gaming state By lottery value of RT state is taken over, lottery is performed.

  Further, for example, “F_6 selection bell_123A” includes “NML17” (name: C_1 single combination A_2nd_A_1), “NML18” (name: C_1 single combination A_2nd_A_2), “NML39” (name: C_1 single combination A_3rd_D_1), "NML40" (name: C_1 sheet combination A_3rd_D_2), "NML59" (name: C_1 sheet combination A_3rd_N_1), "NML60" (name: C_1 sheet combination A_3rd_N_2), "NML65" (name: C_1 sheet combination B_1st_M_1) ”(Name: C_1 single combination B_1st_A_2) and“ NML90 ”(name: C_CD_BEL) are combinations that are permitted to be displayed on the active line (see FIGS. 17 to 21 described later). , Gaming state is RT0 to RT5 state (ie, In the bonus state), it is determined as an internal winning combination with a probability of “1090/65536”, and is not determined as an internal winning combination in other game states (ie, bonus state) (ie, “0” is determined in the lottery value). Stipulated).

  As will be described in detail later, “F_6 option bell_123A” (also “F_6 option bell_123B” to “F_6 option bell_321B”) is determined as an internal winning combination, and so-called “missing” occurs. In this case, as shown in FIGS. 15 and 16, any combination of symbols from “HZR1” (name: R_1st_A_1) to “HZR25” (name: R_2nd_A), which will be described later, is displayed on the effective line. Yes. In this sense, “F_6 selection bell_123A” is an internal winning combination that allows the combination of symbols of “HZR1” (name: R_1st_A_1) to “HZR25” (name: R_2nd_A), which will be described later, to be displayed on the active line. It can be said that it is.

  Although not shown in the figure, the lottery value of at least a part of the replay combination and / or the small combination is changed by changing the set value. Of course, the bonus combination may also be able to change the lottery value. Specifically, when a predetermined probability variation start condition is satisfied, the lottery value of the bonus combination is high (that is, the bonus combination is lottery with a high probability) until the predetermined probability variation end condition is satisfied. An internal lottery process may be performed by a table. In this case, the predetermined probability variation start condition and the predetermined probability variation end condition can be appropriately set as arbitrary conditions during the game.

[Design combination table]
Next, with reference to FIGS. 17-21, the symbol combination table which prescribes | regulates the symbol combination which concerns on winning and action | operation (namely, establishment) in this embodiment is demonstrated.

  As shown in FIGS. 17 to 21, the symbol combination table prescribes a plurality of symbol combinations, and prescribes data indicating the type of these symbol combinations as a display combination (winning action flag). Yes. The symbol combination table is composed of 37-byte data so as to correspond to a winning request flag storage region, a winning action flag storage region (see FIG. 25 described later), and a symbol code storage region (refer to FIG. 30 described later). In addition, data indicating a different display combination (winning operation flag) is defined for each bit of each storage area.

  The display combinations (winning operation flags) “HZR1” to “HZR28” are symbol combinations that are out of place, but are symbol combinations defined as symbol combinations that shift the RT state to the RT1 state (“RT1 transition symbol”). is there. In addition, the display combinations (winning operation flags) “HZR29” to “HZR36” are combinations of outlying symbols, but “F_1 single combination A” or “F_1 single combination B” is determined as an internal winning combination. Thus, when a so-called “missing” occurs, it is a combination of symbols defined as a combination of symbols referred to for control.

  The display combination (winning operation flag) “RB”, “MB1”, “MB2-1” and “MB2-2” are combinations of symbols related to the bonus combination, and each combination of symbols is displayed (established). Then activate the corresponding bonus state. The combination of symbols “MB2-1” and “MB2-2” can also be collectively referred to as a combination of symbols “MB2”.

  In addition, the display combinations (winning operation flags) “REP1” to “REP116” are combinations of symbols related to the replay combination, and each combination of symbols is displayed (established) to activate the replay. Note that the symbol combinations “REP1” to “REP6” are “normal lip” symbols, and the symbol combinations “REP9” to “REP33” are used to change the RT state to the RT1 state. “RT1 transition” (RT1 transition lip) symbol combinations, and the symbol combinations “REP34” to “REP65” are symbols of “RT2 transition” (RT2 transition lip) that transitions the RT state to the RT2 state. The combination of symbols “REP66” to “REP73” is a combination of symbols “RT3 transition” (RT3 transition lip) for shifting the RT state to the RT3 state, and the symbol “REP74”. Is a combination of symbols of “RT4 transition” (RT4 transition lip) for transitioning the RT state to the RT4 state.

  In addition, the symbol combinations “REP78” to “REP101” are symbol combinations “7-matched lip”. Here, “7-set lip” means that 7 lines (in this embodiment, “White 7-1” and “White” are displayed on one line on the reel display window 4 regardless of whether the line is an effective line or not. 7-2 "symbol) means a combination of symbols that allows the symbols to be arranged. The symbol combinations “REP102” to “REP114” are the symbol combinations “chance lip”, and the symbol combinations “REP115” to “REP116” are the symbol combinations “belllip”. . Here, “bell lip” means that a bell symbol (“bell” symbol in the present embodiment) is arranged on one line (cross-up line in the present embodiment) on the reel display window 4 other than the effective line. It means a combination of symbols that makes it possible.

  In addition, the display combinations (winning operation flags) “NML1” to “NML136” are combinations of symbols relating to the small combinations, and each combination of symbols is displayed (established), whereby a corresponding number of medals are paid out. . The symbol combination “NML1” to “NML88” is a combination of “1” symbol from which one medal is paid out, and the symbol combination of “NML90” is that 10 medals are paid out. "Nel 91" and "NML 92" symbols are combinations of symbols of "10 (bells: upper)" from which ten medals are paid out. It is. Here, “10 sheets (bell: upper stage)” means a bell symbol (in this embodiment, “bell”) on one line (in this embodiment, the top line) on the reel display window 4 other than the effective line. "Symbols" means a combination of symbols that allows the symbols to be arranged.

  The symbol combinations “NML93” to “NML96” are combinations of symbols “10 (bell: middle)” from which ten medals are paid out. Here, “10 sheets (bell: middle stage)” means a bell symbol (in this embodiment, “Bell”) on one line (in this embodiment, a center line) on the reel display window 4 other than the effective line. "Symbols" means a combination of symbols that allows the symbols to be arranged. The symbol combinations “NML97” to “NML100” are combinations of symbols “10 (bell: lower)” from which ten medals are paid out. Here, “10 sheets (bell: lower)” means that one line on the reel display window 4 (bottom line in this embodiment) other than the effective line is placed on a bell symbol (in this embodiment, “bell”). "Symbols" means a combination of symbols that allows the symbols to be arranged.

  The symbol combinations “NML101” to “NML113” are combinations of symbols in which 10 medals are paid out in the MB gaming state, and “10 ( It is a combination of symbols that can be either “normal”, “10 (rare: equivalent to upper or lower bell)” or “10 (rare: equivalent to middle bell)”. Note that “10 sheets (rare: equivalent to upper and lower bells)” means a lottery (or a lottery) related to the ART function with the same degree of expectation as the above-mentioned “10 sheets (bell: upper stage)” and “10 sheets (bell: lower stage)”. "10 (Rare: middle bell equivalent)" means lottery (or determination) regarding the ART function with the same degree of expectation as the above "10 (Bell: middle)" (See the column in which the internal winning combination in various lottery tables described later is “upper / lower bell” or “middle bell”). The symbol combinations “NML114” to “NML136” are combinations of “9” symbols from which nine medals are paid out in the MB gaming state.

[Correspondence table between internal winning combination, stop operation order (batting order) and display combination]
Next, with reference to FIG. 22 to FIG. 24, the correspondence among the internal winning combination, the stop operation order (batting order), the display combination and the like will be described. 22 and 23 are diagrams showing a correspondence table of the internal winning combination, stop operation order (batting order), display combination and the like in the gaming state excluding the MB gaming state, and FIG. 24 shows the internal winning combination in the MB gaming state. It is a figure which shows the corresponding | compatible table | surface with a winning combination, stop operation order (batting order), a display combination, etc. FIG.

  In the pachi-slot 1 of the present embodiment, a so-called “push order” is provided in which the symbol combinations displayed differ according to the stop operation order (push order) of the player. Since stop buttons 17L, 17C, and 17R corresponding to the reels 3L, 3C, and 3R are provided, there are a maximum of six stop operation orders (pushing orders).

  22 to 24, the stop operation order (push order) is “left, middle, right” is indicated as “batting order 1”, and the stop operation order (push order) is “left, right, middle”. ”Is shown as“ batting order 2 ”, the stop operation order (push order) is“ middle, left, right ”, as“ batting order 3 ”, and the stop operation order (push order) is The “middle, right, left” order is indicated as “batting order 4”, the stop operation order (push order) is indicated as “right, left, middle” as “batting order 5”, and the stop operation It is indicated as “batting order 6” that the order (pushing order) is “right, middle, left”.

  As shown in FIG. 22 and FIG. 23, in the gaming state excluding the MB gaming state (more specifically, the RT1 to RT3 state and the RB gaming state), “F_7 Lip_ALL” is not a push order but an internal winning combination. When the winning combination is determined, one of the winning “seven matching lips” is established regardless of the stop operation order and the stop operation timing.

  For example, in the left reel 3L, the symbol “white 7-1” constituting the symbol combination “C_CD — 7REP_A” (REP96) is arranged within 5 frames (within the range of 5 symbols), and the middle reel 3C The symbol “white 7-1” constituting the symbol combination “C_CD — 7REP_A” (REP96) is arranged within 5 frames (within the range of 5 symbols), and “C_CD — 7REP_A” (REP96) is arranged in the right reel 3R. The symbol “white 7-1” that constitutes the symbol combination is arranged within 5 frames (within the range of 5 symbols) (see FIG. 14). In other words, “regardless of the timing of the stop operation” means that in principle (ie, when the effective line is one line of “cross-down line” and the maximum number of sliding pieces is “4”), within 5 frames ( This means that the symbols are arranged within a range of five symbols). Hereinafter, the same applies to other display combinations (winning operation flag) and the like.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 to RT3 state and the RT5 state), “F_CD_Chance Lip” is stopped when it is determined as an internal winning combination instead of a push forward combination. Regardless of the operation order and the timing of the stop operation, one of the winning “chance replies” is established.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 to RT3 state and the RT5 state), “F_C_Chance Lip” is stopped when it is determined not as a push forward but as an internal winning combination. Regardless of the operation order and the timing of the stop operation, one of the winning “chance replies” is established.

  In addition, in the game state excluding the MB game state (more specifically, in the RT0 to RT3 state and the RT5 state), “F_CU_Bellip” is a stop operation when it is determined not as a push forward but as an internal winning combination. Regardless of the order and the timing of the stop operation, one of the winning “bell lips” is established.

  In addition, in the game states excluding the MB game state (more specifically, the RT0 state and the RT5 state), “F_normal lip” is not a pushing order but is determined as an internal winning combination. Regardless of the timing of the stop operation, one of the “normal replies” won is established.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 state and the RT5 state), “F_ART Rip” is determined not as a pushing order but as an internal winning combination, Regardless of the timing of the stop operation, one of the “normal lips” that is won is established.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT2 transition_123” is a push order combination, and when the internal winning combination is determined, ", Regardless of the timing of the stop operation, one of the winning" RT2 transition "(RT2 transition lip) is established, and the RT state transitions to the RT2 state. On the other hand, if the stop operation order is other than “batting order 1”, one of the other replay winning combinations is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and RT1 State is maintained (maintained).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT2 transition_132” is a push order combination, and when it is determined as an internal winning combination, ", Regardless of the timing of the stop operation, one of the winning" RT2 transition "(RT2 transition lip) is established, and the RT state transitions to the RT2 state. On the other hand, if the stop operation order is other than “batting order 2”, one of the other replay winning combinations is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and RT1 State is maintained (maintained).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT2 transition_213” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 3 ", Regardless of the timing of the stop operation, one of the winning" RT2 transition "(RT2 transition lip) is established, and the RT state transitions to the RT2 state. On the other hand, if the stop operation order is other than “batting order 3”, regardless of the timing of the stop operation, one of the other replay winning combinations is established, the RT state does not shift to the RT2 state, and RT1 State is maintained (maintained).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT2 transition_231” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 4 ", Regardless of the timing of the stop operation, one of the winning" RT2 transition "(RT2 transition lip) is established, and the RT state transitions to the RT2 state. On the other hand, if the stop operation order is other than “batting order 4”, regardless of the timing of the stop operation, one of the other replay winning combinations is established, the RT state does not shift to the RT2 state, and RT1 State is maintained (maintained).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT2 transition_312” is a push order combination, and when it is determined as an internal winning combination, ", Regardless of the timing of the stop operation, one of the winning" RT2 transition "(RT2 transition lip) is established, and the RT state transitions to the RT2 state. On the other hand, if the stop operation order is other than “batting order 5”, regardless of the timing of the stop operation, one of the other replay winning combinations is established, the RT state does not shift to the RT2 state, and RT1 State is maintained (maintained).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 state), “F_RT2 transition_321” is a push order combination, and when the internal winning combination is determined, ", Regardless of the timing of the stop operation, one of the winning" RT2 transition "(RT2 transition lip) is established, and the RT state transitions to the RT2 state. On the other hand, if the stop operation order is other than “batting order 6”, one of the other replay winning combinations is established regardless of the timing of the stop operation, the RT state does not shift to the RT2 state, and RT1 State is maintained (maintained).

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT3 transition_123” is a push order combination, and when it is determined as an internal winning combination, ", Regardless of the timing of the stop operation, one of the winning" RT3 transition "(RT3 transition lip) is established, and the RT state transitions to the RT3 state. On the other hand, if the stop operation order is other than “batting order 1”, any of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state is changed to the RT1 state. Transition.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT3 transition_132” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order 2”. ", Regardless of the timing of the stop operation, one of the winning" RT3 transition "(RT3 transition lip) is established, and the RT state transitions to the RT3 state. On the other hand, if the stop operation order is other than “batting order 2”, one of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state is changed to the RT1 state. Transition.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT3 transition_213” is a pushing order, and when it is determined as an internal winning combination, the stop operation order is “batting order 3 ", Regardless of the timing of the stop operation, one of the winning" RT3 transition "(RT3 transition lip) is established, and the RT state transitions to the RT3 state. On the other hand, if the stop operation order is other than “batting order 3”, one of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state is changed to the RT1 state. Transition.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT3 transition_231” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 4 ", Regardless of the timing of the stop operation, one of the winning" RT3 transition "(RT3 transition lip) is established, and the RT state transitions to the RT3 state. On the other hand, if the stop operation order is other than “batting order 4”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state becomes the RT1 state Transition.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT3 transition_312” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 5”. ", Regardless of the timing of the stop operation, one of the winning" RT3 transition "(RT3 transition lip) is established, and the RT state transitions to the RT3 state. On the other hand, if the stop operation order is other than “batting order 5”, any of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state is changed to the RT1 state. Transition.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT2 state), “F_RT3 transition_321” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 6”. ", Regardless of the timing of the stop operation, one of the winning" RT3 transition "(RT3 transition lip) is established, and the RT state transitions to the RT3 state. On the other hand, if the stop operation order is other than “batting order 6”, any of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state is changed to the RT1 state. Transition.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT4 transition_123” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 1 ", Regardless of the timing of the stop operation, one of the winning" RT4 transition "(RT4 transition lip) is established, and the RT state transitions to the RT4 state. On the other hand, if the stop operation order is “batting order 2” to “batting order 4”, one of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT1 state. Further, if the stop operation order is “batting order 5” and “batting order 6”, any of the other replay roles that are won is established regardless of the timing of the stopping operation, and the RT state is also changed to the RT4 state. The RT3 state is maintained (maintained) without shifting to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT4 transition_132” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 2 ", Regardless of the timing of the stop operation, one of the winning" RT4 transition "(RT4 transition lip) is established, and the RT state transitions to the RT4 state. On the other hand, if the stop operation order is “batting order 1”, “batting order 5”, and “batting order 6”, any of the winning “RT1 transition” (RT1 transition lip) is won regardless of the timing of the stop operation. The RT state shifts to the RT1 state. Further, if the stop operation order is “batting order 3” and “batting order 4”, any of the other replay winning combinations is established regardless of the timing of the stopping operation, and the RT state is also changed to the RT4 state. The RT3 state is maintained (maintained) without shifting to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT4 transition_213” is a push order combination, and when it is determined as an internal winning combination, ", Regardless of the timing of the stop operation, one of the winning" RT4 transition "(RT4 transition lip) is established, and the RT state transitions to the RT4 state. On the other hand, if the stop operation order is “batting order 4” to “batting order 6”, one of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT1 state. Also, if the stop operation order is “batting order 1” and “batting order 2”, any of the other replay winning combinations is established regardless of the timing of the stopping operation, and the RT state is also changed to the RT4 state. The RT3 state is maintained (maintained) without shifting to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT4 transition_231” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 4”. ", Regardless of the timing of the stop operation, one of the winning" RT4 transition "(RT4 transition lip) is established, and the RT state transitions to the RT4 state. On the other hand, if the stop operation order is “batting order 1” to “batting order 3”, one of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT1 state. Further, if the stop operation order is “batting order 5” and “batting order 6”, any of the other replay roles that are won is established regardless of the timing of the stopping operation, and the RT state is also changed to the RT4 state. The RT3 state is maintained (maintained) without shifting to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT4 transition_312” is a push order combination, and when it is determined as an internal winning combination, the stop operation order is “batting order 5”. ", Regardless of the timing of the stop operation, one of the winning" RT4 transition "(RT4 transition lip) is established, and the RT state transitions to the RT4 state. On the other hand, if the stop operation order is “batting order 1”, “batting order 2”, and “batting order 6”, any one of the winning “RT1 transition” (RT1 transition lip) is determined regardless of the timing of the stop operation. The RT state shifts to the RT1 state. Further, if the stop operation order is “batting order 3” and “batting order 4”, any of the other replay winning combinations is established regardless of the timing of the stopping operation, and the RT state is also changed to the RT4 state. The RT3 state is maintained (maintained) without shifting to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_RT4 transition_321” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 6 ", Regardless of the timing of the stop operation, one of the winning" RT4 transition "(RT4 transition lip) is established, and the RT state transitions to the RT4 state. On the other hand, if the stop operation order is “batting order 3” to “batting order 5”, one of the winning “RT1 transition” (RT1 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT1 state. Also, if the stop operation order is “batting order 1” and “batting order 2”, any of the other replay winning combinations is established regardless of the timing of the stopping operation, and the RT state is also changed to the RT4 state. The RT3 state is maintained (maintained) without shifting to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_7 Lip A_1st” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 1 ”And“ batting order 2 ”, one of the winning“ seven matching lips ”is established regardless of the timing of the stop operation. If the stop operation order is “batting order 3” and “batting order 4”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 5” and “batting order 6”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_7 Lip B_1st” is a push order combination, and when the internal winning combination is determined, ”And“ batting order 2 ”, one of the winning“ seven matching lips ”is established regardless of the timing of the stop operation. If the stop operation order is “batting order 5” and “batting order 6”, one of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 3” and “batting order 4”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_7 Lip A_2nd” is a push order combination, and when the internal winning combination is determined, ”And“ Batting order 4 ”, one of the winning“ seven matching lips ”is established regardless of the timing of the stop operation. If the stop operation order is “batting order 5” and “batting order 6”, one of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 1” and “batting order 2”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_7 Lip B_2nd” is a push order combination, and when the internal winning combination is determined, the stop operation order is “batting order 3 ”And“ Batting order 4 ”, one of the winning“ seven matching lips ”is established regardless of the timing of the stop operation. If the stop operation order is “batting order 1” and “batting order 2”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 5” and “batting order 6”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_7 Lip A_3rd” is a pushing order, and when the internal winning combination is determined, the stop operation order is “batting order 5”. ”And“ batting order 6 ”, one of the winning“ seven matching lips ”is established regardless of the timing of the stop operation. If the stop operation order is “batting order 1” and “batting order 2”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 3” and “batting order 4”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_7 Lip B_3rd” is a pushing order combination, and when the internal winning combination is determined, the stop operation order is “batting order 5 ”And“ batting order 6 ”, one of the winning“ seven matching lips ”is established regardless of the timing of the stop operation. If the stop operation order is “batting order 3” and “batting order 4”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 1” and “batting order 2”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_probability 7 lip A_1st” is a push order combination, and when it is determined as an internal winning combination, the stop operation order is “ In the case of “batting order 1” and “batting order 2”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. If the stop operation order is “batting order 3” and “batting order 4”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 5” and “batting order 6”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_probability 7 lip B_1st” is a push order combination, and when the internal winning combination is determined, In the case of “batting order 1” and “batting order 2”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. If the stop operation order is “batting order 5” and “batting order 6”, one of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 3” and “batting order 4”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_probability 7 lip A_2nd” is a push order combination, and when the internal winning combination is determined, In the case of “batting order 3” and “batting order 4”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. If the stop operation order is “batting order 5” and “batting order 6”, one of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 1” and “batting order 2”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_probability 7 lip B_2nd” is a pushing order combination, and when the internal winning combination is determined, In the case of “batting order 3” and “batting order 4”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. If the stop operation order is “batting order 1” and “batting order 2”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 5” and “batting order 6”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_probability 7 lip A_3rd” is a push order combination, and when the internal winning combination is determined, In the case of “batting order 5” and “batting order 6”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. If the stop operation order is “batting order 1” and “batting order 2”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 3” and “batting order 4”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT4 state), “F_probability 7 lip B_3rd” is a push order combination, and when the internal winning combination is determined, In the case of “batting order 5” and “batting order 6”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. If the stop operation order is “batting order 3” and “batting order 4”, any of the winning “RT3 transition” (RT3 transition lip) is established regardless of the timing of the stop operation, and the RT state Transitions to the RT3 state. If the stop operation order is “batting order 1” and “batting order 2”, regardless of the timing of the stop operation, one of the winning “RT1 transition” (RT1 transition lip) is established, and the RT state Transitions to the RT1 state.

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 to RT3 states), “F_7 Lip_123” is a pushing order combination, and when it is determined as an internal winning combination, the stop operation order is “ If it is “batting order 1”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 1”, one of the other replay winning combinations is established and the current RT state is maintained (maintained) regardless of the timing of the stop operation. .

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 to RT3 states), “F_7 Lip_132” is a push order combination, and when the internal winning combination is determined, In the case of “batting order 2”, any of the winning “seven matching lips” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 2”, any of the other replay winning combinations is established regardless of the timing of the stop operation, and the current RT state is maintained (maintained). .

  In addition, in the game states (more specifically, the RT1 to RT3 states) excluding the MB game state, “F_7 lip — 213” is a push order combination, and when the internal winning combination is determined, If the hitting order is “3”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 3”, any of the other replay winning combinations is established and the current RT state is maintained (maintained) regardless of the timing of the stop operation. .

  In addition, in the game states (more specifically, the RT1 to RT3 states) excluding the MB game state, “F_7 lip — 231” is a pushing order combination, and when the internal winning combination is determined, In the case of “batting order 4”, any of the winning “seven matching lips” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 4”, one of the other replay winning combinations is established and the current RT state is maintained (maintained) regardless of the timing of the stop operation. .

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT1 to RT3 states), “F_7 Lip — 312” is a push order combination, and when the internal winning combination is determined, If the hit order is “5”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 5”, any of the other replay winning combinations is established regardless of the timing of the stop operation, and the current RT state is maintained (maintained). .

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT1 to RT3 states), “F_7 Lip_321” is a push order combination, and when the internal winning combination is determined, If the hit order is “6”, one of the winning “seven matching lips” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 6”, any of the other replay winning combinations is established regardless of the timing of the stop operation, and the current RT state is maintained (maintained). .

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_chance lip_123” is a push order combination, and when the internal winning combination is determined, If “1”, one of the winning “chance replies” is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 1”, one of the other replay winning combinations is established and the current RT state is maintained (maintained) regardless of the timing of the stop operation. .

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_chance lip_132” is a push order combination, and when the internal winning combination is determined, If it is “2”, one of the “chance replies” won is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 2”, any of the other replay winning combinations is established regardless of the timing of the stop operation, and the current RT state is maintained (maintained). .

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_Chance Lip_213” is a push order combination, and when the internal winning combination is determined, If “3”, regardless of the timing of the stop operation, one of the winning “chance replies” is established. On the other hand, if the stop operation order is other than “batting order 3”, any of the other replay winning combinations is established and the current RT state is maintained (maintained) regardless of the timing of the stop operation. .

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT3 state), “F_Chance Lip_231” is a push order combination, and when the internal winning combination is determined, If it is “4”, one of the “chance lips” won is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 4”, one of the other replay winning combinations is established and the current RT state is maintained (maintained) regardless of the timing of the stop operation. .

  Further, in the gaming state excluding the MB gaming state (more specifically, the RT3 state), “F_chance lip — 312” is a push order combination, and when the internal winning combination is determined, If it is “5”, one of the “chance replies” won is established regardless of the timing of the stop operation. On the other hand, if the stop operation order is other than “batting order 5”, any of the other replay winning combinations is established regardless of the timing of the stop operation, and the current RT state is maintained (maintained). .

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the RT3 state), “F_Chance Lip_321” is a push order combination, and when the internal winning combination is determined, If “6”, regardless of the timing of the stop operation, one of the winning “chance replies” is established. On the other hand, if the stop operation order is other than “batting order 6”, any of the other replay winning combinations is established regardless of the timing of the stop operation, and the current RT state is maintained (maintained). .

  In addition, in the game states excluding the MB game state (more specifically, the states of RT0 to RT4), “F_6 option bell_123A” and “F_6 option bell_123B” are push forwards and are determined as internal winning combinations. In this case, if the stop operation order is “batting order 1”, “10 (bell)” is established regardless of the timing of the stop operation, and 10 medals are paid out. On the other hand, if the stop operation order is other than “batting order 1”, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing is not an appropriate timing, one of the associated “RT1 transition symbols” is established. In this case, if the RT state is the RT0 state and the RT2 to RT4 states, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is determined when the stop operation order is “batting order 2” (that is, when the stop operation order of the first stop operation is appropriate) or when the third stop operation is performed. ½ of all the stop operation timings in (1) is an appropriate timing (“one (1/2)”), and the stop operation order is other than “batting order 1” and “batting order 2” (that is, , The stop operation sequence of the first stop operation is not appropriate), 1/4 of all the stop operation timings during the second stop operation, and all the stop operation timings during the third stop operation. The timing of 1/2 (that is, 1/4 × 1/2 = 1/8 as a whole) is an appropriate timing (“one sheet (1/8)”). In the RT5 state, the combination of symbols that are controlled to stop preferentially varies, and when the stop operation order is other than “batting order 1” and “batting order 2”, “10 sheets (bell ) "And 10 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the state of RT0 to RT4), “F_6 selection bell_132A” and “F_6 selection bell_132B” are push forwards and are determined as internal winning combinations. In this case, if the stop operation order is “batting order 2”, “10 (bell)” is established regardless of the timing of the stop operation, and 10 medals are paid out. On the other hand, if the stop operation order is other than “batting order 2”, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing is not an appropriate timing, one of the associated “RT1 transition symbols” is established. In this case, if the RT state is the RT0 state and the RT2 to RT4 states, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is determined when the stop operation order is “batting order 1” (that is, when the stop operation order of the first stop operation is appropriate) or during the third stop operation. 1/2 of the timings of all the stop operations in (1) is an appropriate timing (“one (1/2)”), and the stop operation order is other than “batting order 2” and “batting order 1” (ie , The stop operation sequence of the first stop operation is not appropriate), 1/4 of all the stop operation timings during the second stop operation, and all the stop operation timings during the third stop operation. The timing of 1/2 (that is, 1/4 × 1/2 = 1/8 as a whole) is an appropriate timing (“one sheet (1/8)”). In the RT5 state, the combination of symbols that are controlled to stop preferentially fluctuates, and when the stop operation order is other than “batting order 2” and “batting order 1”, “10 sheets (bell ) "And 10 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the state of RT0 to RT4), “F_6 selection bell_213A” and “F_6 selection bell_213B” are pushing orders and determined as internal winning combinations. In this case, if the stop operation order is “batting order 3”, “10 (bell)” is established regardless of the timing of the stop operation, and 10 medals are paid out. On the other hand, if the stop operation order is other than “batting order 3”, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing is not an appropriate timing, one of the associated “RT1 transition symbols” is established. In this case, if the RT state is the RT0 state and the RT2 to RT4 states, the state shifts to the RT1 state. Whether or not the timing of the stop operation is an appropriate timing is determined when the stop operation order is “batting order 4” (that is, when the stop operation order of the first stop operation is appropriate) or during the third stop operation. ½ of all the stop operation timings in (1) is an appropriate timing (“one (1/2)”), and the stop operation order is other than “batting order 3” and “batting order 4” (that is, , The stop operation sequence of the first stop operation is not appropriate), 1/4 of all the stop operation timings during the second stop operation, and all the stop operation timings during the third stop operation. The timing of 1/2 (that is, 1/4 × 1/2 = 1/8 as a whole) is an appropriate timing (“one sheet (1/8)”). In the RT5 state, the combination of symbols that are controlled to stop preferentially fluctuates, and if the stop operation order is other than “batting order 3” and “batting order 4”, “10 cards (bell ) "And 10 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the states of RT0 to RT4), “F_6 option bell_231A” and “F_6 option bell_231B” are pushing orders and are determined as internal winning combinations. In this case, if the stop operation order is “batting order 4”, “10 (bell)” is established regardless of the timing of the stop operation, and 10 medals are paid out. On the other hand, if the stop operation order is other than “batting order 4”, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing is not an appropriate timing, one of the associated “RT1 transition symbols” is established. In this case, if the RT state is the RT0 state and the RT2 to RT4 states, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is determined when the stop operation order is “batting order 3” (that is, when the stop operation order of the first stop operation is appropriate) or when the third stop operation is performed. ½ of all the stop operation timings in (2) is an appropriate timing (“one (1/2)”), and the stop operation order is other than “batting order 4” and “batting order 3” (that is, , The stop operation sequence of the first stop operation is not appropriate), 1/4 of all the stop operation timings during the second stop operation, and all the stop operation timings during the third stop operation. The timing of 1/2 (that is, 1/4 × 1/2 = 1/8 as a whole) is an appropriate timing (“one sheet (1/8)”). In the RT5 state, the combination of symbols that are controlled to stop preferentially fluctuates, and when the stop operation order is other than “batting order 4” and “batting order 3”, “10 sheets (bell ) "And 10 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 to RT4 states), “F_6 option bell_312A” and “F_6 option bell_312B” are push forwards and are determined as internal winning combinations. In this case, if the stop operation order is “batting order 5”, “10 (bell)” is established regardless of the timing of the stop operation, and 10 medals are paid out. On the other hand, if the stop operation order is other than “batting order 5”, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing is not an appropriate timing, one of the associated “RT1 transition symbols” is established. In this case, if the RT state is the RT0 state and the RT2 to RT4 states, the state shifts to the RT1 state. Whether or not the timing of the stop operation is an appropriate timing is determined when the stop operation order is “batting order 6” (that is, when the stop operation order of the first stop operation is appropriate) or during the third stop operation. 1/2 of the timings of all the stop operations in (1) is an appropriate timing (“one sheet (1/2)”), and the stop operation order is other than “batting order 5” and “batting order 6” (ie , The stop operation sequence of the first stop operation is not appropriate), 1/4 of all the stop operation timings during the second stop operation, and all the stop operation timings during the third stop operation. The timing of 1/2 (that is, 1/4 × 1/2 = 1/8 as a whole) is an appropriate timing (“one sheet (1/8)”). In the RT5 state, the combination of symbols that are controlled to stop preferentially fluctuates, and when the stop operation order is other than “batting order 5” and “batting order 6”, “10 sheets (bell) ) "And 10 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the states of RT0 to RT4), “F_6 selection bell_321A” and “F_6 selection bell_321B” are pushing orders and are determined as internal winning combinations. In this case, if the stop operation order is “batting order 6”, “10 (bell)” is established regardless of the timing of the stop operation, and 10 medals are paid out. On the other hand, if the stop operation order is other than “batting order 6”, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing is not an appropriate timing, one of the associated “RT1 transition symbols” is established. In this case, if the RT state is the RT0 state and the RT2 to RT4 states, the state shifts to the RT1 state. Whether or not the timing of the stop operation is appropriate is determined when the stop operation order is “batting order 5” (that is, when the stop operation order of the first stop operation is appropriate) or when the third stop operation is performed. ½ of all the stop operation timings in (1) is an appropriate timing (“one (1/2)”), and the stop operation order is other than “batting order 6” and “batting order 5” (ie , The stop operation sequence of the first stop operation is not appropriate), 1/4 of all the stop operation timings during the second stop operation, and all the stop operation timings during the third stop operation. The timing of 1/2 (that is, 1/4 × 1/2 = 1/8 as a whole) is an appropriate timing (“one sheet (1/8)”). In the RT5 state, the combination of symbols that are controlled to stop preferentially fluctuates, and when the stop operation order is other than “batting order 6” and “batting order 5”, “10 sheets (bell) ) "And 10 medals are paid out.

  In addition, in the game states (more specifically, the RT0 to RT5 states) excluding the MB game state, “F_common bell” is determined not to be a push order but an internal winning combination, Regardless of the timing of the stop operation, “10 (bell)” is established and 10 medals are paid out.

  In addition, in the game states excluding the MB game state (more specifically, the states of RT0 to RT5), when “F_T_Rarebell” is determined not as a pushing order but as an internal winning combination, Regardless of the operation timing, “10 (bell: upper)” is established and 10 medals are paid out.

  In addition, in the game state excluding the MB game state (more specifically, the states of RT0 to RT5), when “F_B_rarebell” is determined not as a pushing order but as an internal winning combination, Regardless of the operation timing, “10 (bell: lower)” is established, and 10 medals are paid out.

  In addition, in the game state excluding the MB game state (more specifically, the states of RT0 to RT5), when “F_C_Rarebell” is determined as an internal winning combination instead of a pushing order, Regardless of the operation timing, “10 (bell: middle)” is established, and 10 medals are paid out.

  In addition, in the gaming state excluding the MB gaming state (more specifically, in the state of RT0 to RT5), “F_1 single combination A” and “F_1 single combination B” are determined as internal winning combinations instead of pushing forwards. In this case, if the timing of the stop operation is an appropriate timing, the winning “one” is established and one medal is paid out. If the timing of the stop operation is not an appropriate timing, ”Occurs, and medals are not paid out. However, in this case, the current RT state is maintained.

  Further, in the RB gaming state, when “F_RB combination” is determined not as a pressing combination but as an internal winning combination, “10 (bell)” is displayed regardless of the stop operation order and the stop operation timing. It is established and 10 medals are paid out.

  In addition, in the game state excluding the MB game state (more specifically, the states of RT0 to RT4), when “F_MB_L” is determined as an internal winning combination instead of a pushing order, a stop operation sequence and a stop operation are performed. Regardless of the timing, “MB1” is established, and the gaming state shifts to the MB gaming state (MB1 gaming state).

  In addition, in the game states excluding the MB game state (more specifically, in the RT0 to RT4 states), when “F_MB_S” is determined not as a pushing order but as an internal winning combination, a stop operation sequence and a stop operation are performed. Regardless of the timing, “MB2” is established, and the gaming state shifts to the MB gaming state (MB2 gaming state).

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 to RT4 states. However, as described above, the MB gaming state may be included), “F_RB” is not a pushing order but an internal winning combination. If “F_RB” becomes a carryover combination and the winning state is carried over, and the RT state transitions to the RT5 state and the timing of the stop operation is appropriate, “RB” is established. Then, the gaming state shifts to the RB gaming state. On the other hand, if the timing of the stop operation is not an appropriate timing, “missing” occurs in the unit game. In addition, when “F_RB” is carried over and a replay combination or small combination is determined as an internal winning combination (the same applies when “F_RB + F_normal lip” below is determined as an internal winning combination) Since the replay role and the small role are controlled to stop more preferentially than the role “F_RB”, the “RB” can be established even when the timing of the stop operation is appropriate. The game is limited to games that are not won by overlapping roles.

  In addition, in the gaming state excluding the MB gaming state (more specifically, the RT0 to RT4 states. However, as described above, the MB gaming state may be included), “F_RB + F_normal lip” When it is determined as a winning combination, “F_RB” becomes a carryover combination and the winning state is carried over, and the RT state shifts to the RT5 state. In the unit game, the stop operation order and the stop operation timing are set. Regardless, one of the winning “normal lips” is established.

  In this embodiment, when the replay role or small role and the bonus role are determined to overlap as an internal winning role (including the case where the bonus role is carried over), the replay role or small role is more effective than the bonus role. However, stop control for preferentially establishing a bonus combination over a replay combination or small combination may be performed.

  As shown in FIG. 24, in the MB gaming state, “F_RT2 transition_123”, “F_RT2 transition_132”, “F_RT2 transition_213”, “F_RT2 transition_231”, “F_RT2 transition_312”, “F_RT3 transition_132”, “F_RT3” "Transition_213", "F_RT3 transition_231", "F_RT3 transition_312", and "F_RT3 transition_321" are determined to be the stop operation order and the timing of the stop operation when determined as an internal winning combination instead of the push order combination. Regardless, “10 (normal)” is established, and 10 medals are paid out. The same applies to the case where the player has not won the replay role (“other than the following” in FIG. 24).

  In the MB gaming state, “F_7 Lip_ALL”, “F_CD_Chance Lip”, “F_C_Chance Lip”, “F_Normal Lip”, “F_ART Lip”, “F_RT2 Transition_321”, “F_RT3 Transition_123”, “F_ “Clip 7 Lip B_2nd”, “F_Clip 7 Lip B_3rd”, “F_7 Lip_123” to “F_7 Lip_321”, and “F_Chanch Lip_123” to “F_Chanch Lip_321” are not pushing orders but are internal winnings. When it is determined as a winning combination, regardless of the stop operation order and the stop operation timing, “10 (rare: equivalent to upper / lower bell)” is established, and 10 medals are paid out.

  Further, in the MB gaming state, when “F_CU_Bell Lip” and “F_Success 7 Lip B_1st” are determined as an internal winning combination instead of a pushing order, regardless of the stop operation order and the timing of the stop operation, “10 (Rare: Middle bell equivalent)” is established, and 10 medals are paid out.

  Further, in the MB gaming state, “F_RT4 transition_123” is a push order, and if the stop operation order is “batting order 1”, “9 cards” is established regardless of the timing of the stop operation, and 9 cards Medals will be paid out. On the other hand, if the stop operation order is other than “batting order 1”, “10 (normal)” is established regardless of the timing of the stop operation, and 10 medals are paid out.

  Further, in the MB gaming state, “F_RT4 transition_132” is a push order, and if the stop operation order is “batting order 2”, “9 cards” is established regardless of the timing of the stop operation, and 9 cards Medals will be paid out. On the other hand, if the stop operation order is other than “batting order 2”, “10 (normal)” is established regardless of the timing of the stop operation, and 10 medals are paid out.

  Further, in the MB gaming state, “F_RT4 transition_213” is a push order, and if the stop operation order is “batting order 3”, “9 cards” is established regardless of the timing of the stop operation, and 9 cards Medals will be paid out. On the other hand, if the stop operation order is other than “batting order 3”, “10 (normal)” is established regardless of the stop operation timing, and 10 medals are paid out.

  In the MB gaming state, “F_RT4 transition_231” is a push order, and if the stop operation order is “batting order 4”, “9 cards” is established regardless of the timing of the stop operation, and 9 cards Medals will be paid out. On the other hand, if the stop operation order is other than “batting order 4”, “10 (normal)” is established regardless of the timing of the stop operation, and 10 medals are paid out.

  In the MB gaming state, “F_RT4 transition_312” is a push order, and if the stop operation order is “batting order 5”, “9 cards” is established regardless of the timing of the stop operation, and 9 cards Medals will be paid out. On the other hand, if the stop operation order is other than “batting order 5”, “10 (normal)” is established regardless of the timing of the stop operation, and 10 medals are paid out.

  Further, in the MB gaming state, “F_RT4 transition_321” is a push order, and if the stop operation order is “batting order 6”, “9 cards” is established regardless of the timing of the stop operation, and 9 cards Medals will be paid out. On the other hand, if the stop operation order is other than “batting order 6”, “10 (normal)” is established regardless of the timing of the stop operation, and 10 medals are paid out.

  Further, in the MB gaming state, “F_7 Lip A_1st”, “F_7 Lip B_1st”, and “F_Success 7 Lip A_1st” are pushing orders, and the stop operation order is “batting order 1” and “batting order 2” (that is, If the left reel 3L is the first stop), “9” is established regardless of the timing of the stop operation, and 9 medals are paid out. On the other hand, if the stop operation order is other than “batting order 1” and “batting order 2”, “10 (normal)” is established regardless of the timing of the stopping operation, and 10 medals are paid out.

  In the MB gaming state, “F_7 lip A_2nd”, “F_7 lip B_2nd”, and “F_probable 7 lip A_2nd” are pushing orders, and the stop operation order is “batting order 3” and “batting order 4” (ie, If the middle reel 3C is the first stop), “9” is established regardless of the timing of the stop operation, and 9 medals are paid out. On the other hand, if the stop operation order is other than “batting order 3” and “batting order 4”, “10 (normal)” is established regardless of the timing of the stopping operation, and 10 medals are paid out.

  In the MB gaming state, “F_7 lip A_3rd”, “F_7 lip B_3rd”, and “F_probability 7 lip A_3rd” are in the pushing order, and the stop operation order is “batting order 5” and “batting order 6” (that is, If the right reel 3R is the first stop), “9” is established regardless of the timing of the stop operation, and 9 medals are paid out. On the other hand, if the stop operation order is other than “batting order 5” and “batting order 6”, “10 (normal)” is established regardless of the timing of the stopping operation, and 10 medals are paid out.

  Here, in the MB gaming state, it is considered that the pushing order in which ten medals are paid out is always advantageous for the player. However, in this embodiment, the MB gaming state is “149” in the MB1 gaming state. In the MB2 gaming state, it is configured to end by paying out more than 9 medals, and in the MB1 gaming state, the MB2 gaming can be completed by any one game until the end. In the state, if 9 medals are paid out in the first game, the game in the MB gaming state can be performed once more, and 10 medals can be paid out. Become.

  Therefore, in the MB1 gaming state, any one game until the end, and in the MB2 gaming state, in the first game, when the above-mentioned pushing order is determined as the internal winning combination, nine medals The order in which the payouts are paid out is information on the stop operation that is advantageous to the player. In the MB1 game state, the other player games, in the MB2 game state, the second game, the above-mentioned push order is the internal winning combination. Is determined, the order in which the ten medals are paid out is information on the stop operation that is advantageous to the player.

  In the present embodiment, in the MB gaming state, whether 9 medals are paid out or 10 medals are paid out, whether or not the timing of the stop operation is an appropriate timing is determined. Although it is configured so that it is not required, if the timing of the stop operation is an appropriate timing so that the technical intervention of the game can be improved and the health of the game can be secured, 9 or 10 However, if the timing of the stop operation is not an appropriate timing, it may be configured such that nine or ten medals are not paid out.

  Further, in the present embodiment, in the MB gaming state, when the replay combination and the small combination are determined as the internal winning combination, stop control for preferentially establishing the small combination over the replay combination is performed. Although configured, stop control that preferentially establishes a replay combination over a small combination can also be performed.

  As described above with reference to FIG. 22 to FIG. 24, the pushing order that is advantageous for the player is uniquely defined in the pushing order. In the present embodiment, in principle, in a RUSH preparation state, a RUSH state, an ART state, a battle state, and a pull-back state, which will be described later, information on a stop operation indicating a pushing order that is advantageous to the player is notified. That is, in the gaming state other than the RT5 state which is the bonus winning state and the RB gaming state which is the bonus state, the RT state shifts to a more advantageous RT state or the advantageous RT state is maintained. Further, the stop operation order is notified as stop operation information so that the player can receive more medals.

  In this embodiment, stop operation information that is advantageous to the player is transmitted by an instruction monitor controlled by the main control board 71 and other means (for example, the display device 11) controlled by the sub control board 72. Informed.

  For example, when “batting order 1” and “batting order 2” are pushing orders that are advantageous to the player, a numerical value “1” is displayed on the instruction monitor, and the display device 11 displays the pushing order “1-−”. ”Is displayed, and“ batting order 3 ”and“ batting order 4 ”are pushing orders that are advantageous to the player, a numerical value“ 2 ”is displayed on the instruction monitor, and the pushing order“ -1- "is displayed, and when" batting order 5 "and" batting order 6 "are pushing orders advantageous to the player, a numerical value" 3 "is displayed on the instruction monitor, and the display device 11 displays The push order “--1” is displayed.

  Further, for example, when “batting order 1” is a pressing order that is advantageous to the player, a numerical value “4” is displayed on the instruction monitor, and a pressing order “123” is displayed on the display device 11. When the “batting order 2” is a pressing order that is advantageous to the player, a numerical value “5” is displayed on the instruction monitor, a pressing order “132” is displayed on the display device 11, and “batting order 3”. However, if the pressing order is advantageous to the player, the numerical value “6” is displayed on the instruction monitor, the pressing order “213” is displayed on the display device 11, and the “batting order 4” In the case of the pushing order that is advantageous to the player, the numerical value “7” is displayed on the instruction monitor, the pushing order “312” is displayed on the display device 11, and the “batting order 5” is advantageous to the player. In case of the pressing order, the indication monitor displays the value “8”. The display device 11 displays the push order “231”, and when the “batting order 6” is a push order that is advantageous to the player, a numerical value “9” is displayed on the instruction monitor, and the display device 11 Is displayed in the pressing order “321”.

  Of course, the manner in which the pushing order advantageous to the player is notified is not limited to the above, and any manner may be used as long as the player can recognize the pushing order advantageous. For example, instead of the instruction monitor and / or the display device 11, or in addition to this, the sub display device 18, the LED group 85, the speaker group 84, or the like can be used to notify the player of an advantageous push order. .

  In addition, as long as there is no disadvantage for the player, the instruction monitor and / or the display device 11 is notified of a push order other than the push order that is advantageous to the player for the purpose of enhancing the game performance and the effect. It can also be done.

  Here, the stop control (determination method of the stop symbol position) of the reel in the pachi-slot 1 of the present embodiment will be briefly described. In the present embodiment, after the stop operation is detected by the stop switch, the corresponding reel rotates so as to stop within 190 msec (within 75 msec for a specific reel (for example, the right reel 3R) in the MB gaming state). The stop control is performed. Specifically, the number of sliding symbols “0” to “4” (“0” or “1” for a specific reel in the MB gaming state) is set to the value of the symbol counter corresponding to the reel when the stop operation is detected. The symbol position corresponding to the obtained value is determined as the symbol position where the reel rotation stops (hereinafter referred to as “scheduled stop position”). The symbol position corresponding to the value of the symbol counter corresponding to the reel when the stop operation is detected is the symbol position at which the rotation of the reel starts to be stopped (hereinafter referred to as “stop start position”).

  That is, the number of sliding pieces is the amount of rotation of the reel from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. In other words, the number of symbols passing through the middle area of the corresponding reel in the reel display window 4 in the period from when the stop operation is detected by the stop switch until the rotation of the corresponding reel stops. This is grasped by the value of the symbol counter updated after the stop operation is detected by the stop switch.

  Referring to a stop table (not shown), the number of sliding pieces is acquired according to the stop start position of each reel. In the present embodiment, the number of sliding pieces is acquired based on the stop table, but this is a tentative one, and the acquired number of sliding pieces does not immediately determine the planned stop position of the reel. In the present embodiment, when there is a more appropriate number of sliding pieces than the number of sliding pieces acquired based on the stop table (hereinafter referred to as “sliding piece number determination data”), a drawing priority table (not shown) is referred to. To change the number of sliding pieces. The number-of-sliding piece determination data is used to compare the priorities of symbols from the stop start position to the symbol position that is the maximum number of sliding symbols four points ahead (one for a specific reel in the MB gaming state). Referenced to determine the search order when performing.

<Configuration of storage area provided in main RAM>
Next, the configuration of various storage areas provided in the main RAM 103 will be described with reference to FIGS.

[Hit request flag storage area and winning action flag storage area]
First, with reference to FIG. 25, the structure of a winning request flag storage area (internal winning combination storage area) and a winning action flag storage area (display combination storage area) will be described. In the present embodiment, the winning request flag storage area (flag data storage area, winning flag data storage area) and the winning action flag storage area (winning flag data storage area) have the same configuration.

  In the present embodiment, the winning request flag storage area is composed of winning request flag storage areas 1 to 37 each represented by 1-byte data, and the winning action flag storage area is a winning prize each represented by 1-byte data. It consists of working storage areas 1-37. Note that the data stored in the storage areas of the winning request flag storage area and the winning action flag storage area is only 1-byte data in the “data” column in FIG. 25. In FIG. “Combination” indicating the symbol combination of each reel associated with the bit of the storage area (in the drawing, described in the order of the symbol of the left reel 3L, the symbol of the middle reel 3C and the symbol of the right reel 3R), and The contents (see FIGS. 17 to 21) are also described.

  In each of the hit request flag storage areas 1 to 37, when “1” is stored in a predetermined bit, it indicates that the internal winning combination corresponding to the predetermined bit has been won internally. Further, in each of the winning action storage areas 1 to 37, when “1” is stored in a predetermined bit, it indicates that the winning combination (winning action flag) corresponding to the predetermined bit has been won (established). Show. That is, when “1” is stored in a predetermined bit, it indicates that the symbol combination corresponding to the predetermined bit is displayed on the active line.

  The winning request flag storage area and the winning action flag storage area may include one in which a plurality of symbol combinations (combinations) are assigned to one bit (flag) in each storage area.

[Coverage storage area]
Next, the configuration of the carryover combination storage area will be described with reference to FIG. In the present embodiment, the carryover combination storage area is composed of a 1-byte data storage area.

  When the internal winning combination “F_RB” is determined as a result of the internal lottery, the internal winning combination (bonus combination) is stored as a carryover combination in the carryover combination storage area. The carryover combination stored in the carryover combination storage area is held without being cleared until the corresponding symbol combination is displayed on the active line. Further, while the carryover combination is stored in the carryover combination storage area, the carryover combination is stored in the hit request flag storage area in addition to the internal winning combination determined by the internal lottery.

[Game state flag storage area]
Next, the configuration of the game state flag storage area will be described with reference to FIG. The gaming state flag storage area is composed of a 1-byte data storage area. In the present embodiment, as shown in FIG. 27, a unique bonus type or RT type is assigned to each bit in the gaming state flag storage area.

  When “1” is stored in a predetermined bit in the game state flag storage area, it indicates that the bonus game or RT corresponding to the predetermined bit is being operated. For example, when “1” is stored in bit 0 of the gaming state flag storage area, it indicates that the regular bonus “RB” is activated and the gaming state is the RB gaming state. For example, when “1” is stored in bit 6 of the gaming state flag storage area, it indicates that the gaming state is the RT4 state.

[Operation stop button storage area]
Next, the configuration of the operation stop button storage area will be described with reference to FIG. The operation stop button storage area is composed of a 1-byte data storage area and stores an operation stop button flag consisting of 1 byte. In the operation stop button flag, the operation state of the stop button is assigned to each bit.

  For example, if the left stop button 17L is a stop button that has been pressed this time, that is, an operation stop button, “1” is stored in bit 0 of the operation stop button storage area. Also, for example, if the left stop button 17L is a stop button that has not yet been pressed, that is, an effective stop button, “1” is stored in bit 4. Based on the data stored in the operation stop button storage area, the main CPU 101 identifies a stop button that has been pressed this time and a stop button that has not yet been pressed.

[Push order storage area]
Next, the configuration of the pressing order storage area will be described with reference to FIG. The pressing order storage area is composed of a 1-byte data storage area and stores a pressing order flag consisting of 1 byte.

  In the pressing order flag, the type of stop button pressing order is assigned to each bit. For example, when the stop button pressing order is “left, middle, right”, “1” is stored in bit 0 of the pressing order storage area.

[Design code storage area]
Next, the configuration of the symbol code storage area will be described with reference to FIG. In the present embodiment, the symbol code storage area is composed of symbol code storage areas 1 to 37 each represented by 1-byte data. The symbol code storage area has the same configuration as the winning request flag storage area and the winning action flag storage area (see FIG. 25).

  In the symbol code storage area, “1” is stored in the bit corresponding to the symbol combination (combination) that can be stopped on the active line. In addition, after all the reels are stopped, the symbol codes corresponding to the display combination (winning operation flag) are stored in the symbol code storage areas 1 to 37.

[Overall game flow considering whether or not the alarm (ART) function is activated]
In the present embodiment, the main control circuit 90 (main CPU 101) determines whether or not to activate a function (ART function) for notifying information on a stop operation that is advantageous to the player. Therefore, in this embodiment, the main control circuit 90 (main CPU 101) manages various control states related to the operation / non-operation state of the ART function. FIG. 13 is a diagram for explaining transitions of various control states relating to the operation / non-operation state of the ART function. With reference to this, the flow of the entire game of the pachislot machine according to this embodiment (that is, game playability) will be described. To do.

  In this embodiment, as a basic control state, a state in which the ART function is activated (that is, a control state in which information on a stop operation advantageous to the player is notified) and a state in which the ART function is not activated ( That is, it can be roughly classified into a control state in which stop operation information advantageous to the player is not notified and a disadvantageous state disadvantageous to the player.

  In the present embodiment, the ART function is activated in the RUSH preparation state (RT0 to RT3), the RUSH state (RT4), the ART state (RT3), the battle state (RT3), and the pullback state (RT3). The control state of the normal state (RT1) and the precursor state (RT1) is specified as the state where the control state is defined and the ART function is not activated.

  In the present embodiment, various types of control described later that can be performed by the main CPU 101 and the sub CPU 201 are performed at an arbitrary timing from the start of a unit game to the end of the unit game in principle. For example, when various lotteries (decision) are performed with reference to the internal winning combination, a start operation is performed, and various controls are performed when the internal winning combination is determined, and combinations of symbols to be displayed (established) When various types of lottery (decision) are performed with reference to a combination, first to third stop operations are performed, and various controls are performed when a combination of symbols to be displayed is determined. However, the timing at which various types of control described below are performed is not limited to this. For example, the timing may be performed at a timing that straddles unit games.

(Normal state)
When the set value is changed (updated) or when other initialization conditions are satisfied, the gaming state shifts to the initial gaming state (RT0), and in the initial gaming state (RT0), “RT1 transition When the “design” is established and the state shifts to the RT1 state, the normal state (RT1) starts. In addition, when the ART state (RT3) or the pullback state (RT3) ends and the “RT1 transition symbol” or “RT1 transition lip” is established and the state transitions to the RT1 state, the normal state (RT1) starts. The normal state (RT1) is the most disadvantageous game state for the player, and the player usually starts the game from this normal state (RT1).

  Note that even when the ART function is not activated and in the initial gaming state (RT0), the control state may be managed as a normal state. Further, even in the normal state, there may be a case where a transition to another RT state (for example, the RT2 to RT4 state) occurs accidentally. In this case as well, the control state may be managed as the normal state.

  In the normal state (RT1), the mode transition lottery is performed, the transition lottery to the RUSH state is performed, and when the lottery to the RUSH state is won (RUSH winning), the precursor state (RT1) and the RUSH ready state ( Transition to the RUSH state (RT4) via RT0 to RT3). The contents of various lotteries (giving determination) and control performed in the normal state will be described in detail later with reference to FIGS.

  In addition, when the RUSH state transition confirmation opportunity is established (confirmation opportunity establishment), the RUSH preparation state (RT0 to RT3) is entered. Here, the confirmation trigger for the RUSH state transition is, for example, winning the above-mentioned “F_RB”, ending the RB gaming state based thereon, and the above-mentioned “F_7 Lip_ALL” and “F_7 Lip_123”-“ F_7 Lip_321 ”is won, and based on this,“ 7-match Lip ”is established. That is, “F_RB” and “F_7 Lip_ALL” are decisive roles for shifting to the RUSH state (that is, the ART function is activated). This is the same in other control states. For example, in the state where the ART function is already in operation, when the RUSH state transition is confirmed, the right granted to transition to the RUSH state, that is, The right to decide to extend the advantage (RUSH stock) is additionally granted.

  In the case of winning from “F_7 Lip_123” to “F_7 Lip_321”, the stop where the entire navigation (that is, “7-matched Lip”) is established with a predetermined probability (for example, a probability of 1/2). (The entire operation order is notified) or the first stop navigation (that is, a part of the stop operation order (only the stop operation order of the first stop operation) in which the “seven matching lip” is established is notified) Is to be done.

(Predictive state)
In the normal state (RT1), when winning the lottery for transition to the RUSH state (RUSH winning), the state shifts to the precursor state (RT1). The precursor state (RT1) is a standby state in which the ART function is determined to be activated but the ART function is not yet activated. This precursor state (RT1) continues until the game for the number of precursor games determined at the time of winning the RUSH, and when the game for the number of precursor games is performed (the number of precursor games is consumed), the RUSH ready state (RT0 to RT3) (In principle, unless the RT state is changed accidentally, the state moves to the RUSH ready state (RT1)).

  Even when the above-described RUSH state transition is confirmed, the RUSH preparation state may be transitioned via the precursor state. Further, even if the lottery for the transition to the RUSH state is not won, the false precursor state may be shifted with a predetermined probability (for example, 1/2 of the normal mode promotion described later). In this case as well, the game is continued until the game for the number of precursor games determined at the time of transition to the false precursor state is performed, and when the game for the number of precursor games is performed (the number of precursor games is used), the normal state (RT1 ). In this way, even if the player has not won the lottery for the transition to the RUSH state, the interest of the game can be maintained.

  In the precursor state (RT1), a RUSH type promotion lottery is performed in which the degree of advantage of the RUSH state already won is changed until the number of precursor games is exhausted and the RUSH ready state is reached. The contents of various lotteries (giving determination) and control performed in the precursor state will be described in detail later with reference to FIGS. 37 and 38.

(RUSH ready state)
In the precursor state (RT1), when the number of precursor games is exhausted (the precursor game number is exhausted), in principle, the state shifts to the RUSH preparation state (RT1). Further, when the RT state is changed accidentally in the precursor state, the state shifts to the RUSH preparation state (RT2 / RT3). At this time, if the RT state is already the RT4 state, the state immediately shifts to the RUSH state (RT4). Moreover, in all the states, when the RB gaming state ends (confirmation trigger establishment), the state shifts to the RUSH preparation state (RT0). Further, in the normal state (RT1 to RT3) or the precursor state (RT1 to RT3), when “seven matching lip” is established (confirmed trigger establishment), the state shifts to the RUSH preparation state (RT1 to RT3). The RUSH preparation state (RT0 to RT3) is a preparation state in which the AT function is activated but the RT function is not activated yet among the ART functions. Alternatively, the RUSH preparation state (RT0 to RT3) may be a preparation state in which the ART function is operating but the game period of the ART state has not been given yet.

  The RUSH ready state (RT0 to RT3) is notified when the stop operation information (push order) is notified, and when “RT4 transition lip” is established and the RT4 state is entered (RT4 transition lip establishment). Further, in a game in which “RT4 transition lip” can be established, stop operation information (push order) was notified, but the stop operation was not performed according to the notified push order, and “RT4 transition lip” was not established. In some cases, the process ends (a push order error occurs).

  Further, in the RUSH preparation state (RT0 to RT3), the RUSH type promotion lottery is performed to change the degree of advantage of the RUSH state already won until the RUSH state is entered. Further, when shifting to the RUSH state, various lotteries are performed for specifically determining the degree of advantage of the RUSH state based on the RUSH type. The contents of various lotteries (giving determination) and control performed in the RUSH preparation state and the contents of the effects to be executed will be described in detail later with reference to FIGS.

(RUSH state)
In the RUSH ready state (RT0 to RT3) (more specifically, the RUSH ready state (RT3)), when “RT4 transition lip” is established and the state transitions to the RT4 state (RT4 transition lip is established), the RUSH state ( Move to RT4). When the above-described pushing order error occurs, the state shifts to the RUSH state (RT1) or the RUSH state (RT3). The RUSH state (RT4) is a grant state in which the ART function is activated and a basic duration (art state game period) of the ART function is granted.

  In the present embodiment, the RUSH state includes a normal RUSH state (RT4) and a special RUSH state (RT4). Both of them are in the notification period described later (that is, the period in which the number of notifications is 1 or more), and every time “7-match lip” is established based on the notification of stop operation information (push order), It is common in that an ART period (art game period) is given.

  Of course, in the normal RUSH state (RT4), when the notification period ends, other benefits are not given, and “RT3 transition lip” is “RT3 transition lip” in a game where both “7-match lip” and “RT3 transition lip” can be established. Information on the stop operation (push order) that will be established is notified, and in response to the notification, “RT3 transition lip” is established and the transition is made to the RT3 state (RUSH end), whereas the special RUSH state (RT4) is different in that a RUSH stock can be given every time a predetermined period (9 games in this embodiment) continues regardless of whether or not it is a notification period. Of course, even in the special RUSH state (RT4), after the notification period is over, in a game in which both “7-matched lip” and “RT3 transition lip” can be established, a stop operation that will result in “RT3 transition lip” being established. Information (push order) is notified, and when “RT3 transition lip” is established and transitions to the RT3 state according to the notification, the process ends (RUSH end).

  That is, the special RUSH state (RT4) is more advantageous than the normal RUSH state (RT4) in that the RUSH stock is provided each time if it can be continued for a predetermined period even if it is not a notification period, for example. When the special RUSH state (RT4) is selected as the RUSH state, the ART period is given (or extended) than when the normal RUSH state (RT4) is selected. Expectation is high. The contents of various lotteries (giving determination) and control performed in the RUSH state, and the contents of the effects to be executed will be described in detail later with reference to FIGS. 42 to 44.

(ART state)
In the RUSH state (RT4), when the notification period ends and “RT3 transition lip” is established and the state transitions to the RT3 state (RUSH end), the state transitions to the ART state (RT3). In the battle state (RT3), when the battle condition end condition is satisfied (battle end), the state shifts to the ART state (RT3). The ART state (RT3) is an advantageous state (ART execution state) in which the ART function operates in the assigned ART period.

  In the ART state (RT3), when the game of the given ART period is digested (ART end), if there is a RUSH stock (with RUSH stock), again (more specifically, via the RUSH state (RT3)) ) Transition to the RUSH state (RT4). In this case, the state may be shifted to the RUSH state (RT4) via the RUSH preparation state (RT3).

  Also, in the ART state (RT3), when the game for the given ART period is digested (ART end), there is no RUSH stock (no RUSH stock), but if there is a CZ stock (the sphere described below) (CZ stock present) ), Transition to the pull-back state (RT3). In addition, if there is no RUSH stock (no RUSH stock) and no CZ stock (no sphere described below) (no CZ stock), the ART function is deactivated, resulting in “RT1 transition symbol” or “RT1 transition”. “Rip” is established, and the state shifts to the normal state (RT1).

  In the ART state (RT3), a lottery for shifting to the battle state is performed, and when the lottery for shifting to the battle state is won, the state shifts to the battle state via a precursor game (battle start). In addition, when the sphere grant lottery is performed and the sphere grant lottery is won, the sphere is granted. Here, the sphere functions as a split right (point) for determining whether or not RUSH stock is granted during the ART state (RT3). In the embodiment, 3 points) will be awarded to RUSH stock.

  In addition, when the sphere finishes the ART state (RT3), the right to make a transition to the pull-back state or extend the pull-back state, that is, the right to make another decision whether to make a transition to the RUSH state, that is, an advantageous state It functions as a lottery right (CZ stock) in which whether or not to extend the lottery, and when it wins the lottery, it can return to the RUSH state again.

  Thus, in the present embodiment, the sphere (the right to determine whether or not to extend the advantageous state) is the RUSH stock (the right to be determined to extend the advantageous state) as the upper privilege (upper privilege). In this case, it is positioned as a lower privilege (lower privilege). The contents of various lotteries (giving determination) and control performed in the ART state will be described in detail later with reference to FIGS. 45 to 47.

(Battle state)
In the ART state (RT3), when winning the battle state transition lottery (battle start), the state shifts to the battle state (RT3). The battle state (RT3) is determined whether or not to extend the ART period directly, and whether or not RUSH stock (upper privilege) and / or sphere (lower privilege) is granted is added. State. In the battle state (RT3), when the battle condition end condition is satisfied (battle end), the state shifts to the ART state (RT3).

  In the battle state (RT3), basically, a battle effect between the ally character and the enemy character is performed over a predetermined period (8 games in the present embodiment), a damage lottery is performed, and the result of the lottery is accumulated. When the damaged damage (granting points) satisfies a predetermined condition (in this embodiment, 10 points or more as the specified points), the above-mentioned privilege is granted according to the accumulated damage (granting points). It is supposed to be. The contents of various lotteries (giving determination) and control performed in the battle state, and the contents of the effects to be executed will be described in detail later with reference to FIGS. 48 to 53.

(Withdrawn state)
In the ART state (RT3), when the game of the given ART period is digested (ART end), there is no RUSH stock (no RUSH stock), but if there is a CZ stock (the sphere described later) (with CZ stock), Transition to the pullback state (RT3). The pullback state (RT3) is a challenge state that determines whether or not the advantageous state can be resumed after the ART period has elapsed.

  In the pull-back state (RT3), when the lottery for the transition to the RUSH state (the pull-back lottery) is won (successful pullback), the state shifts to the RUSH preparation state (RT3), but the lottery for the transition to the RUSH state (the pull-back lottery). Without winning, if the end condition of the pullback state is satisfied (pulling back failure), the ART function is deactivated. As a result, the “RT1 transition symbol” or “RT1 transition lip” is established, and the normal state ( Move to RT1).

  The pull-back state (RT3) continues for three games per sphere (CZ stock). For example, in a state where there are two spheres (CZ stock) and the state shifts to the pullback state (RT3), the pullback state (RT3) continues for six games. The contents of various lotteries (giving determination) and control performed in the retracted state will be described in detail later with reference to FIGS. 54 and 55.

  Further, in this embodiment, the retraction state (RT3) is assumed to shift when there is no RUSH stock and there is CZ stock. However, the present invention is not limited to this. For example, when the RUSH stock and CZ stock exist, When the probability (for example, 1/2) or a predetermined condition is satisfied (for example, there is a RUSH stock but the player is not informed of that fact. That is, the RUSH stock is potentially held. )), It is also possible to shift to the retracted state (RT3). In this case, the pull-back state (RT3) can function as a precursor state to shift to the RUSH preparation state (RT3).

  As described above, in the present embodiment, in the normal state (unfavorable state), when it is determined to shift to the RUSH state (granted state), the RUSH ready state (directly or via the precursor state) Next, the game state of the ART state (advantageous state) is granted in the RUSH state (granted state), and the ART state (advantageous state) is executed over the given game period. Further, when it is determined in the ART state (advantageous state) that a transition to the battle state (additional state) is made, it is determined whether or not the game period of the ART state (advantageous state) is extended in the battle state. If the RUSH stock (right to be determined to extend the advantageous state) is granted when the ART state (advantageous state) ends, the RUSH state (granted state) is entered again, and the CZ stock ( If the right to lottery whether or not to extend the advantageous state is granted, it is determined whether or not the advantageous state can be resumed in the pullback state (challenge state). In the present embodiment, as described above, by setting the various control states described above, the game is improved.

  However, the game playability of the pachislot machine 1 according to the present embodiment is not limited to that described above. For example, in the present embodiment, in the ART state (RT3), in principle, the state is not shifted to the RUSH state (RT4). However, when the RUSH stock is given in the ART state (RT3), immediately (or It is also possible to shift from the ART state (RT3) to the RUSH state (RT4) via the precursor state.

  Further, for example, in this embodiment, in the normal state (RT1), as a rule, the state does not shift to the battle state (RT3) or the pull-back state (RT3), but the transition lottery is performed also in the normal state (RT1) When the transfer lottery is won, it may be transferred to the battle state (RT3) or the pull-back state (RT3) via the precursor state (or immediately). In this case, in the battle state (RT3) or the pull-back state (RT3), when the RUSH winning is achieved, the so-called “first win” is transferred to the RUSH preparation state (RT3), and the RUSH winning is not achieved. May be shifted to the normal state (RT1). That is, the battle state (RT3) and the pullback state (RT3) may be made to function as a chance zone with a high degree of expectation for shifting to the advantageous state.

  In this embodiment, as a technique for managing the game period in the advantageous state (more specifically, the “ART state”), the number of games (that is, the number of games that can be notified of stop operation information advantageous to the player). In addition, except for the battle state, the number of games is, in principle, given in the RUSH state, but even in the ART state, for example, an extra lottery based on an internal winning combination is performed, An additional number of games may be added.

  Further, in this embodiment, once the state is shifted to the advantageous state (more specifically, the “ART state”), the right (RUSH stock) determined to extend the advantageous state is basically the battle state. In the ART state, for example, an extra lottery based on an internal winning combination may be performed to directly add the RUSH stock.

  Further, various other techniques can be adopted as a technique for managing the game period in the advantageous state. For example, it may be managed by the number of sets (that is, a predetermined number of games is set as one unit), or may be managed by a difference number (that is, a net increase number obtained by subtracting the number of input from the number of payouts). Alternatively, it may be managed based on the number of times of notification of pushing order (for example, 6-option bell) (that is, the number of times of information on a stop operation that is advantageous for the player actually paying out medals). . In these cases, if an increase occurs, the difference number or the number of notifications may be added.

  Further, extending the advantageous state (adding, continuing) is not limited to adding the number of games, the RUSH stock or the CZ stock, and the difference number or the number of notifications described above. ) May be increased. For example, when a continuous lottery (end lottery) is performed every time the ART state ends, the continuation probability can be increased to substantially increase the continuation probability.

  In addition, for example, when the above-mentioned ART function is activated and the bonus state is managed as a series of advantageous sections, and the number of continuations of the advantageous sections reaches a predetermined number of games (for example, 1500 games), it is still Even if the ART period, RUSH stock, and CZ stock remain, the state in which the ART function is forcibly terminated is terminated, and the state in which the ART function is not operated (for example, the normal state) is transferred. You may do it. In other words, a certain limit (limiter) may be provided for continuation of the advantageous section that is advantageous to the player. By configuring in this way, it is possible to prevent the player from being excessively involved in the game.

  In the present embodiment, lottery regarding the ART function is performed on the main control circuit 90 side. Therefore, in order to reduce the control burden at the time of lottery related to the ART function, when the internal winning combination used for the lottery related to the ART function (see FIGS. 32 to 55 to be described later) is determined, these internal winning combinations are determined. Information to be grouped (grouping information) may be generated (that is, information related to the internal winning combination is compressed), and lottery regarding the ART function may be performed based on the generated grouping information.

[Normal game flow]
Next, with reference to FIGS. 32 to 36, the flow of the game in the normal state described above will be described. FIG. 32 is a diagram for explaining the flow of the game in the normal state, and is a diagram for explaining the outline of various controls performed by the main CPU 101. 33 to 36 are diagrams illustrating examples of various data tables (lottery tables) stored in the main ROM 102 that are referred to when the main CPU 101 performs various controls in a normal state.

  As shown in FIG. 32, in the normal state, the main CPU 101 performs RUSH (ART) transfer lottery based on the current normal mode and the random number value. Specifically, with reference to the RUSH transition lottery table shown in FIG. 33, it is determined whether or not to transition to the RUSH state.

  In the present embodiment, normal modes “0” to “4” are defined as the normal mode. Of these, the RUSH (ART) transfer lottery can be determined to shift to the RUSH state only in the normal modes “3” and “4”, and in the normal modes “0” to “2”. Is not determined to shift to the RUSH state until the above-described confirmation opportunity is established. That is, the normal modes “3” and “4” are relatively advantageous modes (lottery state), and the normal modes “0” to “2” are relatively disadvantageous modes (lottery state).

  When the main CPU 101 wins the RUSH (ART) transition lottery (RUSH win), the main CPU 101 performs the RUSH type lottery based on the current normal mode and the random number value. Specifically, the RUSH type is determined with reference to the RUSH type lottery table shown in FIG.

  In the present embodiment, RUSH types “1” to “4” are defined as RUSH types. The RUSH type changes the degree of advantage in the RUSH state (that is, the assigned ART period), that is, determines the value of the advantageous state (ART state). As will be described later, the RUSH type “2” has the lowest expected level (value of advantageous state) of the ART period to be given, and in the order of the RUSH type “3”, the RUSH type “1”, and the RUSH type “4”. It is set so that the degree of expectation (value of the advantageous state) of the given ART period is high (see FIG. 40 described later). In addition, when the RUSH type is determined in the RUSH type lottery, the RUSH type “1” is not determined, but is determined when the RUSH state transitions based on the establishment of the above-described fixed opportunity.

  When the RUSH type is determined as a result of the RUSH type lottery, the main CPU 101 performs the precursor game number lottery based on the determined RUSH type and the random value. Specifically, the number of precursor games is determined with reference to the precursor game number lottery table shown in FIG. Then, the main CPU 101 shifts the control state to the precursor state.

  In the present embodiment, “super short”, “short”, “medium”, and “long” are defined as the number of precursor games. These indicate the game state of the precursor state (that is, the number of precursor games). For example, “super short” indicates that any of the 0 to 5 games is determined, and “short” indicates that any of the 6 to 20 games is determined. “Medium” indicates that the number of precursor games is determined from 21 to 32 games, and “Long” indicates that one of the precursor games is determined from 33 to 50 games Is shown. In determining the number of precursor games, a predetermined number of precursor games may be determined within the range of the number of games, or a lottery may be performed to determine the range of the number of games. One predictive game number may be determined from within.

  In the present embodiment, when a relatively advantageous RUSH type is determined, a longer number of precursor games is more easily determined than when a relatively unfavorable RUSH type is determined. That is, as the game period in the precursor state is longer, the expectation of the privilege granted in the RUSH state is increased. As will be described later, the longer the game state in the precursor state, the higher the degree of expectation that the RUSH type will be promoted.

  When the main CPU 101 does not win the RUSH (ART) transition lottery (RUSH non-winning), based on whether or not it is in a specific mode, which will be described later, the current normal mode, the internal winning combination, and the random number value, A lottery for shifting to the normal mode is performed. Specifically, referring to the normal mode transition lottery table shown in FIG. 34 or 35, the normal mode (including no transition) of the transition destination is determined.

  In the present embodiment, the normal mode is likely to shift to a relatively advantageous normal mode (that is, easy to be promoted) when in the specific mode and when not in the specific mode (non-specific mode). In addition, the normal mode does not shift to a relatively disadvantageous normal mode (that is, does not fall) (see FIGS. 34 and 35). In other words, the specific mode is a mode (preferential state) for preferentially promoting a mode for giving an advantageous state (lottery state).

  When the normal mode is shifted as a result of the normal mode transition lottery (that is, when the current normal mode is different from the normal mode of the transfer destination), the main CPU 101 changes the normal mode of the transfer destination to the current mode. The normal mode is set, and the processing in the normal state is terminated. Note that “when the normal mode shifts” may indicate only when the normal mode is promoted. Further, even when the normal mode is shifted, a specific mode shifting lottery described later may be performed.

  When the normal mode is not changed as a result of the normal mode transition lottery (that is, when the normal mode is not shifted), the main CPU 101 determines that the current normal mode and the internal winning combination are not in the specific mode. Based on the numerical value, the lottery for the specific mode is performed. Specifically, it is determined with reference to the specific mode transition lottery table shown in FIG. 36 whether to shift to the specific mode. Note that even in the specific mode, the specific mode transition lottery may be performed. In this case, when it is decided to shift to the specific mode, similarly, a specific mode game number lottery described later is performed so that the specific mode is extended by the specific mode game number given as a result of the lottery. That's fine.

  In the present embodiment, except for the case where the current normal mode is the most advantageous normal mode “4”, in principle, the lower the expectation of the advantageous state transition in the current normal mode (that is, the lower the normal mode). It ’s easier to switch to a specific mode. This makes it possible to maintain the player's sense of expectation even when the current normal mode has a low expectation of the advantageous state transition. In addition, when the mode is shifted to the specific mode, there is a possibility that the normal mode “4” has the highest expectation of the shift to the advantageous state, so the current normal mode (lottery state) may be advantageous. It is also possible to suggest. In any case, it is possible to increase the player's expectation regarding the advantageous state transition and improve the interest of the game.

  Although not shown, in the present embodiment, the sub CPU 201 performs an effect different from that in the non-specific mode (non-preferential state) during the specific mode (preferential state). This suggests that the player is in a specific mode (preferred state).

  When the main CPU 101 determines that the specific mode shifts as a result of the specific mode transition lottery, the main CPU 101 performs the specific mode game number lottery. Specifically, based on the random number value, for example, the specific mode game number “short” is determined with a probability of 3/4, and the specific mode game number “long” is determined with a probability of 1/4. For example, the specific mode game number “short” may be set to 10 games for the duration of the specific mode, and the specific mode game number “long” may be set to 50 games for the duration of the specific mode, for example. Then, the main CPU 101 ends the process in the normal state. Also, the main CPU 101 ends the process in the normal state even when the specific mode transition lottery does not determine that the specific mode is to be shifted.

  In the normal state, the main CPU 101 shifts the control state to the precursor state when the RUSH win is achieved, and shifts the control state to the RUSH preparation state when the above-described confirmation trigger is established. On the other hand, when there is no transition to another control state, the game in the normal state is controlled by repeatedly performing the above-described process in the normal state (see FIG. 32).

  As described above, in the present embodiment, control is performed to a preferential state (for example, a specific mode) in which a transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to a player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also the non-preferential state (for example, non-specific mode), the advantageous state based on the current lottery state Whether or not is given is determined. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

  Further, in the present embodiment, control is performed to a preferential state (for example, a specific mode) in which a transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. In the lower lottery state (for example, the normal mode “0” to “2”), the advantageous state is not given unless the specific combination (for example, “F_RB”) is won, but the upper lottery state (for example, the normal mode “ 3 ”and“ 4 ”) are configured such that an advantageous state may be given without winning the specific combination. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

  Further, in the present embodiment, control is performed to a preferential state (for example, a specific mode) in which a transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. In the preferential state, the lottery state may be more advantageous but may not be more disadvantageous. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

  Further, in the present embodiment, when the lottery state transition control is not performed in the non-preferential state, it is determined whether or not to shift to the preferential state. Therefore, even if the lottery state does not shift, it can be suppressed that the interest of the game is lowered.

[The flow of games in the precursor state]
Next, with reference to FIG.37 and FIG.38, the flow of the game in the above-mentioned precursor state is demonstrated. FIG. 37 is a diagram for explaining the flow of the game in the precursor state, and is a diagram for explaining an outline of various controls performed by the main CPU 101. FIG. 38 is a diagram illustrating an example of various data tables (lottery tables) stored in the main ROM 102 that are referred to when the main CPU 101 performs various controls in the precursor state.

  As shown in FIG. 37, in the precursor state, the main CPU 101 performs the RUSH type promotion lottery based on the current RUSH type, the internal winning combination, and the random value. Specifically, referring to the RUSH type promotion lottery table shown in FIG. 38, the RUSH type of the promotion destination (including no promotion) is determined.

  When the main CPU 101 does not win the RUSH type promotion lottery (RUSH type promotion non-winning), the main CPU 101 updates the number of precursor games (that is, subtracts one number of precursor games) and digests the number of precursor games ( That is, when the number of precursor games becomes 0), the control state is shifted to the RUSH preparation state. On the other hand, when the number of precursor games is not exhausted (that is, when the number of precursor games is still 1 or more), the processing in the precursor state is terminated.

  When the main CPU 101 wins the RUSH type promotion lottery (RUSH type promotion win), the main CPU 101 updates the current RUSH type to the promoted RUSH type, and updates the number of precursor games (that is, the number of precursor games). When the number of precursor games is exhausted (ie, when the number of precursor games becomes zero), the control state is shifted to the RUSH preparation state. On the other hand, when the number of precursor games is not exhausted (that is, when the number of precursor games is still 1 or more), the processing in the precursor state is terminated.

  As described above, the precursor state continues for the number of precursor games determined at the time of winning the RUSH. Therefore, the longer the determined number of precursor games, the higher the degree of expectation regarding promotion of the RUSH type. In addition, the longer the number of RUSH types that are determined, the easier it is to determine the number of precursor games. Therefore, the longer the determined number of precursor games, the higher the expectation of the RUSH type itself.

  In addition, although illustration is abbreviate | omitted, in this embodiment, in order that the sub CPU201 may suggest the expectation degree in a precursor state, it produces | generates by several production | presentation stages (prediction effect state). For example, the production stages “1” to “3” are set as the production stage, and the production stage “1” has the lowest expectation level and the production stage “3” has the highest expectation level. Here, “high expectation level (low)” in the production stage indicates that the expectation level of winning the RUSH is high (low) in the precursor state including the false precursor state. Alternatively, it may indicate that the expected degree of the determined RUSH type is high (low) on the assumption that RUSH has been won, and indicate the length of the number of precursor games. May be.

  When the precursor state (or false precursor state) starts (or may be in the middle), the sub CPU 201 determines one stage from among the plurality of stage stages (in the middle of the precursor state) When it is, it is decided whether or not to promote the decided production stage).

  As described above, at this time, the stage may be determined (or promoted) by lottery depending on whether or not RUSH has been won, or the stage stage by lottery according to the determined RUSH type. May be determined (or promoted), or the production stage may be determined (or promoted) by lottery according to the number of precursor games determined. Alternatively, these may be determined in combination to determine (or promote) the stage of production.

  In addition, when the stage stage “1” is determined, the stage of expectation of the stage stage is determined, but it is unknown whether it is a true precursor state or a false precursor state, and the stage stage “2” is determined. When it is, it is clear that the state is a true precursor state (that is, the transition to the RUSH state is confirmed), but the expectation level of the RUSH type is unknown, and the stage stage “3” is When it is determined, the state is a true precursor state (that is, it is determined that the RUSH state is entered), and the RUSH type is highly expected (for example, the RUSH type is other than “2”). The expectation level of the production stage may be associated with the production stage so that it is clear that the production stage is selected.

  In the precursor state, the main CPU 101 shifts the control state to the RUSH preparation state when the number of precursor games is exhausted. On the other hand, when there is no transition to another control state, the game in the precursor state is controlled by repeatedly performing the processing in the precursor state (see FIG. 38) described above.

[RUSH ready game flow]
Next, with reference to FIGS. 39 to 41, the flow of the game in the above-described RUSH preparation state will be described. FIG. 39 is a diagram illustrating the flow of the game in the RUSH preparation state, and is a diagram illustrating an overview of various controls performed by the main CPU 101 and the sub CPU 201. FIG. 40 is a diagram showing an example of various data tables (lottery tables) stored in the main ROM 102 that are referred to when the main CPU 101 performs various controls in the RUSH preparation state. It is a figure which shows an example of the production | presentation control performed in a RUSH preparation state.

  As shown in FIG. 39, in the RUSH preparation state, the sub CPU 201 makes a transition to the RUSH preparation state when the number of precursor games becomes 0 and makes a transition from the precursor state to the RUSH preparation state, that is, wins the RUSH. An announcement lottery is made as to whether or not to make a winning announcement to announce that it has been.

  Note that, in this lottery, for example, if the stage “3” has already been selected in the sign state, the winning announcement may be made without fail. That is, for example, in the event that the warning state has already been definitively notified that the transition to the RUSH state has been made, the winning notification may be performed without performing a special warning described later.

  Further, for example, it may be determined whether or not the winning notification is performed with a probability according to the current RUSH type. Specifically, when the current RUSH type has a relatively high degree of expectation (for example, the RUSH type “3” or “4”), the current RUSH type has a relatively low degree of expectation. The notification lottery may be performed so that the probability that the winning notification is determined to be performed is lower than in the case of (for example, RUSH type “2”). In other words, the fact that the winning notification is not performed means that the sign state continues in a pseudo manner for the effect (the effect display by the effect stage in the sign state is apparently continued). Therefore, the effect based on the law that the expectation of the privilege (ART period) given in the RUSH state is higher as the precursor state is longer can be performed also in the RUSH preparation state following the precursor state.

  Further, for example, it may be determined whether or not the winning notification is performed with a probability corresponding to the relationship between the current RUSH type and the stage. Specifically, the current RUSH type has a relatively high expectation (for example, the RUSH type “3” or “4”), but the current stage has a relatively low expectation (for example, In the case of the production stage “1”), the winning announcement is performed as compared with the case where the current production stage is relatively high in expectation (for example, the production stage “2” or “3”). An announcement lottery may be performed so that the probability of the event being determined decreases. That is, when there is a gap between the expectation level of the RUSH type and the expectation level of the performance stage, it is difficult to make a winning announcement and it is only necessary to make a special sign described later easily.

  When the sub CPU 201 determines to perform the winning notification as a result of the notification lottery (notification winning), the sub CPU 201 performs the winning notification with the liquid crystal pattern alignment. On the other hand, if the sub CPU 201 does not decide to perform the winning notification as a result of the notification lottery (not-winning notification), the sub CPU 201 performs a special sign. The special sign gives an effect as a pseudo sign state even in the RUSH ready state (that is, the state in which it is determined to shift to the advantageous state), and an example is shown in FIG.

  As shown in FIG. 41, in this embodiment, a plurality of decorative symbols (for example, decorative symbols “1” to “9”) are displayed in a plurality of columns (for example, 3 in the display device 11) at least in the normal state and the precursor state. In this way, the display is changed and displayed in a stopped state, whereby an effect of suggesting the current normal mode or suggesting the expectation level of the effect stage in the precursor state is performed.

  Here, in the case where the winning notification is performed with the liquid crystal pattern matching (in the case of winning notification in FIG. 41), when the number of precursor games becomes 0, a plurality of decorative symbols are displayed in a specific display mode (for example, the same In this manner, the display is stopped and displayed in a RUSH state (more specifically, the RUSH preparation state that is the preparation state). Then, in the transitioned RUSH preparation state, the notification of the procedure of the stop operation advantageous to the player is started, and on the display device 11, the display of the stage stage in the precursor state is changed to the presentation display in the RUSH preparation state. .

  On the other hand, when a special warning is given without performing the winning notification (in the case of no winning notification in FIG. 41), even when the number of warning games becomes 0, a plurality of decorative symbols are stopped and displayed in a specific display mode. Instead, the state transitions to the RUSH preparation state while displaying the stage in the precursor state. That is, on the display device 11, the precursory state continues in a pseudo manner. However, since the control state is the RUSH preparation state, when the winning order is won, the stop operation procedure that is advantageous to the player is notified. Therefore, in this case, the transition to the RUSH state (more specifically, the RUSH ready state that is the ready state) is not notified, but the stop operation procedure that is advantageous to the player is notified. A special production state (special sign) will occur. Thereby, the game nature of a precursor state can be made various, the alerting | reporting regarding advantageous state transfer can be made various, and the interest of a game can be improved.

  In addition, during the special sign, in addition to the above, an effect of promoting the effect stage in the sign state may be performed. Specifically, the sub CPU 201 performs the stage stage promotion lottery based on the current stage stage, the current RUSH type, and the random number value in the special sign, and appropriately promotes the stage stage according to the result. You can do it. This effect stage promotion lottery may be performed for each unit game until the RUSH preparation state is completed, or may be performed for each predetermined number of games (for example, three games). In addition, in the stage stage promotion lottery, the lottery result of the RUSH type promotion lottery described later may be considered.

  For example, when the current stage is “1” and the current RUSH type is “3”, the sub CPU 201 promotes the stage with a probability of 1/8 and sets the stage to “2”. If the current RUSH type is “4”, the stage is promoted with a probability of ½ and the stage is determined to be “2”. In addition, when the current stage is “2” and the current RUSH type is “3”, the stage is determined to be “3” by promoting the stage with a probability of 1/16. If the current RUSH type is “4”, the stage is promoted with a probability of 1/4 and the stage is determined to be “3”.

  For example, when the current stage is “1” and the current RUSH type is “3”, the sub CPU 201 promotes the stage with a probability of 1/8 and sets the stage to “2”. If the current RUSH type is “4”, the stage is promoted with a probability of 1/16, and if the current RUSH type is “4”, the probability is 1/2. The production stage is promoted and the production stage is determined to be “2”, and the production stage is promoted with a probability of 1/4 and the production stage is determined to be “3”.

  That is, the stage promotion may be promoted stepwise or non-stepwise. Also, whether or not to promote the performance stage may be determined in advance when a special omen starts (that is, when there is no announcement when the number of omen games becomes 0). Good. Alternatively, the production stage may be promoted every time the RUSH preparation state continues for a predetermined period (for example, 10 games).

  In the RUSH preparation state, the main CPU 101 performs RUSH type promotion lottery based on the current RUSH type, the internal winning combination, and the random value. Specifically, referring to the RUSH type promotion lottery table shown in FIG. 38, the RUSH type of the promotion destination (including no promotion) is determined.

  When the main CPU 101 wins the RUSH type promotion lottery (RUSH type promotion win), the main RUSH type is updated to the RUSH type of the promotion destination. If the RUSH type promotion lottery is not won (RUSH type promotion non-winning), the current RUSH type is held. When the main CPU 101 wins the push order, the main CPU 101 notifies the push order.

  Specifically, control is performed to display instruction information (navigation data) indicating a stop operation procedure (see FIGS. 22 to 24) advantageous to the player on the instruction monitor in accordance with the type of push order that has been won. At the same time, information (command) including instruction information (navigation data) is transmitted so that the sub CPU 201 can recognize it (the same is true for the push order notification in other control states). In the RUSH preparation state, a stop operation procedure for shifting the RT state to the RT4 state is notified, and a stop operation procedure that can receive more medals is notified. Further, as described above, when winning from “F_7 Lip_123” to “F_7 Lip_321”, the procedure of the stop operation to become the full navigation or the first stop navigation may be notified with a predetermined probability. Similarly, when “F_chance lip_123” to “F_chance lip_321” are won, the procedure of the stop operation to become all navigation or the first stop navigation may be notified with a predetermined probability. That is, in the above-described various data tables (lottery table) and various data tables (lottery table) described later, when “chance lip” is written in the internal winning combination column, “F_chance lip_123” to “ When “F_chance lip — 321” is won, the procedure for the stop operation is appropriate, so that “chance lip” is established as a result, and the procedure for the stop operation is not appropriate. Does not include the case where is not satisfied.

  When the “RT4 transition lip” is not established in the game in which “RT4 transition lip” cannot be established as a result of the stop operation in the game in which the push order can be notified, the main CPU 101 (RT4 transition lip is not yet established). The process in the RUSH ready state is terminated.

  In the game in which the order of pushing can be notified, the main CPU 101 performs the stop operation as a result of “RT4 transition lip” being established (RT4 transition lip establishment), and in the game in which “RT4 transition lip” can be established. If “RT4 transition lip” is not established in accordance with the notified push order, a RUSH state distribution lottery is performed based on the random number value. Specifically, it is determined with reference to the RUSH state distribution lottery table shown in FIG. 40 whether the transition destination RUSH state is the normal RUSH state or the special RUSH state.

  The main CPU 101 performs the security notification period lottery based on the RUSH state determined as a result of the RUSH state distribution lottery, the current RUSH type, and the random value. Specifically, with reference to the security notification period lottery table shown in FIG. 40, the security notification period, which is the number of times the stop operation procedure for establishing the “seven matching lip” in the RUSH state is notified. To decide.

  The main CPU 101 performs additional notification period determination rate lottery based on the RUSH state determined as a result of the RUSH state distribution lottery, the current RUSH type, and the random value. Specifically, with reference to the additional notification period determination rate lottery table shown in FIG. 40, the number of times of notification of the stop operation procedure for establishing the “seven matching lip” in the RUSH state is added (ie, notification The security notification period determination rate that is referred to when lottery for extending the period is performed is determined. Then, the main CPU 101 shifts the control state to the RUSH state (normal RUSH state or special RUSH state).

  The additional notification period determination rate “extremely low” indicates, for example, that the additional notification period determination rate is a probability of about 1 to 5%, and the additional notification period determination rate “high” is, for example, the additional notification period determination rate. The rate is a probability of about 75 to 89%, and the additional notification period determination rate “extremely high” indicates that the additional notification period determination rate is a probability of about 90 to 95%, for example. Therefore, when the additional notification period determination rate “extremely low” is determined, it is unlikely that an additional notification period is added, and the additional notification period determination rate “high” or “extremely high” is determined. In such a case, there is a high possibility that an additional notification period is given.

  In the RUSH preparation state, the main CPU 101 shifts the control state to the RUSH state (normal RUSH state or special RUSH state) when the RT4 transition lip is established or when a pressing order error occurs. On the other hand, when there is no transition to another control state, the game in the RUSH preparation state is controlled by repeatedly performing the above-described processing in the RUSH preparation state (see FIG. 39).

  Thus, in this embodiment, when the value (for example, RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value Is high, it is easy to determine the second precursor effect in the precursor state, but if the value of the advantageous state is high and the first precursor effect is performed, the precursor state is further It is configured such that a special sign effect (for example, a special sign) is performed in a preparation state (for example, a RUSH preparation state) after the end. That is, even when a precursor effect with a relatively low degree of expectation is performed, it is possible to expect that the value of the advantageous state is high when the special precursor effect is performed in the preparation state. In addition, the interest of the sign production itself, including special sign production, can be dramatically improved. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

  In the present embodiment, when the value (for example, RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value is high. In this case, it is easy to determine the second precursor effect in the precursor state, but when the value of the advantageous state is high and the first precursor effect is performed, the notification effect of transition to the advantageous state is performed. If it is not performed, a special sign effect (for example, a special sign) is further performed in a preparation state (for example, a RUSH preparation state) after the sign state ends. In other words, even when a precursor effect with a relatively low degree of expectation is performed, when the special precursor effect is performed in the preparation state without performing the notification effect, it is expected that the value of the advantageous state is high. In addition, it is possible to dramatically improve the interest of the sign production itself, including the special sign production. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

  In the present embodiment, when the value (for example, RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value is high. In this case, it is easy to determine the second precursor effect in the precursor state, but when the value of the advantageous state is high and the first precursor effect is performed, further, after the end of the precursor state In the preparation state (for example, the RUSH preparation state), a special sign effect (for example, a special sign) is performed until the preparation state ends. That is, even when a precursor effect with a relatively low degree of expectation is performed, it is possible to expect that the value of the advantageous state is high when the special precursor effect is performed in the preparation state. In addition, the interest of the sign production itself, including special sign production, can be dramatically improved. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

  In the present embodiment, in the preparation state of the advantageous state, the notification of the procedure of the stop operation that is advantageous to the player is started, but there is a case in which the state of the precursor remains in effect. That is, it is possible to give a surprise to the player as if the notification of the procedure of the stop operation that was advantageous in the sign state was suddenly started. Therefore, the interest can be improved with respect to the effect performed before the start of the advantageous state in which the procedure of the stop operation advantageous to the player is notified.

[RUSH game flow]
Next, with reference to FIGS. 42 to 44, the flow of the game in the above-described RUSH state will be described. FIG. 42 is a diagram for explaining the flow of the game in the normal RUSH state, and is a diagram for explaining the outline of various controls performed by the main CPU 101 and the sub CPU 201. FIG. 43 is a diagram for explaining the flow of the game in the special RUSH state, and is a diagram for explaining the outline of various controls performed by the main CPU 101 and the sub CPU 201. FIG. 44 is a diagram illustrating an example of effect control performed by the sub CPU 201 in the RUSH state.

(Normal RUSH state)
As shown in FIG. 42, when the normal RUSH state is started (when the normal RUSH state is started), or when the winning of the additional notification period lottery is continued in the normal RUSH state (continuation of the additional notification period lottery). The additional notification period lottery is performed based on the additional notification period determination rate (any one of “extremely low” to “extremely high”) determined in the RUSH preparation state and a random value.

  When the main CPU 101 wins the additional notification period lottery (additional notification period lottery continuation), the main CPU 101 adds the number of notifications in the RUSH state once (that is, extends the notification period by a predetermined period and increases the notification period). In this case, the number of notifications to be added may be further determined by lottery, or it may be determined in advance how many times the additional notification period lottery is added. That is, the number of notifications added may be a plurality of times.

  When the sub CPU 201 wins the additional notification period lottery (the additional notification period lottery continues), the sub CPU 201 performs lamp lighting lottery based on the random number value. Specifically, it is determined by lottery whether or not the lamp group 21 is lit in a predetermined display mode (for example, a lamp lighting effect is performed) for a predetermined period (for example, about 1 second). It should be noted that, instead of or together with the lamp group 21, display in a predetermined display mode may be performed at a predetermined location of the sub display device 18 for a predetermined period (for example, about 1 second). Further, a predetermined display mode may be displayed at a predetermined location of the display device 11 for a predetermined period (for example, about 1 second). Further, a predetermined sound may be output from the speakers 65L and 65R for a predetermined period (for example, about 1 second). This lamp lighting effect is an effect for notifying that the winning of the additional notification period lottery continues, and an example thereof is shown in FIG.

  In the example of the lamp lighting effect shown in FIG. 44, in the normal RUSH state (the same applies to the special RUSH state described later), the winning of the additional notification period lottery continues from the start of the RUSH state (first game) to the sixth game. In addition, in the sixth game, the lamp lighting lottery is won and the lamp lighting effect is performed. Here, at the start of the RUSH state (first game), although the start notification indicating that the RUSH state has started (that is, the additional notification period lottery has started) is performed, up to the first to fifth games Since there is no continuous notification indicating that the lottery of the additional notification period lottery is continued, if the push order in which 7 rips are established is notified during this period, it is the security notification period. It is not possible for the player to recognize whether or not the notification has been made, or whether or not the push order has been notified by adding a notification period.

  On the other hand, in the sixth game, it is notified that the winning of the additional notification period lottery is continued by performing the lamp lighting effect (that is, continuous notification). Thereby, the player can recognize for the first time that the winning of the additional notification period lottery continues. Further, for example, when one notification period is added per winning of the additional notification period lottery, the player can recognize that a total of six notification periods have been added. Further, for example, when a plurality of notification periods can be added for one additional notification period lottery, the player can recognize that at least six notification periods have been added.

  The elements used for the lamp lighting lottery can be set as appropriate. For example, on the assumption that the lottery of the additional notification period is continued, it may be determined whether or not to perform the lamp lighting effect with a predetermined probability (for example, 1/8) for each unit game. Then, it may be determined whether or not the lamp lighting effect is performed with a similar probability every predetermined period (for example, three games).

  Further, for example, it may be determined whether or not to perform the lamp lighting effect with different probabilities according to the additional notification period determination rate determined in the RUSH preparation state. In this case, for example, it may be determined whether or not the lamp lighting effect is performed with a predetermined probability (for example, 1/8) only when the additional notification period determination rate is “extremely high”. In this manner, when the lamp lighting effect is performed, not only that the additional notification period lottery is continued and the number of added notification periods, but also the additional notification period determination rate is most advantageous. This can also be notified, and the player's expectation can be further improved.

  Also, in this case, for example, the case where the additional notification period determination rate is “extremely low” is higher than the case where the additional notification period determination rate is “high” or “extremely high” (for example, the former case 1/16, or 1/2) in the latter case, it may be determined whether or not the lamp lighting effect is to be performed. In this way, when the additional notification period determination rate is unfavorable, it is easy to be notified and it can be compensated for the disadvantage, and even if the lamp lighting effect is not performed, the additional notification Since the possibility that the period determination rate is advantageous remains, the player's expectation can be maintained.

  Further, for example, it may be determined whether or not to perform the lamp lighting effect with different probabilities according to the RUSH type, or the lamp lighting effect with different probabilities according to the actually determined number of security notifications. You may make it determine whether it performs. Similarly, in this case, when the advantageous RUSH type or the advantageous number of times of guarantee notification is determined, the lamp lighting effect may be more easily performed, or the disadvantageous RUSH type or the number of disadvantageous guarantee notification times. It may be easier for the lamp lighting effect to be performed when the is determined.

  Based on the result of the additional notification period lottery described above, the main CPU 101 refers to the internal winning combination in the unit game and the remaining number of notifications (including the assigned security notification period). If the player does not win “7 lip” (“F_7 lip A_1st” to “F_probable 7 lip B_3rd”) in the RT4 state (7 lip non-winning), the other push order notification is given if the push is forward. If not, the process in the normal RUSH state is terminated. In the other push order notification, for example, a stop operation procedure that can receive more medals is notified.

  Further, in the case of winning “7 lips” (“F_7 lip A_1st” to “F_probability 7 lip B_3rd”) in the RT4 state (7 lip winning) and the number of notifications is 1 or more (ie, In the case of the notification period), a procedure for a stop operation for establishing “7-set lip” is notified. Then, the ART period grant lottery is performed based on the notification of the procedure of the stop operation for establishing “7-set lip”. Note that the ART period grant lottery may be performed based on the fact that the “seven matching lip” is actually established (that is, the stop operation procedure for establishing the “seven matching lip” is notified). In the case where “7 replies” is not established, the ART period may not be given).

  In addition, the ART period grant lottery grants either a basic ART period (for example, 30 games) or a special ART period (for example, 100 games) based on a random value. For example, the basic ART period is given with a probability of 255/256, and the special ART period is given with a probability of 1/256. Note that any number of games between 30 to 100 games may be given as the ART period simply depending on the lottery result.

  Further, in the ART period grant lottery, as described above, an ART period as the number of games may be directly granted. For example, as in the case of granting a RUSH type, the ART period is indirectly set. A kind of granting right that can be granted may be granted. In other words, “granting an ART period” in the normal RUSH state (the same applies to the special RUSH state described below) includes all those that give the ART period to the player as a result, .

  The main CPU 101 subtracts 1 from the number of notifications based on the fact that the ART period grant lottery has been performed (that is, decreases the notification period). Then, the process in the normal RUSH state is terminated.

  In addition, when “7 lip” (“F_7 lip A_1st” to “F_probability 7 lip B_3rd”) in the RT4 state is won (7 lip win) and the number of notifications is 0 (ie, notification) If it is not during the period, the procedure of the stop operation for establishing “RT3 transition lip” is notified. Then, based on the notification of the procedure of the stop operation for establishing “RT3 transition lip”, the control state is shifted to the ART state.

  In the normal RUSH state, the main CPU 101 shifts the control state to the ART state when the RT3 transition lip is established when the “7 lip” in the RT4 state is reached when it is not the notification period. On the other hand, when there is no transition to another control state, the game in the normal RUSH state is controlled by repeatedly performing the above-described processing in the normal RUSH state (see FIG. 42).

(Special RUSH condition)
Since the game flow in the special RUSH state is basically the same as that in the normal RUSH state, only the parts different from the normal RUSH state will be described below.

  As shown in FIG. 43, when the main CPU 101 is not hitting “7 lips” (“F_7 lip A_1st” to “F_7 lip B_3rd”) in the RT4 state (7 lip non-winning), the other presses In the case where the forward notification is performed and “7 lip” (“F_7 lip A_1st” to “F_probability 7 lip B_3rd”) in the RT4 state is won (7 lip winning), and the number of notifications is 1 or more. In some cases (that is, during the notification period), the stop operation procedure for establishing “7-matched lip” is notified, and the stop operation procedure for establishing “7-matched lip” is notified. Based on the above, the ART period grant lottery is performed, and then the number of continuations is incremented by 1 (that is, the duration of the special RUSH state is counted).

  When the number of continuations reaches nine games (number of continuations = 9), the main CPU 101 performs a RUSH type lottery that determines the RUSH type to be added based on the random number value. Specifically, the RUSH type is determined with reference to Table A (see FIG. 51, which will be described later) of an addition RUSH type lottery table which will be described later.

  In addition, the privilege given when the number of continuations is nine games is not limited to the grant of the RUSH type. As described above, a kind of granting right that can be indirectly granted ART period may be granted, for example, the ART period is directly given as the number of games in the same manner as granting ART period. You may do it. In other words, the “RUSH type lottery” in the special RUSH state only requires that the ART period be additionally given to the player as a result, and includes all of those that are granted the right related to the ART period.

  The main CPU 101 additionally stores the RUSH type determined as a result of the RUSH type lottery as the RUSH stock. Thereby, when the ART period ends, it becomes possible to shift to the RUSH state again (see FIG. 31). In addition, with the addition of the RUSH stock, the continuation count is cleared (initialized), and the process in the special RUSH state is terminated.

  That is, the number of continuations is 9 games, RUSH stock is awarded, and the special RUSH state continues even if the number of continuations is cleared once. Then, as long as the special RUSH state continues, the continuation count is added again, and when the continuation count becomes 9 games again, RUSH stock is further given. Here, in the special RUSH state, since the number of games as the end condition is not set, it is possible to continue to provide the RUSH stock every time nine games are continued. Therefore, in the special RUSH state, the internal winning combination other than “7 lip” in the RT4 state (for example, push order small combination) is an extendable combination of the special RUSH state, and winning the extended combination combination is a game. Even if it is advantageous to the player, even in a game won by an internal winning combination other than “7 lip” in the RT4 state, a game that can enhance the interest of the game is realized.

  Note that although not shown in FIG. 43, the sub CPU 201 produces a narrative effect that is completed in nine games each time the game in the special RUSH state progresses once (the continuation number is incremented by one). Produce a progress suggestion effect that is advanced once. The progress suggestion effect is displayed, for example, as “1/9” if the number of continuations is “1”, and as “2/9” if the number of continuations is “2”. For example, a display in which the number of games corresponding to the current number of continuations and the target number of games can be grasped simultaneously may be performed. Then, when the number of times of continuation becomes “9”, it may be notified that a right (RUSH stock) that is advantageous to the player is granted directly or indirectly. That is, the progress suggestion effect suggests that the degree of progress of the number of continuations in the special RUSH state is suggested, and that the number of continuations reaches a predetermined number (9 games) has some meaning. Can be used.

  In addition, although not shown in FIG. 43, the number of notifications becomes 0 before the number of continuations reaches nine games, the procedure of the stop operation for establishing “RT3 transition lip” is notified, and the control state is ART. In the case of a transition to a state, the number of continuations in the middle is maintained until the transition to the next special RUSH state, and in the next special RUSH state, the count of the number of continuations is restarted from the number of continuations in the middle Is done. For example, if the number of continuations in the current special RUSH state is 5 games, when the next special RUSH state is started, the initial value of the number of continuations is 5 games, and this next special RUSH state is continued for 4 games. If it can be made, the number of continuations will be 9 games, and RUSH stock will be additionally provided (added). Therefore, even if the special RUSH state ends without the duration in the special RUSH state reaching the period during which the RUSH stock can be additionally granted (added), the expectation in the next special RUSH state is maintained. It can be maintained, and it can prevent that the interest of a game declines.

  Here, the number of midway continuations is retained until the next transition to the special RUSH state, but in the special RUSH state, it is retained until additional RUSH stock is added (added). You can also That is, even in the next special RUSH state, if the special RUSH state ends without the continuation period in the special RUSH state reaching the period during which RUSH stock can be additionally granted (added), the result is further calculated. It is also possible to hold the number of halfway continuations, and restart the counting of the number of continuations from the number of continuations in the middle in the subsequent special RUSH state.

  Note that the number of continuations in the middle of the number of times held is determined when a series of advantageous states ends (that is, when the ART state ends and the RUSH stock and the CZ stock are shifted to the normal state, or in the withdrawal state, the withdrawal fails. (When transitioning to the normal state), it may be cleared (initialized), or cleared (initialized) when a setting change or initialization condition is satisfied (see FIG. 13). You may do it. In addition, it may not be cleared (initialized) depending on other triggers until RUSH stock is additionally provided (added) in the special RUSH state.

  In the special RUSH state, the main CPU 101 shifts the control state to the ART state when the RT3 transition lip is established when “7 lip” in the RT4 state is reached when it is not the notification period. On the other hand, when there is no transition to another control state, the game in the special RUSH state is controlled by repeatedly performing the process in the special RUSH state (see FIG. 43).

  As described above, in this embodiment, a notification period is provided (for example, a guarantee notification period and an additional notification period are provided) by a plurality of different triggers, and the game period is in an advantageous state (for example, an ART state). In a specific state in which a right can be granted (for example, a RUSH state), if the notification period is set, the right is granted in response to a specific notification being made. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the present embodiment, in a specific state (for example, a special RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted, a special combination (for example, “7 lip” in RT4) is won. Sometimes, in the notification period, the right is granted in response to the specific notification being performed. On the other hand, if it is not the notification period, the specific state ends without performing the specific notification. Otherwise, when a predetermined combination (for example, other than “7 Lip” in RT4) is won, the specific state continues. And when a specific state continues for a predetermined period (for example, between 9 games), the said right is separately provided. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the present embodiment, in a specific state (for example, a special RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted, a special combination (for example, “7 lip” in RT4) is won. Sometimes, in the notification period, the right is granted in response to the specific notification being performed. On the other hand, if it is not the notification period, the specific state ends without performing the specific notification. Otherwise, when a predetermined combination (for example, other than “7 Lip” in RT4) is won, the specific state continues. And when a specific state continues for a predetermined period (for example, between 9 games), the said right is separately provided. In addition, even if the specific state ends without continuing for a predetermined period, the midway continuation period is maintained until the next specific state, and in the next specific state, the predetermined period starts from the held midway continuation period. Configured to resume. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  In the present embodiment, a predetermined lottery (for example, an additional notification period lottery) is provided for each predetermined opportunity in a specific state (for example, a RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted. When a win is made, a predetermined right (for example, the number of notifications) is given and the predetermined lottery is continued. On the other hand, when not winning, the predetermined right is not given and the predetermined lottery ends. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only when it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues, and even when the notification is not performed, the predetermined lottery may continue. Therefore, it is possible to make a player play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

  In the present embodiment, a predetermined lottery (for example, an additional notification period lottery) is performed for each game in a specific state (for example, a RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted. If the player wins, a predetermined right (for example, the number of notifications) is given and the predetermined lottery continues. On the other hand, if the player does not win, the predetermined right is not given and the predetermined lottery ends. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only in a game for which it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues, and even when the notification is not performed, the predetermined lottery may continue. Therefore, it is possible to make a player play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

  In the present embodiment, a predetermined lottery (for example, an additional notification period lottery) is performed for each game in a specific state (for example, a RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted. In the event of winning, a predetermined right (for example, the number of notifications) to be given once is given and a predetermined lottery is continued, while in the case of not winning, a predetermined right is granted. The predetermined lottery is finished. In the specific state, a specific right (for example, an ART period) is granted in response to the specific notification. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only when it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues and the number of times that the specific notification can be performed, and even if the notification is not performed, the player can recognize the predetermined lottery. Since there are cases where the game continues, it is possible to cause the player to play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

[Game flow in ART state]
Next, with reference to FIGS. 45 to 47, the flow of the game in the above-described ART state will be described. FIG. 45 is a diagram for explaining the flow of the game in the ART state, and is a diagram for explaining an outline of various controls performed by the main CPU 101 and the sub CPU 201. FIG. 46 is a diagram showing an example of various data tables (lottery tables) stored in the main ROM 102 that are referred to when the main CPU 101 performs various controls in the ART state. It is a figure which shows an example of the presentation control performed in an ART state.

  As shown in FIG. 45, the main CPU 101 performs a sphere grant lottery based on the internal winning combination and the random number value. Specifically, the presence / absence of sphere addition is determined with reference to the sphere addition lottery table shown in FIG. As described above, the sphere functions as a split right (point) for determining whether or not RUSH stock is granted during the ART state (RT3), and at the end of the ART state (RT3), the withdrawal state Or functions as a right (CZ stock) for extending the retracted state.

  When the sphere giving lottery results in 3 points (sphere = 3) as a result of the sphere grant lottery, the main CPU 101 performs a RUSH type lottery that determines the RUSH type to be added based on the random number value. Specifically, the RUSH type is determined with reference to Table A (see FIG. 51, which will be described later) of an addition RUSH type lottery table which will be described later.

  The main CPU 101 additionally stores the RUSH type determined as a result of the RUSH type lottery as the RUSH stock. Thereby, when the ART period ends, it becomes possible to shift to the RUSH state again (see FIG. 31). In addition, as the RUSH stock is added, the sphere is cleared (initialized).

  The sub CPU 201 performs the sphere conversion effect when the sphere is 3 points and the RUSH stock is added. This sphere conversion effect is an effect for notifying that the right related to the ART period (in this case, RUSH stock) has been granted, and an example thereof is shown in FIG.

  As shown in FIG. 47, in the ART state (including the acquisition result in the battle state), when the player acquires three spheres, the display device 11 is notified of this and the spheres are synthesized. Thus, the fact that the RUSH stock has been acquired is notified (Sphere 3 → RUSH1). That is, a lower privilege is converted into a higher privilege and notified. Thereby, the player can recognize that the RUSH stock has been added.

  On the other hand, as shown in FIG. 47, the flow effect described above is also performed when the RUSH stock is directly acquired in the ART state (including the acquisition result in the battle state) (RUSH1 → Sphere 3). In other words, even if the upper privilege is directly granted, it is once converted into a lower privilege for the production, and it is reported that the upper privilege is granted by converting the lower privilege. It has become.

  In the present embodiment, in the ART state, until the ART period ends, the sphere (lower privilege) is collected and converted into the RUSH stock (upper privilege) to continue the advantageous state (or by pulling back) Since the game is one of the game characteristics, the player's interest in acquiring the sphere is high. Therefore, even if the upper privilege is directly granted, on the production, once converted to the lower privilege, by performing the effect as if the lower privilege was acquired and the upper privilege was granted, Various notifications in the advantageous state.

  Although not shown, in the ART state, the current number of spheres (the number of points and the number of divided rights) is always displayed on the sub display device 18. However, the display mode for displaying the current number of spheres is not limited to this. For example, the current number of spheres may be constantly displayed in a predetermined area of the display device 11, or a dedicated sphere lamp (not shown) may be provided to constantly display the current number of spheres.

  The main CPU 101 performs a battle transfer lottery based on the internal winning combination and the random value. Specifically, referring to the battle transition lottery table shown in FIG. 46, the presence / absence of transition to the battle state and the type (pattern) of the battle state when transitioning are determined.

  When the main CPU 101 determines to shift to the battle state as a result of the battle transfer lottery (battle winning), the main CPU 101 performs the sign game number lottery based on the random number value. In this precursor game number lottery, the number of precursor games is determined from the number of precursor games within five games. However, the number of precursor games exceeding the remaining ART period is not determined. For example, if the remaining ART period is 0 games, the number of precursor games is 0 games.

  The main CPU 101 selects the “normal pattern 1” or “normal pattern 2” as the battle state as a result of the battle transfer lottery, and selects the “special pattern” in the battle state before the previous time. In addition, when the “special pattern” is held based on the fact that the battle state has ended without any additional occurrence (privilege is given), the battle state is rewritten to the “special pattern”. That is, the “special pattern” carried over is resumed from the state carried over.

  The main CPU 101 notifies the pressing order. In the ART state, a stop operation procedure for maintaining the RT state in the RT3 state is notified, and a stop operation procedure that can receive more medals is notified. Further, as described above, when winning from “F_7 Lip_123” to “F_7 Lip_321”, the procedure of the stop operation to become the full navigation or the first stop navigation may be notified with a predetermined probability. Similarly, when “F_chance lip_123” to “F_chance lip_321” are won, the procedure of the stop operation to become all navigation or the first stop navigation may be notified with a predetermined probability.

  When the main CPU 101 determines to shift to the battle state as a result of the battle shift lottery (battle winning), the main CPU 101 shifts the control state to the battle state.

  When the main CPU 101 has not decided to enter the battle state as a result of the battle transfer lottery (the battle is not winning) and is in the ART period (the ART period is not digested), the processing in the ART state is performed. Exit.

  When the ART period ends (ART period consumption), if the RUSH stock is 1 or more, the main CPU 101 shifts the control state to the RUSH state. Further, if the sphere (CZ stock) is 1 or more, the control state is moved to the pull back state. If both the RUSH stock and the sphere (CZ stock) are 0, the advantageous state is terminated and the control state is shifted to the normal state.

  In the ART state, the main CPU 101 shifts the control state to the RUSH state when the ART period is exhausted and the RUSH stock is 1 or more, and changes the control state to the pull-back state when the CZ stock is 1 or more. When the RUSH stock and the CZ stock are 0, the control state is shifted to the normal state. Further, when the battle is won, the control state is shifted to the battle state. On the other hand, when there is no transition to another control state, the game in the ART state is controlled by repeatedly performing the above-described processing in the ART state (see FIG. 45).

  As described above, in the present embodiment, as the right related to the game period in the advantageous state (for example, the ART state), the first right (for example, the subordinate privilege) that can be used to determine whether to extend the game period in the advantageous state or not. CZ stock) and a second right (for example, RUSH stock, which is a superior privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, three) ), The second right is granted. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the present embodiment, as a right related to a game period in an advantageous state (for example, ART state), a first right (for example, a subordinate privilege) that can be used to determine whether or not to extend the game period in the advantageous state. CZ stock) and a second right (for example, RUSH stock, which is a higher-order privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, three) The second right is granted when the other right conditions are met, and at this time, the player is informed that the first right number has increased by a predetermined number. Has been. That is, even when the upper privilege is given, it is converted into a lower privilege and notified. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state and to improve the interest of the game. In addition, it is possible to provide highly interesting notifications by utilizing the rule of privilege provision based on game play.

  Further, in the present embodiment, as a right related to a game period in an advantageous state (for example, ART state), a first right (for example, a subordinate privilege) that can be used to determine whether or not to extend the game period in the advantageous state. CZ stock) and a second right (for example, RUSH stock, which is a higher-order privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, three) The second right is granted. In the advantageous state, the first right number is notified. That is, the number of lower-order benefits that can be converted into higher-order benefits is indicated to the player. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state and to improve the interest of the game. In addition, it is possible to provide highly interesting notifications by utilizing the rule of privilege provision based on game play.

  Further, in the present embodiment, even if the advantageous game period has elapsed without the first right number being a predetermined number, the advantageous state withdrawal lottery is performed in a period corresponding to the first right number. Is configured to be performed. In other words, even when the second right (upper privilege) is not granted, the granted first right (lower privilege) is not wasted. Therefore, even if it is not determined to extend the advantageous game period, it is possible to suppress a decrease in the interest of the game and thereby maintain the player's expectation.

[Battle game flow]
Next, with reference to FIGS. 48 to 53, the flow of the game in the battle state described above will be described. FIG. 48 is a diagram for explaining the flow of the game in the battle state, and is a diagram for explaining the outline of various controls performed by the main CPU 101 and the sub CPU 201. 49 to 51 are diagrams illustrating examples of various data tables (lottery tables) stored in the main ROM 102 that are referred to when the main CPU 101 performs various controls in the battle state, and are illustrated in FIGS. 52 and 53. These are figures which show an example of the presentation control which sub CPU201 performs in a battle state.

  As shown in FIG. 48, the main CPU 101 performs map lottery based on the random number value when the battle state is started (when the battle is started) or when the battle state is continued (when the battle is continued). Specifically, a battle map is determined with reference to a battle map lottery table shown in FIG.

  As shown in FIG. 49, the battle map indicates in advance the degree of expectation (degree of advantage) that damage (points) is given for each unit game in a battle state that continues for a predetermined period (8 games in this embodiment). It is determined. For example, a game with a specified damage expectation level of “low” is more difficult to receive points than a game with a expected level of damage expectation of “high”, or lottery values are specified so that fewer points are granted. The Therefore, if a battle map with many games with a high expectation of damage “High” (for example, battle map “8”) is determined, a battle map with many games with a low expectation of damage “Low” is determined. (For example, when the battle map “0”) is determined, the degree of expectation that the points given in the battle state are greater than or equal to the specified points (that is, an extra is generated (a privilege is given)) is higher. .

  In the determined battle map, which game in the battle state is defined as the damage expectation “high” is displayed on the display device 11 (see FIGS. 52 and 53). .

  The main CPU 101 notifies the pressing order. In the battle state, a stop operation procedure for maintaining the RT state in the RT3 state is notified, and a stop operation procedure for receiving more medals is notified. Further, as described above, when winning from “F_7 Lip_123” to “F_7 Lip_321”, the procedure of the stop operation to become the full navigation or the first stop navigation may be notified with a predetermined probability. Similarly, when “F_chance lip_123” to “F_chance lip_321” are won, the procedure of the stop operation to become all navigation or the first stop navigation may be notified with a predetermined probability. In the battle state, since the ART period does not decrease (that is, the number of games given is not subtracted), it can be said that the transition of the battle state itself is an extension of the advantageous game period.

  The main CPU 101 performs damage lottery (ie, grant point lottery) based on the expected damage level, internal winning combination, and random value in the game. Specifically, the damage (given points) is determined with reference to the damage lottery table shown in FIG. Note that FIG. 50 shows a damage lottery table when the damage expectation level is “low”, and the damage lottery table when the damage expectation level is “high” is not shown, but from that shown in FIG. In addition, the lottery value is defined so that the degree of expectation of the granted points is high (the points are easily given). Then, the main CPU 101 cumulatively stores the damage (points) applied as a result of the damage lottery.

  The main CPU 101 ends the process in the battle state when the battle period (8 games from the start of the battle or the continuation of the battle) has not elapsed (the battle period has not been consumed).

  When the battle period has passed (maintenance of the battle period) and the points assigned at that time have reached the specified points (10 points or more in the present embodiment) (the specified points have been reached), the main CPU 101 Based on the random number value, the ART period extra lottery for determining the ART period to be extended (the number of ART games to be added) is performed. Specifically, the ART period to be extended (the number of ART games to be added) is determined with reference to the ART period additional grant lottery table shown in FIG.

  Here, in the ART period extra lottery table shown in FIG. 51, the specified points (that is, the cumulative points given in the battle state) are “10” or more and less than “15” (that is, “10” to “14”). Range), when it is “15” or more and less than “20” (that is, a range of “15” to “19”), and when it is “20” (in this example) Then, the content of the ART period) may be different. Specifically, the degree of advantage related to the granting of rights is higher when the accumulated points are in the range of “15” to “19” than in the range of “10” to “14” (ie, , More ART period is more likely to be granted), and the degree of advantage for granting rights in the range of “10” to “14” and in the range of “20” than in the range of “15” to “19” (That is, more ART periods are likely to be given).

  In the present embodiment, the maximum value of the specified points is “20”, but the points may be accumulated up to an arbitrary value exceeding “20” (for example, “99”). In this case, when the specified point is “20” or more and is in a range up to the arbitrary value (for example, a range of “20” to “99”), the column “20” in FIG. 51 is referred to. The ART period may be determined. The same applies to the later-described Sphere / RUSH addition grant lottery table shown in FIG.

  The main CPU 101 determines the type of additional privilege (sphere and / or RUSH stock to be added) based on the result of the ART period extra grant lottery, the specified points, and the random number value. Do lottery. Specifically, the ART period to be extended (the number of ART games to be added) is determined with reference to the Sphere / RUSH extra grant lottery table shown in FIG. The type of privilege to be additionally given is determined.

  Here, in the Sphere / RUSH extra grant lottery table shown in FIG. 51, the specified point (that is, the total of points granted in the battle state) is “10” or more and less than “15” (that is, “10” to “14”). ), And “15” or more and less than “20” (that is, the range of “15” to “19”), and “20”, the degree of advantage regarding the granting of rights (in this example, The RUSH stock as the upper privilege and / or the sphere as the lower privilege) may be different. Specifically, it is more advantageous for granting rights when the accumulated points are in the range of “10” to “14” and in the range of “20” than in the range of “15” to “19”. The degree is increased (that is, the higher privilege is easily given). However, in the above-mentioned ART period extra lottery table, the number of ART games “50” or “100” is more in the range of “15” to “19” than in the range of “10” to “14”. Is more likely to be determined, so that the degree of advantage related to the granting of rights is substantially higher in the range of “15” to “19” than in the range of “10” to “14”. (In other words, the upper privilege is easily given). In the same way as the above-mentioned ART period extra lottery table, lottery values may be set so that the degree of advantage related to the grant of rights increases in accordance with the points given.

  Further, the technique for varying the degree of advantage related to the right grant is not limited to the technique using the ART period extra lottery table or the Sphere / RUSH extra lottery table shown in FIG. If the number of points granted is large, as a result, the degree of advantage related to the granting of rights may be relatively increased, and if the number of points granted is small, the degree of advantage related to the granting of rights may be relatively reduced as a result. For example, other various methods can be employed.

  Further, the range of points for varying the degree of advantage related to the right granting is not necessarily a continuous numerical range, and is not limited to the one in which the degree of advantage related to the right grant increases sequentially as the number of points increases. For example, a predetermined numerical range including the specified point “15” (for example, “15” to In the range of “17”, the degree of advantage relating to the granting of rights is higher, and in the range of these ranges, a predetermined numerical range including the specified point “20” (for example, “20” to “99”) is obtained. The degree of advantage related to the granting of rights may be increased in the range of In this case, for example, in the range of the specified points “13” to “14” and in the range of “18” to “19”, the degree of advantage related to the right grant is lower than that in the range of “10” to “12”. It can also be done. If it does in this way, the advantageous degree of grant of a right can be changed further, the tension feeling for every game in a battle state can be raised, and an interest can be improved more.

  When the main CPU 101 decides to add RUSH stock as a result of the sphere / RUSH extra lottery, the main CPU 101 determines the RUSH based on the table (that is, the table A or the table B) designated at that time and the random value. Perform type lottery. Specifically, the RUSH type to be added is determined with reference to the extra RUSH type lottery table shown in FIG. Then, the battle state is terminated and the control state is shifted to the ART state.

  When the battle period has passed (digestion of the battle period) and the points assigned at that time have not reached the specified point (10 points or more in the present embodiment) (the specified point has not been reached), the main CPU 101 Based on the state pattern type (that is, “normal pattern 1”, “normal pattern 2”, and “special pattern”) and a random number value, a battle continuation lottery for determining whether or not to continue the battle state is performed. For example, in the case of “normal pattern 1” or “special pattern”, it is determined to continue the battle state with a probability of 1/10, and in the case of “normal pattern 2”, the probability of ½ It is decided to continue the battle state. Note that the timing at which the battle continuation lottery is performed may be when the battle state starts.

  When the main CPU 101 determines to continue (extend) the battle state as a result of the battle continuation lottery (battle continuation), the main CPU 101 ends the process in the battle state.

  When the main CPU 101 does not decide to continue (extend) the battle state as a result of the battle continuation lottery (battle end), if it is a “special pattern”, as described above, in the next battle state, In order to resume the “special pattern”, information to that effect is held, and damage (granting points) is also carried over to the next battle state, so that information relating to points given halfway to the specified points is also held. As a result, in the next battle state, the “special pattern” is resumed with the granted points carried over.

  Note that, for example, only damage (given points) is retained (that is, carried over), and the type of battle state (that is, pattern) is determined again by the lottery result of the battle transition lottery (see FIG. 45). You may do it. Further, for example, only the state (that is, the pattern) of the battle state is retained (that is, carried over), and the damage (given point) may not be retained (that is, not carried over). In this case, it is preferable that the “special pattern” is a type of battle state in which a right related to the most advantageous game period is easily given.

  In the battle state, the main CPU 101 is in a case where the battle period is exhausted, when the granted point has not reached the specified point and the battle has ended, and when the assigned point has reached the specified point and the battle has ended, The control state is shifted to the ART state. On the other hand, when there is no transition to another control state, the game in the battle state is controlled by repeatedly performing the above-described process in the battle state (see FIG. 48).

  Next, an example of the effect display in the battle state will be described with reference to FIGS. 52 and 53.

  FIG. 52 is an example of an effect display showing a state in which the damage (granting point) has reached the specified point in the battle state and has further reached the maximum value of the specified point (20 in the present embodiment).

  In the battle state, for example, a display corresponding to the above-described battle map (that is, a display corresponding to 8 squares indicating the expected damage degree for 8 games) and a display corresponding to the current damage (giving points) (ie, For battle production, display of 10 squares displayed as enemy character's HP (enemy HP) and enemy character type display (that is, “normal pattern 1”, “normal pattern 2”, or “special pattern”) Display corresponding to the battle map and the display content corresponding to the current damage (granting points) are appropriately changed as the battle state progresses. .

  As shown in FIG. 52, in this example, the battle map “0” is selected, damage is given 5 in the battle state 4th game (5 points are given), and in the battle state 5th game, Damage of 5 is given (5 points are given), and the minimum value of 10 is reached. In addition, when the battle state is 7th game, further damage is given (5 points are given), and when the battle state is 8th game, 5 damage is given (5 points are given), and the battle state ends. It is shown that the maximum value 20 of the specified points has been reached.

  FIG. 53 shows a case where damage (granting points) does not reach the specified point in the battle state, and “normal pattern” is selected and “special pattern” is selected. It is an example of the effect display which shows each of these.

  As shown in FIG. 53, when the “normal pattern” (“enemy 1” in FIG. 53) is selected and the battle state ends without reaching the specified point, the next battle state Since neither the “special pattern” nor the granted points are carried over, the specified point must be reached again from 0 points in the next battle state.

  On the other hand, as shown in FIG. 53, when the “special pattern” (“enemy 2” in FIG. 53) is selected and the battle state ends without reaching the specified point, the next battle state Since it is a “special pattern” and given points are also carried over, it is only necessary to reach the specified point from the resumed point in the next battle state. In the example of FIG. 53, it is shown that the damage (granting points) is 3 points in the battle state by the first “special pattern”, and these 3 points are carried over in the battle state by the next “special pattern”. Has been.

  As described above, in a specific state (for example, battle state) in which a right related to a game period in an advantageous state (for example, ART state) can be granted, the points awarded within a predetermined period (for example, 8 games) are equal to or more than a specified point. In such a case, the right may be granted and the degree of advantage regarding the grant of the right may differ depending on the range within the specified point or more. Specifically, when the given point is equal to or greater than a second value (for example, “15”), it is equal to or greater than the first value (for example, “10”) and less than the second value. The degree of advantage related to the granting of the right is higher than the case where the right is granted. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in this embodiment, although the degree of advantage related to the granting of rights may vary depending on the range within which the granted points are equal to or higher than the specified points, the right is granted when the specified points are exceeded. It is configured to be granted. Therefore, the gameability in a specific state can be varied without impairing the player's sense of expectation for granting rights.

  Further, in the present embodiment, in a specific state (for example, battle state) where a right related to a game period in an advantageous state (for example, ART state) can be granted, points given within a predetermined period (for example, 8 games) are defined. The right may be granted when the number of points is exceeded, and the degree of advantage regarding the granting of the right may differ depending on the range within the specified points or more. Specifically, when the given point is greater than or equal to a third value (for example, “20”) when the predetermined period ends, it is less than the third value. Rather, the degree of advantage related to the granting of the right is increased. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in this embodiment, it is comprised so that the advantageous degree regarding a right provision may increase sequentially according to in which range the provided point is beyond a regulation point. Therefore, the expectation regarding the granting of rights in a specific state can be sequentially increased, and the interest of the game can be improved.

  Further, in the present embodiment, in a specific state (for example, battle state) where a right related to a game period in an advantageous state (for example, ART state) can be granted, points given within a predetermined period (for example, 8 games) are defined. The right may be granted when the number of points is exceeded, and the degree of advantage regarding the granting of the right may differ depending on the range within the specified points or more. Further, in a specific state, it is determined in advance whether the game is easy to give points (for example, damage expectation “high”) or difficult to receive points (for example, damage expectation “low”). The game is informed of which game it is. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the present embodiment, in a specific state (for example, battle state) where a right related to a game period in an advantageous state (for example, ART state) can be granted, points given within a predetermined period (for example, 8 games) are defined. In the case of a point, the right is granted. On the other hand, if the granted point does not become a specified point, the right is not granted. In this case, however, the second specific state (for example, “special” Pattern "), the assigned points are carried over to a specific state after the next time. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the present embodiment, in a specific state (for example, battle state) where a right related to a game period in an advantageous state (for example, ART state) can be granted, points given within a predetermined period (for example, 8 games) are defined. In the case of a point, the right is granted. On the other hand, if the granted point does not become a specified point, the right is not granted. In this case, however, the second specific state (for example, “special” If “pattern”), the second specific state can be performed from the previous time the next time the specific state is started. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the present embodiment, in a specific state (for example, battle state) where a right related to a game period in an advantageous state (for example, ART state) can be granted, points given within a predetermined period (for example, 8 games) are defined. When the number of points is exceeded, the right is granted. On the other hand, when the granted point does not become the specified point, the right is not granted. In this case, however, the second specific state (for example, “ In the case of “special pattern”), the assigned points are carried over to a specific state after the next time. And in a specific state, it is comprised so that the said right of the more advantageous content may be provided, so that there are many points provided. That is, even if the right is not granted in a specific state, if the granted points are carried over, it is expected that the right with more advantageous contents will be granted in the specific state after the next time. The degree will increase. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

[Returned game flow]
Next, with reference to FIG. 54 and FIG. 55, the flow of the game in the pull-back state described above will be described. FIG. 54 is a diagram for explaining the flow of the game in the pull-back state, and is a diagram for explaining an outline of various controls performed by the main CPU 101. FIG. 55 is a diagram showing an example of various data tables (lottery tables) stored in the main ROM 102 that are referred to when the main CPU 101 performs various controls in the retracted state.

  As shown in FIG. 54, the main CPU 101 notifies the pressing order. In the retracted state, a stop operation procedure for maintaining the RT state in the RT3 state is notified, and a stop operation procedure for receiving more medals is notified. Further, as described above, when winning from “F_7 Lip_123” to “F_7 Lip_321”, the procedure of the stop operation to become the full navigation or the first stop navigation may be notified with a predetermined probability. Similarly, when “F_chance lip_123” to “F_chance lip_321” are won, the procedure of the stop operation to become all navigation or the first stop navigation may be notified with a predetermined probability. As described above, the withdrawal state continues for three games per sphere, so the transition of the withdrawal state itself can be said to be an extension of the gaming period in the advantageous state.

  The main CPU 101 performs a RUSH (ART) pull-back lottery that determines whether or not to return to the RUSH state again based on the internal winning combination and the random number value. Specifically, referring to the RUSH pullback lottery table shown in FIG. 55, whether or not to return to the RUSH state again and the RUSH type in the case of returning are determined. In the RUSH pullback lottery table shown in FIG. 55, “other rare roles” are “F_CD_chance lip”, “F_C_chance lip”, “F_chance lip_123” to “F_chance lip_321” (“chance lip”). "F_T_rare bell", "F_B_rare bell" (including 10 sheets (including Lerea: upper and lower stages)), "F_1 sheet combination A", "F_1 sheet combination B", and the like.

  When the main CPU 101 wins the RUSH (ART) pull-back lottery (RUSH win), the main CPU 101 shifts the control state to the RUSH preparation state. At this time, if there is a sphere that has not been used for lottery, it may be carried over to the next ART state, or the sphere may be cleared to 0 (initialized).

  When the main CPU 101 does not win the RUSH (ART) pull-back lottery (RUSH non-win), the main CPU 101 subtracts 1 from the pull-back game number (decreases the pull-back period). At this time, if the number of withdrawal games is not 0, the processing in the withdrawal state is terminated.

  When the number of withdrawal games is 0 (number of withdrawal games = 0) and the sphere is also 0 (no sphere), the main CPU 101 ends the withdrawal state and shifts the control state to the normal state. .

  When the number of withdrawal games is 0 (number of withdrawal games = 0) and the sphere is still 1 or more (there is a sphere), the main CPU 101 subtracts 1 from the sphere and performs a withdrawal game (this implementation) In the embodiment, 3 games) are reset, and the process in the retracted state is terminated.

  In the present embodiment, the duration in the withdrawal state is set to 3 games per sphere, but is not limited to this. For example, the number of games per sphere may be determined by lottery. For example, when there is one sphere, the duration period lottery may be performed, and the duration period may be determined within a range of 3 to 10 games.

  When the main CPU 101 wins the RUSH in the pull-back state, the control state is shifted to the RUSH state, the number of the pull-back games becomes 0 (the pull-back period is consumed), and the CZ stock becomes 0 The control state is shifted to the normal state. On the other hand, when there is no transition to another control state, the game in the pullback state is controlled by repeatedly performing the process in the pullback state (see FIG. 54).

<Description of main control circuit operation>
Next, the contents of various processes executed by the main CPU 101 of the main control circuit 90 using a program will be described with reference to FIGS.

[Processing at power-on (reset interrupt)]
First, the process at the time of power-on (reset interrupt) of the pachislot 1 performed under the control of the main CPU 101 will be described with reference to FIGS. FIG. 56 is a flowchart showing a procedure of processing at power-on (reset interrupt). FIGS. 57A to 57C are sources for executing the processing of S2, S7 and S8 and S13 in the flowchart, respectively. It is a figure which shows an example of a program. The power-on (reset interrupt) process shown in FIG. 56 is performed when the power management circuit 93 detects that the supply of power supply voltage to the microprocessor 91 is started. This is executed based on an interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 determines whether or not the power monitoring port (power monitoring means) is in an on state (S1).

  In S1, when the main CPU 101 determines that the power monitoring port is on (when S1 is YES), the main CPU 101 repeats the process of S1. Here, the power monitoring port being in the ON state is a state where the power supply voltage (DC + 5V) supplied to the main CPU 101 is not stable.

  On the other hand, when the main CPU 101 determines in S1 that the power monitoring port is not in the ON state (when S1 is NO), the main CPU 101 performs initialization processing of the timer circuit 113 (PTC) (S2). In this process, the main CPU 101 performs initial setting of the timer circuit 113. Specifically, the main CPU 101 sets a division ratio in a timer prescaler register (not shown), sets an interrupt enable setting in the timer control register (not shown), and sets a timer counter (not shown). Set the initial count value.

  Next, the main CPU 101 initializes the first serial communication circuit 114 (SCU1) between the main control circuit 90 and the sub control circuit 200, and the second serial communication circuit 115 (SCU2) for the second interface board. An initialization process is performed (S3). Next, the main CPU 101 performs initialization processing of the random number circuit 110 (RDG) (S4). Next, the main CPU 101 performs a write test on the main RAM 103 (S5).

  Next, the main CPU 101 determines whether or not writing to the main RAM 103 has been normally performed as a result of the writing test (S6).

  In S6, when the main CPU 101 determines that the writing to the main RAM 103 has not been performed normally (when S6 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S6 that the writing to the main RAM 103 has been performed normally (when S6 is YES), the main CPU 101 determines the state of the timer control register (not shown) of the timer circuit 113. Is acquired (S7).

  Next, the main CPU 101 determines whether or not the current state is the generation timing of the interrupt process based on the acquired state of the timer control register (S8). Specifically, the main CPU 101 determines whether 1.1172 ms has elapsed since the start of the timer count based on the acquired state of the timer control register.

  In the present embodiment, when the timer time 1.1172 ms is set by the initialization process of the timer circuit 113 in S2, the count process of the CPU built-in timer is started. Thereafter, the status of the timer circuit 113 can be acquired by reading information in a timer control register (not shown). In this embodiment, a bit (determination bit) that can determine (refer to) whether or not the current state is the generation timing of an interrupt process (whether or not it is a timer interrupt state) in the timer control register. ) Is provided.

  Therefore, in the process of S7, the main CPU 101 reads information in the timer control register (not shown), and in the process of S8, the main CPU 101 turns on / off the discrimination bit in the timer control register ( By referring to “1” / “0”), it is determined whether or not the current state is the generation timing of the interrupt process. When 1.1172 ms elapses from the count start by the timer circuit 113 (if the count value of the timer circuit 113 is 0), the determination bit is turned on.

  In S8, when the main CPU 101 determines that the current state is not the generation timing of the interrupt process (when S8 is NO), the main CPU 101 returns the process to the process of S7 and repeats the processes after S7.

  On the other hand, when the main CPU 101 determines in S8 that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 performs a sum check process (not specified) (S9). . In this process, the main CPU 101 performs a sum check process of the main RAM 103, and the work of this process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. The program used in the sum check process is stored in an unspecified area in the main ROM 102 (see FIG. 12B). Details of the sum check process will be described later with reference to FIGS. 71 and 72 described later.

  In S8, when the main CPU 101 determines that the current state is the generation timing of the interrupt process (when S8 is YES), the main CPU 101 determines the below-described interrupt before the process of S9. (See FIG. 113 described later). As a result of this interrupt processing, a no-operation command is transmitted from the main control circuit 90 (main control board 71) to the sub control circuit 200 (sub control board 72).

  After the process of S9, the main CPU 101 determines whether or not the setting key type switch 54 is in an on state (S10).

  In S10, when the main CPU 101 determines that the setting key type switch 54 is in the ON state (when S10 is YES), the main CPU 101 performs the process of S15 described later. On the other hand, when the main CPU 101 determines in S10 that the setting key switch 54 is not in the ON state (when S10 is NO), the main CPU 101 determines the sum check based on the result of the sum check process in S9. It is determined whether or not the result is normal (S11).

  In S11, when the main CPU 101 determines that the sum check determination result is not normal (when S11 is NO), the main CPU 101 performs the process of S13 described later. On the other hand, when the main CPU 101 determines in S11 that the sum check determination result is normal (when S11 is YES), the main CPU 101 performs a game return process (S12). In this process, the main CPU 101 performs a process of returning the game state to the state before the power interruption detection. The details of the game return process will be described later with reference to FIG.

  When S6 or S11 is NO, the main CPU 101 displays a character string “rr” indicating an error occurrence on the information display 6 (7-segment LED display) (S13). Thereafter, the main CPU 101 repeats the WDT clear process (S14).

  Here, returning to the process of S10 again, if S10 is YES, the main CPU 101 performs a setting change confirmation process (S15). In this process, the main CPU 101 mainly performs a setting change command generation and storage process at the start of setting change. The details of the setting change confirmation process will be described later with reference to FIG.

  Next, the main CPU 101 performs a RAM initialization process (S16). In this process, the main CPU 101 sets the address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared). After the process of S16, the main CPU 101 starts a main process (described later, see FIG. 74).

  In the present embodiment, processing at power-on (reset interrupt) is performed as described above. Then, the process of S2 during the above power-on (reset interrupt) process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 57A.

  In the source program of FIG. 57A, 10 MHz is set as the CPU clock (supply clock is 20 MHz), 228 is set as the prescaler register setting value, and 49 is set as the initial count value. As a result, 1.1172 ms (= 1 / (10 MHz / 288) × 49) is calculated as the timer time (execution cycle) of the interrupt process.

  Further, the processing of S7 and S8 during the above-described power-on (reset interrupt) processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 57B. Specifically, the process of acquiring the state of the timer control register in S7 is executed by the “LD” instruction in FIG. 57B, and the determination process in S8 is executed by the “JBIT” instruction in FIG. 57B. Then, the “LD” instruction in FIG. 57B and the “JBIT” instruction in FIG. 57B are repeatedly performed until 1.1172 ms has elapsed since the timer circuit 113 started counting, and when 1.1172 ms has elapsed since the timer circuit 113 started counting. Then, an interrupt request signal is output from the timer circuit 113 to the main CPU 101 via the interrupt controller 112. The main CPU 101 starts the interrupt process of the first 1.1172 ms cycle after the power is restored, triggered by the input of this interrupt request signal.

  Note that in the first 1.1172 ms interrupt process immediately after the power is restored (after initialization at the time of power-on), no command related to the game operation is set, so that the main control circuit 90 transfers to the sub control circuit 200. A no-operation command is sent. In this way, by permitting the interrupt processing immediately after the power is restored, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  In addition, the communication parameters 1 to 5 constituting the no-operation command transmitted in this communication operation are set with data stored in the L register, H register, E register, D register, and C register, respectively, when the power is restored. Is done. Therefore, in the present embodiment, the data set in the communication parameters 1 to 5 of the no-operation command transmitted in the first interrupt process after the power return is made different (undefined) at each power return. Can do. That is, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power return (after initialization at the time of power-on) can be made different for each power return. In this case, fraudulent acts such as goto can be suppressed.

  Further, the processing of S13 (interrupt prohibition processing) during the above-described power-on (reset interrupt) processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 57C. . Then, the control for displaying the error code “rr” on the 2-digit 7-segment LED in the information display 6 is executed by one source code “LDW HL, 100H * cZCHRAR + cBX_PAYSEG” as shown in FIG. 57C. Then, the output operation of the 7-segment common output data to the 2-digit 7-segment LED and the output operation of the 7-segment cathode output data are simultaneously performed.

  That is, in the pachi-slot 1 of the present embodiment, when the two-digit 7-segment LED is controlled to be dynamically lit, 7-segment common output data and 7-segment cathode output data are simultaneously output. In this case, it is possible to reduce the number of instruction codes necessary for dynamic lighting control of the 7-segment LED on the source program, and to reduce the capacity of the source program (usage capacity of the main ROM 102). Therefore, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Here, “7-segment common output data” is LED drive data output to the common (common) terminal of the 7-segment LED when the 7-segment LED is dynamically controlled, and “7-segment cathode output data” is , LED drive data output to each cathode terminal of the 7-segment LED when the 7-segment LED is dynamically controlled.

[Game return processing]
Next, with reference to FIG. 58 and FIG. 59, the game return process performed in S12 during the power-on (reset interrupt) process (see FIG. 36) will be described. FIG. 58 is a flowchart showing the procedure of the game return process, and FIG. 59 is a diagram showing an example of a source program for executing the processes of S25 to S32 in the flowchart.

  First, the main CPU 101 sets the stack pointer at the time of power interruption to the stack pointer (SP) (S21). Next, the main CPU 101 clears (turns off) the on-edge data before the interrupt processing of the input port and the currently set on-edge data (S22). Next, the main CPU 101 sets the backup data of the output port to the output port (S23). Next, the main CPU 101 reads the data of the input port and saves the data in the data storage area of the current input port and before the one interrupt process (S24).

  Next, the main CPU 101 sets the address of the spinning cylinder control data storage area (S25). Next, the main CPU 101 sets the number of reels to be checked (“3” in this embodiment) (S26).

  Next, the main CPU 101 acquires reel control management information (data relating to display row fluctuation control when power interruption occurs) based on the address of the set spinning cylinder control data storage area (S27). Note that the reel control management information (display row variation control management information) is information related to the control state (rotation state) of each reel, and is backed up and stored when power is interrupted.

  Next, the main CPU 101 determines whether or not the reel control management information is information corresponding to the rotation state during the reel acceleration, the constant speed waiting, or the constant speed (S28).

  In S28, when the main CPU 101 determines that the condition of S28 is not satisfied (when S28 is NO), the main CPU 101 performs a process of S31 described later. On the other hand, when the main CPU 101 determines in S28 that the condition of S28 is satisfied (when S28 is YES), the main CPU 101 clears the spinning control data (reel control management information) (S29). With this process, after the game returns, the reel rotation control is started from the acceleration process. Next, the main CPU 101 sets a reel operation timing value (rotation control data execution start timing “1”) (S30). When “1” is set as the reel operation timing, the main CPU 101 accelerates the rotation control of the reel because the excitation change timing is reached in the reel control processing (see S903 in FIG. 113 described later). Start with

  After the process of S30 or when S28 is NO, the main CPU 101 subtracts 1 from the value of the number of reels (S31). Next, the main CPU 101 determines whether or not the value of the number of reels after subtraction is “0” (S32).

  In S32, when the main CPU 101 determines that the value of the number of reels after subtraction is not “0” (when S32 is NO), the main CPU 101 changes the reel to be checked and changes the process to the process of S27. Return and repeat the processing from S27.

  On the other hand, when the main CPU 101 determines in S32 that the value of the number of reels after subtraction is “0” (when S32 is YES), the main CPU 101 performs a RAM initialization process (S33). In this process, the main CPU 101 sets the address at the time of “power recovery” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the start of initialization, and starts from the start address to the end of the game RAM area. Erase (clear) information up to the address.

  Next, the main CPU 101 restores all the register data saved at the time of detecting power interruption to all the registers (S34). After the process of S34, the main CPU 101 ends the game return process and returns the process to the process at the time of detecting the power interruption.

  In this game return process, the main CPU 101 generates game return command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 67B described later) provided in the main RAM 103. The game return command that is saved and saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Also good. In this case, the game return command may be configured to include each parameter for specifying the return to the state before the power interruption return.

  In the present embodiment, the game return process is performed as described above. In the game return process of the present embodiment, as described above, the input / output state of each port at the time of power failure is ensured at the time of power recovery, and when the reel is rotating at the time of power failure, the reel control management is performed at the time of power recovery. The processing necessary for acquiring the information and starting the reel re-rotation is also performed (refer to the processing of S25 to S32). Therefore, in the present embodiment, even when the power is restored from the power interruption during the rotation of the spinning cylinder, the reel re-rotation control can be stably performed, and the player does not feel uncomfortable.

  Further, the processing of S25 to S32 during the game return processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As described above, in the microprocessor 91 with a security function for gaming machines used in the pachislot machine 1 of this embodiment, various instruction codes dedicated to the main CPU 101 are provided. For example, the “LDQ” instruction (predetermined read instruction) in FIG. 59 is one of instruction codes dedicated to the main CPU 101.

  For example, when the source code “LDQ HL, k” is executed on the source program, the address specified by the contents (stored data) of the Q register and the 1-byte integer k (direct value) is stored in the HL register. To be loaded. At this time, the contents of the Q register become the address value on the higher side of the designated address, and the integer k (direct value) becomes the address value on the lower side of the designated address. Therefore, when the source code “LDQ HL, .LOW.wR1_CTRL” in FIG. 59 is executed, the contents of the Q register (the address value on the upper side of the address of the spinning cylinder control data storage area) and the integer value “. The address (address of the spinning cylinder control data storage area) specified by “LOW.wR1_CTRL” (address value on the lower side of the address of the spinning cylinder control data storage area) is loaded into the HL register. “.LOW.” Is not an actual instruction but a pseudo instruction. In this pseudo-instruction function, only the lower address of the storage area address defined following “.LOW.” Is validated. The pseudo instruction is not an instruction stored in the actual ROM, but an instruction for a conversion program (assembler) to refer to when converting the source file into a format for storing in the ROM.

  As described above, in the present embodiment, by using the instruction code dedicated to the main CPU 101 that performs addressing using the Q register (extension register), the main ROM 102, the main RAM 103, and the memory map I / O can be directly converted. Can be accessed. In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Setting change confirmation process]
Next, the setting change confirmation process performed in S15 during the power-on (reset interrupt) process (see FIG. 56) will be described with reference to FIGS. 60 is a flowchart showing the procedure of the setting change confirmation process, FIG. 61A is a diagram showing an example of a source program for executing the processes of S44 to S47 in the flowchart, and FIG. It is a figure which shows an example of the source program for performing the process of S57 in this flowchart.

  First, the main CPU 101 performs an initialization process for an unspecified RAM area in the main RAM 103 (S41). Next, the main CPU 101 performs one interrupt waiting process (S42). In this process, the main CPU 101 stands by until the transmission process of the no-operation command to the sub control circuit 200 by the interrupt process is completed.

  Next, the main CPU 101 performs a RAM initialization process (S43). In this process, the main CPU 101 sets the address “at the time of RAM abnormality or setting change start” in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the initialization start, and the game starts from the start address. The information up to the last address in the RAM area is erased (cleared).

  Next, the main CPU 101 determines whether or not the setting key type switch 54 is on (S44). A setting key (not shown) inserted into the setting key type switch 54 is an operation key for operating the setting (setting values 1 to 6) of the pachislot 1. When the setting key is turned on, the setting key is set. The key switch 54 is turned on.

  In S44, when the main CPU 101 determines that the setting key type switch 54 is not in the ON state (in the case where S44 is NO), the main CPU 101 ends the setting change confirmation processing and turns on the power (reset interrupt). ) The process proceeds to S16 in the time process (see FIG. 56). On the other hand, when the main CPU 101 determines in S44 that the setting key type switch 54 is in the ON state (when S44 is YES), the main CPU 101 performs a medal acceptance prohibition process (S45). By this process, the solenoid of the selector 66 (see FIG. 7) is not driven, and the inserted medal is discharged from the medal payout opening 24 (see FIG. 2).

  Next, the main CPU 101 sets setting change start or setting check start information (005H: first value) in the L register, and generates and stores a setting change command (setting change / setting check start) (S46). . In this process, the main CPU 101 generates setting change command data (first command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the start of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. A setting change command (setting change / setting confirmation start) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in an interrupt processing described later with reference to FIG. Sent to.

  Next, the main CPU 101 sets the error count relay to an on state (S47). Next, the main CPU 101 determines which setting change or setting confirmation has been performed (S48).

  In S48, when the main CPU 101 determines that the setting has not been changed (setting has been confirmed) (when S48 is NO), the main CPU 101 performs the process of S55 described later.

  On the other hand, when the main CPU 101 determines in S48 that the setting has been changed (the setting has not been confirmed) (when S48 is YES), the main CPU 101 performs a setting value update process (S49). ). Next, the main CPU 101 performs setting value 7-segment display setting processing (S50). By this processing, the updated set value can be displayed by the 7-segment LED in the information display 6.

  Next, the main CPU 101 determines whether or not the reset switch 76 is on (S51).

  When the main CPU 101 determines in S51 that the reset switch 76 is in the on state (when S51 is YES), the main CPU 101 returns the process to the process of S49 and repeats the processes after S49. On the other hand, when the main CPU 101 determines in S51 that the reset switch 76 is not in the on state (when S51 is NO), the main CPU 101 determines whether or not the start switch 79 is in the on state (S52). .

  In S52, when the main CPU 101 determines that the start switch 79 is not on (when S52 is NO), the main CPU 101 returns the process to the process of S51 and repeats the processes after S51. On the other hand, when the main CPU 101 determines in S52 that the start switch 79 is on (when S52 is YES), the main CPU 101 sets a setting value storage area (not shown) provided in the main RAM 103. The value is stored (S53).

  Next, the main CPU 101 determines whether or not the setting key switch 54 is in an OFF state (S54).

  In S54, when the main CPU 101 determines that the setting key switch 54 is not in the OFF state (when S54 is NO), the main CPU 101 repeats the process of S54. On the other hand, when the main CPU 101 determines in S54 that the setting key type switch 54 is in the off state (when S54 is YES), the main CPU 101 performs the process of S55 described later.

  When S48 is NO or S54 is YES, the main CPU 101 determines whether setting change or setting confirmation has been performed (S55).

  When the main CPU 101 determines in S55 that the setting has not been changed (setting confirmation has been performed) (when S55 is NO), the main CPU 101 performs the process of S57 described later. On the other hand, when the main CPU 101 determines in S55 that the setting has been changed (the setting has not been confirmed) (when S55 is YES), the main CPU 101 performs a RAM initialization process (S56). . In this process, the main CPU 101 uses, as a start address for starting initialization, an address at the “setting change end” (not shown) in the game RAM area of the main RAM 103 shown in FIG. The information from the head address to the last address of the game RAM area is erased (cleared).

  After the process of S56 or when S55 is NO, the main CPU 101 sets setting change end information or setting check end information (004H: second value) in the L register, and a setting change command (setting change / setting check end). ) Is generated and stored (S57). In this process, the main CPU 101 generates setting change command data (second command data) transmitted from the main control circuit 90 to the sub control circuit 200 at the end of the setting change process or the setting confirmation process. The data is stored in a communication data storage area provided in the main RAM 103. Details of the setting change command generation / storage process will be described later with reference to FIG. Also, the setting change command (setting change / setting confirmation end) saved in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. Sent to. After the process of S57, the main CPU 101 ends the setting change confirmation process, and moves the process to the process of S16 of the power-on (reset interrupt) process (see FIG. 56).

  In the present embodiment, the setting change confirmation process is performed as described above. The processing of S44 to S47 during the setting change confirmation processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 61A. Among them, for example, the setting key state determination process in S44 is executed by the source code “BITQ 7, (.LOW. (WIBUF + 4))” in FIG. 61A, and the error count relay in S47 is set to the ON state. The processing is executed by the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 61A.

  Both the “BITQ” instruction and the “SETQ” instruction are instruction codes dedicated to the main CPU 101 for performing addressing using the Q register (extension register).

  For example, when the source code “BITQ b, (k)” is executed on the source program, data stored in the Q register (upper address value) and 1-byte integer value k (direct value: lower address value) ) Is checked, and if the bit b stores “1”, the zero flag (bit 6: see FIG. 11) of the flag register F is set to “0”. If “0” is stored in the bit b, “1” is set in the zero flag (predetermined bit area) of the flag register F. Therefore, when the source code “BITQ 7, (.LOW. (WIBUF + 4)” in FIG. 61A is executed, the address specified by the data stored in the Q register and the integer value “.LOW. (WIBUF + 4)” If bit 7 of this memory is checked and "1" is stored in bit 7, "0" is set in the zero flag of flag register F, and if "0" is stored in bit 7 , “1” is set in the zero flag of the flag register F.

  For example, when the source code “SETQ b, (k)” is executed on the source program, data stored in the Q register (upper address value) and 1-byte integer value k (direct value: lower side) "1" is set in the bit b of the memory at the address specified by (address value). Therefore, when the source code “SETQ 1, (.LOW.wECRREQ)” in FIG. 61A is executed, the data stored in the Q register and the memory at the address specified by the integer value “.LOW.wECRREQ” are stored. Bit 1 is set to “1”.

  That is, in the setting change confirmation process of the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extended register) as described above are used, and by using these main CPU 101 dedicated instruction codes, a direct value is obtained. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to increase the free space of the main ROM 102 and to increase the processing speed.

  In addition, the setting change command (initialization command) generation / storage process performed at the start of the setting change / setting check in S46 during the setting change checking process described above is performed by the main CPU 101 executing the “CALLF” instruction in FIG. 61A. The process for generating and storing the setting change command (initialization command) performed at the end of the setting change / setting confirmation in S57 described above is performed by the main CPU 101 executing the “CALLF” instruction in FIG. 61B. The “CALLF” instruction is also a dedicated instruction code for the main CPU 101.

  For example, when the source code “CALLF mn” is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is designated by the stack pointer (SP). The data is saved in the memory, the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address specified by "mn". However, the “CALLF” instruction is a 2-byte instruction, and an address range that can be jumped is a range of 0000H to 11FFH. Therefore, for example, when the source code “CALLF SB_PCINIT_00” in FIG. 61A is executed, the current PC register value is stored in the memory specified by the stack pointer (SP), and the stack pointer is updated by −2. The address of “SB_PCINIT_00” is stored in the PC register, and the process jumps to the address specified by “SB_PCINIT_00”.

  In the present embodiment, an instruction code called a “CALL” instruction is also prepared as an instruction code of the same type as the “CALLF” instruction. For example, when the source code “CALL mn” is executed on the source program, the value (stored data) of the current PC register (program counter PC: see FIG. 11) is stored as in the “CALLF” instruction. The data is stored in the memory designated by the stack pointer (SP), the stack pointer is updated by -2, "mn" is stored in the PC register, and the process jumps to the address designated by "mn". However, the “CALL” instruction is a 3-byte instruction, and the address range that can be jumped is different from that of the “CALLF” instruction, and the address range that can be jumped is the range of 0000H to FFFFH. Since the “CALLF” instruction is an instruction code having a smaller number of bytes than the “CALL” instruction, the capacity of the source program (usable capacity of the main ROM 102) can be reduced and the processing efficiency can be improved. be able to.

  Further, in the setting change confirmation processing of this embodiment, as shown in FIGS. 61A and 61B, the jump destination address “SB_PCINIT_00” designated by the “CALLF” instruction in S46 is the jump destination designated by the “CALLF” instruction in S57. Is the same address as That is, in the present embodiment, a setting change command (initialization command) generation and storage process to be transmitted to the sub-control circuit 200 at the time of setting change (when a gaming machine is started), at the time of setting check start (during normal operation), and at the end of setting check Are the same as each other, and the source program of the setting change command generation / storage process used in both the processes of S46 and S57 is shared (modularized).

  In this case, since it is not necessary to provide a source program for the setting change command generation / storage process separately in both the processes of S46 and S57, the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. . As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Setting change command generation and storage processing]
Next, the setting change command generation / storage process performed in S46 and S57 in the setting change confirmation process (see FIG. 60) will be described with reference to FIGS. FIG. 62 is a flowchart showing a procedure of setting change command generation / storage processing, and FIG. 63 is a diagram showing an example of a source program for executing setting change command generation / storage processing.

  First, the main CPU 101 sets information of setting values (1 to 6) in the E register (S61). Next, the main CPU 101 sets RT state information in the C register (S62). Next, the main CPU 101 sets the command type information (02H) of the setting change command in the A register (S63).

  Next, the main CPU 101 performs communication data storage processing (S64). In this process, the main CPU 101 determines the information set in each register in S61 to S63 and the information set in the D register in S46 or S57 (see FIG. 60) (setting change start / setting change end / setting status). The setting change command data is generated using the setting confirmation start / setting confirmation end), and the generated command data is stored in the communication data storage area. Details of the communication data storage process will be described later with reference to FIG. 64 described later.

  After the process of S64, the main CPU 101 ends the setting change command generation / storage process. When ending the setting change command generation / storage process performed in S46 during the setting change confirmation process (see FIG. 60), the main CPU 101 executes the process of the setting change confirmation process (see FIG. 60) after the process in S64. The process proceeds to S47. Further, when ending the setting change command generation / storage process performed in S57 during the setting change confirmation process (see FIG. 60), the main CPU 101 ends the setting change command generation / storage process after the process of S64 and sets the setting. The change confirmation process (see FIG. 60) is also terminated.

  In the present embodiment, the setting change command generation / storage process is performed as described above. The above-described setting change command generation / storage process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  As described above, in the setting change command generation / storage process, the setting status is stored in the D register as the communication parameter 4 immediately before the setting change command generation / storage process is executed, and the setting value is set during the execution of the setting change command generation / storage process. Is stored in the E register as communication parameter 3, and RT information is stored in the C register as communication parameter 5. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), the communication parameters 3 to 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1 and 2 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. Therefore, the values stored in the L register and the H register at the present time are set, respectively. Therefore, the values of the communication parameters 1 and 2 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Communication data storage processing]
Next, with reference to FIGS. 64 and 65, for example, the communication data storage process performed in S64 during the setting change command generation / storage process (see FIG. 62) will be described. Note that the communication data storage process is executed not only when the setting change command is generated but also when other commands are generated. FIG. 64 is a flowchart showing a procedure of the communication data storage process, and FIG. 65 is a diagram showing an example of a source program for executing the processes of S71 to S76 during the communication data storage process.

  First, the main CPU 101 stores the data set in the A register as communication command type data in a communication data temporary storage area (not shown) in the main RAM 103 (S71). Next, the main CPU 101 stores the data set in the H register and the L register in the communication data temporary storage area (predetermined storage area) in the main RAM 103 as communication command parameters 1 and 2, respectively (S72). .

  Next, the main CPU 101 stores the data set in the D register and E register as communication command parameters 3 and 4 in the communication data temporary storage area in the main RAM 103 (S73). Next, the main CPU 101 stores the data set in the B register and the C register in the communication data temporary storage area in the main RAM 103 as the communication command parameter 5 and the RT state data, respectively (S74).

  Next, the main CPU 101 generates BCC data (sum value) of the communication command from the data values set in the A register to the L register (S75). Next, the main CPU 101 stores the generated BCC data in a communication data temporary storage area in the main RAM 103 (S76).

  After the process of S76, the main CPU 101 determines whether or not there is an empty communication data storage area in the main RAM 103 (S77). In the present embodiment, a maximum of nine command data can be stored in the communication data storage area (see FIG. 67B described later).

  In S77, when the main CPU 101 determines that there is no free space in the communication data storage area (when S77 is NO), the main CPU 101 ends the communication data storage process and, for example, a setting change command generation storage process ( 62) also ends.

  On the other hand, when the main CPU 101 determines in S77 that the communication data storage area is free (when S77 is YES), the main CPU 101 is stored in the communication data temporary storage area by the processes of S71 to S76 described above. The communication data is stored in the communication data storage area as communication command data (S78).

  Next, the main CPU 101 performs communication data pointer update processing (S79). In this process, the main CPU 101 mainly performs a process of updating a communication data pointer indicating a storage address of communication data in the communication data storage area. Details of the communication data pointer update process will be described later with reference to FIG. 66 described later.

  Then, after the process of S79, the main CPU 101 ends the communication data storage process and, for example, also ends the setting change command generation / storage process (see FIG. 62).

  In the present embodiment, the communication data storage process is performed as described above. Note that the processing of S71 to S76 in the communication data storage processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In this series of processes, the storage process of the communication command type data, various communication parameters, gaming state flag data, and BCC data included in the command data is performed in the Q register on the source program as shown in FIG. It is executed using an “LDQ” instruction, which is a dedicated instruction code for the main CPU 101 that performs addressing using (extension register).

  Specifically, when the source code “LDQ (.LOW. (WPDT_TMP + 0)), A” is executed, the type data of the communication command stored in the A register becomes the stored data (upper address value) of the Q register and 1 It is stored in the communication data temporary storage area at the address specified by the integer value “.LOW. (WPDT_TMP + 0)” (lower address value). Further, when the source code “LDQ (.LOW. (WPDT_TMP + 1)), HL” is executed, the communication parameter 1 stored in the L register is changed to the data stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 1)”. The communication parameter 2 stored in the communication data temporary storage area at the address designated by "" and stored in the H register is stored in the communication data temporary storage area at the next address. In addition, when the source code “LDQ (.LOW. (WPDT_TMP + 3)), DE” is executed, the communication parameter 3 stored in the E register is stored in the Q register and the integer value “.LOW. (WPDT_TMP + 3) in 1 byte. The communication parameter 4 stored in the communication data temporary storage area of the address designated by “” and stored in the D register is stored in the communication data temporary storage area of the next address. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 5)), BC”, the communication parameter 5 stored in the C register is stored in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 5)”. The gaming state flag data stored in the communication data temporary storage area of the address designated by “B” and stored in the B register is stored in the communication data temporary storage area of the next address.

  Further, the BCC data serving as the sum value of the command data set in the communication data storing process is calculated by executing a series of source codes “ADD (addition instruction code) A, H” to “ADD A, B”. Stored in a register. Then, by executing the source code “LDQ (.LOW. (WPDT_TMP + 7)), A”, the BCC data stored in the A register becomes the stored data in the Q register and the 1-byte integer value “.LOW. (WPDT_TMP + 7)”. And stored in the communication data temporary storage area at the address specified by.

  As described above, in this embodiment, when one packet (8 bytes) of communication data (command data) is created, various parameters are transferred from the register and stored in a communication data temporary storage area (communication buffer). In such a command data creation method, data stored in each register at the time of command generation is directly stored in the communication data temporary storage area as various parameters of the command data. Therefore, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. In this case, even if there is command data of the same type and the value of the use parameter is the same, the command data sum value (BCC data) can be changed every time the command is created. In this embodiment, the sum value, which is one of the error codes, is calculated by ADD (addition instruction code). However, instead of the addition instruction code, SUB (subtraction instruction code), XOR (exclusive OR) The same effect can be obtained by calculating the error code using the instruction code. Further, the same effect can be obtained by calculating an error code using MUL (multiplication instruction code) or DIV (division instruction code), which is a dedicated instruction for the main CPU 101.

  Therefore, in this embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress illegal acts such as goto, and it is necessary to add unnecessary goth countermeasure processing. Therefore, it is possible to suppress the compression of the program capacity of the main control circuit 90 due to the addition of the anti-going process.

[Communication data pointer update processing]
Next, with reference to FIGS. 66 and 67, the communication data pointer update process performed in S79 in the communication data storage process (see FIG. 64) will be described. 66 is a flowchart showing the procedure of the communication data pointer update process, FIG. 67A is a diagram showing an example of a source program for executing the communication data pointer update process, and FIG. 67B is a communication data pointer. It is a figure which shows the structure of the communication data storage area | region actually set on the source program of an update process.

  First, the main CPU 101 acquires the value of the currently set communication data pointer (S81).

  Next, the main CPU 101 adds and updates the value of the communication data pointer for one packet (8 bytes) (S82). In this process, when the updated communication data pointer value is equal to or larger than the upper limit size of the communication data storage area (see FIG. 67B), the main CPU 101 sets the updated communication data pointer value to “0”. Thus, all the command data stored in the communication data storage area are invalidated (the state is the same as the discarded state).

  In the present embodiment, the amount of data (one packet) transmitted in one transmission operation is 8 bytes. That is, in this embodiment, one command data can be transmitted by one transmission operation. In the present embodiment, since a maximum of nine command data can be stored in the communication data storage area (see FIG. 67B), the upper limit size of the communication data storage area is 72 bytes (= 8 bytes × 9). . Therefore, in this embodiment, the range of the communication data pointer is set to “0” to “71”, and the value of the communication data pointer after the update (when the communication data pointer is updated by +8) is “71 ( If the value exceeds the upper limit value), set the updated communication data pointer value to “0” (return the communication data storage destination address to the top address) and store the communication data. Invalidate all command data stored in the area (similar to the discarded state). If the value of the communication data pointer is set to “0”, the next time command data is stored in the communication data storage area, it is stored from the start address of the communication data storage area. The command data is overwritten with new command data. Therefore, in this embodiment, it is not necessary to initialize (clear) the communication data storage area when the value of the communication data pointer exceeds “71 (upper limit value)”.

  After the process of S82, the main CPU 101 ends the communication data pointer update process and also ends the communication data storage process (see FIG. 64).

  In the present embodiment, the communication data pointer update process is performed as described above. The communication data pointer update process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 67A. Among them, the communication data pointer update processing in S82 is executed by the “ADD” instruction and the “ICPLD” instruction (predetermined update instruction) in FIG. 67A. This “ICPLD” instruction is also dedicated to the main CPU 101. Instruction code.

  In the source program, for example, when the source code “ICPLD A, n” is executed, the content (stored data) of the A register is compared with the integer n, and the content of the A register is less than the integer n. When “1” is added to the contents of the A register and the contents of the A register are equal to or greater than the integer n, “0” is set in the A register.

  Therefore, when the communication data pointer update process of S82 is executed, the source code “ADD A, 7” is first executed on the source program of FIG. 67A, and the contents of the A register (the communication data pointer before the update are updated). “7” is added to the value), and the addition result is stored in the A register. Next, the source code “ICPLD A, 71” is executed, and the content of the A register (the value of the communication data pointer after addition of 7) is compared with the integer “71”, and the content of the A register is less than the integer “71”. In some cases, “1” is added to the content of the A register, and when the content of the A register is equal to or greater than the integer “71”, “0” is set in the A register. That is, in the process of S82, when the value of the communication data pointer is updated by +7 and the updated communication data pointer value exceeds the upper limit “71”, the process of clearing the communication data pointer to zero (communication Processing for returning the data storage address to the start address of the communication data storage area is performed. On the other hand, if the updated communication data pointer value does not exceed the upper limit value “71”, “1” is further added to the communication data pointer by the “ICPLD” instruction, so that the communication data pointer value is totaled. +8 update.

  As described above, in this embodiment, in the communication data pointer update process, communication data is updated by one “ICPLD” instruction code (an instruction code in which a transmission buffer upper limit determination instruction and a determination branch instruction are integrated). The pointer update (addition of 1) process, the updated communication data pointer determination check process, and the communication data pointer clear process can be executed together. In this case, there is no need to provide an instruction code for executing each process separately. For example, it is possible to omit the branch instruction code for determining whether or not the value of the updated communication data pointer exceeds the upper limit “71”.

  Therefore, by using the “ICPLD” instruction code dedicated to the main CPU 101 in the communication data pointer update processing or the like, the capacity of the source program (the capacity used by the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Power failure (external) processing]
Next, the process at the time of power failure of pachislot 1 performed by the control of the main CPU 101 (external) will be described with reference to FIG. FIG. 68 is a flowchart showing a procedure of processing at the time of power interruption (external). 68, the power interruption (external) process is performed when the power management circuit 93 detects a drop (power interruption) in the power supply voltage supplied to the microprocessor 91. And is executed based on the interrupt request signal output from the interrupt controller 112 of the microprocessor 91 to the main CPU 101.

  First, the main CPU 101 saves data set in all registers (S91). Next, the main CPU 101 reads data set in the power interruption detection port (S92).

  Next, the main CPU 101 determines whether or not the power failure detection port is on (S93).

  In S93, when the main CPU 101 determines that the power interruption detection port is not in the on state (when S93 is NO), the main CPU 101 sets the interrupt processing permission (S94). Then, after the processing of S94, the main CPU 101 terminates the power interruption (external) processing. It should be noted that these processes performed when S93 is NO corresponds to the instantaneous power failure countermeasure process that occurs when the power management circuit 93 instantaneously detects a power interruption.

  On the other hand, when the main CPU 101 determines in S93 that the power failure detection port is in the ON state (when S93 is YES), the main CPU 101 sets the medal insertion impossible and sets the stop of the hopper device 51. (S95).

  Next, the main CPU 101 stores the value of the currently set stack pointer (SP) in the stack area of the game RAM area in the main RAM 103 (S96).

  Next, the main CPU 101 performs checksum generation processing of the main RAM 103 (S97). This process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. Further, the program used in the checksum generation process is stored in an unspecified area in the main ROM 102 (see FIG. 12B). Details of the checksum generation process will be described later with reference to FIG. 69 described later.

  Next, the main CPU 101 sets prohibition of access to the main RAM 103 (S98). Then, after the process of S98, an infinite loop process is performed until the power supply stops (until the power supply voltage reaches a voltage at which the main CPU 101 cannot operate).

[Checksum generation processing (not specified)]
Next, with reference to FIGS. 69 and 70, the checksum generation process performed in S97 during the power interruption (external) process (see FIG. 68) will be described. 69 is a flowchart showing the procedure of the checksum generation process, FIG. 70A is a diagram showing an example of a source program for executing the checksum generation process, and FIG. 70B is the checksum generation process. It is a figure which shows the mode of the update operation of the stack pointer performed, and the operation | movement of reading the data from the main RAM103 to a register | resistor.

  First, the main CPU 101 stores the current stack pointer (SP) value (the in-use address of the stack area of the game RAM area) in the non-standard stack area of the non-standard RAM area of the main RAM 103 (S101). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (S102). Next, the main CPU 101 sets an upper address value (F0H) of the RAM address (non-standard stack area address) in the Q register (S103). Next, the main CPU 101 sets a power interruption occurrence flag (S104).

  Next, the main CPU 101 sets the calculation start address of the sum value in the game RAM area to the stack pointer, and sets the sum calculation counter to the value obtained by dividing the number of bytes in the storage area for the sum value calculation by “2”. Set (S105). The sum calculation counter is a counter for determining the end timing of the sum value calculation, and is provided in the main RAM 103. When the sum calculation counter set in S105 becomes “0”, the game RAM area sum value calculation process of the main RAM 103 ends.

  Next, the main CPU 101 clears the HL register to 0 (sets the value “0”) (S106). By this process, the initial value “0” of the sum value is set.

  Next, the main CPU 101 executes an instruction code called “POP instruction” (specific instruction) (source code “POP DE” described in FIG. 70A) and stores it in the main RAM 103 set in the stack pointer (SP). Data (stored value) of the area of 2 bytes is read from the area address to the DE register (S107).

  When the “POP” instruction is executed, the data (memory contents) stored in the 1-byte area at the address specified by the stack pointer is loaded into the lower register of the pair register and specified by the stack pointer. The data (memory contents) stored in the 1-byte area of the address obtained by updating the updated address by 1 is loaded into the upper register of the pair register. When the “POP” instruction is executed, an address update process for 2 bytes (a process of adding “2” to the address) is performed on the address set in the stack pointer (SP).

  Therefore, in the processing of S107, the data (memory contents) stored at the address specified by the stack pointer is loaded into the E register and stored at the address obtained by adding “1” to the address specified by the stack pointer. Data (memory contents) is loaded into the D register.

  FIG. 70B shows how data is read into the DE register and the address set in the stack pointer is updated when the “POP” instruction is executed. If the address set in the stack pointer (SP) is “F010h” at the start of the calculation of the sum value, the data (memory contents) stored in the address “F010h” is loaded into the E register, and the address Data (memory contents) stored in “F011h” is loaded into the D register. At this time, an update process of adding 2 to the address set in the stack pointer (SP) is performed, and the address set in the stack pointer (SP) is changed from “F010h” to “F012h”. Next, when the “POP” instruction is executed again, the data (memory content) stored at the address “F012h” is loaded into the E register, and the data (memory content) stored at the address “F013h” is loaded. Loaded into the D register. At this time, the address set in the stack pointer (SP) is updated, and the address set in the stack pointer (SP) is changed from “F012h” to “F014h”. Thereafter, every time the “POP” instruction is executed, the above-described operation for reading data into the DE register and the operation for updating the address set in the stack pointer are repeated.

  After the process of S107, the main CPU 101 performs a sum value calculation process (S108). Specifically, the main CPU 101 adds the value stored in the DE register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S109). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S110).

  In S110, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S110 is NO), the main CPU 101 returns the process to the process of S107 and repeats the processes after S107. That is, the processes of S107 to S110 are repeated until the sum value calculation process of the game RAM area of the main RAM 103 is completed.

  On the other hand, when the main CPU 101 determines in S110 that the value of the sum calculation counter is “0” (in the case where S110 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S111). The non-standardized thumb count value is the number of bytes in the non-standardized storage area. Therefore, when the sum calculation counter set in S111 becomes “0”, the sum value calculation process for the non-standard RAM area of the main RAM 103, that is, the sum value calculation process for the entire main RAM 103 is completed.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S112).

  Next, the main CPU 101 performs a sum value calculation process (S113). Specifically, the main CPU 101 adds the value stored in the A register to the value stored in the HL register, and stores the added value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register, and subtracts 1 from the value of the sum calculation counter (S114). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S115).

  In S115, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S115 is NO), the main CPU 101 returns the process to the process of S112 and repeats the processes after S112. That is, the processes of S112 to S115 are repeated until the process of adding the sum value of the unspecified RAM area of the main RAM 103 to the sum value of the game RAM area is completed.

  On the other hand, when the main CPU 101 determines in S115 that the value of the sum calculation counter is “0” (in the case where S115 is YES), the main CPU 101 uses the value stored in the HL register when the power interruption occurs. Is stored in a sum value storage area (not shown) in the main RAM 103 (S116). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S101 to the stack pointer (S117). After the process of S117, the main CPU 101 ends the checksum generation process, and moves the process to the process of S98 of the power interruption (external) process (see FIG. 68).

  In the present embodiment, the checksum generation process is performed as described above. The checksum generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program in FIG. 70A. As described above, in the present embodiment, the checksum of the main RAM 103 when a power interruption occurs is calculated by an addition formula. At this time, in the calculation of the sum value of the game RAM area, an addition process is performed in units of 2 bytes (refer to the source code “ADD HL, DE” in FIG. 70A). (See source code “ADDWB HL, A” in FIG. 70A).

[Sum check processing (not specified)]
Next, the sum check process performed in S9 during the power-on process (see FIG. 56) will be described with reference to FIGS. 71 and 72 are flowcharts showing the procedure of the sum check process, and FIG. 73 is a diagram showing an example of a source program for executing the processes of S122 to S132 during the sum check process.

  First, the main CPU 101 stores the current stack pointer (SP) value in the non-standard stack area (S121). Next, the main CPU 101 sets the address of the sum value storage area in the stack pointer, and sets a value obtained by dividing the number of bytes in the sum value calculation target storage area by “2” in the sum calculation counter (S122). The sum calculation counter set here is a counter for determining the end timing of the sum value calculation (sum value subtraction process), and is provided in the main RAM 103. Next, the main CPU 101 obtains a sum value (check sum) from the sum value storage area (S123). By this process, the checksum (initial value before subtraction) generated when the power interruption occurs is stored in the HL register.

  Next, the main CPU 101 executes a “POP” instruction, and reads data (stored value) of 2 bytes from the storage area address of the main RAM 103 set in the stack pointer (SP) to the DE register (S124). . At this time, by executing the “POP” instruction, the data (memory contents) stored in the 1-byte area of the address specified by the stack pointer is loaded into the E register, and the address specified by the stack pointer is set. Data (memory contents) stored in the 1-byte area of the updated address is loaded into the D register (see FIG. 70B). When the “POP” instruction is executed, an address update process for two bytes (a process for adding two addresses) is performed on the address set in the stack pointer (SP).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S125). Specifically, the main CPU 101 subtracts the value stored in the DE register from the value stored in the HL register (the initial value of the sum value or the sum value after the previous subtraction process). The value is stored in the HL register as a sum value.

  Next, the main CPU 101 subtracts 1 from the value of the sum calculation counter (S126). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S127).

  In S127, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S127 is NO), the main CPU 101 returns the process to the process of S124 and repeats the processes after S124. That is, the processes of S124 to S127 are repeated until the sum value subtraction process is completed over the entire game RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S127 that the value of the sum calculation counter is “0” (in the case where S127 is YES), the main CPU 101 stores the non-standard RAM area in the main RAM 103 in the DE register. The sum calculation start address is set, and the non-standard sum count value is set in the sum calculation counter (S128). The non-standard thumb count value is the number of bytes in the non-standard RAM area.

  Next, the main CPU 101 reads data (stored value) of an area of 1 byte from the address of the non-regulated RAM area set in the DE register to the A register (S129).

  Next, the main CPU 101 performs a sum value calculation (subtraction) process (S130). Specifically, the main CPU 101 subtracts the value stored in the A register from the value stored in the HL register, and stores the subtracted value in the HL register as a sum value.

  Next, the main CPU 101 adds 1 to the address stored in the DE register and subtracts 1 from the value of the sum calculation counter (S131). Next, the main CPU 101 determines whether or not the updated sum calculation counter value is “0” (S132).

  In S132, when the main CPU 101 determines that the value of the sum calculation counter is not “0” (when S132 is NO), the main CPU 101 returns the process to the process of S129 and repeats the processes after S129. That is, the processes of S129 to S132 are repeated until the subtraction process of the sum value is completed over the entire non-standard RAM area of the main RAM 103.

  On the other hand, when the main CPU 101 determines in S132 that the value of the sum calculation counter is “0” (when S132 is YES), the main CPU 101 sets “sum abnormality” in the determination result of the sum check process. (S133). Next, the main CPU 101 determines whether or not the calculated sum value is “0” (S134).

  In this process, the main CPU 101 refers to the state (1/0) of the zero flag (bit 6) of the flag register F to determine whether or not the sum value is “0”. In the present embodiment, the sum value is “0” when the value of the sum calculation counter set in S128 becomes “0”, that is, when the sum value subtraction process is completed over the entire area of the main RAM 103. Is set to “1” in the zero flag of the flag register F, and “0” is set in the zero flag of the flag register F when the sum value is not “0”. Therefore, if “1 (ON state)” is set in the zero flag of the flag register F at the time of the processing of S134, the main CPU 101 determines that the sum value is “0”.

  In S134, when the main CPU 101 determines that the calculated sum value is not “0” (when S134 is NO), the main CPU 101 performs the process of S139 described later. On the other hand, when the main CPU 101 determines in S134 that the calculated sum value is “0” (when S134 is YES), the main CPU 101 sets “power failure abnormality” as the determination result (S135). ).

  Next, the main CPU 101 acquires a power interruption occurrence flag (S136). Next, the main CPU 101 determines whether or not the power interruption occurrence flag is in a state without power interruption (off state) (S137).

  In S137, when the main CPU 101 determines that the power interruption occurrence flag is in a state where there is no power interruption (when S137 is YES), the main CPU 101 performs a process of S139 described later. On the other hand, when the main CPU 101 determines in S137 that the power interruption occurrence flag is not in the state without power interruption (when S137 is NO), the main CPU 101 sets “normal” as the determination result (S138).

  After S138, if S134 is NO or S137 is YES, the main CPU 101 stores the determination result in the sum check determination result and clears (turns off) the power interruption occurrence flag (S139). Next, the main CPU 101 sets the value of the stack pointer (SP) stored in the non-standard stack area in S121 to the stack pointer (S140). After the process of S140, the main CPU 101 ends the sum check process, and moves the process to the process of S10 of the power-on process (see FIG. 56).

  In the present embodiment, the sum check process is performed as described above. Then, the processing of S122 to S132 during the above-described sum check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  As described above, in the thumbchock determination process of the main RAM 103 in the present embodiment, first, the checksum value generated when the power interruption occurs is sequentially subtracted by the data stored in the main RAM 103 when the power is restored. At this time, a subtraction process (see source code “SUB HL, DE” in FIG. 73) is performed in the game RAM area in units of 2 bytes, and a subtraction process (in FIG. 73, in the non-specified RAM area). Source code “SUBWB HL, A”). Next, whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is “0” (whether or not the zero flag is on). When the subtraction result is “0” (when the zero flag is in the on state), it is determined as normal, and when the subtraction result is not “0” (when the zero flag is in the off state), it is determined as abnormal. Determined.

  In other words, in the present embodiment, the checksum generation process when power interruption occurs is performed by the addition method, and the checksum determination process when power is restored is performed by the subtraction method. Then, normal / abnormal determination is performed based on the final checksum subtraction result. When such checksum generation processing and determination processing are performed, it is not necessary to generate the checksum again when the power is restored and to check the checksum against the checksum when the power interruption occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, a free space corresponding to the omission of the collation instruction code can be secured, and the increased free space can be used to improve the game performance. Note that the “POP” instruction executed in the checksum generation process when the power interruption occurs and the checksum determination process when the power is restored is a stack pointer (SP) operation-dedicated instruction, and the source code “ In addition to “POP DE”, source codes “POP HL”, “POP AF”, and the like exist.

[Main processing of pachislot by control of main CPU]
Next, with reference to FIG. 74, the main process (main operation process) of the pachi-slot 1 executed under the control of the main CPU 101 will be described. FIG. 74 is a flowchart (hereinafter referred to as main flow) showing the procedure of the main processing.

  First, the main CPU 101 performs a RAM initialization process (S201). In this process, the main CPU 101 sets the address at the end of one game in the game RAM area of the main RAM 103 shown in FIG. 12C as the start address of the start of initialization, and starts from the start address in the game RAM area. Erase (clear) information up to the last address. The storage area in this range is a storage area that needs to be erased for each unit game (game) such as an internal winning combination storage area or a display combination storage area.

  Next, the main CPU 101 performs medal acceptance / start check processing (S202). In this processing, the main CPU 101 performs input check processing such as a medal sensor (not shown) and the start switch 79. The details of the medal acceptance / start check process will be described later with reference to FIG. 75 described later.

  Next, the main CPU 101 performs random number acquisition processing (S203). In this processing, the main CPU 101 uses a random number value for internal winning combination lottery (0 to 65535: the value of the random number register 0 of the random number circuit 110 to be a hard latch random number) or a random number value for effects used in various lotteries related to ART ( 0 to 65535: each value of the random number registers 1 to 3 of the random number circuit 110 serving as a soft latch random number, 0 to 255: each value of the random number registers 4 to 7 of the random number circuit 110 serving as a soft latch random number) The various random numbers extracted are stored in a random value storage area (not shown) provided in the main RAM 103. Details of the random number acquisition process will be described later with reference to FIG. 83 described later.

  Next, the main CPU 101 performs an internal lottery process (S204). In this process, the main CPU 101 performs an internal winning combination determination process by lottery based on the random number value (hard latch random number) extracted in S203. Details of the internal lottery process will be described later with reference to FIG. 84 described later.

  Next, the main CPU 101 performs a symbol setting process (S205). In this process, the main CPU 101, for example, generates an internal winning combination from the hit request flag status (flag status information), expands the hit request flag data, and stores the hit request flag data in the hit request flag storage area. Etc. That is, the main CPU 101 sets a combination of symbols allowed to be stopped and displayed on the active line in the current unit game among a plurality of predetermined symbol combinations (see FIGS. 17 to 21). Process.

  Although detailed control is omitted, the main CPU 101 determines that the bonus combination (RB in the present embodiment) is already stored in the carryover combination storage area (see FIG. 26) in the symbol setting process of S205. In this unit game, including the bonus combination (RB in this embodiment), a combination of symbols allowed to be displayed on the active line is set, and the bonus combination (RB in this embodiment) is set. ) Is determined as the internal winning combination, the bonus combination (in this embodiment, RB) is stored as a carryover combination in the carryover combination storage area (see FIG. 26). In this case, in this process, the RT5 state may be set as the RT state.

  Next, the main CPU 101 performs a start command generation / storage process (S206). In this process, the main CPU 101 generates start command data to be transmitted to the sub-control circuit 200 and stores the command data in a communication data storage area (see FIG. 67B) provided in the main RAM 103. The start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. Note that the start command includes each parameter that specifies a game state, an internal winning combination, a control state, and other various types of information related to the ART function.

  Next, the main CPU 101 performs a second interface board control process (S207). Note that the second interface board control process is executed in a non-standard work area of the main RAM 103. Details of the second interface board control process will be described later with reference to FIG. 86 described later.

  Next, the main CPU 101 performs state-specific control processing (S208). In this process, the main CPU 101 mainly starts the game according to various control states (see FIGS. 31 to 55) for managing the progress of the game (that is, the start operation is performed and the internal winning in the unit game is performed). A game start process (start process) for performing the above-described various controls necessary when a winning combination is determined) is performed.

  Next, the main CPU 101 performs reel stop initial setting processing (S209). In this process, the main CPU 101 refers to a reel stop initial setting table (not shown), and acquires a drawing priority table selection table number, a drawing priority table number, and a stop table number based on the internal winning combination and the gaming state. And a process of storing “3” in the stop button non-operation counter.

  Next, the main CPU 101 performs reel rotation start processing (S210). In this process, the main CPU 101 requests the start of rotation of all reels. When the start of rotation of all reels is requested, three stepping motors (not shown) are driven by an interrupt process (see FIG. 113, which will be described later) executed at a constant cycle (1.1172 msec). Controlled, rotation of the left reel 3L, middle reel 3C and right reel 3R is started. Next, each reel is controlled to be accelerated until its rotational speed reaches a constant speed, and then controlled so as to maintain the constant speed.

  Next, the main CPU 101 performs reel rotation start command generation / storage processing (S211). In this process, the main CPU 101 generates reel rotation start command data to be transmitted to the sub control circuit 200, and stores the command data in a communication data storage area (see FIG. 67B) provided in the main RAM 103. The reel rotation start command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. The reel rotation start command includes a parameter indicating that the reel rotation start operation has started.

  Next, the main CPU 101 performs a pull-in priority storage process (S212). In this process, the main CPU 101 acquires the pull-in priority data and stores it in the pull-in priority data storage area. The details of the pull-in priority storage process will be described later with reference to FIG. 88 described later.

  Next, the main CPU 101 performs a reel stop control process (S213). In this process, the main CPU 101 performs stop control of rotation of the corresponding reel based on the timing when the left stop button 17L, the middle stop button 17C, and the right stop button 17R are respectively pressed and the internal winning combination. Details of the reel stop control process will be described later with reference to FIG. 96 described later.

  Next, the main CPU 101 performs a winning search process (S214). In this process, the main CPU 101 stores the data in the symbol code storage area (see FIG. 30) in the winning action flag storage area (see FIG. 25). In this process, the main CPU 101 displays the display combination on the effective line (that is, which symbol combination among the plurality of predetermined symbol combinations shown in FIGS. 17 to 21 is the active line). It is determined whether or not it has been displayed, and the number of medals to be paid out is set based on the determination result. The details of the winning search process will be described later with reference to FIG. 103 described later.

  Next, the main CPU 101 performs an illegal hit check process (S215). In this process, the main CPU 101 combines a winning request flag (internal winning combination) and a winning action flag (display combination), and determines the presence or absence of an illegal hit error based on the combined result. The details of the illegal hit check process will be described later with reference to FIG.

  Next, the main CPU 101 performs a winning check / medal payout process (S216). In this process, the main CPU 101 performs a winning operation command generation process. Further, in this process, the main CPU 101 drives the hopper device 51 and updates the number of credits based on the number of display combination payouts determined in S214, and performs a medal payout process. Details of the winning check / medal payout process will be described later with reference to FIG.

  Next, the main CPU 101 performs a bonus check process (S217). In this process, the main CPU 101 controls the operation and termination of the bonus state. Details of the bonus check process will be described later with reference to FIG.

  Next, the main CPU 101 performs RT check processing (S218). In this process, the main CPU 101 performs RT state transition control based on the symbol combination and the like that are stopped and displayed on the active line. Details of the RT check process will be described later with reference to FIG.

  Next, the main CPU 101 performs control processing according to the state at the end of the game (S219). In this process, the main CPU 101 determines the combination of symbols displayed at the end of the game (that is, all reels are stopped) in accordance with various control states (see FIGS. 31 to 55) for managing the progress of the game. When the game is finalized, a process at the end of the game for performing the various controls described above (that is, a process after all stops) is performed. After the process of S219 (after the end of one game), the main CPU 101 returns the process to the process of S201.

[Medal reception / start check processing]
Next, with reference to FIGS. 75 and 76, the medal acceptance / start check process performed in S202 in the main flow (see FIG. 74) will be described. 75 is a flowchart showing the procedure of medal acceptance / start check processing, and FIG. 76 is a diagram showing an example of a source program for executing the processing of S231 to S233 during medal acceptance / start check processing. is there.

  First, the main CPU 101 determines whether or not the value of the automatic insertion medal counter is “0” (whether or not there is an automatic insertion request) (S221). In this process, when the automatic insertion medal counter is “1” or more, the main CPU 101 determines that there is an automatic insertion request. The automatic insertion medal counter is data for identifying whether or not a display combination relating to replay (replay) has been established in the previous unit game. When the display combination related to the re-game is established, the medals for the number of coins inserted in the previous unit game are automatically inserted into the automatic insertion medal counter.

  In S221, when the main CPU 101 determines that the value of the automatic insertion medal counter is “0” (when S221 is YES), the main CPU 101 performs the process of S225 described later.

  On the other hand, when the main CPU 101 determines in S221 that the value of the automatic insertion medal counter is not “0” (when S221 is NO), the main CPU 101 performs medal insertion processing (S222). In this process, the main CPU 101 performs a medal insertion command generation / storage process, a medal insertion number LED lighting control process, and the like. The details of the medal insertion process will be described later with reference to FIG. 77 described later.

  Next, the main CPU 101 subtracts 1 from the value of the automatic insertion medal counter (S223). Next, it is determined whether or not the value of the automatically inserted medal counter after subtraction is “0” (S224).

  In S224, when the main CPU 101 determines that the value of the automatic insertion medal counter is not “0” (when S224 is NO), the main CPU 101 returns the process to S222 and repeats the processes after S222.

  On the other hand, when the main CPU 101 determines in S224 that the value of the automatic insertion medal counter is “0” (when S224 is YES), or when S221 is YES, the main CPU 101 stores the medal auxiliary storage. A warehouse switch check process is performed (S225). In this process, the main CPU 101 detects whether or not the medal auxiliary storage 52 is full of medals based on the on / off state of the medal auxiliary storage switch 75.

  Next, the main CPU 101 performs a medal insertion state check process (S226). Next, the main CPU 101 determines whether or not a medal can be inserted based on the result of the medal insertion state check process (S227).

  When the main CPU 101 determines in S227 that the medal cannot be inserted (when S227 is NO), the main CPU 101 performs a process of S231 described later.

  On the other hand, when the main CPU 101 determines in S227 that the medal can be inserted (when S227 is YES), the main CPU 101 performs a medal insertion check process (S228). In this process, for example, based on the medal sensor input state, the main CPU 101 determines whether or not a medal has passed normally, and credits the medal when a medal is inserted beyond a prescribed number. Perform processing. The details of the medal insertion check process will be described later with reference to FIG.

  Next, based on the result of the medal insertion check process, the main CPU 101 determines whether or not a medal can be inserted or credited (S229).

  When the main CPU 101 determines in S229 that the medal can be inserted or credited (YES in S229), the main CPU 101 performs a process of S231 described later. On the other hand, when the main CPU 101 determines in S229 that the medal cannot be inserted or credited (NO in S229), the main CPU 101 performs a medal acceptance prohibition process (S230). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24.

  After S230, when S227 is NO or when S229 is YES, the main CPU 101 determines whether or not the current number of inserted medals is the game start possible number (S231). In the present embodiment, the number of games that can be started is set to 3 regardless of the gaming state.

  In S231, when the main CPU 101 determines that the current number of inserted medals is the game start number (when S231 is YES), the main CPU 101 performs the process of S234 described later. On the other hand, when the main CPU 101 determines in S231 that the current number of inserted medals is not the game start possible number (when S231 is NO), the main CPU 101 determines whether or not there are medals inserted (S232). ).

  When the main CPU 101 determines in S232 that a medal has been inserted (when S232 is YES), the main CPU101 returns the process to S226 and repeats the processes after S226. On the other hand, when the main CPU 101 determines in S232 that no medal has been inserted (NO in S232), the main CPU 101 performs the setting change confirmation process described with reference to FIG. 60 (S233). In this processing, the main CPU 101 performs processing for generating and storing a setting change command at the start of setting confirmation.

  After the processing of S233 or when S231 is YES, the main CPU 101 determines whether or not the start switch 79 is on (S234).

  In S234, when the main CPU 101 determines that the start switch 79 is not in the ON state (when S234 is NO), the main CPU 101 returns the process to S226 and repeats the processes after S226.

  On the other hand, when the main CPU 101 determines in S234 that the start switch 79 is on (when S234 is YES), the main CPU 101 performs a medal acceptance prohibition process (S235). By this process, the solenoid of the selector 66 (see FIG. 4) is not driven, and the inserted medal is discharged from the medal payout opening 24. After the process of S235, the main CPU 101 ends the medal acceptance / start check process, and moves the process to S203 of the main flow (see FIG. 74).

  In the present embodiment, the medal acceptance / start check process is performed as described above. Then, the processing of S231 to S233 during the above-described medal acceptance / start check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. Among them, in the process of S233, the process is jumped to the address “SB_WVSC_00” of the execution program of the setting change confirmation process by the “CALLF” instruction which is the instruction code dedicated to the main CPU 101, and the setting change confirmation explained in FIG. 60 and FIG. Process.

  Then, the processing of S233 during the above-described medal acceptance / start check processing, that is, the setting change confirmation processing is executed regardless of the gaming state. Therefore, in this embodiment, regardless of the gaming state, that is, even if the gaming state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power interruption history, etc.)) are displayed. It is possible to confirm, and it is possible to suppress illegal acts such as goto.

[Medal insertion processing]
Next, with reference to FIGS. 77 and 78, the medal insertion process performed in S222 during the medal acceptance / start check process (see FIG. 75) will be described. FIG. 77 is a flowchart showing a procedure of medal insertion processing, and FIG. 78 is a diagram showing an example of a source program for executing medal insertion processing.

  First, the main CPU 101 adds “1” to the value of the medal counter (S241). The medal counter is a counter for counting the number of inserted medals, and is provided in the main RAM 103.

  Next, the main CPU 101 performs medal insertion command generation / storage processing (S242). In this process, the main CPU 101 generates medal insertion command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 67B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. That is, the medal insertion command is transmitted from the main control circuit 90 to the sub control circuit 200 every time a medal is inserted. The medal insertion command includes a parameter for specifying the number of inserted coins.

  Next, the main CPU 101 turns off the first to third LEDs for displaying the number of inserted medals included in the LED 82 (see FIG. 7) (S243). Next, the main CPU 101 calculates LED lighting data (lighting control data) corresponding to the medal insertion number based on the medal insertion number (medal counter value) (S244). In this process, for example, when the number of inserted medals is 1, LED lighting data for lighting only the first LED for displaying the number of inserted medals is calculated. For example, the number of inserted medals is 3. LED lighting data for lighting all the first to third LEDs for displaying the number of inserted medals is calculated. The method for calculating the LED lighting data will be described in detail later.

  Next, the main CPU 101 uses the calculated LED lighting data to light up the corresponding medal insertion number display LED (S245). After the process of S245, the main CPU 101 ends the medal insertion process, and moves the process to S223 of the medal acceptance / start check process (see FIG. 75).

  In the present embodiment, the medal insertion process is performed as described above. The medal insertion process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. In the process of S244, the LED lighting data for displaying the number of inserted medals is generated not by the loop process referring to the table but by the calculation process. This calculation process is performed by the main CPU 101 sequentially executing source codes “LD A, L” to “OR L” in the source program shown in FIG.

  In this calculation process, first, by executing the source code “LD A, L”, data of the number of inserted medals stored in the L register is stored in the A register. For example, when the number of inserted medals is 3, “00000011B” (decimal number “3”) is stored in the A register. In the present embodiment, 1-byte data is described as “*******”, but the last character “B” is “0” or “1” indicated before the character “B”. "Means bit data.

  Next, by executing the source code “ADD A, A”, the data stored in the A register is added to the data stored in the A register, and the addition result is stored in the A register. For example, if the data stored in the A register before the execution of the “ADD” instruction is “00000011B” (when the number of inserted medals is three), the addition result is obtained by the “ADD” instruction. “00000110B” is stored in the A register.

  Next, by executing the source code “DEC A”, 1 is subtracted from the data stored in the A register, and the subtraction result is stored in the A register. For example, when the data stored in the A register before the execution of the “DEC” instruction is “00000110B”, “00000101B” as a subtraction result is stored in the A register by the “DEC” instruction. .

  Next, by executing the source code “OR L”, a logical sum operation is performed on the data stored in the L register (the number of inserted medals) and the data stored in the A register, and the operation result is stored in the A register. Stored. For example, when the data stored in the A register before the execution of the “OR” instruction is “00000101B” and the data stored in the L register is “00000011B” (the number of inserted medals is 3) In this case, “000011B”, which is the result of the logical OR operation of both data, is stored in the A register by this “OR” instruction. The data stored in the A register by the execution of the “OR” instruction becomes LED lighting data for displaying the number of medal insertions (data indicating the lighting state of the medal insertion LED).

  For example, when the number of inserted medals is 3, as described above, the final calculation result “00000111B” is displayed for displaying the number of inserted medals by the calculation processing of the LED lighting data for displaying the number of inserted medals in S244. LED lighting data. In this embodiment, “0” of bit 0 of the finally calculated LED lighting data is “ON / OFF” of the output port to the first medal insertion number display LED (first LED). "1/0" of bit 1 corresponds to the "on / off" state of the output port to the LED for displaying the second medal insertion number (second LED), and "1" of bit 2 "/ 0" corresponds to the "ON / OFF" state of the output port to the third medal insertion number display LED (third LED). Therefore, when the number of inserted medals is 3, as described above, “00000111B” is generated as the LED lighting data, so that all output ports of the first to third LEDs for displaying the number of inserted medals are displayed. It is set to the on state, and all the first to third LEDs for displaying the number of inserted medals are turned on.

  When the LED lighting data for displaying the number of inserted medals is generated by the arithmetic processing as described above, the table data to be referred to when generating the LED lighting data for displaying the number of inserted medals is unnecessary, so the table area of the main ROM 102 Free space can be increased, and an increase in program capacity can be minimized. That is, in the above-described medal insertion process of the present embodiment, the medal insertion LED display process can be made more efficient, the free capacity of the main ROM 102 is secured (increased), and the increased free area is utilized, It becomes possible to improve game nature.

[Medal insertion check process]
Next, with reference to FIGS. 79 and 80, the medal insertion check process performed in S228 in the medal acceptance / start check process (see FIG. 75) will be described. 79 is a flowchart showing the procedure of the medal insertion check process, and FIG. 80 is a diagram showing an example of a source program for executing the processes of S255 to S258 during the medal insertion check process.

  First, the main CPU 101 determines whether or not replaying is in progress (S251).

  When the main CPU 101 determines in S251 that the game is being replayed (if S251 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 75). To S229.

  On the other hand, when the main CPU 101 determines in S251 that the game is not being replayed (when S251 is NO), the main CPU 101 permits medal acceptance (S252). In this processing, the solenoid of the selector 66 (see FIG. 4) is driven, and medals inserted from the medal insertion slot 24 are accepted. The received medals are counted and guided to the hopper device 51.

  Next, the main CPU 101 performs a bet button check process (S253). In this process, the main CPU 101 determines whether or not the bet button (MAX bet button 15a or 1 bet button 15b) has been operated based on the on / off state of the BET switch 77. Next, the main CPU 101 determines whether or not the betting operation is completed based on the result of the bet button check process in S253 (S254).

  When the main CPU 101 determines in S254 that the betting operation has been completed (when S254 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check process (see FIG. 75). To S229.

  On the other hand, when the main CPU 101 determines in S254 that the betting operation has not been completed (in the case where S254 is NO), the main CPU 101 determines the medal sensor input state (game medium acceptance state) during the current process, The medal sensor input state at the time of the previous process is acquired (S255). The medal sensor input state is information indicating the passage status of medals received in the medal insertion slot 24 in the selector 66, and the detection results of each medal sensor (not shown) provided at the entrance and the exit of the selector 66. Is generated by

  In this embodiment, the medal sensor input state is represented by 1-byte (8-bit) data, and the first medal sensor (not shown) on the upstream side provided side by side in the medal passage direction at the exit of the selector 66. The detection result corresponds to the information of bit 0 (“0” or “1”), and the detection result of the second medal sensor (not shown) on the downstream side corresponds to the information of bit 1 (“0” or “1”). To do. When the passage of the medal is detected by the first medal sensor, “1” is set to the bit 0, and when the passage of the medal is detected by the second medal sensor, “1” is set to the bit 1. Is done. Therefore, the medal sensor input state “00000000B” indicates the state before or after passing the medal (at the time of passing), and the medal sensor input state “00000001B” indicates the state when the medal passage starts, and the medal sensor input state “ “00000011B” indicates a state in which a medal is passing, and a medal sensor input state “00000010B” indicates a state immediately before completion of medal passing.

  Next, the main CPU 101 determines whether or not the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (S256).

  In S256, when the main CPU 101 determines that the medal sensor input state during the current process has not changed from the medal sensor input state during the previous process (when S256 is NO), the main CPU 101 proceeds to S261 described below. Process.

  On the other hand, when the main CPU 101 determines in S256 that the medal sensor input state during the current process has changed from the medal sensor input state during the previous process (when S256 is YES), the main CPU 101 Based on the medal sensor input state, a normal value (normal change value) of the medal sensor input state obtained in the current process is generated by arithmetic processing (S257).

  In this process, when the medal sensor input state at the time of the previous process is “00000000B” (when both the first and second medal sensors are not detected), the normal change value of the medal sensor input state is used. When “00000001B” (when the first medal sensor is medal detection and the second medal sensor is not medal detection) is generated, and the medal sensor input state at the previous processing is “00000001B”, the medal sensor As a normal change value of the input state, “00000011B” (when both the first and second medal sensors are medal detection) is generated. In this process, if the medal sensor input state at the previous process is “00000011B”, the normal change value of the medal sensor input state is “00000010B” (the first medal sensor is not detected, the second When the medal sensor is medal detection) and the medal sensor input state at the time of the previous process is “00000010B”, the normal change value of the medal sensor input state is “00000000B” (first and second medals). When both medals have not been detected yet). The method for generating (calculating) the normal change value of the medal sensor input state will be described in detail later.

  Next, the main CPU 101 determines whether or not the medal sensor input state at the time of the current process is the same as the normal change value generated in S257 (S258). In this determination process, it is determined whether or not a medal retrograde error has occurred, and if the determination condition in S258 is not satisfied, the main CPU 101 determines that a medal retrograde error has occurred.

  In S258, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not the same as the normal change value generated in S257 (when S258 is NO), the main CPU 101 performs the process of S262 described later. Do.

  On the other hand, when the main CPU 101 determines in S258 that the medal sensor input state at the current process is the same as the normal change value generated at S257 (when S258 is YES), the main CPU 101 It is determined whether or not the medal sensor input state is a medal passing state (“00000000B”) (S259). In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is a state when the medal passes (when S259 is YES), the main CPU 101 performs the process of S263 described later.

  In S259, when the main CPU 101 determines that the medal sensor input state at the time of the current process is not a medal passage state (when S259 is NO), the main CPU 101 sets a medal passage check timer (S260). The time set in the medal passage check timer in this process can be set to any time as long as it is possible to determine whether or not the medal has passed the selector 66. Further, the timer value set in this process may be changed according to the medal sensor input state at the time of the current process, for example.

  After the processing of S260 or when S256 is NO, the main CPU 101 determines whether the medal sensor input state at the time of the current processing is a state in which a medal is passing (“00000011B”) and the medal passing check timer is stopped. Is determined (S261). In this determination process, it is determined whether or not a medal passage error (inserted medal passage time error) has occurred, and when the determination condition of S261 is satisfied, the main CPU 101 determines that a medal passage error has occurred.

  In S261, when the main CPU 101 determines that the determination condition of S261 is not satisfied (when S261 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, in S261, when the main CPU 101 determines that the determination condition of S261 is satisfied (when S261 is YES), or when S258 is NO, that is, a medal passing error or a medal retrograde error has occurred. When it is determined that the main CPU 101 performs error processing (S262). In this process, the main CPU 101 performs various processes when an error occurs, such as an error command generation / storage process. Details of error processing will be described later with reference to FIG. 81 described later. After the process of S262, the main CPU 101 returns the process to the process of S253, and repeats the processes after S253.

  Here, returning to the process of S259 again, if S259 is YES, the main CPU 101 determines whether or not a prescribed number (three in this embodiment) of medals has been inserted (S263). .

  In S263, when the main CPU 101 determines that the prescribed number of medals has not been inserted (when S263 is NO), the main CPU 101 performs the medal insertion process described in FIG. 77 (S264). After the process of S264, the main CPU 101 returns the process to the process of S253 and repeats the processes after S253.

  On the other hand, when the main CPU 101 determines in S263 that the specified number of medals has been inserted (when S263 is YES), the main CPU 101 adds “1” to the value of the credit counter (S265). ). Next, the main CPU 101 performs medal insertion command generation storage processing (S266). In this process, the main CPU 101 generates medal insertion command data to be transmitted to the sub-control circuit 200, and stores the command data in a communication data storage area (see FIG. 67B) provided in the main RAM 103. The medal insertion command stored in the communication data storage area is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG.

  Next, the main CPU 101 determines whether or not the credit number of medals is the upper limit value (50 in the present embodiment) based on the value of the credit counter (S267).

  When the main CPU 101 determines that the medal credit number is not the upper limit value in S267 (when S267 is NO), the main CPU 101 returns the process to the process of S253 and repeats the processes after S253. On the other hand, when the main CPU 101 determines in S267 that the credit number of medals is the upper limit value (when S267 is YES), the main CPU 101 ends the medal insertion check process, and the process is a medal acceptance / start check. The process proceeds to S229 in the process (see FIG. 75).

  In the present embodiment, the medal insertion check process is performed as described above. Then, the processing of S255 to S258 during the above-described medal insertion check processing is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among them, the generation process of the normal change value of the medal sensor input state in S257 is performed not by the process of obtaining with reference to the table but by the calculation process. Specifically, the normal change value generation process is performed by the main CPU 101 executing the source code “RLA” and “AND cBX_MDINSW” in the source program shown in FIG. 80 in this order.

  The “RLA” instruction is an instruction code that shifts 1-byte data stored in the A register to the left (in the direction from bit 0 to bit 7) once (one bit). In the example shown in FIG. 80, 1-byte data indicating the previous medal sensor input state stored in the A register by the source code “LD A, B” executed before the “RLA” instruction is the “RLA” instruction. Shifts to the left once. At this time, the bit data newly stored in bit 0 is determined based on the execution result of the source code “CP cBX_MDISW2” executed before the “RLA” instruction.

  The “CP” instruction is an instruction code for executing a comparison operation. “CBX_MDISW2” is 1-byte data, and is “00000010B” in the present embodiment. When the source code “CP cBX_MDISW2” is executed, 1-byte data indicating the previous medal sensor input state stored in the A register is compared with “cBX_MDISW2 (00000010B)”.

  If the result of executing the source code “CP cBX_MDISW2” indicates that the 1-byte data indicating the previous medal sensor input state is less than “cBX_MDISW2 (00000010B)”, the carry flag of the flag register F is obtained. “1” is set in (see FIG. 11), and the carry flag “1” of the flag register F is stored in bit 0 of the A register when the “RLA” instruction is executed. On the other hand, as a result of executing the source code “CP cBX_MDISW2”, if the result that the 1-byte data indicating the previous medal sensor input state is “cBX_MDISW2 (00000010B)” or more is obtained, the carry flag of the flag register F “0” is set in (see FIG. 11), and the carry flag “0” of the flag register F is stored in bit 0 of the A register when the “RLA” instruction is executed.

  Therefore, for example, if the 1-byte data indicating the previous medal sensor input state is “00000000B (before or after passing medal) (<cBX_MDISW2”), the “RLA” command If “00000001B” is generated by execution, and the 1-byte data indicating the previous medal sensor input state is “00000001B (the state at the start of medal passage)” (<cBX_MDISW2 ”), the“ RLA ”instruction is executed. As a result, “00000011B” is generated. On the other hand, for example, if 1-byte data indicating the previous medal sensor input state is “00000011B (medal passing state)” (> “cBX_MDISW2”), “00000110B” is generated by executing the “RLA” instruction. If the 1-byte data indicating the previous medal sensor input state is “00000010B (state immediately before completion of medal passage)” (= “cBX_MDISW2”), “00000100B” is generated by executing the “RLA” instruction. The

  Next, when the source code “AND cBX_MDINSW” is executed, 1-byte data (stored data in the A register) generated by executing the “RLA” instruction is logically ANDed with 1-byte data “cBX_MDINSW”, and the medal sensor A normal change value of the input state is calculated. The 1-byte data “cBX_MDISW” is “00000011B” in the present embodiment. Therefore, when the source code “AND cBX_MDINSW” is executed, only the data of bit 0 and bit 1 in the data stored in the A register is masked, and the other bit data becomes “0”.

  As a result, for example, if 1-byte data indicating the previous medal sensor input state is “00000000B (the state before passing the medal)”, the normal change value of the medal sensor input state is “00000001B (the state when the medal passage is started). ) ”Is generated, and if 1-byte data indicating the previous medal sensor input state is“ 00000001B (the state at the start of medal passage) ”, the normal change value of the medal sensor input state is“ 00000011B (the medal passing state). Status) "is generated. On the other hand, for example, if 1-byte data indicating the previous medal sensor input state is “00000011B (medal passing state)”, the normal change value of the medal sensor input state is “00000010B (state immediately before completion of medal passing)”. ”Is generated, and if the 1-byte data indicating the previous medal sensor input state is“ 00000010B ”(a state immediately before completion of medal passage), the normal change value of the medal sensor input state is“ 00000000B (after the medal passage (passing) State) ”is generated.

  As described above, by changing the detection process of the change state of the medal sensor input state from the table reference process to the calculation process, the free space in the table storage area of the main ROM 102 can be increased, and the program capacity can be increased. Can be minimized. Therefore, by adopting the above-described method, it is possible to improve the efficiency of the medal insertion sensor state detection process, and it is possible to improve the gameability by utilizing the increased free space in the main ROM 102.

[Error handling]
Next, with reference to FIGS. 81 and 82, for example, the error process performed in S262 during the medal insertion check process (see FIG. 79) will be described. FIG. 81 is a flowchart showing a procedure of error processing, and FIG. 82 is a diagram showing an example of the configuration of an error table that is actually referred to on the error processing source program.

  In the error table shown in FIG. 82, for each 1-byte data (eg, 1-byte data stored in the address “dERR_HE” in FIG. 82) indicating the on / off state of the port indicating the type of error factor, Error display data (for example, 1-byte data stored in addresses “dERR_HE + 1” and “dERR_HE + 2” in FIG. 82) is defined. This error display data is output to a 2-digit 7-segment LED (used for both the payout number display and the error display) included in the information display 6.

  First, the main CPU 101 performs a medal solenoid off process (S271). Specifically, the main CPU 101 stops driving the solenoid of the selector 66 (see FIG. 7). Next, the main CPU 101 performs evacuation processing of medal payout number display data (S272).

  Next, the main CPU 101 performs error table setting processing (S273). By this processing, the head address of the error table shown in FIG. 82 is set on the source program.

  Next, the main CPU 101 acquires an error factor (S274). Note that the error factor acquired in this process varies depending on the process from which the currently processed error process is read. As the error factors to be targeted in this embodiment, as shown in FIG. 82, “hopper empty error”, “hopper jam error”, “inserted medal passage count error”, “inserted medal passage check error”, “ The “inserted medal passage check error”, “inserted medal passage time error”, “inserted medal retrograde error”, “inserted medal auxiliary storage full error”, and “illegal hit error” are defined. For example, when the error process is read after the process of S258 during the medal insertion check process, “inserted medal retrograde error (Cr)” in FIG. 82 is acquired as the error factor in this process. For example, when the error process is read after the process of S261 during the medal insertion check process, the “inserted medal passage time error (CE)” in FIG. 82 is acquired as an error factor in this process. .

  Next, the main CPU 101 acquires error display data from the error table and error factors (S275). For example, when the error factor is “inserted medal retrograde error (Cr)”, the error display data shown in FIG. 82 is output as error display data to be output to the upper 7-segment LED of the 2-digit 7-segment LED in this process. 1-byte data “01001110B” stored at address “dERR_CR + 1” in the table is acquired, and 1-byte data “00001001B” stored at address “dERR_CR + 2” is output as error display data to the 7-segment LED of the lower digit. Is acquired. In this case, two characters “Cr” are displayed as error information on the two-digit 7-segment LED.

  Next, the main CPU 101 performs error command (occurrence) generation and storage processing (S276). In this process, the main CPU 101 generates error command data to be transmitted to the sub-control circuit 200 when an error occurs, and stores the command data in a communication data storage area (see FIG. 67B) provided in the main RAM 103. . An error command at the time of occurrence of an error stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by a communication data transmission process in an interrupt process described later with reference to FIG. The error command when an error occurs includes a parameter indicating the error occurrence.

  Next, the main CPU 101 performs standby processing for one interrupt time (1.1172 ms) (S277). Next, the main CPU 101 determines whether or not the error has been canceled (S278).

  When the main CPU 101 determines in S278 that the error has not been canceled (when S278 is NO), the main CPU 101 returns the process to the process of S277 and repeats the processes after S277.

  On the other hand, when the main CPU 101 determines in S278 that the error has been canceled (in the case where S278 is YES), the main CPU 101 performs error factor clear processing (S279). This process is performed in a non-standard work area of the main RAM 103. Next, the main CPU 101 performs a return process of the payout number display data of medals saved in S272 (S280).

  Next, the main CPU 101 performs error command (cancellation) generation and storage processing (S281). In this process, the main CPU 101 generates error command data to be transmitted to the sub-control circuit 200 upon error cancellation, and stores the command data in a communication data storage area (see FIG. 67B) provided in the main RAM 103. . The error command at the time of error cancellation stored in the communication data storage area is transmitted from the main control circuit 90 to the sub control circuit 200 by the communication data transmission process in the interrupt process described later with reference to FIG. The error command at the time of error cancellation includes a parameter indicating error cancellation. Then, after the processing of S281, the main CPU 101 ends the error processing, and moves the processing to S253 in the medal insertion check processing (see FIG. 79), for example. In the error cancellation, the error factor that has occurred is canceled, and the error state is canceled by pressing the reset switch 76.

[Random number acquisition processing]
Next, the random number acquisition process performed in S203 in the main flow (see FIG. 74) will be described with reference to FIG. FIG. 83 is a flowchart showing the procedure of random number acquisition processing.

  First, the main CPU 101 acquires the hard latch random number (0 to 65535) of the random number register 0 of the random number circuit, and uses the acquired random number value as the random number value for the internal winning combination lottery in the random value storage area (invalid) in the main RAM 103. (S291).

  Next, the main CPU 101 determines the soft latch random numbers in the random number registers 1 to 7 of the random number circuit (in this embodiment, 0 to 65535: random number value for effect used in lottery processing for executing the lock effect during MB, 0 to 255: ART related) The setting process of the soft latch random number acquisition register for generating the rendering random number value used in the lottery process is performed (S292). Next, the main CPU 101 sets the number of acquired soft latch random numbers (for example, 7) (S293).

  Next, the main CPU 101 obtains the acquired number of soft latch random numbers at once and stores the acquired number of soft latch random numbers in the random number storage area (S294). At this time, the soft latch random number (effect random number value, 2-byte random value) acquired from the random number register 1 of the random number circuit 110 is the hardware acquired from the random number register 0 of the random number circuit in the random value storage area. It is stored in an area different from the area where the latch random number (random number value for internal winning combination lottery) is stored. Then, after the process of S294, the main CPU 101 ends the random number acquisition process, and moves the process to S204 of the main flow (see FIG. 74). In the present embodiment, a predetermined storage area of the main RAM 103 is allocated as a random number storage area so that a plurality of 2-byte random numbers and 1-byte random numbers can be stored.

[Internal lottery processing]
Next, the internal lottery process performed in S204 in the main flow (see FIG. 74) will be described with reference to FIGS. 84 is a flowchart showing the procedure of the internal lottery process, FIG. 85A is a diagram showing an example of a source program for executing the processes of S302 to S305 during the internal lottery process, and FIG. It is a figure which shows an example of the source program for performing the process of S308-S309 in an internal lottery process.

  First, the main CPU 101 performs a set value / medal insertion number check process (S301). In this process, the main CPU 101 performs a check process for the current game setting value (any one of 1 to 6) and the number of inserted medals (three in this embodiment).

  Next, the main CPU 101 sets the internal lottery table for general games and the number of lotteries (67 times in this embodiment) (S302). In this process, the value of “winning number” (winning request flag status) in the internal lottery tables (RT0 to RT5) shown in FIGS. 15 and 16 is set in the C register, and “determination data” (not shown: address) The value of (data for determining the reference destination) is set in the A register.

  Next, the main CPU 101 determines whether or not the RB is operating (S303). That is, the main CPU 101 determines whether or not the BB gaming state (BB operation is in progress). In S303, when the main CPU 101 determines that the RB is not operating (when S303 is NO), the main CPU 101 performs a process of S305 described later.

  On the other hand, when the main CPU 101 determines in S303 that the RB is operating (in the case where S303 is YES), the main CPU 101 determines that the internal lottery table for RB (this embodiment is shown in FIGS. 15 and 16). Further, the number of lotteries (71 in this embodiment as in the general game) is set (S304). In this process, the internal lottery table and the number of lotteries for the general game set in S302 are overwritten with the internal lottery table for the RB and the number of lotteries. In the internal lottery tables shown in FIGS. 15 and 16, for convenience of explanation, the internal lottery table for general games and the internal lottery table for RBs have the same configuration, but in each gaming state, It is good also as a different structure so that only a required internal winning combination is lottery.

  After the process of S304 or when S303 is NO, the main CPU 101 acquires the determination data of the lottery target combination from the set internal lottery table, and updates the lottery table address (S305).

  Next, the main CPU 101 determines whether the determination data is RT state data (S306). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the RT state. For example, the main CPU 101 determines whether or not the address specified in the determination data of the lottery target combination currently acquired is an address in an RT state-specific lottery value selection table (not shown).

  For example, in the internal lottery table shown in FIGS. 15 and 16, the determination data associated with the internal winning combination “F_normal lip” is the internal winning combination “F_” in the RT state-specific lottery value selection table (not shown). Since the address of “normal lip” is defined, the determination data associated with the internal winning combination “F_normal lip” corresponds to the RT state-specific data. Therefore, when the lottery target combination currently acquired is the internal winning combination “F_normal lip”, in the process of S306, the main CPU 101 determines that the determination data is RT state data.

  In S306, when the main CPU 101 determines that the determination data is not RT state data (when S306 is NO), the main CPU 101 performs the process of S308 described later. On the other hand, in S306, when the main CPU 101 determines that the determination data is the RT state-specific data (when S306 is YES), the main CPU 101 determines the RT state-specific lottery value selection table (not determined) based on the determination data. The selection data is acquired from (shown), and the acquired selection data is set as determination data (S307).

  After the processing of S307 or when S306 is NO, the main CPU 101 determines whether the determination data of the lottery target combination is data by setting (S308). In this process, the main CPU 101 determines whether or not the lottery target combination currently acquired is an internal winning combination whose lottery value changes according to the set value. For example, the main CPU 101 determines whether or not the address defined in the determination data of the lottery target combination that is currently acquired is an address in a setting-specific internal lottery value table (not shown).

  For example, in the internal lottery table shown in FIG. 15 and FIG. 16, when the internal winning combination “F_common bell” is defined such that the lottery value increases as the set value increases, this internal winning combination “F_common bell”. "Is associated with the internal winning combination" F_Common Bell "because the address of the internal winning combination" F_Common Bell "in the setting-specific lottery value selection table (not shown) is defined. The attached determination data corresponds to setting-specific data. Therefore, when the lottery target combination currently acquired is the internal winning combination “F_Common Bell”, in the processing of S308, the main CPU 101 determines that the determination data is setting-specific data.

  In S308, when the main CPU 101 determines that the determination data is not the setting-specific data (when S308 is NO), the main CPU 101 performs the process of S310 described later. On the other hand, when the main CPU 101 determines in S308 that the determination data is data by setting (when S308 is YES), the main CPU 101 adds the set value data (any of 0 to 5) to the determination data. Then, the added value is set in the determination data (S309). The set value data added to the determination data in this process is data associated with the set value. However, the set value data “0” to “5” is not “the set value itself” but “ Data corresponding to “Setting 1” to “Setting 6”.

  After the process of S309 or when S308 is NO, the main CPU 101 calculates the address of the area in which the lottery value of the lottery target role is stored based on the set determination data, and the lottery stored in the address A value is acquired (S310).

  For example, when the lottery target combination is an internal winning combination (for example, “F_C_rarebell”) whose lottery value does not vary depending on either the RT state or the set value, the main CPU 101 determines the lottery from the address indicated by the determination data. The value “66” is acquired.

  For example, when the lottery target combination is an internal winning combination whose lottery value varies depending on the RT state (for example, “F_normal lip”), the main CPU 101 determines the RT0 state (from the address indicated by the determination data). If it is RT0), the lottery value “7912” is acquired, if it is the RT5 state (RT5), the lottery value “6” is acquired, and if it is the other RT state (RT1 to RT4), the lottery value is acquired. The value “0” is acquired.

  Further, for example, when the lottery target combination is an internal winning combination (for example, “F_common bell”) whose lottery value varies depending on the set value, the main CPU 101 determines the set value “ The lottery value corresponding to “1” to “6” is acquired. At this time, the lottery value corresponding to the set value is acquired by specifying the address obtained by adding the set value data to the determination data (processing in S309).

  Further, for example, when the lottery target combination is an internal winning combination whose lottery value varies depending on both the RT state and the set value, the main CPU 101 determines whether the RT lot-specific internal lottery value table and the setting-specific internal lottery value table The lottery value is acquired with reference to both (see S306 to S309).

  Next, the main CPU 101 acquires a random number value (any one of 0 to 65535) for internal winning combination lottery stored in the random number storage area (S311).

  Next, the main CPU 101 performs lottery execution processing (S312). In this process, the main CPU 101 adds the random number acquired in S311 to the lottery value acquired in S310, and sets the addition result as a lottery result (winning / non-winning for the lottery target role). In this lottery execution process, when the sum of the lottery value and the random number value exceeds 65535 (when overflowing), it is determined that the lottery target combination is won (the lottery target combination is determined as an internal winning combination). The

  Next, the main CPU 101 stores a value obtained by adding the lottery value to the random number value (random number value after lottery execution) as a new random number value in the random number storage area (S313). Next, the main CPU 101 determines whether or not a lottery execution process has been won (whether or not an overflow has occurred) (S314).

  In S314, when the main CPU 101 determines that the lottery execution process has been won (when S314 is YES), the main CPU 101 refers to the internal lottery table, and the winning request flag status (corresponding to the internal winning combination won) (Value of “winning number”) is acquired (S315). For example, in a general game, when a lottery execution process is performed when the lottery target combination is “F_normal lip”, “5” is acquired as the winning request flag status in the process of S315. After the process of S315, the main CPU 101 performs a process of S319 described later.

  On the other hand, when it is determined in S314 that the main CPU 101 has not won the lottery execution process (when S314 is NO), the main CPU 101 updates the lottery object combination to the next combination in the internal lottery table, and lottery is performed. The number of times is subtracted by 1 (S316). Next, the main CPU 101 determines whether or not the number of lotteries after subtraction is “0” (S317).

  In S317, when the main CPU 101 determines that the number of lotteries after subtraction is not “0” (when S317 is NO), the main CPU 101 returns the process to the process of S305 and repeats the processes after S305.

  On the other hand, when the main CPU 101 determines in S317 that the number of lotteries after subtraction is “0” (when S317 is YES), that is, when the internal winning combination is “out”, the main CPU 101 The lose status is set (S318). The “losing status” corresponds to a hit request flag status in which the winning number is “0”. After the process of S318, the main CPU 101 performs a process of S319 described later.

  Next, the main CPU 101 determines whether or not the CB is operating (CB gaming state) (S319). That is, the main CPU 101 determines whether or not the MB gaming state (MB is operating). In S319, when the main CPU 101 determines that the CB operation is not being performed (when S319 is NO), the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 74).

  On the other hand, in S319, when the main CPU 101 determines that the CB is operating (when S319 is YES), the main CPU 101 sets the bits of all small combinations in the winning request flag storage area (internal winning combination storage area). Processing to turn on is performed (S320). That is, during the CB operation, the main CPU 101 performs a process of winning all the small combinations regardless of the result of the internal lottery process. Specifically, the main CPU 101 performs a process of storing “1” in bits corresponding to NML1 (C_1 sheets A_1st_A_1) to NML136 (S_MB9_G_4) in the hit request flag storage area (internal winning combination storage area). After the process of S320, the main CPU 101 ends the internal lottery process and moves the process to S205 of the main flow (see FIG. 74).

  In the present embodiment, the internal lottery process is performed as described above. Note that the processing of S302 to S305 during the internal lottery processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 85A. Among them, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 85A.

  For example, when the source code “LDIN ss, (HL)” is executed on the source program, a memory specified by an address set in the HL register (pair register) and an address obtained by adding “1” to the address. Is loaded into the ss (BC, DE, AC, AE, or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 85A is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the determination data acquisition process in S305, as described above, the determination data is stored in the A register by the “LDIN” instruction (predetermined read instruction), and the request flag status is stored in the C register. .

  As described above, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed with one instruction code ("LDIN" instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Further, the processing of S308 and S309 during the internal lottery processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 85B. Among them, the addition processing of the set value data (any one of 0 to 5) in S309 is performed by the main CPU 101 using the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM)” in FIG. 85B. This is done by executing in this order. Note that both the “MUL” instruction and the “ADDQ” instruction are instruction codes dedicated to the main CPU 101, and the “ADDQ” instruction is an instruction code dedicated to the main CPU 101 that performs address designation using the Q register (extension register).

  For example, when the source code “MUL A, n” is executed on the source program, the data stored in the A register is multiplied by the 1-byte integer n, and the multiplication result is stored in the A register. Therefore, in the source code “MUL A, 6” in FIG. 85B, the contents (stored data) of the A register are multiplied by a 1-byte integer 6, and the multiplication result is stored in the A register. This multiplication process is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachislot machine 1 of the present embodiment, an arithmetic dedicated circuit (arithmetic circuit 107) for executing multiplication processing and division processing on the source program is provided, so that the efficiency of the multiplication processing and division processing is improved. Can do.

  For example, when the source code “ADDQ r, (k)” is executed on the source program, the data stored in the Q register (upper address value) and a 1-byte integer k (direct value: lower address value) The data stored in the r register (A, B, C, D, E, H, or L register) is added to the memory contents (stored data) at the address specified in (), and the addition result is stored in the r register. The Therefore, when the source code “ADDQ A, (.LOW.wWAVENUM)” in FIG. 85B is executed, the data stored in the Q register and the memory at the address specified by the integer value “.LOW.wWAVENUM” of 1 byte The contents (stored data) of the A register are added to the contents (set value data), and the addition result is stored in the A register.

  That is, in the example shown in FIG. 85B, in the setting value addition process of S309, the lottery table selection relative value is multiplied by the coefficient “6”, and the setting value data is added to the multiplied value, thereby The address of the lottery table in which the lottery values are stored is calculated.

  As described above, in the present embodiment, in the internal lottery process, the main CPU 101 dedicated instruction code (“ADDQ” instruction) using the Q register (extension register) is used. Thus, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed. Therefore, an instruction relating to address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Second interface board control processing (not specified)]
Next, the second interface board control process performed in S207 in the main flow (see FIG. 74) will be described with reference to FIG. FIG. 86 is a flowchart showing the procedure of the second interface board control process. This process is performed in an unspecified work area (see FIG. 12C) in the main RAM 103. The program used in the second interface board control process is stored in an unspecified area in the main ROM 102 (see FIG. 12B).

  First, the main CPU 101 saves the address data of the stack area in the main RAM 103 set in the stack pointer (SP) (S361). Next, the main CPU 101 sets the address data of the non-standard stack area in the main RAM 103 to the stack pointer (SP) (S362).

  Next, the main CPU 101 acquires navigation data (S363). Next, the main CPU 101 sets the navigation conversion table in an unspecified work area in the main RAM 103 (S364).

  Next, the main CPU 101 refers to the navigation conversion table and acquires the second interface push order number (S365). Next, the main CPU 101 stores the acquired second interface push order number in a specified extra push order number storage area (not shown) provided in the extra work area (S366). Next, the main CPU 101 sets “0” to the value of the pressed position table selection counter provided in the non-standard work area (S367).

  Next, the main CPU 101 determines whether or not the obtained navigation data is push order navigation (push order navigation data) (S368). In S368, when the main CPU 101 determines that the acquired navigation data is push order navigation (when S368 is YES), the main CPU 101 performs the process of S372 described later.

  On the other hand, when the main CPU 101 determines in S368 that the acquired navigation data is not push-sequence navigation (when S368 is NO), the main CPU 101 determines that the acquired navigation data is navigation data for single-player A stop operation. It is determined whether or not (S369).

  In S369, when the main CPU 101 determines that the acquired navigation data is navigation data for single-sheet A stop operation (when S369 is YES), the main CPU 101 performs the process of S371 described later. On the other hand, when the main CPU 101 determines in S369 that the acquired navigation data is not the navigation data for the single piece A stop operation (when S369 is NO), the main CPU 101 sets the value of the pressed position table selection counter. “1” is added (S370). In S370, the process of adding “1” to the value of the pressed position table selection counter is a process performed to acquire the pressed position of the single combination B from the pressed position table (not shown).

  After the process of S370 or when S369 is YES, the main CPU 101 adds “1” to the value of the pressed position table selection counter (S371). In S <b> 371, the process of adding “1” to the value of the pressed position table selection counter is a process that is performed to obtain the pressed position of the single combination A or single combination B from the pressed position table (not shown). .

  After the process of S371 or when S368 is YES, the main CPU 101 selects a pressed position table (not shown) based on the value of the pressed position table selection counter (S372). Next, the main CPU 101 refers to the selected pressing position table, and acquires pressing position data for three reels (left reel 3L, middle reel 3C, and right reel 3R) (S373). Next, the main CPU 101 stores the acquired pressing position data in a non-standard pressing position storage area (not shown) provided in the non-standard working area (S374). If the navigation data is the push order navigation by the processing of S367 to S371, the value of the pressed position table selection counter is “0”, and if the navigation data is the navigation data for the single role A stop operation, the pressed position table. The value of the selection counter is “1”, and if the navigation data is navigation data for single-sheet combination B stop operation, the value of the pressed position table selection counter is “2”. That is, the pressed position data is acquired based on the navigation data.

  Note that the processes in S369 and S371 are processes when there are a plurality of internal winning combinations that require notification of the pressed position, and only one internal winning combination that requires notification of the pressed position is provided. If not, the processes in S369 and S371 are not necessary. Also, in FIG. 86, as described above, the position where the one-piece combination A and the one-piece combination B are pressed can be notified in the state where the ART function is operating. Since there is little profit difference in non-establishment, the pressing position may not be notified. In place of this, or in addition to this, in a game in which “RB” as a bonus combination can be established, the pressed position data corresponding to “RB” is acquired in order to notify the pressed position. ”May be notified of a pressed position that can be established.

  Next, the main CPU 101 performs a second interface board output process (S375). The details of the second interface board output process will be described later with reference to FIG. 87 described later.

  Next, the main CPU 101 performs restoration processing for all registers (S376). Next, the main CPU 101 sets the address data of the stack area saved in S361 to the stack pointer (SP) (S377). After the process of S377, the main CPU 101 ends the second interface board control process, and moves the process to S208 of the main flow (see FIG. 74).

[Second interface board output processing]
Next, the second interface board output process performed in S375 in the second interface board control process (see FIG. 86) will be described with reference to FIG. FIG. 87 is a flowchart showing the procedure of the second interface board output process. The second interface board output process is performed in a non-standard work area of the main RAM 103.

  First, the main CPU 101 determines whether or not a transmission operation is being performed via the second interface serial line (second serial communication circuit 115: SCU2) (S381). When the main CPU 101 determines in S381 that the transmission operation is being performed via the second interface serial line (when S381 is YES), the main CPU 101 ends the second interface board output process, The process moves to S376 of the second interface board control process (see FIG. 86).

  On the other hand, when the main CPU 101 determines in S381 that the transmission operation is not performed via the second interface serial line (when S381 is NO), the main CPU 101 is provided in an unspecified work area. “3” (the number of reels) is set to the value of the loop counter, and the initial value “1” is set to the serial communication thumb value (S382). Next, the main CPU 101 transmits transmission start data via the second interface serial line (second serial communication circuit 115: SCU2) (S383).

  Next, the main CPU 101 refers to the non-regulated pressing position storage area of the predetermined reel (rotating cylinder), and acquires the pressing position data of the predetermined reel (S384). Next, the main CPU 101 updates the non-regulated pressing position storage area to be referred to that of the next target reel (rotor) (S385).

  Next, the main CPU 101 acquires pulse number data corresponding to the pressed position data (design position) based on the pulse conversion data (not shown) and the acquired pressed position data (S386). The details of the correspondence between the pressed position data (symbol position) and the pulse number data are omitted. For example, the acquired pressed position data (symbol position) is “3” (the symbol “bell” in the left reel 3L). When “38” is acquired as the pulse number data, and when the pressed position data (design position) is “10” (design “Cherry 1” in the left reel 3L), “38” is obtained as the pulse number data. When “155” is acquired and the acquired pressing position data (symbol position) is “12” (symbol “white 7-1” in the left reel 3L), “189” is acquired as the pulse number data.

  Next, the main CPU 101 transmits the acquired pulse number data via the second interface serial line (second serial communication circuit 115: SCU2) (S387). Next, the main CPU 101 adds pulse number data to the serial communication sum value (S388). Next, the main CPU 101 subtracts 1 from the value of the loop counter (S389).

  Next, the main CPU 101 determines whether or not the value of the loop counter is “0” (S390). In S390, when the main CPU 101 determines that the value of the loop counter is not “0” (when S390 is NO), the main CPU 101 changes the target reel to the next reel and returns the process to S384. The processes after S384 are repeated.

  On the other hand, when the main CPU 101 determines in S390 that the value of the loop counter is “0” (in the case where S390 is YES), the main CPU 101 converts the serial communication sum value to the second interface serial line (second interface). 2 serial communication circuit 115: SCU2) (S391). After the process of S391, the main CPU 101 ends the second interface board output process, and moves the process to S376 of the second interface board control process (see FIG. 86).

[Retrieve priority storage processing]
Next, with reference to FIG. 88 and FIG. 89, the drawing priority order storing process performed in S212 in the main flow (see FIG. 74) will be described. FIG. 88 is a flowchart showing a procedure of the pull-in priority storage process. FIG. 89 is a diagram showing an example of a source program for executing the later-described processing of S625 and S626 during the pull-in priority storage process.

  First, the main CPU 101 sets “3” as the number of search reels (S621). Next, the main CPU 101 performs a pull-in priority table selection process (S622). In this process, a pull-in priority table (not shown) is selected based on the internal winning combination and the operation stop button.

  Next, the main CPU 101 performs a pull-in priority storage area selection process (S623). In this process, the pull-in priority data storage area of the search target reel is selected. Next, the main CPU 101 sets “20” as the number of symbol checks (number of times) (S624).

  Next, the main CPU 101 performs symbol code acquisition processing (S625). In this process, a symbol code is acquired with reference to a winning action flag storage region and a symbol code storage region corresponding to the number of symbol checks. Details of the symbol code acquisition process will be described later with reference to FIG. 90 described later.

  Next, the main CPU 101 performs a logical product operation process (S626). In this processing, the main CPU 101 performs winning operation flag data generation processing. Details of the AND operation processing will be described later with reference to FIG. 92 described later.

  Next, the main CPU 101 performs a drawing priority order acquisition process (S627). In this process, the main CPU 101 sets the bit to “1” in the winning action flag (display combination) storage area (see FIG. 25), and sets the bit to “1” in the winning request flag storage area. With respect to the winning combination, the drawing priority order data is acquired with reference to the drawing priority table (not shown). The details of the pull-in priority acquisition process will be described later with reference to FIGS. 93 and 94 described later.

  Next, the main CPU 101 stores the acquired pull-in priority data in a pull-in priority data storage area (not shown) in the main RAM 103 (S628). At this time, the pull-in priority data is stored in the pull-in priority data storage area so that each priority value corresponds to a bit in the storage area.

  The pull-in priority data storage area is provided with a priority data storage area for each main reel type. Each drawing priority data storage area stores drawing priority data determined according to the symbol positions “0” to “19” of the corresponding main reel. In the present embodiment, by referring to this pull-in priority data storage area, it is searched whether there is a more appropriate number of sliding symbols in addition to the number of sliding symbols determined based on the stop table.

  The contents of the priority pull-in data stored in the pull-in priority data storage area differ depending on the type of the pull-in priority table number in the pull-in priority table referenced when determining the pull-in priority data. The pull-in priority data indicates that the higher the value, the higher the priority. By referring to the pull-in priority data, it is possible to relatively evaluate the priority among the symbols arranged on the peripheral surface of the main reel. That is, the symbol for which the largest value is determined as the pull-in priority data becomes the symbol with the highest priority. Therefore, it can be said that the pull-in priority data indicates the rank between the symbols arranged on the peripheral surface of the main reel. When there are a plurality of symbols having the same value of the pull-in priority data, one symbol is determined according to the priority order defined by the priority order table.

  Next, the main CPU 101 performs an update process of the pull-in priority storage area (S629). In this process, the main CPU 101 sets a pull-in priority data storage area for the next check symbol. Next, the main CPU 101 subtracts 1 from the number of symbol checks (S630). Next, the main CPU 101 determines whether or not the number of symbol checks is “0” (S631).

  In S631, when the main CPU 101 determines that the number of symbol checks is not “0” (when S631 is NO), the main CPU 101 returns the process to the process of S625, and repeats the processes after S625. On the other hand, when the main CPU 101 determines in S631 that the number of symbol checks is “0” (when S631 is YES), the main CPU 101 performs a search target reel changing process (S632).

  Next, the main CPU 101 subtracts 1 from the number of search reels (S633). Next, the main CPU 101 determines whether or not the number of search reels is “0”, that is, whether or not the above-described series of processing has been performed on all main reels (S634).

  In S634, when the main CPU 101 determines that the number of search reels is not “0” (when S634 is NO), the main CPU 101 returns the process to the process of S622 and repeats the processes after S622. On the other hand, when the main CPU 101 determines in S634 that the number of search reels is “0” (in the case where S634 is YES), the main CPU 101 terminates the pull-in priority storage process, and the process proceeds to the main flow (FIG. 74).

  In the present embodiment, the pull-in priority storage process is performed as described above. The processing of S625 and S626 during the above-described pull-in priority storage process is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  Among them, the logical product calculation process of S626 is performed by the main CPU 101 executing the source code “CALLF SB_DAND_00” in FIG. The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_DAND_00” in FIG. 89 is executed, the process is performed at the address specified by “SB_DAND_00”. The jump is performed, and the logical product operation process is started.

[Design code acquisition processing]
Next, with reference to FIG. 90 and FIG. 91, the symbol code acquisition process performed in S625 in the pull-in priority storage process (see FIG. 88) will be described. FIG. 90 is a flowchart showing a procedure of symbol code acquisition processing, and FIG. 91 is a diagram showing an example of a source program for executing symbol code acquisition processing.

  First, the main CPU 101 performs clear processing of the winning operation flag storage area (S641). In this process, the main CPU 101 sets “0” in all the storage areas in the winning action flag storage area (see FIG. 25). Next, the main CPU 101 sets the first reel symbol arrangement table (see FIG. 14) (S642).

  Next, the main CPU 101 determines whether or not the first reel (left reel 3L) is stopped (S643).

  In S643, when the main CPU 101 determines that the first reel (left reel 3L) is stopped (when S643 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, when the main CPU 101 determines in S643 that it is not when the first reel (left reel 3L) is stopped (when S643 is NO), the main CPU 101 displays the second reel symbol arrangement table (see FIG. 14). Set (S644). In this process, the first reel symbol arrangement table set in S642 is overwritten with the second reel symbol arrangement table.

  Next, the main CPU 101 determines whether or not the second reel (medium reel 3C) is stopped (S645).

  In S645, when the main CPU 101 determines that the second reel (medium reel 3C) is stopped (when S645 is YES), the main CPU 101 performs the process of S647 described later. On the other hand, when the main CPU 101 determines in S645 that it is not when the second reel (medium reel 3C) is stopped (when S645 is NO), the main CPU 101 displays the third reel symbol arrangement table (see FIG. 14). Set (S646). In this process, the second reel symbol arrangement table set in S644 is overwritten with the third reel symbol arrangement table.

  After the process of S646, or when S643 or S645 is YES, the main CPU 101 performs a symbol check process when the stop operation is performed on the reel to be stopped and corresponds to the symbol corresponding to the symbol acquired by the symbol check process. A winning action table (not shown) is acquired (S647). The symbol corresponding winning action table (not shown) stores data indicating a winning action flag (display combination) that can be stopped and displayed according to the stopped symbol. For example, when the first reel (left reel 3L) is stopped and the symbol located on the active line is “red BAR” during the stop operation (see FIGS. 17 to 21), “REP33, 95, 98 to 101” ”And“ NML89, 93 to 96, 108 to 112, 133 to 136 ”are acquired, the head address of the symbol corresponding winning action table is acquired.

  Next, the main CPU 101 sets a winning operation flag storage area (S648). Next, the main CPU 101 performs compressed data storage processing (S649). In this process, the main CPU 101 mainly performs a process of transferring (developing) winning winning action flag data stored in the symbol corresponding winning action table to a corresponding storage area in the winning action flag storage area.

  After the process of S649, the main CPU 101 sets the winning action flag storage area updated by the compressed data storing process, sets the symbol code storage area, and the data length of the winning action flag storage area (7 bytes in this embodiment). Is set (S650). After the process of S650, the main CPU 101 ends the symbol code acquisition process, and moves the process to S626 of the pull-in priority storage process (see FIG. 88).

  In the present embodiment, the symbol code acquisition process is performed as described above. The symbol code acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. Among these, the compressed data storage process of S649 is performed by the main CPU 101 executing the source code “CALLF SB_BTEP_00” in FIG.

  The “CALLF” instruction is a 2-byte instruction code dedicated to the main CPU 101 as described above. When the source code “CALLF SB_BTEP_00” in FIG. 91 is executed, processing is performed at the address specified by “SB_BTEP_00”. The jump is made to start the compressed data storage process. In this compressed data storing process, as described above, the winning action flag data (compressed data) stored in the symbol corresponding winning action flag table of each reel is expanded (copied) in the winning action flag storage area.

  In this embodiment, the compression / decompression processing of the data related to winning is performed according to the processing procedure described in S647 to S649 during the above-described symbol code acquisition processing, and the above-described instruction code dedicated to the main CPU 101 is included in the processing. By using this, it is possible to increase the efficiency of the data compression / decompression processing related to winning, and to effectively utilize the limited capacity of the main RAM 103.

  In the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address “SB_BTEP_00” specified by the “CALLF” instruction is executed in the symbol setting process (see S205 of FIG. 74). In the compressed data storage process (not shown), the jump destination address specified by the “CALLF” instruction is set to be the same. That is, in this embodiment, the source program for executing the compressed data storage process performed in the symbol code acquisition process is the same as the source program for executing the compressed data storage process performed in the symbol setting process. The processing source program is shared (modularized). Therefore, there is no need to provide a separate source program for storing compressed data, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[AND operation]
Next, with reference to FIG. 92, for example, the AND operation process performed in S626 in the pull-in priority storage process (see FIG. 88) will be described. FIG. 92 is a flowchart showing the procedure of the logical product operation process. The logical product calculation process shown in FIG. 92 is performed not only in S626 in the pull-in priority storage process (see FIG. 88) but also in S687 in the pull-in priority acquisition process (see FIGS. 93 and 94 described later). Is also executed.

  In the logical product operation process executed in S626 in the pull-in priority storage process (see FIG. 88), the two data subjected to the logical product operation are stored in the winning action flag set in S650 during the above-described symbol code acquisition process. Area data and symbol code storage area data. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “37” of the data length (37 bytes) set in S650 during the above-described symbol code acquisition process corresponds to the “number of logical products” described later.

  On the other hand, in the AND operation executed in S687 in the below-described pull-in priority acquisition process (see FIG. 93 and FIG. 94 described later), two data to be AND-operated are the hit (withdraw) request flag storage area. And data of a winning action flag storage area. The former data corresponds to “logical product destination data” described later, and the latter data corresponds to “logical product source data” described later. In this case, the number of bytes “4” of the data length (4 bytes) of the RT operation combination display flag described in FIG. 95B described later corresponds to the “number of logical products” described later. Note that the number of bytes “37”, which is the data length of the winning request flag storage area and the winning action flag storage area, may correspond to the “number of logical products” described later.

  First, the main CPU 101 acquires logical product source data (for example, data in a symbol code storage area) (S661). Next, the main CPU 101 performs a logical product operation on the logical product source data and the logical product destination data (for example, data in the winning operation flag storage area), and stores the calculation result as the logical product destination data (S662).

  Next, the main CPU 101 adds 1 to the address of the logical product data to be acquired (S663). Next, the main CPU 101 adds 1 to the address of the logical product destination data to be referred to (S664).

  Next, the main CPU 101 subtracts 1 from the number of logical products (S665). Next, the main CPU 101 determines whether or not the number of logical products is “0” (S666).

  In S666, when the main CPU 101 determines that the number of logical products is not “0” (when S666 is NO), the main CPU 101 returns the process to the process of S661 and repeats the processes after S661. On the other hand, in S666, when the main CPU 101 determines that the number of logical products is “0” (in the case where S666 is YES), the main CPU 101 ends the logical product operation processing and stores the processing, for example, the drawing priority order storage. The process proceeds to S627 in the process (see FIG. 88).

[Withdrawal priority acquisition processing]
Next, with reference to FIG. 93 to FIG. 95, a description will be given of the pull-in priority acquisition process performed in S627 in the pull-in priority storage process (see FIG. 88). FIG. 93 and FIG. 94 are flowcharts showing the procedure of the acquisition priority acquisition process. FIG. 95A is a diagram showing an example of a source program for executing the later-described processing of S680 to S683 during the pull-in priority acquisition process, and FIG. 95B shows the later-described processing of S686 during the pull-in priority acquiring process. It is a figure which shows an example of the source program for performing.

  First, the main CPU 101 determines whether or not the right reel 3R (specific display column) is being checked (S671).

  In S671, when the main CPU 101 determines that it is not at the time of checking the right reel 3R (when S671 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, when the main CPU 101 determines in S671 that the right reel 3R is being checked (when S671 is YES), the main CPU 101 determines “ANY combination” as the symbol combination (winning combination) related to the internal winning combination. It is determined whether or not (predetermined symbol combination) is included (S672). Here, the “ANY combination” means a combination in which a winning is determined regardless of at least the stop symbol of the right reel 3R (a winning combination in which at least the stop symbol of the right reel 3R is an arbitrary symbol). In the present embodiment, the “ANY role” is not provided.

  In S672, when the main CPU 101 determines that “ANY combination” is not included in the symbol combination related to the internal winning combination (when S672 is NO), the main CPU 101 performs the process of S674 described later. On the other hand, in S672, when the main CPU 101 determines that “ANY combination” is included in the symbol combination related to the internal winning combination (when S672 is YES), the main CPU 101 determines “ANY combination” in the winning action flag storage area. The storage area corresponding to “comb” is masked (S673). Specifically, the main CPU 101 sets “1” to a bit corresponding to “ANY combination” in the winning action flag storage area.

  After the processing of S673, or when S671 or S672 is NO, the main CPU 101 adds “1” to the address of the last storage area as the address of the winning action flag storage area (see FIG. 25). Is set, stop prohibition data is set, and a winning action flag data length (data length of the winning action flag storage area: 7 bytes in this embodiment) is set (S674). Next, the main CPU 101 acquires the value of the stock button operation counter and the stop button operation state (S675). The stop button operation counter is a counter for managing the number of stop buttons for which a stop operation has been detected. Further, the stop button operation state is acquired by referring to the operation stop button storage area (see FIG. 28).

  Next, the main CPU 101 subtracts 1 (-1 update) the address of the set winning operation flag storage area (S676). Next, the main CPU 101 generates winning request flag data from the set winning operation flag storage area and the corresponding winning request flag storage area (see FIG. 25), and based on the generated winning request flag data A prohibited winning action position is generated (S677).

  Next, the main CPU 101 determines whether or not the stop operation position is a prohibited winning action position (S678).

  In S678, when the main CPU 101 determines that the stop operation position is not the prohibited winning action position (when S678 is NO), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S678 that the stop operation position is the prohibited winning operation position (when S678 is YES), the main CPU 101 has the value of the stop button operation counter being the value of the third stop. Whether or not (S679).

  In S679, when the main CPU 101 determines that the value of the stop button operation counter is the value of the third stop (when S679 is YES), the main CPU 101 performs a process of S705 described later. On the other hand, when the main CPU 101 determines in S679 that the value of the stop button operation counter is not the value of the third stop (when S679 is NO), the main CPU 101 determines that the value of the stop button operation counter is the second stop. Whether it is a value or not is discriminated (S680).

  In S680, when the main CPU 101 determines that the value of the stop button operation counter is not the second stop value (when S680 is NO), the main CPU 101 performs the process of S684 described later. On the other hand, when the main CPU 101 determines in S680 that the value of the stop button operation counter is the second stop value (when S680 is YES), the main CPU 101 determines whether or not the right reel 3R has stopped. Is discriminated (S681).

  When the main CPU 101 determines in S681 that the right reel 3R has been stopped (when S681 is YES), the main CPU 101 performs a process of S684 described later. On the other hand, when the main CPU 101 determines in S681 that the right reel 3R has not been stopped (NO in S681), the main CPU 101 determines that the hit request flag may be subject to interference “ANY role”. Or not (whether or not “ANY combination” is included in the symbol combination (winning combination) related to the internal winning combination) (S682).

  In S682, when the main CPU 101 determines that the hit request flag is not a flag that may receive the “ANY role” interference (YES in S682), the main CPU 101 performs the process of S684 described later. On the other hand, in S682, when the main CPU 101 determines that the hit request flag is a flag that may be subject to interference of “ANY role” (when S682 is NO), the main CPU 101 determines that the current check is “ANY”. It is determined whether or not it is at the time of checking the hit request flag including “combination” (S683).

  In S683, when the main CPU 101 determines that the current check is a check of the hit request flag including “ANY role” (when S683 is YES), the main CPU 101 performs a process of S705 described later.

  On the other hand, when the main CPU 101 determines in S683 that the current check is not at the time of checking the hit request flag including “ANY role” (when S683 is NO), S678 or S680 is NO, or S681. Alternatively, when S682 is YES, the main CPU 101 subtracts 1 from the winning operation flag data length (S684). Next, the main CPU 101 determines whether or not the winning action flag data length is “0” (S685).

  In S685, when the main CPU 101 determines that the winning action flag data length is not “0” (when S685 is NO), the main CPU 101 returns the process to the process of S676 and repeats the processes after S676.

  On the other hand, when the main CPU 101 determines in S685 that the winning action flag data length is “0” (when S685 is YES), the main CPU 101 performs a stop control pull-in request flag setting process (S686). . This process is performed by the main CPU 101 sequentially executing each process defined by the source program in FIG. 95B. Therefore, in this process, the AND operation process described with reference to FIG. 92 is performed. In the logical product calculation process executed in the process of S686, as described above, the data in the winning (withdrawal) request flag storage area is set to “logical product destination data”, and the data in the winning action flag storage area is In the “logical product source data”, the number of bytes “4” of the data length (4 bytes) of the RT operation combination display flag is set in the “logical product number”. The RT action combination display flag is a storage area in which a symbol combination related to RT transition is defined in the winning action flag storage area. In this embodiment, as shown in FIGS. 17 to 21, the storage areas 1 to 4 are stored. It becomes only. As described above, the number of bytes “37” that is the data length (37 bytes) of the winning request flag storage area and the winning action flag storage area may be set in the “logical product count”.

  Next, the main CPU 101 refers to a pull-in priority table address storage area (not shown) and obtains a pull-in priority table (not shown) (S687).

  Next, the main CPU 101 determines whether or not the data in the pull-in priority table stored at the currently set address is an end code (000H) (S688).

  In S688, when the main CPU 101 determines that the data in the pull-in priority order table stored at the currently set address is an end code (when S688 is YES), the main CPU 101 determines that S705 to be described later. Perform the process. On the other hand, when the main CPU 101 determines in S688 that the data in the drawing priority table stored at the currently set address is not an end code (when S688 is NO), the main CPU 101 A flag storage area is set (S689).

  Next, the main CPU 101 acquires pull-in priority data from the pull-in priority table based on the currently set address (S690). Next, the main CPU 101 sets a block counter in the pull-in priority table (S691). In this embodiment, in this process, the main CPU 101 sets “2” to the value of the block counter in the pull-in priority table.

  Next, the main CPU 101 sets the number of checks in the pull-in priority table, and adds 1 (+1 update) to the address of the pull-in priority table to be referred to (S692). In the present embodiment, in this process, the main CPU 101 sets “8” as an example to the number of checks in the pull-in priority table. Note that the number of checks in the pull-in priority table can be arbitrarily set in accordance with the number of bits of check data defined in the pull-in priority table.

  Next, the main CPU 101 acquires check data based on the updated address of the drawing priority table, and extracts a check bit from the check data (S693).

  Next, the main CPU 101 determines whether or not the value of the extracted check bit is “1” (S694).

  In S694, when the main CPU 101 determines that the value of the extracted check bit is not “1” (when S694 is NO), the main CPU 101 performs the process of S699 described later. On the other hand, when the main CPU 101 determines in S694 that the value of the extracted check bit is “1” (when S694 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced. (+1 update), and based on the updated address, determination data is acquired from the pull-in priority table (S695).

  Next, the main CPU 101 determines based on the determination data acquired in S695 whether or not the currently acquired winning action flag data is a determination target (S696). In this process, the main CPU 101 compares the currently acquired winning action flag data with the determination data, determines whether or not the former corresponds to the latter, and the former corresponds to the latter. In this case, it is determined that the currently acquired winning action flag data is a determination target.

  In S696, when the main CPU 101 determines that the winning action flag data is not a determination target (when S696 is NO), the main CPU 101 performs a process of S699 described later. On the other hand, when the main CPU 101 determines in S696 that the winning operation flag data is the determination target (when S696 is YES), the main CPU 101 performs the update processing of the drawing priority data (S697). In this process, the main CPU 101 updates (overwrites) the currently set pull-in priority data with the pull-in priority data associated with the determination data acquired in S697.

  Next, the main CPU 101 performs check data update processing (S698). In this process, the main CPU 101 shifts the check data rightward by 1 bit (in the direction from bit 7 to bit 0). In this process, “0” is set in bit 7 of the check data after the shift.

  After the processing of S698, or when S694 or S696 is NO, the main CPU 101 determines whether or not there is a bit to be checked (bit in which “1” is set) in the check data (S699).

  In S699, when the main CPU 101 determines that there is no check target bit in the check data (when S699 is NO), the main CPU 101 performs a process of S702 described later. On the other hand, when the main CPU 101 determines in S699 that there is a bit to be checked in the check data (when S699 is YES), the main CPU 101 adds 1 to the address of the winning action flag storage area to be checked (+1 update) And 1 is subtracted from the number of checks (S700).

  Next, the main CPU 101 determines whether or not the number of checks is “0” (S701). In S701, when the main CPU 101 determines that the number of checks is not “0” (when S701 is NO), the main CPU 101 returns the process to the process of S698 and repeats the processes after S698.

  On the other hand, when the main CPU 101 determines in S701 that the number of checks is “0” (in the case where S701 is YES), the main CPU 101 sets the number of checks in the address of the winning action flag storage area that is currently referenced. The initial value “8” is added to update the address of the winning action flag storage area, and the block counter value is decremented by 1 (S702). Next, the main CPU 101 determines whether or not the value of the block counter is “0” (S703).

  In S703, when the main CPU 101 determines that the value of the block counter is not “0” (when S703 is NO), the main CPU 101 returns the process to the process of S692 and repeats the processes after S692.

  On the other hand, in S703, when the main CPU 101 determines that the value of the block counter is “0” (when S703 is YES), the main CPU 101 adds 1 to the address of the pull-in priority table to be referenced (+1 update). (S704). After the process of S704, the main CPU 101 returns the process to the process of S688, and repeats the processes after S688.

  Here, returning to the processing of S679, S683, or S688 again, if S679, S683, or S688 is YES, the main CPU 101 uses the pulling order data set at this time as the final pulling priority data. Set (S705). If S679 or S683 is YES, the main CPU 101 sets “0 (00H)” as final pull-in priority data. In this case, since the end code is assigned to the pull-in priority data “0 (00H)”, no pull-in data (stop prohibition) is set. After the process of S705, the main CPU 101 ends the pull-in priority order acquisition process, and moves the process to S628 in the pull-in priority order storing process (see FIG. 88).

  In the present embodiment, the pull-in priority acquisition process is performed as described above. Note that the “ANY role” pull-in priority handling process of S680 to S683 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 95A. Is called. Among them, for example, the determination process of S683 is executed by a “JCP” instruction (predetermined determination instruction) on the source program. The “JCP” instruction is an instruction for executing an operation equivalent to a comparison instruction, and is a dedicated instruction code for the main CPU 101.

  For example, when the source code “JCP cc, A, n, e” is executed on the source program, the contents (stored data) of the A register are compared with the integer n, and the comparison result is the condition of cc. Then, the process is jumped to the address designated by e. In the “cc condition” of the “JCP” instruction, one of a carry flag state and a zero flag state in the flag register F is designated (see FIG. 11). For example, if “C” is specified for cc, the condition of cc means that the carry flag is “1” (ON state), and if “NC” is specified for cc, the condition of cc Means that the carry flag is “0” (off state). For example, if “Z” is specified for cc, the condition of cc means that the zero flag is “1” (ON state), and if “NZ” is specified for cc, The condition means that the zero flag is “0” (off state).

  When the “JCP” instruction is used on the source program for the pull-in priority handling process for “ANY role”, as shown in FIG. 95A, the instruction relating to address setting can be omitted (the instruction relating to address setting is separately provided). Therefore, the processing efficiency of the “ANY role” pull-in priority handling process can be increased, and the capacity of the source program (the capacity of the main ROM 102) can be reduced.

  In addition, the stop control pull-in request flag setting process of S686 during the pull-in priority acquisition process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 95B. In the stop control pull-in request flag setting process of S686, as shown in FIG. 95B, an “LDQ” instruction for specifying an address using the Q register (extension register), which is a dedicated instruction code for the main CPU 101, and “CALLF” Instructions are used.

  Therefore, by using the “LDQ” instruction using the Q register (extension register) in the stop request pull-in request flag setting process in S686, the main ROM 102, the main RAM 103, and the memory map I / O are accessed by direct values. can do. In this case, an instruction relating to address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced. The “CALLF” instruction is a 2-byte instruction code as described above. Therefore, by using these instruction codes dedicated to the main CPU 101 in the stop control pull-in request flag setting process, the processing efficiency can be improved, and the limited capacity of the main RAM 103 can be effectively utilized. .

  Furthermore, in the present embodiment, in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process, the address “SB_DAND_00” of the logical product operation process of the jump destination specified by the “CALLF” instruction is shown in FIG. This is the same as the jump destination address specified by the “CALLF” instruction in the logical product operation processing of S626 during the pull-in priority storage processing described in (see FIG. 89). That is, in the present embodiment, the source program for executing the AND operation performed in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process is the logic performed in S626 during the pull-in priority storage process. It is the same as the source program for executing the product operation process, and the source program for the AND operation process is shared (modularized) in both processes of S686 and S626. In this case, since it is not necessary to separately provide a source program for the logical product operation process in both the processes of S686 and S626, the capacity of the source program (the capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  As described above, in the various processes during the priority pull-in order acquisition process of the present embodiment, the above-described various instruction codes dedicated to the main CPU 101 are used as appropriate, realizing the efficiency of the corresponding process and the reduction in the capacity of the source program. doing. As a result, in this embodiment, the efficiency of the program processing of the main control circuit 90 and the reduction of the capacity can be achieved, and it is possible to improve the gameability by utilizing the free space corresponding to the reduced capacity. It becomes.

[Reel stop control process]
Next, the reel stop control process performed in S213 in the main flow (see FIG. 74) will be described with reference to FIGS. FIG. 96 is a flowchart showing the procedure of the reel stop control process. FIG. 97 is a diagram illustrating an example of a source program for executing the later-described processing of S711 to S716 during the reel stop control processing, and FIG. 98 executes the later-described processing of S726 during the reel stop control processing. It is a figure which shows an example of the source program for this.

  First, the main CPU 101 performs a reel stop possible signal OFF process (S711). In this process, the main CPU 101 mainly performs a port output process of the reel stop possible signal OFF data. Further, this process is performed using an unspecified work area in the main RAM 103. Details of the reel stop enable signal OFF processing will be described later with reference to FIG. 99 described later.

  Next, the main CPU 101 determines whether or not the rotation speeds of all the reels have reached a predetermined constant speed (whether or not it has become “constant speed”) (S712). In S712, when the main CPU 101 determines that the rotation speeds of all the reels are not “constant speed” (when S712 is NO), the main CPU 101 repeats the process of S712.

  On the other hand, when the main CPU 101 determines in S712 that the rotation speeds of all the reels have become “constant speed” (when S712 is YES), the main CPU 101 performs a reel stop enable signal ON process (S713). In this processing, the main CPU 101 mainly performs port output processing of the reel stop enable signal ON data. Further, this process is performed using an unspecified work area in the main RAM 103. Details of the reel stop enable signal ON process will be described later with reference to FIG.

  Next, the main CPU 101 determines whether or not a valid stop button has been pressed (S714).

  When the main CPU 101 determines in S714 that a valid stop button has not been pressed (in the case where S714 is NO), the main CPU 101 returns the process to the process of S713 and repeats the processes after S713. On the other hand, when the main CPU 101 determines in S714 that a valid stop button has been pressed (in the case where S714 is YES), the main CPU 101 updates the operation stop button storage area (see FIG. 28), and the stop button has not yet been pressed. The value of the operation counter is decremented by 1 (S715).

  Next, the main CPU 101 determines a search target reel from the operation stop button (S716). In addition, in this process, an address (start address) setting process of the spinning control data storage area in which the reel control management information of the search target reel is stored is also performed (source code “LDQ IX, wR1_CTRL− (wR2_CTRL in FIG. 97). -WR1_CTRL) ").

  Next, the main CPU 101 performs a reel stop possible signal OFF process (S717). This process is performed using an unspecified work area of the main RAM 103, as in S711. Details of the reel stop enable signal OFF processing will be described later with reference to FIG. 99 described later. Next, the main CPU 101 stores the stop start position in the main RAM 103 based on the value of the symbol counter (S718).

  Next, the main CPU 101 performs reel stop selection processing (S719). Although a detailed description is omitted, in this process, the main CPU 101 performs the number of sliding pieces selection process.

  Next, the main CPU 101 determines a planned stop position based on the stop start position and the number of sliding pieces determined in S719, and stores the determined planned stop position in the main RAM 103 (S720). In this process, the main CPU 101 adds the number of sliding frames to the stop start position, and sets the addition result as the planned stop position.

  Next, the main CPU 101 executes symbol code storage processing (S721). In this process, the symbol code corresponding to the scheduled stop position is stored in the symbol code storage area. Next, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel (S722). In this process, the main CPU 101 determines whether or not the reel to be controlled is the final stop (third stop) reel based on the value of the stop button non-operating counter. When it is “0”, it is determined that the reel to be controlled is the final stop reel.

  In S722, when the main CPU 101 determines that the reel to be controlled is not the final stop reel (when S722 is NO), the main CPU 101 performs a control change process (S723). In this process, the stop information group used for stopping the reel is updated when the stop position is at a specific stop position. Next, the main CPU 101 performs the pull-in priority storage process described with reference to FIG. 88 (S724).

  Next, the main CPU 101 performs standby interval remaining time standby processing (S725). In this process, the main CPU 101 performs a standby process until a predetermined reel stop interval time has elapsed. After the process of S725, the main CPU 101 returns the process to the process of S711, and repeats the processes after S711.

  Here, the process returns to S722 again, and when the main CPU 101 determines in S722 that the reel to be controlled is the final stop reel (when S722 is YES), the main CPU 101 energizes all reels. It is determined whether or not is in a stopped state (S726). In S726, when the main CPU 101 determines that the excitation of all the reels is not stopped (when S726 is NO), the main CPU 101 repeats the process of S726.

  On the other hand, when the main CPU 101 determines in S726 that the excitation of all the reels is in a stopped state (when S726 is YES), the main CPU 101 remains in the on state in which the stop button operated for the third stop is on. It is determined whether or not (the stop button has not been released) (S727). In S727, when the main CPU 101 determines that the stop button subjected to the third stop operation remains on (when S727 is YES), the main CPU 101 repeats the process of S727. On the other hand, when the main CPU 101 determines in S727 that the stop button for which the third stop operation has been performed is not in the on state (when S727 is NO), the main CPU 101 ends the reel stop control process and performs the process. The process proceeds to S214 in the main flow (see FIG. 74).

  In the present embodiment, the reel stop control process is performed as described above. Note that the processing of S711 to S716 during the reel stop control processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 97, in the source program of the reel stop control process of the present embodiment, for example, an “LDQ” instruction for specifying an address using a Q register (extension register), which is an instruction code dedicated to the main CPU 101, The “CALLF” instruction is used.

  Therefore, by using such an instruction code dedicated to the main CPU 101 in the reel stop control process, it is possible to reduce the capacity of the source program for the reel control process and improve the processing efficiency of the reel stop control process. it can. That is, in the present embodiment, it is possible to increase the efficiency of the program processing speed and reduce the capacity in the main control circuit 90, and to utilize the free space of the main ROM 102 increased according to the reduced capacity, Can be increased.

  Further, the determination process of S726 during the reel stop control process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. As shown in FIG. 98, this processing is executed using “LDQ” instruction and “ORQ” instruction (predetermined OR operation instruction) on the source code.

  The “ORQ” instruction is an instruction code for performing an OR operation, and is a dedicated instruction code for the main CPU 101 for performing address designation using a Q register (extension register). For example, when the source code “ORQ (k)” is executed on the source program, the data stored in the Q register (upper address value) and 1-byte integer k (direct value: lower address value) are used. A logical OR operation is performed on the contents (stored data) of the memory at the specified address and the contents (stored data) of the A register, and the calculation result is stored in the A register.

  Therefore, in the determination process of S726 during the reel stop control process, first, when the source code “LDQ A, (.LOW.wR1_TIM)” in FIG. 98 is executed, the data stored in the Q register and the integer value “ . LOW.wR1_TIM ”is loaded into the A register at the address specified by“ LOW.wR1_TIM ”. In the present embodiment, the address of the area storing the excitation timer value of the first reel in the main RAM 103 is “F032h”. In the determination processing of S726 described above, the upper address value “F0h” of the address “wR1_TIM (F032h)” is set in advance in the Q register when the LDQ instruction is executed, and the lower value is set to the value of k (direct value). The address value (“.LOW.wR2_TIM” = 32h) is substituted.

  Next, when the source code “ORQ (.LOW.wR2_TIM)” in FIG. 98 is executed, the address “wR2_TIM () of the storage data (F0h) of the Q register and the excitation timer value of the second reel are stored. F03Dh) ”is obtained by performing an OR operation between the memory contents (excitation timer value of the second reel) at the address specified by the lower address value (3Dh) and the contents of the A register (excitation timer value of the first reel). The calculation result (combination result of the excitation timer value of the first reel and the excitation timer value of the second reel) is stored in the A register. Next, when the source code “ORQ (.LOW.wR3_TIM)” in FIG. 98 is executed, the address “wR3_TIM () of the storage data (F0h) in the Q register and the excitation timer value of the third reel are stored. F048h) ”lower address value (48h), the memory contents (third reel excitation timer value) and the A register contents (first reel excitation timer value and second reel excitation timer). OR operation with the value (combination result with the value) is performed, and the operation result (combination result of the excitation timer values of the first to third reels) is stored in the A register.

  As described above, in the present embodiment, various main CPU 101 dedicated instruction codes using the Q register (extension register) are used in the reel (rotating cylinder) stop state check process. Therefore, by using these dedicated instruction codes for the main CPU 101, it is possible to access the main ROM 102, the main RAM 103, and the memory map I / O by direct values, and omit instructions related to address setting on the source program. Accordingly, the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  As described above, in the various processes during the reel stop control process of the present embodiment, the above-described various instruction codes dedicated to the main CPU 101 are used as appropriate, thereby realizing the efficiency of the corresponding process and the reduction of the capacity of the source program. ing. As a result, in this embodiment, the efficiency of the program processing of the main control circuit 90 and the reduction of the capacity can be achieved, and it is possible to improve the gameability by utilizing the free space corresponding to the reduced capacity. It becomes.

[Reel stop enable signal OFF processing]
Next, with reference to FIG. 99, the reel stop enable signal OFF process performed in S711 or S717 during the reel stop control process (see FIG. 96) will be described. FIG. 99 is a flowchart showing the procedure of reel stop enable signal OFF processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S731). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S732).

  Next, the main CPU 101 saves the data set in all the registers (S733). Next, the main CPU 101 performs a reel stop enable signal OFF data setting process (S734).

  Next, the main CPU 101 performs non-standard port output processing (S735). In this process, the main CPU 101 generates and outputs OFF output data (output off mode data), which will be described later, based on the reel stop enable signal OFF data. This process is performed using an unspecified work area in the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG.

  Next, the main CPU 101 restores all register data saved in S733 (S736). Next, the main CPU 101 sets the address of the stack area saved in S731 in the stack pointer (SP) (S737).

  Then, after the process of S737, the main CPU 101 ends the reel stop possible signal OFF process. At this time, if the executed reel stop enable signal OFF process is the process of S711 during the reel stop control process (see FIG. 96), the main CPU 101 shifts the process to the process of S712 during the reel stop control process. On the other hand, when the executed reel stop enable signal OFF process is the process of S717 during the reel stop control process (see FIG. 96), the main CPU 101 shifts the process to the process of S718 during the reel stop control process.

[Reel stop enable signal ON process]
Next, with reference to FIG. 100, the reel stop possible signal ON process performed in S713 during the reel stop control process (see FIG. 96) will be described. FIG. 100 is a flowchart showing a procedure of reel stop enable signal ON processing.

  First, the main CPU 101 saves the address of the stack area (see FIG. 12C) of the main RAM 103 set in the stack pointer (SP) (S741). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S742).

  Next, the main CPU 101 saves the data set in all the registers (S743). Next, the main CPU 101 refers to the operation stop button storage area (see FIG. 28) and acquires the stop button state (S744). Next, the main CPU 101 performs a reel stop enable signal ON data setting process (S745).

  Next, the main CPU 101 performs non-standard port output processing (S746). In this process, the main CPU 101 generates and outputs ON output data (output on mode data), which will be described later, based on the reel stop enable signal ON data. This process is performed using an unspecified work area in the main RAM 103. Details of the non-standard port output processing will be described later with reference to FIG.

  Next, the main CPU 101 restores all register data saved in S743 (S747). Next, the main CPU 101 sets the address of the stack area saved in S741 to the stack pointer (SP) (S748). After the process of S748, the main CPU 101 ends the reel stop enable signal ON process, and moves the process to the process of S714 in the reel stop control process (see FIG. 96).

[Non-standard port output processing]
Next, referring to FIG. 101 and FIG. 102, the non-specified port output processing performed in S735 during the reel stop enable signal OFF process (see FIG. 99) and S746 during the reel stop enable signal ON process (see FIG. 100). explain. FIG. 101 is a flowchart showing a procedure of non-standard port output processing. FIG. 102 is a diagram showing an example of a source program for executing non-standard port output processing.

  First, the main CPU 101 determines whether or not the port output setting is the ON output mode (S751). In this process, the main CPU 101 determines that the port output setting is the ON output mode when the reel stop enable signal ON data is set, and when the reel stop enable signal OFF data is set. It is determined that the port output setting is not the ON output mode.

  In S751, when the main CPU 101 determines that the port output setting is the ON output mode (when S751 is YES), the main CPU 101 performs the process of S753 described later. On the other hand, when the main CPU 101 determines in S751 that the port output setting is not in the ON output mode (when S751 is NO), the main CPU 101 performs processing for generating OFF output data (output off mode data) (S752). ). In this process, among the ports (bits) that are currently in the output on state, the ports (bits) that are to be turned off are turned off, and the ports (bits) that are currently in the output off state are turned off. OFF output data for maintaining the state is generated.

  After the processing of S752 or when S751 is NO, the main CPU 101 performs processing for generating ON output data (output on mode data) (S753). In this process, among the ports (bits) that are currently in the output off state, the ports (bits) that are to be turned on are turned on, and the ports (bits) that are currently in the output on state are turned on. ON output data for maintaining the state is generated. Next, the main CPU 101 outputs the generated output data from the designated port (S754).

  Then, after the processing of S754, the main CPU 101 ends the non-standard port output processing. At this time, if the executed non-regulated port output process is the process of S735 during the reel stop enable signal OFF process (see FIG. 99), the main CPU 101 executes the process of S736 during the reel stop enable signal OFF process. Move to. On the other hand, if the executed non-regulated port output process is the process of S746 during the reel stop enable signal ON process (see FIG. 100), the main CPU 101 shifts the process to the process of S747 during the reel stop enable signal ON process. Move.

  In the present embodiment, the non-specified port output process is performed as described above. The unspecified port output processing described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  Among them, the OFF output data generation process of S752 during the non-regulated port output process described above executes the source codes “XOR (HL)” and “AND (HL)” in FIG. 102 in this order. Done. The generation processing of the ON output data in S753 during the non-standard port output processing described above is performed by executing the source code “OR (HL)” in FIG.

  By performing such output data generation processing on the source program, the OFF output data generated in S752 even if the ON output data generation processing in S753 is performed after the OFF output data generation processing in S752. Does not change.

  For example, the port output setting is the OFF output mode, the output data indicating the non-standard port to be turned off in this processing is “000111011” (“1” is the bit to be turned off), and the non-standard port is currently set. When the output data (backup data) output to is “01010011” (“1” is currently an on-state bit), the data of bit 0, bit 1 and bit 5 of the backup data is changed from “1” to “1”. OFF output data for generating “0” is generated. In this case, first, when the source code “XOR (HL)” in FIG. 102 is executed, an exclusive OR operation is performed on the output data “00010111” and the backup data “01010011”. 01000100 "is obtained. Next, when the source code “AND (HL)” in FIG. 102 is executed, a logical product operation of the operation result “01000100” and the backup data “01010011” is performed, and the operation result “01000000” is set as OFF output data. Generated.

  After that, when the ON output data generation process of S753 (source code “OR (HL)” in FIG. 102) is executed, the calculation result “01000000” (OFF output data) is turned on in this process. An OR operation is performed on the output data “00000000” indicating the non-standard port to be set (the port output setting is the OFF output mode, so each bit of the output data is set to “0”). “01000000” is obtained, and the OFF output data does not change. Qualitatively, when the port output setting is the OFF output mode, the output for maintaining the port (bit) that is in the output ON state in the OFF output data in the ON output data generation processing in S753 is maintained in the ON state. Since the data is generated, the OFF output data generated in S752 does not change even if the ON output data generation processing in S753 is performed after the OFF output data generation processing in S752.

[Winning Search Process]
Next, with reference to FIGS. 103 and 104, the winning search process performed in S214 in the main flow (see FIG. 74) will be described. FIG. 103 is a flowchart showing the winning search processing procedure. FIG. 104 is a diagram showing an example of a source program for executing the winning search process.

  First, the main CPU 101 transfers and stores the data of each storage area stored in the symbol code storage area (see FIG. 30) to the corresponding storage area of the winning action flag storage area (see FIG. 25) (S761). . At the end of this process, the last address of the winning operation flag storage area is set in the DE register.

  Next, the main CPU 101 sets the address of the payout number data table (not shown) in the HL register (S762). Next, the main CPU 101 sets the number of payout number tables as the initial value of the winning search counter, and sets the initial value in the B register (S763).

  Next, the main CPU 101, based on the address set in the HL register, data of the number of medals to be paid out (in this embodiment, any one of 14, 13, 9, 7, 3, and 1). Is set in the C register, the determination target data is set in the A register, and "2" is added (+2 update) to the address set in the HL register (S764).

  Next, the main CPU 101 extracts the value of the determination bit from the medal payout number data set in the C register (S765). This determination bit is information indicating whether or not it is a determination target block for winning search. Next, the main CPU 101 determines whether the block is a determination target block based on the extracted determination bit value (S766). In this process, the main CPU 101 determines that the block is a determination target block when the value of the extracted determination bit is “1”.

  In S766, when the main CPU 101 determines that the block is not a determination target block (when S766 is NO), the main CPU 101 performs a process of S768 described later. On the other hand, when the main CPU 101 determines in S766 that the block is a determination target block (when S766 is YES), the main CPU 101 subtracts 1 from the address of the winning action flag storage area set in the DE register (- 1 update) (S767).

  After the process of S767 or when S766 is NO, the main CPU 101 extracts the data in the storage area specified by the address of the winning action flag storage area set in the DE register as the determination data (S768).

  Next, the main CPU 101 determines whether or not the determination result is a win based on the determination target data set in the A register in S764 and the determination data extracted in S768 (S769). In this process, if the determination target data set in the A register in S764 is the same as the determination data extracted in S768, the main CPU 101 determines that the determination result is a win.

  In S769, when the main CPU 101 determines that the result of the determination is not a win (when S769 is NO), the main CPU 101 performs a process of S776 described later. On the other hand, when the main CPU 101 determines in S769 that the result of the determination is a win (when S769 is YES), the main CPU 101 determines that the current game is three games (the number of medals bet is three). ) Is determined (S770).

  In S770, when the main CPU 101 determines that the current game is a three-game game (when S770 is YES), the main CPU 101 performs the process of S772 described later. On the other hand, when the main CPU 101 determines in S770 that the current game is not a three-game (when S770 is NO), the main CPU 101 pays out a two-game (a game with two medal bets). The number of sheets (2 sheets) is set in the C register (S771). In the present embodiment, the number of games that can be started is three, so the processing of S770 is always YES.

  After the processing of S771 or when S770 is YES, the main CPU 101 performs payout number update processing (S772). Specifically, the main CPU 101 adds the payout number of medals set in the C register to the current value of the winning number counter, and sets the value after the addition as the payout number.

  Next, the main CPU 101 determines whether or not the value of the payout number is less than the maximum payout number “10” (S773).

  In S773, when the main CPU 101 determines that the value of the payout number is less than the maximum payout number “10” (when S773 is YES), the main CPU 101 performs a process of S775 described later. On the other hand, when the main CPU 101 determines in S773 that the value of the payout number is not less than the maximum payout number “10” (when S773 is NO), the main CPU 101 sets the maximum payout number “10” as the payout number. (S774).

  After the processing of S774 or if S773 is YES, the main CPU 101 stores the payout number in the winning number counter (S775).

  After the processing of S775 or when S769 is NO, the main CPU 101 determines whether or not there is another winning (S776). When the main CPU 101 determines that there is another winning in S776 (when S776 is YES), the main CPU 101 returns the process to the process of S769 and repeats the processes after S769.

  On the other hand, when the main CPU 101 determines in S776 that there are no other winnings (when S776 is NO), the main CPU 101 subtracts 1 from the winning search counter (-1 update) (S777). Note that, when there is one active line as in the present embodiment, a plurality of small roles will not be won in duplicate, so the process of S776 is always NO.

  Next, the main CPU 101 determines whether or not the value of the winning search counter is “0” (S778).

  In S778, when the main CPU 101 determines that the value of the winning search counter is not “0” (when S778 is NO), the main CPU 101 returns the process to the process of S764 and repeats the processes after S764. On the other hand, when the main CPU 101 determines in S778 that the value of the winning search counter is “0” (in the case where S778 is YES), the main CPU 101 ends the winning search process, and the process proceeds to the main flow (FIG. 74), the process proceeds to S215.

  In the present embodiment, the winning search process is performed as described above. The winning search process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. Among these, the payout number and determination target data setting processing in S764 is performed by the main CPU 101 executing the source code “LDIN AC, (HL)”.

  For example, when the source code “LDIN ss, (HL)” is executed on the source program, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( Data) is loaded into the ss (BC, DE, AC, AE or BD) pair register, and the address set in the HL register is updated by +2 (added by 2). Therefore, when the source code “LDIN AC, (HL)” in FIG. 104 is executed, the contents of the memory specified by the address set in the HL register (pair register) and the address obtained by adding 1 to the address ( The payout number and determination target data) are loaded into the AC register, and the address set in the HL register is updated by +2 (added by 2). In the process of S764, in accordance with the “LDIN” instruction, the payout number data is stored in the A register, the determination target data is stored in the C register, and the address set in the HL register is updated by +2.

  As described above, in the winning search process of the present embodiment, both the data load process and the address update process can be performed by one “LDIN” instruction. In this case, an instruction relating to address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  In addition, the medal counter value acquisition process referred to in the determination process of S770 during the above-described winning search process, the winning sheet counter value acquisition process referred to in the process of S772, and the winning number counter executed in the process of S775. As shown in FIG. 104, all the storage (update) processes are executed by an “LDQ” instruction (instruction code dedicated to the main CPU 101) that performs addressing using the Q register (extended register). Therefore, in the winning search process of the present embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values by using the “LDQ” instruction. A command related to the setting can be omitted (there is no need to separately provide a command related to the address setting), and accordingly, the capacity of the source program (used capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

  Further, the determination process of S769 during the above-described winning search process is executed by a “JSLAA” instruction (predetermined determination instruction) on the source program as shown in FIG. The “JSLAA” instruction is an instruction for executing an operation equivalent to a left shift (SLA) instruction.

  For example, when the source code “JSLAA cc, e” is executed on the source program, if the condition of cc is satisfied, the process is jumped to the address specified by e. The “cc condition” defined by the “JSLAA” instruction specifies the state of the carry flag in the flag register F. For example, if “C” is specified for cc, the condition of cc means that the carry flag is “1” (ON state), and if “NC” is specified for cc, the condition of cc Means that the carry flag is “0” (off state). Therefore, in the source code “JSLAA NC, MN_CKLN — 06” in FIG. 104, if the carry flag is “0” (off state), the processing jumps to the address specified by “MN_CKLN — 06”.

  Further, the determination processing of S770 and S773 during the above-described winning search processing is executed by a “JCP” instruction on the source program as shown in FIG. As described above, the “JCP” instruction is an instruction for executing an operation corresponding to the comparison instruction, and is a dedicated instruction code for the main CPU 101.

  Therefore, when the above-described “JSLAA” instruction and “JCP” instruction are used in the source program for winning search processing, the instruction for address setting can be omitted (the instruction for address setting needs to be provided separately). Therefore, the capacity of the source program (capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[Illegal hit check processing]
Next, the illegal hit check process performed in S215 in the main flow (see FIG. 74) will be described with reference to FIGS. FIG. 105 is a flowchart showing the procedure of the illegal hit check process. FIG. 106 is a diagram showing an example of a source program for executing the illegal hit check process. The illegal hit is a lottery in the internal lottery process (see FIG. 84) and based on the internal winning combination stored in the winning request flag storage area in the symbol setting process, the left reel 3L, the middle reel 3C and the right reel 3R. Is a term indicating that a combination of symbols that cannot be established in (i.e., a combination of symbols that are not permitted to be stopped) is stopped on the active line (design combination is not established).

  First, the main CPU 101 sets the address of the winning action flag storage area (see FIG. 25) (S781). Next, the main CPU 101 sets the size (number of bytes, “37” in the present embodiment) of the winning action flag storage area to the value of the check counter (S782).

  Next, the main CPU 101, based on the address of the currently set winning action flag storage area, stores the internal winning combination stored in the storage area in the winning request flag storage area (internal winning combination storage area) corresponding to the address. (Hit request flag data) is acquired (S783). Next, the main CPU 101 synthesizes the winning combination data (winning operation flag data) stored at the address of the currently set winning operation flag storage area and the internal winning combination data (winning request flag data) ( S784).

  In this composition process, first, the main CPU 101 obtains an exclusive OR of the winning combination data (winning operation flag data) and the internal winning combination data (winning request flag data) (source program shown in FIG. 106). Source code "XOR (HL)"). Next, the main CPU 101 obtains a logical product of the obtained exclusive OR calculation result and winning combination data (winning operation flag data) (source code “AND (HL)” in the source program shown in FIG. 106). ), The calculation result of the logical product is taken as the synthesis result. If an illegal hit error has not occurred, the value of the synthesis result is “0”.

  Next, the main CPU 101 determines whether an illegal hit error has occurred based on the result of the synthesis process in S784 (S785).

  In S785, when the main CPU 101 determines that an illegal hit error has not occurred (when S785 is NO), the main CPU 101 updates the address of the winning action flag storage area to be referred to by +1 (S786). Next, the main CPU 101 subtracts 1 from the value of the check counter (S787). Next, the main CPU 101 determines whether or not the value of the check counter is “0” (S788).

  In S788, when the main CPU 101 determines that the value of the check counter is not “0” (when S788 is NO), the main CPU 101 returns the process to the process of S783 and repeats the processes after S783. On the other hand, in S788, when the main CPU 101 determines that the value of the check counter is “0” (when S788 is YES), the main CPU 101 ends the illegal hit check process, and the process proceeds to the main flow (FIG. 74)).

  Here, returning to the process of S785 again, when the main CPU 101 determines in S785 that an illegal hit error has occurred (in the case where S785 is YES), the main CPU 101 determines that the error processing described with reference to FIG. (S789). By this process, the two characters “EE” indicating the occurrence of the illegal hit error are displayed as error information on the 2-digit 7-segment LED (used for displaying the number of payouts and for error display) included in the information display 6. Error display data is output. The occurrence state (error state) of the illegal hit error is canceled by pressing the reset switch 76 (see FIG. 7).

  Next, the main CPU 101 clears the value of the winning number counter and the data in the winning request flag storage area (S790). After the process of S790, the main CPU 101 ends the illegal hit check process, and moves the process to the process of S216 in the main flow (see FIG. 74).

  In the present embodiment, the illegal hit check process is performed as described above. The illegal hit check process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

  In this embodiment, as shown in FIG. 25, the winning action flag storage area (display combination storage area) has the same configuration as that of the winning request flag storage area (internal winning combination storage area). The winning request flag storage area and the winning action flag storage area arranged in the main RAM 103 during the combination process of the combination of the storage area and the internal winning combination can be configured in the same configuration. Therefore, the calculation result of S784 in the illegal hit check process of the present embodiment (the result of combining the winning combination data and the internal winning combination data) is, as described above, the winning combination data and the internal It is obtained by simply ANDing (executing with an “AND” instruction) with the winning data. As a result, in this embodiment, the illegal hit check process can be streamlined and simplified, the free capacity of the main control program can be secured (increased), and the increased free capacity can be used to increase game play. It becomes possible to increase.

[Winning check / medal payout processing]
Next, with reference to FIG. 107 and FIG. 108, the winning check / medal payout process performed in S216 in the main flow (see FIG. 74) will be described. FIG. 107 is a flowchart showing the procedure of the winning check / medal payout process. FIG. 108 is a diagram showing an example of a source program for executing the processes of S804 to S808 described later during the winning check / medal payout process.

  First, the main CPU 101 performs a winning operation command generation process (S801). In this process, the main CPU 101 generates type data and various communication parameters included in the winning action command transmitted to the sub control circuit 200. The winning action command includes a parameter for specifying a winning action flag (display combination) and the like.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 64 (S802). With this processing, the winning operation command data is stored in the communication data storage area (see FIG. 67B) provided in the main RAM 103. The winning operation command is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in the interrupt processing described with reference to FIG.

  Next, the main CPU 101 determines whether or not the value of the winning number counter is “0” (S803). In S803, when the main CPU 101 determines that the value of the winning number counter is “0” (in the case of YES determination in S803), the main CPU 101 ends the winning check / medal payout process, and the process proceeds to the main flow ( The process proceeds to S217 in FIG.

  On the other hand, in S803, when the main CPU 101 determines that the value of the winning number counter is not “0” (NO in S803), the main CPU 101 determines that the number of credits (stored number) of medals is the upper limit number (the number of books). It is determined whether or not the number is 50 or more in the embodiment (S804).

  In S804, when the main CPU 101 determines that the number of credits of the medal is not equal to or greater than the upper limit (when S804 is NO), the main CPU 101 adds “1” to the value of the credit counter (+1 update) ( S805). The added credit counter value is displayed by a two-digit 7-segment LED (not shown) for displaying the number of stored sheets included in the information display 6. Next, the main CPU 101 performs a medal payout number check process (S806). Details of the medal payout number check process will be described later with reference to FIG. 109 described later.

  Next, the main CPU 101 determines whether or not the medals have been paid out (S807). When the main CPU 101 determines in S807 that the payout of medals has ended (when S807 is YES), the main CPU 101 ends the winning check / medal payout process, and the process is in the main flow (see FIG. 74) The process proceeds to S217.

  On the other hand, when the main CPU 101 determines in S807 that the payout of medals has not ended (when S807 is NO), the main CPU 101 performs payout interval waiting processing (S808). In this process, the main CPU 101 waits until a preset medal payout interval time (in this embodiment, 60.33 msec: 54 cycles of an interrupt process (1.1172 msec cycle) described in FIG. 113 described later). Wait. After the process of S808, the main CPU 101 returns the process to the process of S803 and repeats the processes after S803.

  Here, returning to the processing of S804 again, when the main CPU 101 determines in S804 that the number of credits of medals is equal to or greater than the upper limit number (50) (when S804 is YES), the main CPU 101 A medal payout process is performed (S809). Through this process, one medal is paid out. Then, after the processing of S809, the main CPU 101 ends the winning check / medal payout processing, and shifts the processing to S217 in the main flow (see FIG. 74).

  In the present embodiment, the winning check / medal payout process is performed as described above. Note that the processing of S804 to S808 during the above-described winning check / medal payout processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  In this embodiment, when the payout operation is continued after the credit counter is updated (+1), the main CPU 101 performs a wait (payout interval waiting) process for 60.33 ms in the process of S808. On the source program, the main CPU 101 executes the source codes “LD BC, cTM_PAYC” and “RST SB_W1BC_00” in this order. In this way, in the winning check / medal payout process, when the payout operation is continued after the credit counter is updated (+1), when waiting for 60.33 ms (waiting for payout interval) is performed, useless waiting time is reduced. Can reduce the mental burden of the player.

[Medal payout number check process]
Next, with reference to FIG. 109 and FIG. 110, the medal payout number check process performed in S806 during the winning check / medal payout process (see FIG. 107) will be described. FIG. 109 is a flowchart showing the procedure of the medal payout number check process. FIG. 110A is a diagram showing an example of a source program for executing the later-described processing of S811 to S814 during the medal payout number check process, and FIG. 110B shows later-described S816 and during the medal payout number check process. It is a figure which shows an example of the source program for performing the process of S817.

  First, the main CPU 101 adds “1” to the value of the medal OUT counter (+1 update) (S811). The medal OUT counter is a counter for counting the number of medals paid out. Next, the main CPU 101 adds “1” to the value of the payout number counter (+1 update) (S812). The payout number counter is a counter for counting the number of medals to be paid out.

  Next, the main CPU 101 performs a payout number 7 SEG display process (S813). In this process, the main CPU 101 performs a control process for displaying the value of the payout number counter by a 2-digit 7-segment LED (not shown) for displaying the payout number included in the information display 6.

  Next, the main CPU 101 performs update processing of the combination end number counter (S814). The consecutive end number counter is a counter for counting the remaining number of medals to be paid out corresponding to the winning combination. In this process, the main CPU 101 compares the value of the consecutive end number counter with its lower limit “0”, and when the value of the end of consecutive number counter is greater than the lower limit “0”, The counter value is decremented by 1 (-1 is updated), and when the value of the combination end number counter is equal to or lower than the lower limit “0”, the value of the combination end number counter is held at “0”.

  Next, the main CPU 101 subtracts 1 (updates -1) the value of the winning number counter (S815).

  Next, the main CPU 101 performs a credit information command generation process (S816). In this process, the main CPU 101 generates type data and various communication parameters included in the credit information command transmitted to the sub control circuit 200. The credit information command includes a parameter for specifying the number of medals for credit.

  Next, the main CPU 101 performs the communication data storage process described with reference to FIG. 64 (S817). By this processing, the credit information command data is stored in the communication data storage area (see FIG. 67B) provided in the main RAM 103. The credit information command is transmitted from the main control circuit 90 to the sub-control circuit 200 by communication data transmission processing in interrupt processing described later with reference to FIG. After the process of S817, the main CPU 101 ends the medal payout number check process, and shifts the process to the process of S807 in the winning check / medal payout process (see FIG. 107).

  In the present embodiment, the medal payout number check process is performed as described above. Note that the processing of S811 to S814 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 110A. Among them, the update processing of the combination end number counter in S814 is executed by the “DCPLD” command (predetermined update command) in FIG. 110A. The “DCPLD” instruction is an instruction code dedicated to the main CPU 101.

  For example, when the source code “DCPLD (HL), n” is executed on the source program, the contents (stored data) of the memory at the address specified by the HL register are compared with the integer n, and the contents of the memory are If it is larger than the integer n, 1 is subtracted from the contents of the memory, and if the memory content is less than or equal to the integer n, the integer n is stored in the memory at the address specified by the HL register. Therefore, when the source code “DCPLD (HL), 0” in FIG. 110A is executed, the contents of the memory at the address specified by the HL register (the value of the combination end number counter) and the integer 0 (lower limit) Are compared, and if the memory content (the value of the combination end number counter) is larger than the integer 0, the memory content is decremented by 1, and if the memory content is less than or equal to the integer 0, the memory content “0” is set to (the value of the counter end number counter). In other words, if the current value of the consecutive end number counter is greater than “0”, the update process of the consecutive end number counter is performed, and if the current end of number counter value is “0” or less. Then, a process of holding the value of the combination end number counter at “0” is performed.

  As described above, in the process of S814 during the medal payout number check process, the number of consecutively completed sheets is determined by one “DCPLD” command (a command that combines the lower limit determination command of the number management counter and the determination branch command). Both the counter update (subtraction) process and the process of holding the value of the consecutive end number counter at “0” can be executed. In this case, there is no need to provide an instruction code for executing both processes separately. For example, the determination branch instruction code for determining whether or not the value of the consecutive end number counter is “0” can be omitted. Therefore, in the medal payout number check process according to the present embodiment, the capacity of the source program (usage capacity of the main ROM 102) can be reduced, and a free capacity can be secured (increased) in the main ROM 102. It is possible to improve the playability by utilizing the free space.

  Also, the processing of S816 and S817 during the above-described medal payout number check processing is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 110B.

  Among them, in the process of S816, as shown in FIG. 110B, the communication parameter 1 of the credit information command is set to the value of the payout number counter via the L register, and the communication parameter 5 is credited via the C register. The counter value is set. However, values (undefined values) stored in the H register, E register, and D register at the present time are set in the other communication parameters 2 to 4 constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Bonus check processing]
Next, with reference to FIG. 111, the bonus check process performed in S217 in the main flow (see FIG. 74) will be described. FIG. 111 is a flowchart showing the procedure of bonus check processing.

  First, the main CPU 101 determines whether or not the current gaming state is the RB gaming state (S821). In S821, when the main CPU 101 determines that the current gaming state is not the RB gaming state (when S821 is NO), the main CPU 101 performs a process of S825 described later.

  On the other hand, when the main CPU 101 determines in S821 that the current gaming state is the RB gaming state (when S821 is YES), the main CPU 101 determines the number of winnings (winning number counter) and the number of games that can be played (playable The number counter) is updated (subtracted by 1) (S822). That is, in the RB gaming state, the main CPU 101 subtracts 1 from the winning number counter when a small role winning occurs, and subtracts 1 from the possible gaming number counter when a game is played. In the present embodiment, the initial values of these counters are “8”.

  Next, the main CPU 101 determines whether or not the number of wins (winning number counter) or the possible number of games (gameable number counter) is “0” (S823). That is, the main CPU 101 determines whether or not the RB gaming state end condition is satisfied. When the main CPU 101 determines in S823 that the number of winnings (winning number counter) or the possible number of games (gameable number counter) is not “0” (when S823 is NO), the main CPU 101 performs bonus check processing. The process ends, and the process proceeds to S218 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S823 that the number of winnings (winning number counter) or the possible number of games (gameable number counter) is “0” (when S823 is YES), the main CPU 101 determines that the RB Processing at the end is performed (S824). In this processing, the main CPU 101 turns off bit 0 of the gaming state flag storage area (see FIG. 27) (clears “0”), and turns off all the gaming state flag storage area (see FIG. 27) bits 3 to 7. (That is, the RT state is changed to the RT0 state). Then, after the process of S824, the bonus check process is terminated, and the process proceeds to the process of S218 in the main flow (see FIG. 74).

  In S821, when the main CPU 101 determines that the current gaming state is not the RB gaming state (when S821 is NO), the main CPU 101 determines whether or not the current gaming state is the MB gaming state ( S825). In S825, when the main CPU 101 determines that the current gaming state is not the MB gaming state (when S825 is NO), the main CPU 101 performs the process of S829 described later.

  On the other hand, when the main CPU 101 determines in S825 that the current gaming state is the MB gaming state (when S825 is YES), the main CPU 101 is in the bonus state (in the present embodiment, the MB gaming state). The number of medals paid out in the winning check / medal payout process is subtracted from the value of the bonus payout number counter for counting the number of medals that can be paid out (S826).

  Next, the main CPU 101 determines whether or not the value of the bonus bonus payout counter is less than “0” (S827). In S827, when the main CPU 101 determines that the value of the bonus payout number counter is not less than “0” (NO in S827), if the current gaming state is the MB gaming state, the CB gaming state (CB operation) The bonus check process is terminated, and the process proceeds to S218 in the main flow (see FIG. 74).

  On the other hand, when the main CPU 101 determines in S827 that the value of the bonus payout number counter is less than “0” (YES in S827), the main CPU 101 performs MB end processing (S828). In this process, the main CPU 101 turns off (“0” clear) bit 1 and bit 2 of the gaming state flag storage area (see FIG. 27). Then, after the process of S828, the bonus check process is terminated, and the process proceeds to the process of S218 in the main flow (see FIG. 74).

  In S825, when the main CPU 101 determines that the current gaming state is not the MB gaming state (when S825 is NO), the main CPU 101 determines whether or not RB has been established (S829). That is, the main CPU 101 determines whether or not an RB symbol combination (“C_RB” symbol combination) is displayed in the current game. When the main CPU 101 determines in step S829 that the RB has not been established (NO in step S829), the main CPU 101 performs processing in step S831 described later.

  On the other hand, when the main CPU 101 determines in step S829 that the RB has been established (in the case of YES determination in step S829), the main CPU 101 performs an RB start time process (S830). In this process, the main CPU 101 turns off bit 0 of the carryover combination storage area (see FIG. 26) (clears “0”) and turns on bit 0 of the gaming state flag storage area (see FIG. 27) (“1”). And “8” is set to the winning counter and the possible game counter. And after the process of S830, a bonus check process is complete | finished and a process is moved to the process of S218 in a main flow (refer FIG. 74).

  On the other hand, when the main CPU 101 determines in S829 that the RB has not been established (NO in S829), the main CPU 101 determines whether or not the MB has been established (S831). That is, the main CPU 101 determines whether or not an MB symbol combination (“C_MB_L”, “C_MB_S_1”, or “C_MB_S_2” symbol combination) is displayed in the current game. When the main CPU 101 determines in S831 that the MB has not been established (when S831 is NO), the main CPU 101 ends the bonus check process, and the process is the process of S218 in the main flow (see FIG. 74). Move to.

  On the other hand, when the main CPU 101 determines in S831 that the MB has been established (YES in S831), the main CPU 101 performs MB start time processing (S832). In this process, the main CPU 101 turns on bit 1 and bit 2 (stores “1”) in the game state flag storage area (see FIG. 27), and if “MB1” is established, the bonus payout counter Is set to “149”, and if “MB2” is established, “9” is set to the value of the bonus payout number counter. Then, after the process of S832, the bonus check process is terminated, and the process proceeds to the process of S218 in the main flow (see FIG. 74). Note that the value of the bonus payout number counter represents an example of the present embodiment, and this value can be set by varying as appropriate.

[RT check processing]
Next, the RT check process performed in S218 in the main flow (see FIG. 74) will be described with reference to FIG. FIG. 112 is a flowchart showing the procedure of the RT check process.

  First, the main CPU 101 determines whether or not the current gaming state is a bonus state (S841). That is, the main CPU 101 determines whether or not the current gaming state is the RB gaming state or the MB gaming state. In S841, when the main CPU 101 determines that the current gaming state is the bonus state (when S841 is YES), the main CPU 101 ends the RT check process and the process is in the main flow (see FIG. 74). The process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S841 that the current gaming state is not the bonus state (when S841 is NO), the main CPU 101 determines whether or not the RT state is the RT5 state (S842). . In S842, when the main CPU 101 determines that the RT state is the RT5 state (when S842 is YES), the main CPU 101 ends the RT check process, and the process proceeds to S219 in the main flow (see FIG. 74). Move on to processing.

  On the other hand, when the main CPU 101 determines that the RT state is not the RT5 state in S842 (when S842 is NO), the main CPU 101 determines whether or not the RB has been won (S843). That is, the main CPU 101 determines whether or not RB is determined as an internal winning combination in the current game. When the main CPU 101 determines in S843 that the RB has been won (when S843 is YES), the main CPU 101 sets the RT5 status flag to the on state (S844). By this process, when the RT state is another RT state, the RT state is shifted to the RT5 state. After the process of S844, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 74). As described above, for example, when RB is determined as an internal winning combination, the RT5 status flag is set in the internal lottery process (see S204 in FIG. 74) and the symbol setting process (see S205 in FIG. 74). A process of setting to the on state may be performed.

  On the other hand, when the main CPU 101 determines in S843 that the RB has not been won (when S843 is NO), the main CPU 101 determines whether or not the “RT1 transition symbol” has been established (S845). That is, the main CPU 101 determines whether or not any combination of symbols “HZR1” to “HZR28” is displayed on the active line. In S845, when the main CPU 101 determines that the “RT1 transition symbol” has been established (when S845 is YES), the main CPU 101 performs the process of S847 described later.

  On the other hand, when the main CPU 101 determines in S845 that the “RT1 transition symbol” has not been established (when S845 is NO), the main CPU 101 determines whether or not “RT1 transition lip” has been established ( S846). That is, the main CPU 101 determines whether or not any combination of symbols “REP9” to “REP33” is displayed on the active line. When the main CPU 101 determines in S846 that the “RT1 transition lip” has not been established (NO in S846), the main CPU 101 performs processing in S848 described later.

  When the main CPU 101 determines that the “RT1 transition symbol” is established in S845 (when S845 is YES), and when the main CPU 101 determines that the “RT1 transition lip” is established in S846 ( When S846 is YES, the main CPU 101 sets the RT1 state flag to the on state (S847). With this process, when the RT state is another RT state, the RT state is shifted to the RT1 state. After the process of S847, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 74).

  Here, the process returns to S846 again, and when S846 is NO, the main CPU 101 determines whether or not “RT2 transition lip” is established (S848). That is, the main CPU 101 determines whether or not any symbol combination among the symbol combinations “REP34” to “REP65” is displayed on the active line. In S848, when the main CPU 101 determines that the “RT2 transition lip” has not been established (NO in S848), the main CPU 101 performs the process of S850 described later.

  On the other hand, when the main CPU 101 determines in S848 that “RT2 transition lip” has been established (YES in S848), the main CPU 101 sets the RT2 status flag to the on state (S849). With this process, when the RT state is another RT state, the RT state is shifted to the RT2 state. After the process of S849, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 74).

  Here, returning to the processing of S848 again, if S848 is NO, the main CPU 101 determines whether or not “RT3 transition lip” has been established (S850). That is, the main CPU 101 determines whether or not one of the symbol combinations “REP66” to “REP73” is displayed on the active line. In S850, when the main CPU 101 determines that the “RT3 transition lip” has not been established (NO in S850), the main CPU 101 performs a process of S852 described later.

  On the other hand, when the main CPU 101 determines in S850 that “RT3 transition lip” has been established (YES in S850), the main CPU 101 sets the RT3 state flag to the on state (S851). By this process, when the RT state is another RT state, the RT state is shifted to the RT3 state. After the process of S851, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 74).

  Here, returning to the processing of S850 again, if S850 is NO, the main CPU 101 determines whether or not “RT4 transition lip” is established (S852). That is, the main CPU 101 determines whether or not the symbol combination “REP74” is displayed on the active line. In S852, when the main CPU 101 determines that “RT4 transition lip” has not been established (NO in S852), the main CPU 101 ends the RT check process, and the process is in the main flow (see FIG. 74). The process proceeds to S219.

  On the other hand, when the main CPU 101 determines in S852 that “RT4 transition lip” has been established (YES in S852), the main CPU 101 sets the RT4 status flag to the on state (S853). By this process, when the RT state is another RT state, the RT state is shifted to the RT4 state. After the process of S853, the main CPU 101 ends the RT check process, and moves the process to the process of S219 in the main flow (see FIG. 74).

[Interrupt processing under the control of the main CPU (1.1172 msec)]
Next, an interrupt process performed by the main CPU 101 at a cycle of 1.1172 msec will be described with reference to FIG. FIG. 113 is a flowchart showing the procedure of interrupt processing. 1. Interrupt processing repeatedly executed at a period of 1172 msec is generated based on the output timing of the time-out signal of the timer circuit 113 set in the initialization processing of the timer circuit 113 (PTC) (see S2 in FIG. 56). This is a process executed when an interrupt request signal from the interrupt controller 112 is input to the main CPU 101.

  First, the main CPU 101 performs a register saving process (S901). Next, the main CPU 101 performs input port check processing (S902). In this process, signals input from various switches such as a stop switch are checked.

  Next, the main CPU 101 performs a reel control process (S903). In this process, the main CPU 101 starts rotation of the left reel 3L, the middle reel 3C, and the right reel 3R when the start of rotation of all reels is requested, and thereafter, each reel rotates at a constant speed. Three stepping motors are driven and controlled. When the number of sliding symbols is determined, the main CPU 101 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 101 waits for the updated symbol counter to match the value corresponding to the planned stop position (the symbol at the planned stop position reaches the area on the effective line of the display window), and The corresponding stepping motor is driven and controlled so that the rotation is decelerated and stopped.

  Next, the main CPU 101 performs communication data transmission processing (S904). In this processing, various commands stored in the communication data storage area are mainly transmitted to the sub control circuit 200 via the first serial communication circuit 114 (see FIG. 9) of the main control circuit 90. After transmitting a command to the sub control circuit 200, the main CPU 101 subtracts and updates the communication data pointer by one packet (not shown), and clears the transmitted command data in the communication data storage area. If a plurality of command data is stored in the communication data storage area, the command data is transmitted to the sub-control circuit 200 in the oldest stored order. When no command data is stored in the communication data storage area, that is, when the value of the communication data pointer is “0”, a no-operation command is generated and transmitted to the sub-control circuit 200. Next, the main CPU 101 performs inserted medal passage check processing (S905). In this process, the main CPU 101 checks whether or not the inserted medal has passed through the selector 66 based on the detection result (medal sensor input state) of the medal sensor (not shown). Next, the main CPU 101 performs a WDT restart process (S906).

  Next, the main CPU 101 performs a 7-segment LED drive process (S907). In this process, the main CPU 101 drives and controls various 7-segment LEDs included in the information display 6 and displays, for example, the number of medals paid out, the number of credits, stop button pressing order data, and the like. Details of the 7-segment LED driving process will be described later with reference to FIG. 114 described later.

  Next, the main CPU 101 performs timer update processing (S908). In this processing, the main CPU 101 performs count (subtraction) processing for various timers that have been set. Details of the timer update process will be described later with reference to FIG. 119 described later.

  Next, the main CPU 101 performs error detection processing (S909). Next, the main CPU 101 performs a door open / close check process (S910). In the door open / close check process, the main CPU 101 checks the open / closed state of the front door 2b (see FIG. 2) by checking the on / off (door closed) / off (door open) state of the door open / close monitoring switch 67.

  Next, the main CPU 101 performs a test firing test signal control process (S911). In this processing, control processing is performed when various test signals are output to the testing machine via the second interface boat or the like. Further, this process is executed by using an unspecified work area (see FIG. 12C) of the main RAM 103. In the present embodiment, this process is also performed at times other than during the test firing test (after the pachislot 1 is installed in the amusement store). At this time, the main control board 71 is connected via the second interface boat or the like. Since it is not connected to a testing machine, various test signals are generated but not output. Details of the test test signal control process will be described later with reference to FIG. 121 described later.

  Next, the main CPU 101 performs a register restoration process (S912). Then, after the process of S912, the main CPU 101 ends the interrupt process.

[7-segment LED drive processing]
Next, with reference to FIGS. 114 and 115, the 7-segment LED driving process performed in S907 during the interrupt process (see FIG. 113) will be described. FIG. 114 is a flowchart showing the procedure of the 7-segment LED driving process. FIG. 115A is a diagram illustrating an example of a source program for executing the processes of S923 to S925 described later during the 7-segment LED driving process, and FIG. 115B illustrates a process of S931 described later during the 7-segment LED driving process. It is a figure which shows an example of the source program for performing the process of S936.

  First, the main CPU 101 adds “1” to the value of the interrupt counter (+1 update) (S921). Next, the main CPU 101 determines whether or not the value of the interrupt counter is an odd number (S922).

  In S922, when the main CPU 101 determines that the value of the interrupt counter is not an odd number (when S922 is NO), the main CPU 101 ends the 7-segment LED driving process, and the process is interrupted (see FIG. 113). ) In S908. That is, in this embodiment, the 7-segment LED driving process is performed every two interrupt cycles. In this embodiment, the example in which the 7-segment LED driving process is executed when the interrupt counter value is an even number has been described. However, the present invention is not limited to this, and the 7-segment LED drive process is performed when the interrupt counter value is an odd number. The LED driving process may be executed, or the execution timing of the 7-segment LED driving process may be determined using the quotient or the remainder when the value of the interrupt counter is divided by an arbitrary integer.

  On the other hand, when the main CPU 101 determines in S922 that the value of the interrupt counter is an odd number (when S922 is YES), the main CPU 101 acquires navigation data from the navigation data storage area (S923). Next, the main CPU 101 sets the address of the push order display data storage area for storing the push order display data output to each cathode of the 7-segment LED (S924).

  Next, the main CPU 101 performs 7-segment display data generation processing (S925). In this process, the main CPU 101 creates push order display data (7-segment display data) based on the navigation data, and stores the generated push order display data in the push order display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 116 described later.

  Next, the main CPU 101 acquires the value of the credit counter (S926). Next, the main CPU 101 sets an address of a credit display data storage area for storing credit display data output to each cathode of the 7-segment LED (S927).

  Next, the main CPU 101 performs a 7-segment display data generation process (S928). In this process, the main CPU 101 generates credit display data (7-segment display data) based on the value of the credit counter, and stores the generated credit display data in the credit display data storage area. The details of the 7-segment display data generation process will be described later with reference to FIG. 116 described later.

  Next, the main CPU 101 sets an address of a 7-segment common counter storage area for storing a value of a 7-segment common counter described later (S929). Next, the main CPU 101 adds “1” to the value of the 7-segment common counter (+1 update) (S930). In this process, when the updated 7-segment common counter value is “8”, the main CPU 101 sets the 7-segment common counter value to “0”. In the present embodiment, since the 7-segment LED is dynamically controlled, the value of the 7-segment common counter is updated every 8 cycles.

  Next, the main CPU 101 creates common selection data based on the value of the 7-segment common counter, and the address of the target cathode data storage area (the target storage area in the push order display data storage area or the credit display data storage area). Is set (S931). Next, the main CPU 101 outputs clear data to the cathode of the 7-segment LED (S932). This process is performed to turn off the 7-segment LED and eliminate the influence of afterimages.

  Next, the main CPU 101 acquires and sets 7-segment cathode output data from the target cathode data storage area (S933). Next, the main CPU 101 generates 7-segment common output data from the 7-segment common backup data and the common selection data (S934).

  Next, the main CPU 101 stores the 7-segment common output data and the 7-segment cathode output data in the 7-segment common backup data and the 7-segment cathode backup data, respectively (S935). Next, the main CPU 101 outputs 7-segment cathode output data and 7-segment common output data (S936). After the process of S936, the main CPU 101 ends the 7-segment LED drive process, and moves the process to the process of S908 in the interrupt process (see FIG. 113).

  In the present embodiment, the 7-segment LED driving process is performed as described above. Note that the processing of S923 to S925 during the 7-segment LED driving process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG. 115A. Further, the processing of S931 to S936 during the 7-segment LED driving process described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG. 115B.

  Among them, the output processing of each 7-segment output data in S936 is executed by one source code “LD (cPA_SEGCOM), BC” as shown in FIG. 115B. Therefore, in the 7-segment LED driving process of the present embodiment, 7-segment common output (selection) data and 7-segment cathode output data are output simultaneously when dynamic lighting control is performed on a 2-digit 7-segment LED. That is, in the 7-segment LED dynamic lighting control when carrying out the push order navigation on the instruction monitor, and in the 7-segment LED dynamic lighting control when displaying credit information with the 2-digit 7-segment LED, the 7-segment common output ( Selection) data and 7-segment cathode output data are output simultaneously.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Therefore, it becomes possible to improve game playability. In this embodiment, an example in which a 7-segment drive circuit (not shown) that performs 7-segment LED drive processing is configured by a cathode common circuit and controlled by the cathode has been described. However, the present invention is not limited to this, The segment drive circuit may be configured by an anode common circuit, and the 7-segment LED may be controlled by the anode.

  In addition, the navigation data acquisition process of S923 and the address setting process of the push display data storage area of S924 during the 7-segment LED driving process described above both use the Q register (extension register) as shown in FIG. 115A. This is executed by an “LDQ” instruction (instruction code dedicated to the main CPU 101) for specifying an address. Therefore, in the 7-segment LED driving process of this embodiment, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values by using the “LDQ” instruction. The command for address setting can be omitted (there is no need to separately provide the command for address setting), and accordingly, the capacity of the source program (capacity of the main ROM 102) can be reduced. As a result, in the present embodiment, it is possible to secure (increase) the free space in the main ROM 102, and it is possible to improve the gameability by utilizing the increased free space.

[7-segment display data generation processing]
Next, the 7-segment display data generation process performed in S925 and S928 in the 7-segment LED drive process (see FIG. 114) will be described with reference to FIGS. FIG. 116 is a flowchart showing the procedure of the 7-segment display data generation process. FIG. 117 is a diagram illustrating an example of a source program for executing the 7-segment display data generation process. FIG. 118 is a diagram showing an example of the configuration of a 7-segment cathode table that is actually referred to on the source program of the 7-segment display data generation process.

  Note that “display data”, which will be described later, generated in the 7-segment display data generation process performed in S925 in the 7-segment LED drive process (see FIG. 114) corresponds to the push order display data, and the 7-segment LED drive process (see FIG. 114), “display data” described later generated in the 7-segment display data generation process performed in S928 corresponds to the credit display data.

  First, the main CPU 101 divides the display data set in the cathode data storage area by “10”, obtains the quotient value of the division result as the display data of the upper digits of the 2-digit 7-segment LED, and divides the data. The remainder of the result is acquired as display data for the lower digits (S941). Next, the main CPU 101 determines whether or not to perform upper digit display based on the acquired upper digit display data (S942).

  In S942, when the main CPU 101 determines to display the upper digits (when S942 is YES), the main CPU 101 performs the process of S944 described later. On the other hand, when the main CPU 101 determines in S942 that the upper digit display is not performed (when S942 is NO), the main CPU 101 sets no upper digit display (S943).

  After the processing of S943 or when S942 is YES, the main CPU 101 refers to the 7-segment cathode table (see FIG. 118) and acquires the display data of the upper digits (S944). Next, the main CPU 101 stores the acquired upper digit display data in the upper digit display data storage area (not shown) (S945).

  Next, the main CPU 101 refers to the 7-segment cathode table (see FIG. 118) and acquires display data for the lower digits (S946). Next, the main CPU 101 stores the acquired lower-digit display data in a lower-digit display data storage area (not shown) (S947).

  After the process of S947, the main CPU 101 ends the 7-segment display data generation process. At this time, if the executed 7-segment display data generation process is the process of S925 during the 7-segment LED drive process (see FIG. 114), the main CPU 101 shifts the process to the process of S926 during the 7-segment LED drive process. Move. On the other hand, when the executed 7-segment display data generation process is the process of S928 during the 7-segment LED drive process (see FIG. 114), the main CPU 101 shifts the process to the process of S929 during the 7-segment LED drive process. .

  In the present embodiment, the 7-segment display data generation process is performed as described above. The 7-segment display data generation process described above is performed by the main CPU 101 sequentially executing each source code defined by the source program of FIG.

[Timer update processing]
Next, the timer update process performed in S908 during the interrupt process (see FIG. 113) will be described with reference to FIGS. FIG. 119 is a flowchart showing the procedure of timer update processing. FIG. 120 is a diagram illustrating an example of a source program for executing the processes of S951 to S954 described later during the timer update process.

  First, the main CPU 101 sets an update start address of a 2-byte timer storage area (not shown) in the HL register, and sets a 2-byte timer number in the B register (S951).

  Next, the main CPU 101 compares the number of 2-byte timers with the lower limit value “0”. When the number of 2-byte timers is greater than the lower limit value “0”, the main CPU 101 subtracts 1 from the 2-byte timer number (-1 update). If the 2-byte timer number is less than or equal to the lower limit “0”, the 2-byte timer number is held at “0” (S952). Further, in the process of S952, the main CPU 101 subtracts 2 (-2 update) the update start address of the 2-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (updates -1) the 2-byte timer number set in the B register (S953). Next, the main CPU 101 determines whether or not the number of 2-byte timers set in the B register is “0” (S954).

  In S954, when the main CPU 101 determines that the number of 2-byte timers set in the B register is not “0” (when S954 is NO), the main CPU 101 returns the process to the process of S952, and after S952 Repeat the process.

  On the other hand, when the main CPU 101 determines in S954 that the number of 2-byte timers set in the B register is “0” (when S954 is YES), the main CPU 101 stores the 1-byte timer storage area in the HL register. The update start address is set, and the 1-byte timer number is set in the B register (S955).

  Next, the main CPU 101 compares the number of 1-byte timers with the lower limit value “0”. When the number of 1-byte timers is larger than the lower limit value “0”, the main CPU 101 subtracts 1 (1 update) the number of 1-byte timers. If the number of 1-byte timers is less than or equal to the lower limit “0”, the number of 1-byte timers is held at “0” (S956). Further, in the process of S956, the main CPU 101 subtracts 1 (-1 update) the update start address of the 1-byte timer storage area set in the HL register.

  Next, the main CPU 101 subtracts 1 (-1 update) the number of 1-byte timers set in the B register (S957). Next, the main CPU 101 determines whether or not the number of 1-byte timers set in the B register is “0” (S958).

  In S958, when the main CPU 101 determines that the number of 1-byte timers set in the B register is not “0” (when S958 is NO), the main CPU 101 returns the process to the process of S956, and after S956 Repeat the process.

  On the other hand, when the main CPU 101 determines in S958 that the number of 1-byte timers set in the B register is “0” (when S958 is YES), the main CPU 101 performs electromagnetic counter control processing (S959). ). In this process, an output control process when a signal indicating IN / OUT of medals is output to the external concentration terminal board 47 is performed. After the process of S959, the main CPU 101 ends the timer update process and shifts the process to the process of S909 during the interrupt process (see FIG. 113).

  In the present embodiment, the timer update process is performed as described above. Note that the processing of S951 to S954 (2-byte timer update processing) during the timer update processing described above is performed by the main CPU 101 sequentially executing each source code defined in the source program of FIG.

  Among them, the process of S952 (2-byte timer update process) is executed by the “DCPWLD” instruction (predetermined update instruction) in FIG. The “DCPWLD” instruction is an instruction code dedicated to the main CPU 101.

  On the source program, for example, when the source code “DCPWLD (HL), n” is executed, the memory content (stored data) for 2 bytes from the address specified by the HL register is compared with the integer n, If the memory content for 2 bytes is larger than the integer n, 1 is subtracted from the memory content for 2 bytes. If the memory content for 2 bytes is less than or equal to the integer n, it is specified by the HL register. An integer n is stored in a 2-byte memory from the address.

  Therefore, in the source code “DCPWLD (HL), 0” in FIG. 120, the memory contents for 2 bytes (the number of 2-byte timers) and the integer “0” (lower limit value) from the address specified by the HL register When the contents of the memory for 2 bytes are larger than the integer “0”, the contents of the memory for 2 bytes are decremented by 1 and the contents of the memory for 2 bytes are less than the integer “0”. “0” is set in the memory contents of 2 bytes. That is, when the current 2-byte timer number is larger than “0”, the 2-byte timer update process is performed. When the current 2-byte timer number is “0” or less, the 2-byte timer number is “0”. Is held.

  As described above, in the timer update process of the present embodiment, both the update (subtraction) process of the timer number and the process of holding the timer number to “0” are executed by the “DCPWLD” instruction that is the instruction code dedicated to the main CPU 101. can do. In this case, there is no need to provide an instruction code for executing both processes separately. Also, the decision branch instruction code for determining whether or not the number of timers is “0” can be omitted. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Therefore, it becomes possible to improve game playability. In this embodiment, an example in which the “DCPWLD” instruction is used only in the update process of the 2-byte timer has been described. May be used.

[Trial test signal control processing (not specified)]
Next, with reference to FIG. 121, the test firing test signal control process performed in S911 during the interrupt process (see FIG. 113) will be described. FIG. 121 is a flowchart showing the procedure of the test test signal control process.

  First, the main CPU 101 saves the address of the stack area of the main RAM 103 (S961). Next, the main CPU 101 sets the address of the non-standard stack area in the stack pointer (SP) (S962). Next, the main CPU 101 saves data in all registers (S963).

  Next, the main CPU 101 performs a rotating brake signal generation process (S964). In this process, the main CPU 101 generates and outputs a rotation control signal (drive signal) for each reel that is output to the testing machine via the second interface boat or the like. The details of the rotation brake signal generation process will be described later with reference to FIG. 122 described later.

  Next, the main CPU 101 performs a special signal control process (S965). In this process, the main CPU 101 performs an output process of a bonus (special prize) ON / OFF signal (test signal) output to the testing machine. Details of the special signal control process will be described later with reference to FIG. 123 described later.

  Next, the main CPU 101 performs a conditional device signal control process (S966). In this process, the main CPU 101 performs a control signal output process corresponding to the state of the conditional device signal control flag. Details of the condition device signal control processing will be described later with reference to FIGS. 124 and 125 described later.

  Next, the main CPU 101 performs a process for restoring the data of all registers saved in the process of S963 (S967). Next, the main CPU 101 sets the address of the stack area saved in the process of S961 in the stack pointer (SP) (S968). Then, after the process of S968, the main CPU 101 ends the test firing test signal control process and shifts the process to the process of S912 in the interrupt process (see FIG. 113).

[Rotating brake signal generation processing]
Next, with reference to FIG. 122, a rotating drum braking signal generation process performed in S964 in the test fire test signal control process (see FIG. 121) will be described. FIG. 122 is a flowchart showing the procedure of the rotating drum brake signal generation process.

  First, the main CPU 101 sets a spinning cylinder control data storage area (not shown) in an unspecified work area (S971). Next, the main CPU 101 sets “3” as the number of reels, and clears the spinning cylinder control signal and its generation state (1 byte data) (S972).

  Next, the main CPU 101 determines whether or not the rotation control data is “less than stopped” data (S973). Note that the “less than stop” rotation control data here refers to rotation control data other than the rotation control data for stopping the reel, that is, rotation control data (acceleration for rotating the reel). Preparation, acceleration, waiting for constant speed, waiting for constant speed, and waiting for stop start position).

  In S973, when the main CPU 101 determines that the rotation control data is “less than stopped” data (when S973 is YES), the main CPU 101 performs the process of S975 described later. On the other hand, in S973, when the main CPU 101 determines that the rotation control data is not “less than stopped” data (when S973 is NO), the main CPU 101 determines that the rotation control data is “end of static hold control”. It is determined whether or not the data is “S” (S974). Note that the “rotation control data” of “end of static hold control” here is the rotation control data indicating the all-phase all-stop state of the reels.

  In S974, when the main CPU 101 determines that the spinning cylinder control data is “end of static hold control” (when S974 is YES), the main CPU 101 performs the process of S976 described later. On the other hand, in S974, when the main CPU 101 determines that the rotation control data is not “end of the static hold control” (when S974 is NO), or when S973 is YES, the main CPU 101 Bit 3 of the rotation control signal generation state (1-byte data) is turned on (“1”) (S975).

  After the process of S975 or when S974 is NO, the main CPU 101 shifts the data of each bit in the generated state by one bit to the right (in the direction from bit 7 to bit 0) (S976). Next, the main CPU 101 updates the address of the spinning cylinder control data storage area to the address of the next reel to be controlled (S977).

  Next, the main CPU 101 subtracts 1 from the number of reels (S978). Next, the main CPU 101 determines whether or not the number of reels is “0” (S979).

  In S979, when the main CPU 101 determines that the number of reels is not “0” (when S979 is NO), the main CPU 101 returns the process to the process of S973 and repeats the processes after S973.

  On the other hand, when the main CPU 101 determines in S979 that the number of reels is “0” (in the case where S979 is YES), the main CPU 101 sends the generated state data to the testing machine via the rotating brake signal output port. To the first interface board 301 (see FIG. 7) (S980). Then, after the processing of S980, the main CPU 101 ends the rotation brake signal generation processing, and shifts the processing to the processing of S965 in the test firing test signal control processing (see FIG. 121).

[Special signal control processing]
Next, with reference to FIG. 123, the special prize signal control process performed in S965 in the test fire test signal control process (see FIG. 121) will be described. FIG. 123 is a flowchart showing the procedure of the special signal control process.

  First, the main CPU 101 refers to the gaming state flag storage area (see FIG. 27) and acquires a gaming state flag (S991). Next, the main CPU 101 determines whether or not the gaming state is an RB gaming state (S992).

  In S992, when the main CPU 101 determines that the gaming state is the RB gaming state (when S992 is YES), the main CPU 101 sends an ON signal from the RB signal port for the test signal to the first interface for the testing machine. The data is output to the board 301 (see FIG. 7) (S993). On the other hand, when the main CPU 101 determines in S992 that the gaming state is not the RB gaming state (when S992 is NO), the main CPU 101 sends an OFF signal from the RB signal port for the test signal to the first for testing machine. The data is output to the interface board 301 (see FIG. 7) (S994).

  After the processing of S993 or S994, the main CPU 101 refers to the gaming state flag storage area (see FIG. 27) to determine whether or not the gaming state is the MB gaming state (S995).

  In S995, when the main CPU 101 determines that the gaming state is the MB gaming state (when S995 is YES), the main CPU 101 sends an ON signal from the MB signal port for the test signal to the first interface for the testing machine. The data is output to the board 301 (see FIG. 7) (S996). On the other hand, when the main CPU 101 determines in S995 that the gaming state is not the MB gaming state (when S995 is NO), the main CPU 101 sends an OFF signal from the MB signal port for the test signal to the first for testing machine. The data is output to the interface board 301 (see FIG. 7) (S997).

  Then, after the process of S996 or S997, the main CPU 101 ends the special prize signal control process, and shifts the process to the process of S966 in the trial test signal control process (see FIG. 121).

  In the present embodiment, the MB1 gaming state and the MB2 gaming state are provided as the MB gaming state. Here, the signal from the MB signal port may be output only when in the MB1 gaming state, or may be output both when in the MB1 gaming state and when in the MB2 gaming state. It may be.

[Condition device signal control processing]
Next, with reference to FIGS. 124 and 125, the condition device signal control process performed in S966 in the test firing test signal control process (see FIG. 121) will be described. 124 and 125 are flowcharts showing the procedure of the conditional device signal control process.

  First, the main CPU 101 determines whether or not the conditional device signal control flag is in the initial state (S1001). In S1001, when the main CPU 101 determines that the condition device signal control flag is in the initial state (when S1001 is YES), the main CPU 101 ends the condition device signal control process, and the process is a test firing test signal control process. The process proceeds to S967 in (see FIG. 121).

  On the other hand, when the main CPU 101 determines in S1001 that the condition device signal control flag is not in the initial state (when S1001 is NO), the main CPU 101 determines that the condition device signal control flag indicates that the re-game state identification signal is on. It is determined whether or not it is to be shown (S1002).

  In S1002, when the main CPU 101 determines that the conditional device signal control flag indicates the ON state of the re-playing state identification signal (when S1002 is YES), the main CPU 101 serves the conditional device signal control state. The on state of the object condition apparatus signal is set (S1003). Next, the main CPU 101 outputs information on the RT state from the condition device 1-6 signal port to the first interface board 301 for tester (see FIG. 7) (S1004). After the process of S1004, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 121).

  On the other hand, when the main CPU 101 determines in S1002 that the conditional device signal control flag does not indicate the ON state of the re-playing state identification signal (when S1002 is NO), the main CPU 101 determines that the conditional device signal control flag is It is determined whether or not the re-playing state identification signal indicates an off state (S1005).

  In S1005, when the main CPU 101 determines that the conditional device signal control flag indicates the off state of the re-playing state identification signal (when S1005 is YES), the main CPU 101 detects the conditional device 1-8 signal port. The OFF signal is output to the first interface board 301 for testing machine (see FIG. 7) (S1006). After the process of S1006, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 121).

  On the other hand, when the main CPU 101 determines in S1005 that the conditional device signal control flag does not indicate the off state of the re-gaming state identification signal (when S1005 is NO), the main CPU 101 indicates that the conditional device signal control state is It is determined whether or not the accessory condition device signal is in an ON state (S1007).

  In S1007, when the main CPU 101 determines that the condition device signal control state is the ON state of the accessory condition device signal (when S1007 is YES), the main CPU 101 receives the special prize winning from the condition devices 1 to 8 signal port. The number information is output to the first interface board 301 for tester (see FIG. 7), and at this time, the ON signal is output from the condition device 8 signal port to the first interface board 301 for tester (see FIG. 7) (see FIG. 7). S1008). Next, the main CPU 101 sets a predetermined waiting time (24.58 ms in this embodiment) to the conditional device signal output waiting timer (S1009). Next, the main CPU 101 sets the condition device signal output waiting state to the condition device signal control state (S1010). Then, after the process of S1010, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 121).

  On the other hand, when the main CPU 101 determines in S1007 that the condition device signal control state is not the ON state of the accessory condition device signal (when S1007 is NO), the main CPU 101 determines that the condition device signal control state is the condition device signal. It is determined whether or not the output is waiting (S1011).

  In S1011, when the main CPU 101 determines that the condition device signal control state is the condition device signal output waiting state (when S1011 is YES), the main CPU 101 sets the value of the condition device signal output waiting timer to “0”. Is determined (S1012).

  In S1012, when the main CPU 101 determines that the value of the conditional device signal output waiting timer is not “0” (when S1012 is NO), the main CPU 101 ends the conditional device signal control processing and performs the test test. The process proceeds to S967 in the signal control process (see FIG. 121). On the other hand, when the main CPU 101 determines in S1012 that the value of the conditional device signal output waiting timer is “0” (when S1012 is YES), the main CPU 101 enters the small device condition device in the conditional device signal control state. The signal on state or the condition device signal off state is set (S1013). After the process of S1013, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 121).

  Here, returning to the processing of S1011 again, in S1011, when the main CPU 101 determines that the condition device signal control state is not a condition device signal output waiting state (when S1011 is NO), the main CPU 101 It is determined whether or not the device signal control state is the ON state of the small role condition device signal (S1014).

  In S1014, when the main CPU 101 determines that the condition device signal control state is the ON state of the small role condition device signal (when S1014 is YES), the main CPU 101 starts the small role from the condition devices 1 to 8 signal port. Information of a winning number (for example, a winning number defined in advance as a winning number included in the winning number (see FIGS. 15 and 16)) is output to the first interface board 301 for testing machine (see FIG. 7). At this time, an ON signal is output from the condition device 7 signal port to the first interface board 301 for tester (see FIG. 7) (S1015). Next, a predetermined waiting time (24.58 ms in this embodiment) is set to the conditional device signal output waiting timer (S1016). Next, the main CPU 101 sets the condition device signal output waiting state to the condition device signal control state (S1017). Then, after the process of S1017, the main CPU 101 ends the condition device signal control process, and shifts the process to the process of S967 in the test firing test signal control process (see FIG. 121).

  On the other hand, when the main CPU 101 determines in S1014 that the condition device signal control state is not the ON state of the small role condition device signal (when S1014 is NO), the main CPU 101 turns OFF from the condition devices 1 to 8 signal port. The signal is outputted to the first interface board 301 for tester (see FIG. 7) (S1018). After the process of S1018, the main CPU 101 ends the condition device signal control process, and moves the process to the process of S967 in the test firing test signal control process (see FIG. 121).

<Description of operation of sub-control circuit>
Next, the contents of various processes executed by the sub CPU 201 of the sub control circuit 200 using a program will be described with reference to FIGS. 126 to 132.

[Sub CPU power-on processing]
First, with reference to FIG. 126, the power-on process of the sub CPU 201 will be described. FIG. 126 is a flowchart showing the procedure of power-on processing.

  First, when the power of the sub CPU 201 is turned on, a sub CPU initial setting process is executed (S1101). In this processing, for example, initialization processing of the sub CPU 201, initialization processing of connected devices (IC (Integrated Circuit), LSI (Large-scale Integration), etc.), initialization processing of the memory (DRAM), OS (Operating System) The initialization process is performed.

  Next, the sub CPU 201 issues an accessory control task activation request as a subtask activation request (S1102). The “act” here refers to an effect device that produces an effect by a physical operation. In the present embodiment, when the effect device is provided and an effect using the effect device can be executed, The operation of the rendering device is controlled by the accessory control task. For example, in the power-on process of the sub CPU, the accessory control task is executed when an accessory control task request is generated from the OS in response to an activation request for the accessory control task by the sub CPU 201.

  Next, the sub CPU 201 makes a startup request for the lamp control task described above (S1103). Next, the sub CPU 201 makes an activation request for the above-described sound control task (S1104).

  Next, the sub CPU 201 makes a request for starting the main board communication task described above (S1105). The main board communication task is executed, for example, when a main board communication task request is generated from the OS in response to an activation request for the main board communication task by the sub CPU 201 in the power-on process of the sub CPU. Details of the main board communication task will be described later with reference to FIG. 128 described later.

  Next, the sub CPU 201 makes a startup request for the animation task described above (S1106). The animation task is executed when, for example, an animation task request is generated from the OS in response to an animation task activation request from the sub CPU 201 in the power-on process of the sub CPU. In addition, the animation task is repeated at a cycle of 33 msec including the processing time in order to control the image display operation of the display device 11 (projector mechanism 211) and / or the sub display device 18, for example.

  Next, the sub CPU 201 performs backup recovery processing (S1107). In this process, the sub CPU 201 works on various game data (game state data, assigned ART period, number of RUSH stock, number of CZ stock, etc.) and various history data stored in SRAM (static RAM). Copy to DARM (dynamic RAM). By this processing, the content of the effect in the pachislot 1 can be returned to the state before the power interruption. Then, after the processing of S1107, the sub CPU 201 ends the power-on processing.

[Sub CPU power interruption processing]
Next, the power interruption interrupt processing of the sub CPU 201 will be described with reference to FIG. This process is, for example, an interrupt process that is executed when an abnormality such as a power interruption occurs. FIG. 127 is a flowchart showing the procedure of the power interruption interrupt process.

  When power interruption (reduction of power supply voltage) occurs, the sub CPU 201 performs backup creation processing (S1111). In this process, the sub CPU 201 copies various data to be held from the DRAM to the SRAM when power interruption is detected. That is, the sub CPU 201 performs a process opposite to the above-described backup recovery process (S1107 during the power-on process). With this processing, even if the data is destroyed, correct data is saved as backup data.

[Main board communication task]
Next, with reference to FIG. 128, the main board communication task executed by the sub CPU 201 will be described. FIG. 128 is a flowchart showing the procedure of the main board communication task.

  First, the sub CPU 201 performs reception check of the command transmitted from the main control circuit 90, and acquires command registration data (S1121). Next, the sub CPU 201 extracts the type of the received command (S1122). In this embodiment, command data is composed of 8-byte data, and the first byte of data indicates the type of command.

  Next, the sub CPU 201 determines whether or not the command type is a specified type (S1123).

  In this embodiment, the command type is associated with one of a plurality of predetermined codes, and when the game is operating normally, the command type is one of the codes within the regulations. Become. Therefore, in the process of S1123, if the type of the received command is one of the codes within the specification, the sub CPU 201 determines that the command type is valid (specified type). On the other hand, if the command type is an unspecified code, the sub CPU 201 determines that some abnormality (including an illegal act) has occurred during the game, and determines that the command type is invalid.

  In S1123, when the sub CPU 201 determines that the command type is not the specified type (when S1123 is NO), the sub CPU 201 returns the process to S1121 and repeats the processes after S1121. On the other hand, when the sub CPU 201 determines in S1123 that the command type is the specified type (when S1123 is YES), the sub CPU 201 stores the message in the message queue based on the received command ( S1124). The message queue is a mechanism for exchanging information between processes. Then, after the processing of S1124, the sub CPU 201 returns the processing to S1121, and repeats the processing after S1121.

  Although not shown, the sub CPU 201 extracts a message (that is, each received command) when a message (that is, information included in each parameter of the received command) is stored in the message queue. The information contained in the parameter is acquired), and processing (processing upon receiving various commands) according to the command type and the content of the command is executed. For example, the processes shown in FIGS. 129, 131, and 132, which will be described later, are examples of the command reception process.

[Sub-side navigation control processing]
Next, the sub-side navigation control process will be described with reference to FIG. FIG. 129 is a flowchart illustrating a procedure of sub-side navigation control processing.

  First, the sub CPU 201 determines whether or not navigation data has been acquired (S1131). The sub CPU 201 acquires navigation data determined by the main control board 71 from the start command data received from the main control board 71. Therefore, in the process of S1131, the sub CPU 201 determines whether navigation data is included in the received start command data.

  In the present embodiment, the determined navigation data is included in the start command data, but the navigation data transmission mode is not limited to this. For example, the main CPU 101 generates and stores specific state command data including at least navigation data only in a specific state where the navigation data needs to be transmitted (for example, a state in which the ART function is activated). It may be determined whether or not navigation data is included in the specific state command data.

  When the sub CPU 201 determines that the navigation data has been acquired in S1131 (when S1131 is YES), the sub CPU 201 sets the sub navigation data corresponding to the navigation data (S1132). For example, when the sub CPU 201 acquires the navigation data “4”, the navigation data for notifying the push order “left, middle, right” as the sub-side navigation data is set in this process. As a result, the contents of the stop operation can be notified on both the main side and the sub side. Then, after the process of S1132, the sub CPU 201 ends the sub-side navigation control process.

  On the other hand, when it is determined in S1131 that the sub CPU 201 has not acquired navigation data (NO in S1101), the sub CPU 201 determines whether navigation (notification of stop operation) is necessary. (S1133). When the sub CPU 201 determines that navigation is not necessary in S1133 (when S1133 is NO), the sub CPU 201 ends the sub-side navigation control process.

  On the other hand, when the sub CPU 201 determines that the navigation is necessary in S1133 (when S1133 is YES), the sub CPU 201 sets sub-side navigation data corresponding to various lottery results (S1134). For example, when the sub CPU 201 is in a state where the ART function is activated (the ART function may not be activated) and an internal winning combination that is not a push order is determined, In order to enhance the effect, it is possible to determine effect data for notifying the details of the stop operation on the sub side alone. Then, after the process of S1134, the sub CPU 201 ends the sub-side navigation control process.

[Player registration process]
Next, a player registration process will be described with reference to FIG. FIG. 130 is a flowchart showing the procedure of player registration processing.

  First, the sub CPU 201 determines whether or not a registration operation has been accepted (S1141). For example, when the operation of the registration button 222b is accepted on the menu screen 222 (see FIG. 5B) of the sub display device 18 and a predetermined operation is accepted on the registration screen (not shown) displayed in that case, the sub CPU 201 performs the registration operation. Is determined to have been accepted.

  When the sub CPU 201 determines in S1141 that the registration operation has been accepted (in the case where S1141 is YES), the sub CPU 201 sets a player registration state (S1142). In the situation where the player registration state is set, the sub CPU 201 sets the sub display device 18 so that the game information screens 223, 224, and 225 (see FIGS. 5C to 5E) can be displayed on the sub display device 18. Control the display screen. Then, after the process of S1142, the sub CPU 201 ends the player registration process.

  On the other hand, when it is determined in S1141 that the sub CPU 201 has not accepted a registration operation (when S1141 is NO), the sub CPU 201 determines whether or not a registration deletion operation has been accepted (S1143). For example, when a specific operation is accepted on the registration screen of the sub display device 18, the sub CPU 201 determines that a registration deletion operation has been accepted.

  When the sub CPU 201 determines in S1143 that the registration deletion operation has not been accepted (NO in S1113), the sub CPU 201 ends the player registration process.

  On the other hand, when it is determined in S1143 that the sub CPU 201 has accepted the registration deletion operation (YES in S1143), the sub CPU 201 clears the player registration state (S1144). In the situation where the player registration state is cleared, the sub CPU 201 causes the sub display device 18 so that the game information screens 223, 224, and 225 (see FIGS. 5C to 5E) cannot be displayed on the sub display device 18. Control the display screen. Then, after the process of S1144, the sub CPU 201 ends the player registration process.

[History management processing]
Next, the history management process will be described with reference to FIG. FIG. 131 is a flowchart showing the procedure of history management processing.

  First, the sub CPU 201 acquires a game result from various command data received from the main control board 71 (S1151). For example, in this process, the sub CPU 201 can grasp the type of the combination determined as the internal winning combination from the start command data. Further, for example, in this process, the sub CPU 201 can grasp the symbol combination displayed from the winning action command data (that is, whether or not a winning combination is determined as an internal winning combination). Further, for example, in this process, the sub CPU 201 can grasp the current gaming state and the transition state of the gaming state from the start command data or the like.

  Next, the sub CPU 201 performs a game history update process based on the acquired game result (S1152). By this processing, the sub CPU 201 can manage various game histories such as the number of games (number of games), the number of bonuses, and the number of ARTs (see FIG. 5) based on the game results acquired from various command data. it can. Then, after the processing of S1152, the sub CPU 201 ends the history management processing.

[Production control processing]
Next, the effect control process will be described with reference to FIG. FIG. 132 is a flowchart showing the procedure of the effect control process.

  First, the sub CPU 201 acquires information on each parameter from the received command and updates the game information (S1161). For example, the sub CPU 201 compares information on the current gaming state with information on the gaming state before one game, and stores the gaming information indicating that there is a change in the gaming state. Further, for example, the sub CPU 201 compares information on the current control state with information on the control state before one game, and if there is a change in the control state, stores the game information to that effect. Further, for example, the sub CPU 201 compares information on the current mode (for example, normal mode or specific mode) with information on the mode one game before, and stores the game information to that effect if there is a change in the mode.

  Next, the sub CPU 201 determines whether or not it is an effect determination timing based on the updated game information (S1162). That is, for example, the sub CPU 201 determines whether or not it is time to perform lottery (or determination) related to the effect control described with reference to FIGS. In S1162, when the sub CPU 201 determines that it is the effect determination timing (when S1162 is YES), the sub CPU 201 performs an effect determination process (S1163). In this process, the sub CPU 201 performs various types of lottery (or determination) relating to the above-described effect control, and registers effect data according to the result. Then, after the process of S1163, the sub CPU 201 ends the effect control process.

  On the other hand, when the sub CPU 201 determines in S1162 that it is not the effect determination timing (when S1162 is NO), the sub CPU 201 determines whether or not it is the effect execution timing based on the registered effect data. (S1164). In S1164, when the sub CPU 201 determines that it is the performance execution timing (when S1164 is YES), the sub CPU 201 performs an effect execution process (S1165). In this process, the sub CPU 201 controls the execution of effects by various effect devices according to the registered effect data (that is, the determined effect). Then, after the process of S1165, the sub CPU 201 ends the effect control process. In addition, when the sub CPU 201 determines in S1164 that it is not the effect execution timing (when S1164 is NO), the sub CPU 201 ends the effect control process.

  So far, the gaming machine according to the present embodiment has been described. And from this embodiment, the technical idea (namely, invention which concerns on this embodiment) as shown at least below can be grasped | ascertained as an example. However, these technical ideas are not limited to those described in the present embodiment, and various changes and modifications can be made. Further, a plurality of technical ideas (a part thereof, that is, including a part of the configuration of the invention according to the present embodiment) can be combined into another technical idea, or a certain technical idea A part of the idea can be used as another technical idea. In addition, a technical idea that is subordinately described in a certain technical idea may be an independent technical idea, or may be subordinated in another technical idea.

  In this embodiment, a pachislot machine has been described as an example of a gaming machine, but this is not intended to limit the invention according to this embodiment. For example, all the inventions according to the present embodiment, except for the case described in the present embodiment, which has a pachislot-specific configuration such as a configuration related to reel control when a stop operation is performed or a configuration related to setting change and confirmation, It can also be applied to a game machine called “pachinko”. For example, checksum generation and determination processing, various processing using an instruction code dedicated to the main CPU 101 (address designation processing using a Q register, soft timer update processing, 7 segment LED drive processing, communication data generation and storage processing, etc. ), Features such as various processes using the non-standard ROM area and non-standard RAM area are also suitable for the pachinko machine.

  That is, the invention according to the present embodiment performs an internal lottery (determination of whether or not to win) based on the fact that a predetermined variation start condition is satisfied (for example, the game ball has passed through the starting region) Variable display is started (identification information is variably displayed), and variable display is stopped (identification information is stopped and displayed) when a predetermined variation end condition is satisfied (for example, the variation time has ended). A pachinko that can be shifted to a special game state (winning game state) based on a predetermined display result being derived, a pachinko that includes game control means for controlling the progress of these games, and an effect display An effect display means for controlling the effect display means, and an effect display control means for controlling the effect display means. The effect display means performs variable display and stop display of decorative symbols according to variable display, and other effect tables. It can be applied to a pachinko to perform.

  Similarly, a slot machine that uses a game ball as a game medium, an enclosed game machine that encloses the game medium and electronically adds game value, and a management frame that can be used and managed by multiple manufacturers in common. The invention can also be applied to other gaming machines such as a gaming machine called a management-type gaming machine in which a gaming board can be mounted in the management frame.

  Further, for example, the various counters and various timers managed by the control of the main CPU 101 or the sub CPU 201 shown in the present embodiment can be managed in a range not departing from the gist of the invention according to the present embodiment. It can be changed as appropriate. For example, various counters and various timers managed by “addition” may be managed by “subtraction”, and various counters and various timers managed by “subtraction” may be “addition”. It is good also as managed by. In this case, for example, the determination of whether or not “to be greater than or equal to” is read as the determination of whether or not it is “less than or equal to”, and the determination of whether or not “exceeds” is “less than” It is assumed that the determination of whether or not the value has become a predetermined value is read as the determination of whether or not the value is “0”.

  Further, for example, various data such as various counters, various flags, and various timers managed by the control of the main CPU 101 shown in the present embodiment are within the scope not departing from the gist of the invention according to the present embodiment. The various data managed by the control of the sub CPU 201 may be managed by the control of the main CPU 101 without departing from the gist of the invention according to the present embodiment. It is good.

  In addition, for example, the internal states such as various gaming states and various control states managed by the control of the main CPU 101 shown in the present embodiment are within the scope of the invention according to the present embodiment. The state relating to various effects managed by the control of the sub CPU 201 may be managed by the control of the main CPU 101 without departing from the gist of the invention according to the present embodiment. It is good as well.

[Gameability in RUSH state]
In the pachi-slot 1 of the present embodiment, a notification period is given (for example, a guarantee notification period and an additional notification period are given) by a plurality of different triggers, and a right related to a game period in an advantageous state (eg, an ART state). In a specific state (for example, a RUSH state) that can be granted, the right is granted in response to a specific notification being made during the notification period. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the pachislot machine 1 of the present embodiment, in a specific state (for example, a special RUSH state) to which a right related to a game period in an advantageous state (for example, an ART state) can be granted, a specific role (for example, “7 lip” in RT4) If it is a notification period, the right is granted in response to the specific notification being performed, while the specific state ends without performing the specific notification if it is not the notification period. Even if it is not the notification period, when a predetermined combination (for example, other than “7 Lip” in RT4) is won, the specific state continues. And when a specific state continues for a predetermined period (for example, between 9 games), the said right is separately provided. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the pachislot machine 1 of the present embodiment, in a specific state (for example, a special RUSH state) to which a right related to a game period in an advantageous state (for example, an ART state) can be granted, a specific role (for example, “7 lip” in RT4) If it is a notification period, the right is granted in response to the specific notification being performed, while the specific state ends without performing the specific notification if it is not the notification period. Even if it is not the notification period, when a predetermined combination (for example, other than “7 Lip” in RT4) is won, the specific state continues. And when a specific state continues for a predetermined period (for example, between 9 games), the said right is separately provided. In addition, even if the specific state ends without continuing for a predetermined period, the midway continuation period is maintained until the next specific state, and in the next specific state, the predetermined period starts from the held midway continuation period. Configured to resume. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in the pachislot machine 1 of this embodiment, since the right regarding a game period is provided whenever the specific state continues for a predetermined period, a plurality of rights are selected according to the period during which the specific state continues. May be granted. That is, even if it is not the notification period, for example, when the predetermined combination continues to win and the specific state continues, there are cases where many of the rights can be obtained. Therefore, it is possible to further improve the expectation of granting rights in a specific state.

  The rights related to the gaming period in the advantageous state that can be granted in the specific state (RUSH state) (rights related to the ART period) are not limited to those described above, but may extend the gaming period in the advantageous state as appropriate directly or indirectly. All the benefits you get can be applied. Further, a part or all of the right that can be granted in the specific state can be a right (privilege) that is not related to the advantageous game period but can be beneficial to the player.

  Further, the notification period in the specific state may be the number of times that the specific procedure is actually notified, the number of games in which the specific procedure can be notified, or the time in which the specific procedure can be notified. It may be. In addition, for a predetermined period in the specific state (9 games in the present embodiment), a game won by the specific combination (in this embodiment, the winning numbers “25” to “36”, that is, “7 lip” in RT4). You may make it count except. In this case, the predetermined period may be set as appropriate by comparing and considering the average grant period of the notification period, the ratio of the winning probability between the specific winning combination and the internal winning combination other than the specific winning combination, and the like.

  That is, these technical ideas are determined based on a plurality of elements (see FIGS. 42 and 43) in a specific state (RUSH state) in which the value of the advantageous state (for example, the gaming period of the advantageous state) can be determined. It is intended to include all forms in which the value of the advantageous state to be changed can be varied, and the playability regarding the continuation of the advantageous state can be varied.

[Gameability under normal conditions]
In the pachi-slot 1 of the present embodiment, control is performed to a preferential state (for example, a specific mode) in which a transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. Also, in this preferential state, not only the lottery state transition control is preferential, but also the non-preferential state (for example, non-specific mode), the advantageous state is based on the current lottery state. Whether or not to be granted is determined. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

  Further, in the pachislot machine 1 of the present embodiment, the preferential state (for example, the specific mode) in which the transition control of a plurality of lottery states (for example, the normal mode) relating to the advantageous state (for example, the ART state) advantageous to the player is preferentially performed. In addition, in this preferential state, not only the lottery state transition control is preferential, but also the non-preferential state (for example, non-specific mode) is advantageous based on the current lottery state. Whether or not the state is given is determined. In the lower lottery state (for example, the normal mode “0” to “2”), the advantageous state is not given unless the specific combination (for example, “F_RB”) is won, but the upper lottery state (for example, the normal mode “ 3 ”and“ 4 ”) are configured such that an advantageous state may be given without winning the specific combination. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

  Further, in the pachislot machine 1 of the present embodiment, the preferential state (for example, the specific mode) in which the transition control of a plurality of lottery states (for example, the normal mode) relating to the advantageous state (for example, the ART state) advantageous to the player is preferentially performed. In addition, in this preferential state, not only the lottery state transition control is preferential, but also the non-preferential state (for example, non-specific mode) is advantageous based on the current lottery state. Whether or not the state is given is determined. In the preferential state, the lottery state may be more advantageous but may not be more disadvantageous. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

  Further, the pachislot machine 1 of the present embodiment is configured to determine whether or not to shift to the preferential state when the lottery state shift control is not performed in the non-preferential state. Therefore, even if the lottery state does not shift, it can be suppressed that the interest of the game is lowered.

  In the present embodiment, the preferential state is described as one of the modes in the normal state, but the preferential state may be provided as the control state (or game state). Moreover, the conditions for starting the preferential state are not limited to those described above, and can be set as appropriate. For example, the preferential state may be started when a specific combination is won, when a specific combination is established, or when a specific lock effect is executed. Moreover, the conditions for ending the preferential state are not limited to those described above, and can be set as appropriate. For example, the preferential state may be ended when a specific combination is won, when a specific combination is established, or when a specific lock effect is executed. Further, the preferential state may be continued until it is determined that the advantageous state is given.

  In addition, the subject to be preferentially treated in the preferential state is not limited to the normal mode transition. For example, the probability of winning a RUSH may be directly preferential. Further, for example, when a RUSH win is made, a probability that a more advantageous RUSH type is selected may be preferentially used.

  That is, these technical ideas provide a preferential state in which a winning probability (or non-winning probability) is preferentially given for a lottery in a normal state, and this preferential state is started according to a predetermined start condition. All forms that can enhance the interest in the normal state and maintain the expectation in the normal state that is more disadvantageous than the advantageous state by being terminated according to the predetermined end condition are included.

[Gameability in battle state]
In the pachi-slot 1 of the present embodiment, points given within a predetermined period (for example, 8 games) in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. The right is granted when the specified point or more is reached, and the degree of advantage regarding the granting of the right may differ depending on the range above the specified point. Specifically, when the given point is equal to or greater than a second value (for example, “15”), it is equal to or greater than the first value (for example, “10”) and less than the second value. The degree of advantage related to the granting of the right is higher than the case where the right is granted. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in the pachislot 1 of this embodiment, although the degree of advantage regarding right granting may differ depending on which range the given point is within the specified point or more, if it becomes the specified point or more The right is necessarily granted. Therefore, the gameability in a specific state can be varied without impairing the player's sense of expectation for granting rights.

  Moreover, in the pachislot 1 of this embodiment, in the specific state (for example, battle state) which can grant the right regarding the game period of an advantageous state (for example, ART state), it was provided within a predetermined period (for example, 8 games). The right is granted when the point becomes a specified point or more, and the degree of advantage regarding the grant of the right may differ depending on the range within the specified point or more. Specifically, when the given point is greater than or equal to a third value (for example, “20”) when the predetermined period ends, it is less than the third value. Rather, the degree of advantage related to the granting of the right is increased. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, the pachi-slot 1 of the present embodiment is configured such that the degree of advantage relating to the right grant is sequentially increased in accordance with which range the given points are within the specified points or more. Therefore, the expectation regarding the granting of rights in a specific state can be sequentially increased, and the interest of the game can be improved.

  Moreover, in the pachislot 1 of this embodiment, in the specific state (for example, battle state) which can grant the right regarding the game period of an advantageous state (for example, ART state), it was provided within a predetermined period (for example, 8 games). The right is granted when the point becomes a specified point or more, and the degree of advantage regarding the grant of the right may differ depending on the range within the specified point or more. Further, in a specific state, it is determined in advance whether the game is easy to give points (for example, damage expectation “high”) or difficult to receive points (for example, damage expectation “low”). The game is informed of which game it is. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in the pachislot 1 of this embodiment, in the specific state (for example, battle state) which can grant the right regarding the game period of an advantageous state (for example, ART state), it was provided within a predetermined period (for example, 8 games). If the point becomes a specified point, the right is granted. On the other hand, if the granted point does not become the specified point, the right is not granted. In this case, however, the second specific state (for example, , “Special pattern”), the assigned points are carried over to a specific state after the next time. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in the pachislot 1 of this embodiment, in the specific state (for example, battle state) which can grant the right regarding the game period of an advantageous state (for example, ART state), it was provided within a predetermined period (for example, 8 games). If the point becomes a specified point, the right is granted. On the other hand, if the granted point does not become the specified point, the right is not granted. In this case, however, the second specific state (for example, , "Special pattern"), the second specific state can be performed from the previous time when the specific state is started next time. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Moreover, in the pachislot 1 of this embodiment, in the specific state (for example, battle state) which can grant the right regarding the game period of an advantageous state (for example, ART state), it was provided within a predetermined period (for example, 8 games). If the points are higher than the specified points, the right is granted. On the other hand, if the granted points are not the specified points, the right is not granted. For example, in the case of “special pattern”), the assigned points are carried over to a specific state after the next time. And in a specific state, it is comprised so that the said right of the more advantageous content may be provided, so that there are many points provided. That is, even if the right is not granted in a specific state, if the granted points are carried over, it is expected that the right with more advantageous contents will be granted in the specific state after the next time. The degree will increase. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  In the present embodiment, in the battle state, points (including all parameters indicating the possibility of granting points, points, and other benefits) are collected, and when the score is equal to or higher than a specified point, an advantageous state (for example, an ART state) ) For the game period (for example, ART period, sphere, RUSH stock) is granted, but the method of collecting points (giving points) is not limited to this. For example, in the battle state, the granted point is subtracted from the initial point, and the right may be granted when the value is equal to or less than a negative value. In the battle state, a task (for example, 8 games) If you are able to clear a given challenge, you will be granted the right according to the difficulty of the challenge. May be.

  In this embodiment, the battle state is, in principle, continued for a predetermined period (8 games). However, the method for determining whether or not to continue the battle state is not limited to this. For example, in the battle state, instead of giving points, it is assumed that a game state in the battle state is given (although, for example, 3 games are separately given as a guarantee period), and a game period in the battle state is given, As a result of extending the game period in the battle state, when the battle state continues for a predetermined period (for example, 10 games) or more, the right may be granted according to the period during which the battle state has continued. In this case, the maximum value of the predetermined period is set to 20 games (corresponding to 20 points in the present embodiment), and the most advantageous privilege may be given when the predetermined period reaches the maximum value. Further, when the battle state is “special pattern”, the number of games in the battle state may be carried over. In this way, even in the battle state, the procedure of the stop operation that is advantageous to the player is notified, so that it is possible to substantially extend to the advantageous state, and to further diversify the game playability. Can do.

  In addition, the rights relating to the gaming period in the advantageous state that can be granted in the specific state (battle state) (rights relating to the ART period) are not limited to those described above, and the game period in the advantageous state can be extended as appropriate directly or indirectly. All the benefits you get can be applied. Further, a part or all of the right that can be granted in the specific state can be a right (privilege) that is not related to the advantageous game period but can be beneficial to the player.

  That is, these technical ideas are based on whether or not a predetermined condition is achieved in a specific state (battle state) in which the value of the advantageous state (for example, the gaming period of the advantageous state) can be determined (for example, a specified point or more). And the degree of achievement (the number of points granted) can vary the value of the determined advantageous state, thereby making it possible to diversify the playability related to the continuation of the advantageous state. All forms are included.

[Gameability in ART state]
In the pachi-slot 1 of the present embodiment, as a right related to a game period in an advantageous state (for example, ART state), a first right (for example, a subordinate privilege) that can be used to determine whether to extend the game period in the advantageous state or not. A certain CZ stock) and a second right (for example, RUSH stock, which is a high-order privilege) for deciding to extend the advantageous game period, and the first right number is a predetermined number (for example, three) In such a case, the second right is granted. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  Further, in the pachislot machine 1 of the present embodiment, as a right related to a game period in an advantageous state (for example, ART state), a first right (for example, a subordinate) that can be used to determine whether to extend the game period in the advantageous state or not. CZ stock that is a privilege) and a second right (for example, RUSH stock that is a superior privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, 3 2) and when the other grant conditions are satisfied, the second right is granted, but at this time, the player is notified that the first right number has increased by a predetermined number. It is configured as follows. That is, even when the upper privilege is given, it is converted into a lower privilege and notified. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state and to improve the interest of the game. In addition, it is possible to provide highly interesting notifications by utilizing the rule of privilege provision based on game play.

  Further, in the pachislot machine 1 of the present embodiment, as a right related to a game period in an advantageous state (for example, ART state), a first right (for example, a subordinate) that can be used to determine whether to extend the game period in the advantageous state or not. CZ stock that is a privilege) and a second right (for example, RUSH stock that is a superior privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, 3 The second right is granted. In the advantageous state, the first right number is notified. That is, the number of lower-order benefits that can be converted into higher-order benefits is indicated to the player. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state and to improve the interest of the game. In addition, it is possible to provide highly interesting notifications by utilizing the rule of privilege provision based on game play.

  Further, in the pachislot machine 1 of the present embodiment, even if the game period in the advantageous state has elapsed without the first right number being a predetermined number, the advantageous state is maintained in the period corresponding to the first right number. The pulling-back lottery is performed. In other words, even when the second right (upper privilege) is not granted, the granted first right (lower privilege) is not wasted. Therefore, even if it is not determined to extend the advantageous game period, it is possible to suppress a decrease in the interest of the game and thereby maintain the player's expectation.

  In the present embodiment, at least in the ART state or the battle state, the first right (lower privilege) and the second privilege (upper privilege) can be granted, but the present invention is not limited to this. Even in the control state, the first right (lower privilege) and / or the second privilege (upper privilege) may be granted. For example, if it is possible to grant the first right (subordinate privilege) in the normal state as in the ART state, the second right when the first right number reaches a predetermined number (for example, three) in the normal state. The right (higher level privilege) may be granted to shift to the precursor state. In this way, even in a normal state, it is possible to maintain a sense of expectation depending on the degree of grant of the first right (lower privilege), and to suppress a decrease in the interest of the game.

  In addition, for example, when the first right (subordinate privilege) can be granted in any state among the precursor state, the RUSH ready state, and the RUSH state, as in the ART state, the first right in that state If (subordinate privilege) is granted, it can be taken over and the ART state can be started. In addition, if the first right number is a predetermined number (for example, three) and the second right (higher privilege) is granted, the ART state is started in a state in which the ART state is confirmed to be extended. be able to. Therefore, the feeling of expectation when the ART state starts can be changed, and the gameability regarding the continuation of the advantageous state can be varied.

  Further, for example, in the withdrawal state, if the first right (lower privilege) can be granted in the same manner as the ART state, the withdrawal state is extended if the first right (lower privilege) is granted in that state. In addition, before the first right (lower privilege) is consumed, the first right number becomes a predetermined number (for example, three) and the second right (higher privilege) becomes If given, it may be possible to return to the ART state. Therefore, it is possible to make the gameability in the pulled-back state various and improve the interest of the game in the pulled-back state.

  In the present embodiment, the number of first rights that can be given the second right (upper privilege) by the first right (lower privilege) is a predetermined number (three in this embodiment). However, the present invention is not limited to this. For example, it may be changed for each ART state (in this case, it is only necessary to perform lottery using the RUSH type as a parameter).

  Further, in the present embodiment, an example of a lower privilege is a right that can be used to determine whether or not to extend an advantageous game period, and an example of an upper privilege is determined to extend an advantageous game period. However, it is possible to apply all the other benefits that have a lower and higher relationship to these benefits.

  That is, these technical ideas have at least a privilege with a relatively low value (lower privilege) and a privilege with a higher value (higher privilege) as privileges given to the player, By allowing the lower level privilege to be converted into the higher level privilege, all forms that can make the gameability varied are included.

  In addition, these technical ideas have at least a privilege with a relatively low value (lower privilege) and a privilege with a higher value (higher privilege) as a privilege given to the player, When a higher privilege is granted, all forms that can be highly interesting notifications using the rules of privilege grant based on game playability can be notified by converting to lower benefits. It is included.

  In addition, these technical ideas may be converted into a lower privilege and notified when the upper privilege is simply given, regardless of whether the lower privilege can be converted into a higher privilege. Good. That is, the technical idea for making the notification itself when the upper privilege is given highly interesting is also possible.

  For example, in a pachinko game, for example, a jackpot gaming state (lower privilege) with 5 rounds and a jackpot gaming state (upper privilege) with 15 rounds are provided. Is given, “5R × 1 time” is notified, and when the upper privilege is given, “5R × 3 times” is notified. In this case, the accumulation of the jackpot gaming state given in the probability variation gaming state may be displayed as “5R × XX times”. In this way, it is possible to easily understand the approximate number of game media acquired in the probability variation gaming state, and it is more informative than simply displaying the number of times each privilege has been granted. be able to.

[Lamp lighting effect]
In the pachislot machine 1 according to the present embodiment, a predetermined lottery (for example, an additional notification period lottery) for each predetermined opportunity in a specific state (for example, RUSH state) in which a right related to a game period in an advantageous state (for example, ART state) can be granted If a win is made, a predetermined right (for example, the number of notifications) is given and the predetermined lottery continues. On the other hand, if no win is made, the predetermined lottery ends without being given the predetermined right. . The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only when it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues, and even when the notification is not performed, the predetermined lottery may continue. Therefore, it is possible to make a player play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

  Further, in the pachislot machine 1 of the present embodiment, a predetermined lottery (for example, an additional notification period lottery) for each game in a specific state (for example, a RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted. ) Is performed, a predetermined right (for example, the number of notifications) is granted and a predetermined lottery is continued, while if not won, the predetermined lottery ends without being granted the predetermined right. To do. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only in a game for which it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues, and even when the notification is not performed, the predetermined lottery may continue. Therefore, it is possible to make a player play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

  Further, in the pachislot machine 1 of the present embodiment, a predetermined lottery (for example, an additional notification period lottery) for each game in a specific state (for example, a RUSH state) in which a right related to a game period in an advantageous state (for example, an ART state) can be granted. ) Is given, and a predetermined right (for example, the number of notifications) is given and a predetermined lottery is continued while a predetermined lottery is continued. The predetermined lottery ends without being granted. In the specific state, a specific right (for example, an ART period) is granted in response to the specific notification. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only when it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues and the number of times that the specific notification can be performed, and even if the notification is not performed, the player can recognize the predetermined lottery. Since there are cases where the game continues, it is possible to cause the player to play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

  In the present embodiment, an example of a predetermined lottery (so-called loop lottery) is described as an additional notification period lottery in the RUSH state, but the specification of the lamp lighting effect is when other loop lotteries are performed. Can also be applied. For example, in any of the control states of the present embodiment, when lottery for giving a sphere is performed and the lottery is won, a loop lottery is performed, and the spheres are increased one by one until the loop lottery is non-winning. When it is possible to give the lamp, the lamp lighting effect can be performed in a state where the spheres are given one by one.

  Also, for example, in any of the control states of the present embodiment, when a lottery for giving RUSH stock is performed and the lottery is won, a loop lottery is performed until the loop lottery becomes non-winning. When it is possible to give stock one by one, the lamp lighting effect can be performed in a state where the RUSH stock is given one by one.

  Also, an end lottery that simply determines whether or not to end a relatively advantageous state for the player (as another example of this embodiment, for example, whether or not the preferential state is ended by each game end lottery). If the end lottery in the case of determination is performed by a loop lottery, the lamp lighting effect may notify that the end of the advantageous state (falling) has been avoided. In this case, in this embodiment, it can also be set as the specification which determines whether a RUSH state, a battle state, or a pullback state is complete | finished by a loop lottery. Further, the present invention can be applied to all loop lotteries that can be performed in other pachislot machines, and can also be applied to all loop lotteries that can be performed in pachinko (for example, falling lotteries in the probability variation gaming state).

  In other words, these technical ideas are based on the fact that a loop lottery is performed when deciding whether or not any privilege that is advantageous to the player is given (or whether or not to end the advantageous state). By notifying the result of the loop lottery, all forms that can improve the interest of the game are included.

[Special sign production]
In the pachi-slot 1 of the present embodiment, when the value (for example, RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value is If it is high, it is easy to determine the second precursor effect in the precursor state, but if the value of the advantageous state is high and the first precursor effect is performed, the precursor state ends. It is configured such that a special sign effect (for example, a special sign) is performed in a later preparation state (for example, a RUSH preparation state). That is, even when a precursor effect with a relatively low degree of expectation is performed, it is possible to expect that the value of the advantageous state is high when the special precursor effect is performed in the preparation state. In addition, the interest of the sign production itself, including special sign production, can be dramatically improved. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

  Further, in the pachi-slot 1 of the present embodiment, when the value (for example, RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, When the value is high, the second precursor effect is easily determined in the precursor state, but when the value of the advantageous state is high and the first precursor effect is performed, the transition to the advantageous state is made. If the notification effect is not performed, a special sign effect (for example, a special sign) is further performed in a preparation state (for example, a RUSH preparation state) after the sign state ends. In other words, even when a precursor effect with a relatively low degree of expectation is performed, when the special precursor effect is performed in the preparation state without performing the notification effect, it is expected that the value of the advantageous state is high. In addition, it is possible to dramatically improve the interest of the sign production itself, including the special sign production. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

  Further, in the pachi-slot 1 of the present embodiment, when the value (for example, RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, When the value is high, the second sign production is easily determined in the sign state, but when the value of the advantageous condition is high and the first sign production is performed, the sign indication is further performed. In the ready state (for example, the RUSH ready state) after the state ends, a special sign effect (for example, a special sign) is performed until the ready state ends. That is, even when a precursor effect with a relatively low degree of expectation is performed, it is possible to expect that the value of the advantageous state is high when the special precursor effect is performed in the preparation state. In addition, the interest of the sign production itself, including special sign production, can be dramatically improved. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

  In addition, the pachislot machine 1 of the present embodiment is configured such that in the preparatory state in the advantageous state, the notification of the stop operation procedure advantageous to the player is started, but there is a case where the sign remains in the precursor state. ing. That is, it is possible to give a surprise to the player as if the notification of the procedure of the stop operation that was advantageous in the sign state was suddenly started. Therefore, the interest can be improved with respect to the effect performed before the start of the advantageous state in which the procedure of the stop operation advantageous to the player is notified.

  In addition, during the special sign production, as described in the present embodiment, for example, it may be more positively improved by performing a lottery promotion of the production stage, or simply the production in the sign state Will be handed over even in the RUSH ready state, and the push order notification will start in this handed over state, creating a sense of incongruity between the production and the control state. You may do it.

  In addition, during the special sign production, as a general rule, the production related to the production in the precursor state is performed, but it is also possible to perform the production that cannot be performed in the precursor state. For example, an effect stage “4” used only for the special sign effect may be provided, and it may be determined whether or not to move to the effect stage “4” with a probability corresponding to the RUSH type.

  In addition, for example, when the specification is such that the RUSH state is started without providing the RUSH preparation state, or when the RUSH preparation state is finished in a short period of time, the special precursor effect is performed even in the RUSH state. It can also be. Including this case, the period during which the special precursor effect can be executed (for example, five games after the end of the precursor state) can be determined in advance.

  In other words, this technical idea is related to the production in the precursor state of the advantageous state by performing the production related to the precursor state even after the end of the precursor state in the gaming machine capable of performing the precursor state of the advantageous state. All forms that can improve the above are included.

[Game history display function]
In the pachi-slot 1 of the present embodiment, a sub display device 18 is provided separately from the display device 11 (projector mechanism 211 and display unit 212), and various information useful to the player is displayed by the sub display device 18. For example, as shown in FIGS. 5A to 5E, a top screen 221 representing an outline game history, a menu screen 222 capable of various operations on the pachislot 1, and game information screens 223, 224, and 225 representing a detailed game history are displayed as sub-display devices. 18 can be displayed.

  Further, the pachislot machine 1 of the present embodiment has a function of enabling registration of a player who performs a game and a function of providing a unique service to the registered player via the sub display device 18. For example, in this embodiment, when the player registration is not accepted, the game information screens 223, 224, and 225 representing the detailed game history are not displayed on the sub display device 18, but the player registration is not performed. If it is received, the game information screens 223, 224, and 225 showing the detailed game history are displayed on the sub display device 18. Making it possible to confirm a more detailed game history leads to an improvement in the convenience of the player. Therefore, in the present embodiment, the convenience can be improved when registration of the player is accepted.

  Further, in the pachislot machine 1 of the present embodiment, the sub display device 18 is provided separately from the display device 11 that produces effects. The sub display device 18 is controlled by the sub control board 72 (sub CPU 201) via the liquid crystal relay board 87. Moreover, the display unit 212 which comprises the display apparatus 11 is controlled by the sub control board 72 (sub CPU201) via the accessory relay board | substrate (not shown). Therefore, in the present embodiment, the sub display device 18 can be controlled separately from the display device 11. Specifically, the display screen of the sub display device 18 can be switched even during the game (that is, during the performance of the display device 11). Therefore, even during the game, the player can acquire various information by switching the display of the sub display device 18 without interfering with the effect performed by the display device 11.

  Further, in the display device 11 of the pachislot machine 1 of the present embodiment, a planar image display is used by switching a plurality of screen mechanisms (display units 212) that cause an image to appear by irradiation of irradiation light from the projector mechanism 211. When performing an effect, an effect using an image display with a sense of depth (stereoscopic effect), and an effect using a curved image display, the effect can be remarkably enhanced. However, such a display form of information is not suitable for displaying information that is not related to an effect such as a game history during the effect. Therefore, in the pachi-slot 1 of the present embodiment, information that is not related to the effect can be displayed on the sub display device 18 provided separately from the display device 11, so that the effect of the effect is not impaired and the game Various information such as history can be displayed appropriately.

  By the way, in a general pachislot, as viewed from the player side, a medal slot 14 is provided on the right side of the pedestal portion 13, and bet buttons 15 a and 15 b and a start lever 16 are provided on the left side of the pedestal portion 13. Therefore, usually, when the game is advanced, the player operates the operation unit on the right side or the left side (side) of the pedestal unit 13.

  On the other hand, in the pachislot machine 1 of the present embodiment, the sub display device 18 is provided on the side (left side) of the surface erected substantially vertically from the pedestal portion 13, and the sub display device 18 is displayed on the screen of the sub display device 18. A touch sensor 19 for switching the display screen is provided. Therefore, in this embodiment, the sub display device 18 and the input device (touch sensor 19) for controlling the display are provided at a place where the player's hand is located during the game. Can be improved. In particular, as in this embodiment, when the sub display device 18 with the touch sensor 19 is provided on the surface of the pedestal portion 13 that is erected from the horizontal plane, the player places his / her hand on the pedestal portion 13. However, the sub display device 18 can be operated. In this case, not only the operability of the player is improved, but also the fatigue of the player accompanying the operation can be reduced, and as a result, an improvement in the operating rate can be expected.

[Non-standard ROM area and non-standard RAM area]
In the pachi-slot 1 of the present embodiment, as shown in FIG. 12B, various programs and various types used for various processes (various processes that do not affect the game characteristics) that are not directly related to the game performance of the game performed by the player. Data (table) is stored in a non-specified ROM area located at an address different from the game ROM area in the main ROM 102.

  In such a configuration of the main ROM 102, programs and data that are not necessary for the game itself actually performed by the player are placed in the ROM area (non-regulated ROM area) where it is impossible to place a program or the like according to conventional rules. can do. Therefore, in the present embodiment, it is possible to avoid compression of the capacity of the game ROM area in the main ROM 102 of the main control board 71, and it is possible to improve the expandability of programs and tables in the main ROM 102.

[Processing at power-on (reset interrupt)]
In the power-on (reset interrupt) process of the pachislot machine 1 according to the present embodiment, as shown in FIG. 36, the first 1.1172 ms cycle interrupt process is performed immediately after power recovery (before the sum check) (S7 and S8). ), A no-operation command is transmitted from the main control circuit 90 to the sub-control circuit 200. In this way, by permitting the interrupt processing immediately after the power is restored, the no-operation command is transmitted in the shortest time after the power is restored, and the communication connection between the main control circuit 90 and the sub control circuit 200 can be established. The communication operation between the main control circuit 90 and the sub control circuit 200 can be stabilized.

  Further, the communication parameters 1 to 5 constituting the no-operation command transmitted immediately after the power is restored are set with the data stored in the L register, H register, E register, D register and C register, respectively, when the power is restored. Is done. Therefore, in the present embodiment, the sum value (BCC) of the no-operation command transmitted in the interrupt process immediately after the power recovery can be made different every time the power is recovered, thereby suppressing illegal acts such as goto. it can.

  Furthermore, the control for displaying the error code “rr” on the 2-digit 7-segment LED in the information display 6 performed in the process of S13 during the process of turning on the power (reset interrupt) is performed by one “LDW”. ”Command (predetermined read command), the 7-segment common output (selection) data output operation to the 2-digit 7-segment LED and the 7-segment cathode output data output operation are performed simultaneously (see FIG. 37C). That is, in the pachislot machine 1 of the present embodiment, when the 2-digit 7-segment LED is dynamically controlled in the power-on (reset interrupt) process, the 7-segment common output (selection) data and the 7-segment cathode output data are Output simultaneously.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

[Game return processing]
In the game return process of the pachi-slot 1 of the present embodiment, as shown in FIG. 38, the input / output state of each port at the time of occurrence of power interruption is secured at the time of power return, and when the rotating cylinder is rotating at the time of power interruption, The reel control management information is acquired when the power is restored, and processing necessary for starting the reel re-rotation is also performed (see S25 to S32). Therefore, in this embodiment, even when the power is restored from the power interruption during the reel rotation, the reel re-rotation control can be stably performed, and the player is not discomforted.

  Moreover, the pachislot 1 of this embodiment is provided with the microprocessor 91 with the security function for game machines as mentioned above. The microprocessor 91 is provided with various kinds of instruction codes (instruction codes dedicated to the main CPU 101) specific to the microprocessor 91 that can be defined in the source program, and the instruction codes dedicated to the main CPU 101 are used in various processes. As a result, processing efficiency and program capacity can be reduced.

  For example, in the game return process, as shown in FIG. 38, the “LDQ” instruction, which is one of the instruction codes dedicated to the main CPU 101, is used on the source program. The “LDQ” instruction is an instruction code for performing address designation using a Q register (extension register), and can access the main ROM 102, the main RAM 103, and the memory map I / O as direct values as described above. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program for the game return process (the capacity used for the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Setting change confirmation process]
In the setting change confirmation process of the pachi-slot 1 of this embodiment, as shown in FIG. 41A, the “BITQ” instruction and the “SETQ” instruction (predetermined instructions), which are instruction codes dedicated to the main CPU 101, are used on the source program. . Each of the “BITQ” instruction and the “SETQ” instruction is an instruction code for specifying an address using a Q register (extension register). When these instruction codes are used, the main RAM 103 is a direct value as described above. And the memory map I / O can be accessed. In this case, the instruction code relating to the address setting can be omitted, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, according to the present embodiment, it is possible to increase the free capacity of the main ROM 102 and to increase the processing speed.

  Also, the setting change command (initialization command) generation and storage process performed at the time of setting change / setting confirmation in S46 and at the time of setting change / setting confirmation end in S57 during the setting change confirmation process is as shown in FIGS. 41A and 41B. In addition, it is executed by a “CALLF” instruction which is an instruction code dedicated to the main CPU 101 on the source program. The jump destination address designated by the “CALLF” instruction in S46 is the same as the jump destination address designated by the “CALLF” instruction in S57. That is, in the present embodiment, a setting change command (initialization command) generation and storage process to be transmitted to the sub-control circuit 200 at the time of setting change (when a gaming machine is started), at the time of setting check start (during normal operation), and at the end of setting check Are the same as each other, and the source program is shared (modularized) in both processes of S46 and S57.

  In this case, since it is not necessary to provide a source program for generating and storing the setting change command separately in both the processes of S46 and S57, the capacity of the source program (the capacity of the main ROM 102) can be reduced correspondingly. it can. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Setting change command generation and storage processing]
In the setting change command generation / storage processing of the pachi-slot 1 of this embodiment, as shown in FIG. 42, the setting value is stored as the communication parameter 3 in the E register, and the RT information is stored as the communication parameter 5 in the C register. That is, among the communication parameters 1 to 5 constituting the setting change command (initialization command), communication parameters 3 and 5 are communication parameters (use parameters) used (analyzed) on the sub-control circuit 200 side. New information is set in the communication parameter. On the other hand, the other communication parameters 1, 2, and 4 constituting the setting change command (initialization command) are communication parameters (unused parameters) that are not used (analyzed) on the sub-control circuit 200 side. And 4 are set to values currently stored in the L register, H register, and D register, respectively. Therefore, the values of the communication parameters 1, 2, and 4 when the setting change command (initialization command) is transmitted are undefined values. In this case, the sum value (BCC) of the setting change command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[Communication data storage processing]
In the communication data storing process of the pachi-slot 1 of this embodiment, as shown in FIG. 44, the data stored in the A register is set as the type data of the communication command, and the L register, H register, E register, D register, and C The data stored in the register is set as communication parameters 1 to 5 of the communication command, and the data stored in the B register is set as gaming state flag data of the communication command. That is, in this embodiment, when creating communication data (command data) of one packet (8 bytes), various parameters are transferred from the register and stored in a communication data temporary storage area (communication buffer).

  In this case, when command data including an unused parameter is created, the value of the unused parameter becomes an indefinite value every time it is created. That is, in command data including unused parameters, even if there is command data of the same type and the values of the used parameters are the same, the command data sum value (BCC data) can be changed every time the command is created. . Therefore, in this embodiment, by setting the unused parameter to an indefinite value, it is possible to make it difficult to analyze the communication data and suppress illegal acts such as goto, and it is necessary to add unnecessary goth countermeasure processing. Therefore, it is possible to suppress the compression of the program capacity of the main control circuit 90 due to the addition of the anti-going process.

[Communication data pointer update processing]
In the communication data pointer update process of the pachislot 1 of the present embodiment, as shown in FIG. 47A, an “ICPLD” instruction that is an instruction code dedicated to the main CPU 101 is used on the source program.

  In the communication data pointer update process, the “ICPLD” instruction is an instruction code in which the upper limit determination instruction of the transmission buffer and the determination branch instruction are integrated. Therefore, an instruction code for executing each instruction process separately is provided. There is no need to provide it. Therefore, by using the “ICPLD” instruction, it is possible to reduce the capacity of the source program for the communication data pointer update process (the capacity used by the main ROM 102). As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Checksum generation processing and sumcheck processing]
In the pachi-slot 1 of this embodiment, in the checksum generation process (not specified) performed at the time of power interruption, as shown in FIG. 49, the checksum is calculated by sequentially adding data in the main RAM 103. On the other hand, in the sum check process (not specified) performed when the power is turned on (when the power is restored), as shown in FIG. 51, the check sum value generated when the power interruption occurs is stored in the main RAM 103 when the power is restored. The data is sequentially subtracted, and whether or not an abnormality has occurred is determined based on whether or not the final subtraction result is “0”. In other words, in the present embodiment, the checksum generation process when power interruption occurs is performed by the addition method, and the checksum determination process when power is restored is performed by the subtraction method.

  When such checksum generation processing and determination processing are employed, it is not necessary to generate the checksum again when the power is restored and to check the checksum with the checksum when the power interruption occurs. In this case, the collation instruction code can be omitted on the source program, and the capacity of the source program can be reduced. As a result, in the present embodiment, in the main ROM 102, it is possible to secure (increase) the free space corresponding to the omission of the collation instruction code, and it is possible to improve the gameability by utilizing the increased free space. Become.

[Medal reception / start check processing]
In the medal acceptance / start check process of the pachi-slot 1 of this embodiment, as shown in FIG. 55, a setting change confirmation process (the process of S233) is performed, but this process is executed regardless of the gaming state. Therefore, in this embodiment, even if the gaming state is a bonus state (special prize operating state), the set value and the hall menu (various history data (error, power interruption history, etc.)) can be confirmed, Can be suppressed.

[Medal insertion processing]
In the medal insertion process of the pachi-slot 1 of the present embodiment, as shown in FIG. 57, in the process of S244, the LED lighting data for displaying the number of medal insertions is generated not by the loop process referring to the table but by the calculation process. . Specifically, a series of source codes “LD A, L” to “OR L” in the source program shown in FIG. 58 are sequentially executed to generate LED lighting data for displaying the number of inserted medals.

  When the LED lighting data for displaying the number of inserted medals is generated by calculation processing, the free space in the table area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. That is, in the medal insertion process of the present embodiment, the medal insertion LED display process can be made more efficient, the free capacity of the main ROM 102 is secured (increased), and the increased free area is utilized to increase the game performance. Can be increased.

[Medal insertion check process]
In the medal insertion check process (see FIG. 59) of the pachi-slot 1 of the present embodiment, the normal change value generation process of the medal sensor input state in S257 is performed by an arithmetic process, not a process of obtaining with reference to a table. Specifically, the medal sensor input state normal change value is calculated by sequentially executing the source code “RLA” and “AND cBX_MDINSW” in the source program shown in FIG.

  By changing the detection process of the change state of the medal sensor input state from the table reference process to the calculation process, the free space in the table storage area of the main ROM 102 can be increased and the increase in the program capacity can be minimized. it can. Therefore, by adopting the processing method described above, it is possible to increase the efficiency of the detection process of the change state of the medal insertion sensor state, and it is possible to improve the gameability by utilizing the increased free space in the main ROM 102. it can.

[Internal lottery processing]
In the internal lottery process (see FIG. 64) of the pachi-slot 1 of this embodiment, the determination data acquisition process of S305 is executed by the source code “LDIN AC, (HL)” in FIG. 65A. As a result of the execution of the “LDIN” instruction, in the processing of S305, determination data is stored in the A register and a request flag status is stored in the C register. Also, by executing the “LDIN” instruction, the address set in the HL register is updated by +2 (added by 2).

  That is, in the determination data acquisition process of S305 during the internal lottery process, both the data load process and the address update process can be performed with one instruction code ("LDIN" instruction). In this case, the instruction code relating to the address setting can be omitted in the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  In addition, the addition processing of the set value data (any one of 0 to 5) in S309 of the internal lottery processing is performed by the main CPU 101 using the source codes “MUL A, 6” and “ADDQ A, (.LOW.wWAVENUM) in FIG. 65B. ) "In this order.

  The “MUL” instruction is an instruction code for multiplication processing dedicated to the main CPU 101, and the execution of this instruction is executed by the arithmetic circuit 107 (see FIG. 9) included in the microprocessor 91. That is, in the pachislot machine 1 of the present embodiment, an arithmetic dedicated circuit (arithmetic circuit 107) for executing multiplication processing and division processing on the source program is provided, so that the efficiency of the multiplication processing and division processing is improved. Can do.

  The “ADDQ” instruction (predetermined addition instruction) is an instruction code dedicated to the main CPU 101, and is an instruction code for performing address designation using the Q register (extension register). By using this “ADDQ” instruction, the main ROM 102, the main RAM 103, and the memory map I / O can be accessed by direct values. Therefore, by using the “ADDQ” instruction, an instruction relating to address setting can be omitted on the source program of the internal lottery process, and the capacity of the source program (usage capacity of the main ROM 102) is reduced correspondingly. Can do. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Design code acquisition processing]
In the symbol code acquisition process (see FIG. 75) of the pachi-slot 1 of this embodiment, the compression / decompression process of data related to winning is performed according to the process procedure described in S647 to S649, and the instruction dedicated to the main CPU 101 in the process By using a code (“CALLF” instruction or the like), it is possible to improve the efficiency of compression / decompression processing of data related to winning, and to effectively utilize the limited capacity of the main RAM 103.

  In the present embodiment, in the compressed data storage process of S649 during the symbol code acquisition process, the jump destination address specified by the “CALLF” instruction is the compression executed in the symbol setting process (see S205 of FIG. 54). In the data storage process (not shown), it is the same as the jump destination address specified by the “CALLF” instruction. That is, in the present embodiment, the source program for executing the compressed data storage process is shared (modularized) in both the symbol code acquisition process and the symbol setting process. In this case, since it is not necessary to provide a source program for compressed data storage processing separately in each process, the capacity of the source program (usable capacity of the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Withdrawal priority acquisition processing]
In the pull-in priority acquisition process (see FIGS. 78 and 79) of the pachislot 1 of the present embodiment, the determination process of S683 during the pull-in priority corresponding process of “ANY role” is a command code dedicated to the main CPU 101 on the source program. It is executed by a certain “JCP” instruction (comparison instruction) (see FIG. 80A).

  When the “JCP” instruction is used in the “ANY role” pull-in priority processing, the address setting command can be omitted as described above. The processing efficiency of the processing can be increased, and the capacity of the source program (used capacity of the main ROM 102) can be reduced.

  Further, in the stop request pull-in request flag setting process in S686 during the pull-in priority acquisition process, as shown in FIG. 80B, the Q register (extended register), which is a dedicated instruction code for the main CPU 101, is used in the source program. An “LDQ” instruction and “CALLF” instruction for addressing are used.

  Therefore, in the stop control pull-in request flag setting process of S686, by using the “LDQ” instruction, an instruction for address setting can be omitted on the source program, and the capacity of the source program (use of the main ROM 102) can be omitted. Capacity) can be reduced. The “CALLF” instruction is a 2-byte instruction code as described above. Therefore, by using these instruction codes dedicated to the main CPU 101 in the stop control pull-in request flag setting process, the processing efficiency can be improved, and the limited capacity of the main RAM 103 can be effectively utilized. .

  Further, in the present embodiment, in the stop request pull-in request flag setting process in S686 during the priority pull-in order acquisition process, the address of the logical product operation process of the jump destination specified by the “CALLF” instruction is the pull-in priority storage process ( This is the same as the jump destination address designated by the “CALLF” instruction in the logical product operation process of S626 in FIG. 73 (see FIG. 74). That is, in this embodiment, the source program for executing the AND operation processing is shared (modularized) in both the priority pull-in order acquisition process and the pull-in priority order storage process.

  In this case, since it is not necessary to provide a source program for logical product operation processing separately in both the priority pull-in order acquisition process and the pull-in priority order storage process, the capacity of the source program (the capacity used in the main ROM 102) correspondingly. Can be reduced. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Reel stop control process]
In the reel stop control process (see FIG. 81) of the pachislot machine 1 of this embodiment, in the processes of S711 to S715, as shown in FIG. 82, address designation is performed using the Q register (extension register) on the source program. An “LDQ” instruction and a “CALLF” instruction are used.

  Therefore, in this embodiment, by using these instruction codes dedicated to the main CPU 101, it is possible to reduce the capacity of the source program of the reel control process and improve the processing efficiency of the reel stop control process. That is, in this embodiment, it is possible to increase the efficiency of the program processing speed and reduce the capacity in the main control circuit 90, and to utilize the free area of the main ROM 102 that increases according to the reduced capacity, Can be increased.

  Further, in the determination processing of S726 (reel (rotating drum) stop state check processing) during the reel stop control processing, as shown in FIG. 83, the “LDQ” instruction and “ORQ” instruction (Q An instruction code dedicated to the main CPU 101 that performs addressing using a register (extended register) is used.

  Therefore, in the present embodiment, an instruction for address setting can be omitted on the source program of the reel stop control process, and the capacity of the source program (usable capacity of the main ROM 102) can be reduced accordingly. . As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Winning Search Process]
In the payout search process (see FIG. 88) of the pachislot 1 of the present embodiment, the “LDIN” instruction is used on the source program as shown in FIG. 89 in the payout number and determination target data setting process of S764.

  Therefore, in the winning search process of this embodiment, both the data load process and the address update process can be performed by one “LDIN” instruction. In this case, an instruction relating to address setting can be omitted from the source program of the winning search process, and the capacity of the source program (the capacity used by the main ROM 102) can be reduced accordingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Further, the medal counter value acquisition process referred to in the determination process of S770 during the winning search process, the winning sheet counter value acquisition process referred to in the process of S772, and the winning number counter stored in the process of S775 ( In each of the (update) processing, as shown in FIG. 89, an “LDQ” instruction for specifying an address using a Q register (extended register) is used. Therefore, in the winning search process of the present embodiment, an instruction relating to address setting can be omitted on the source program, and the capacity of the source program (usage capacity of the main ROM 102) can be reduced correspondingly. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

  Furthermore, in the determination process of S769 during the winning search process, as shown in FIG. 89, the “JSLAA” instruction is used in the source program, and in the determination processes of S770 and S773, the “JCP” instruction is used. When the “JSLAA” instruction and the “JCP” instruction are used on the source program of the winning search process, as described above, the address setting instruction can be omitted, and the capacity of the source program (main ROM 102) Used capacity) can be reduced. As a result, in the present embodiment, free space can be secured (increased) in the main ROM 102, and the increased free space can be utilized to improve game play.

[Illegal hit check processing]
In this embodiment, as shown in FIG. 22, the configuration of the winning action flag storage area (display combination storage area) is the same as that of the winning request flag storage area (internal winning combination storage area). Therefore, in the arithmetic processing of S784 in the illegal hit check processing of the present embodiment, the winning combination data and the internal winning combination data are simply ANDed (“AND” instruction) on the source program (see FIG. 91). Just execute it, you can get the result of combining the winning combination data and the internal winning combination data.

  Therefore, in this embodiment, the illegal hit check process can be made efficient and simplified, and as a result, the free space of the main control program can be secured, and the free space is used to improve the game performance. be able to.

[Winning check / medal payout processing]
In the winning check / medal payout process (see FIG. 92) of the pachislot 1 of the present embodiment, when the payout operation is continued after the credit counter is updated (+1), a wait of 60.33 ms (payout interval) in the process of S808. Wait) processing is performed. In this case, useless waiting time can be reduced, and the mental burden on the player can be reduced.

[Medal payout number check process]
In the update processing of the combination end number counter in S814 during the medal payout number check process (see FIG. 94) of the pachislot 1 of this embodiment, as shown in FIG. 95A, the instruction code dedicated to the main CPU 101 is displayed on the source program. A “DCPLD” instruction is used.

  In the process of S814, the “DCPLD” instruction is an instruction code in which the lower limit determination instruction of the number management counter and the determination branch instruction are integrated. Both processes for holding the value of the counter at “0” can be executed. In this case, there is no need to provide an instruction code for executing both processes separately. Therefore, in the medal payout number check process according to the present embodiment, the capacity of the source program (usage capacity of the main ROM 102) can be reduced, and a free capacity can be secured (increased) in the main ROM 102. The free space can be used to improve gameplay.

  In the process of S816 during the medal payout number check process, as shown in FIG. 95B, the payout number counter value is set in communication parameter 1 of the credit information command, and the credit counter value is set in communication parameter 5. Is done. However, values stored in the H register, E register, and D register at the present time are set in the other communication parameters 2 to 4 (unused parameters) constituting the credit information command. Therefore, the values of the communication parameters 2 to 4 at the time of transmitting the credit information command are indefinite values. As a result, in the present embodiment, the sum value (BCC) of the credit information command can be set to an indefinite value for each transmission, and illegal acts such as goto can be suppressed.

[7-segment LED drive processing]
The output processing of the 7-segment common output (selection) data and the 7-segment cathode output data performed in S936 during the 7-segment LED driving process (see FIG. 101) of the pachislot 1 of this embodiment is performed as shown in FIG. It is executed by the code “LD (cPA_SEGCOM), BC”. That is, in the present embodiment, in the 7-segment LED driving process, the 7-segment common output data and the 7-segment cathode output data are simultaneously output when dynamic lighting control is performed on the 2-digit 7-segment LED. This output control is also performed when the push order display data is displayed on the instruction monitor in the information display 6.

  In this case, the number of instruction codes necessary for dynamic lighting control of the 7-segment LED can be reduced on the source program of the 7-segment LED driving process. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

[Timer update processing]
In the process of S952 (2-byte timer update process) in the timer update process (see FIG. 106) of the pachislot 1 of this embodiment, as shown in FIG. 107, the instruction code dedicated to the main CPU 101 is “ DCPWLD "instruction is used.

  When the “DCPWLD” instruction is executed in the timer update process, both the update (subtraction) process of the timer number (2-byte timer number) and the process of holding the timer number at “0” are executed as described above. Can do. In this case, there is no need to provide an instruction code for executing both processes separately. Therefore, in this embodiment, it is possible to reduce the capacity of the source program (usage capacity of the main ROM 102), to secure (increase) the free capacity in the main ROM 102, and to utilize the increased free capacity. Thus, the playability can be improved.

<Appendix (Summary of the Invention of the Present Embodiment)>
[Amusement machines of the first to twelfth inventions]
In a conventional gaming machine, for each unit game in an advantageous state (for example, ART) advantageous to a player, an additional lottery is performed to determine whether or not to continue the advantageous state. There is known one that continues the advantageous state by a certain number (see, for example, JP 2013-17520 A).

  However, in the gaming machine disclosed in Japanese Patent Laid-Open No. 2013-17520, it is determined whether or not the advantageous state continues depending on whether or not the extra lottery is won. Therefore, the gaming property regarding the continuation of the advantageous state becomes monotonous. There was a problem.

  The first to twelfth inventions have been made based on such a background, and a gaming machine that can improve the interest of the game by making the gameability related to the continuation of the advantageous state various. The purpose is to provide.

  To achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following first to third inventions can be provided.

The gaming machine of the first invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A notification means (for example, the display device 11) for notifying a procedure of a stop operation advantageous to the player;
Advantageous state control means (for example, the main CPU 101) for controlling an advantageous state (for example, ART state) in which the notification by the notification means is performed;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, RUSH state) capable of granting a right related to the advantageous gaming period,
The internal winning combination determining means can determine a specific combination (for example, “7 Lip” in RT4) as an internal winning combination in the specific state,
When the stoppage is performed in a specific procedure, the specific combination can display a specific combination of symbols (for example, “7 uniform lip”), and the stop operation is performed in a procedure different from the specific procedure. If it is, it is an internal winning combination in which the specific symbol combination is not displayed,
The specific state control means includes
In the specific state, when the specific combination is determined as an internal winning combination,
If it is a notification period, the specific procedure can be notified by the notification means, and the right can be granted.
If it is not the notification period, the specific means is not notified by the notification means, the right is not granted,
First notification period granting means (for example, provision of a security notification period by the main CPU 101) for preliminarily providing the notification period;
A second notification period granting unit (for example, provision of an additional notification period by the main CPU 101) that performs lottery for each game in the specific state and grants the notification period until the lottery is non-winning. Can be characterized.

  In the gaming machine configured as described above, a notification period is provided (for example, a security notification period and an additional notification period are provided) by a plurality of different triggers, and a right relating to a gaming period in an advantageous state (for example, an ART state) is provided. In a specific state that can be granted (for example, the RUSH state), the right is granted in response to a specific notification being made during the notification period. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

The gaming machine of the second invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A notification means (for example, the display device 11) for notifying a procedure of a stop operation advantageous to the player;
Advantageous state control means (for example, the main CPU 101) for controlling an advantageous state (for example, ART state) in which the notification by the notification means is performed;
Specific state control means (for example, the main CPU 101) for controlling a specific state (for example, a special RUSH state) to which a right related to the advantageous game period can be granted,
The internal winning combination determining means can determine a specific combination (for example, “7 Lip” in RT4) as an internal winning combination in the specific state,
When the stoppage is performed in a specific procedure, the specific combination can display a specific combination of symbols (for example, “7 uniform lip”), and the stop operation is performed in a procedure different from the specific procedure. If this is an internal winning combination in which a predetermined symbol combination (for example, “RT3 transition lip”) is displayed,
The specific state control means includes
In the specific state, when the specific combination is determined as an internal winning combination,
If it is a notification period, the specific procedure is notified by the notification means, and the right can be granted when the specific symbol combination is displayed,
If it is not the notification period, the specific procedure is not notified by the notification means, and the specific state is ended when the predetermined symbol combination is displayed,
In the specific state, when a predetermined combination different from the specific combination (for example, other than “7 lip” in RT4) is determined as an internal winning combination, the specific state is set regardless of whether or not it is the notification period. Continue,
When the specific state continues for a predetermined period (for example, for 9 games), the right can be further granted.

  In the gaming machine having the above-described configuration, in a specific state (for example, a special RUSH state) where a right related to a gaming period in an advantageous state (for example, an ART state) can be granted, a specific combination (for example, “7 Lip” in RT4) is won. Sometimes, in the notification period, the right is granted in response to the specific notification being performed. On the other hand, if it is not the notification period, the specific state ends without performing the specific notification. Otherwise, when a predetermined combination (for example, other than “7 Lip” in RT4) is won, the specific state continues. And when a specific state continues for a predetermined period (for example, between 9 games), the said right is separately provided. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

The gaming machine of the third invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A notification means (for example, the display device 11) for notifying a procedure of a stop operation advantageous to the player;
Advantageous state control means (for example, the main CPU 101) for controlling an advantageous state (for example, ART state) in which the notification by the notification means is performed;
Specific state control means (for example, the main CPU 101) for controlling a specific state (for example, a special RUSH state) to which a right related to the advantageous game period can be granted,
The internal winning combination determining means can determine a specific combination (for example, “7 Lip” in RT4) as an internal winning combination in the specific state,
When the stoppage is performed in a specific procedure, the specific combination can display a specific combination of symbols (for example, “7 uniform lip”), and the stop operation is performed in a procedure different from the specific procedure. If this is an internal winning combination in which a predetermined symbol combination (for example, “RT3 transition lip”) is displayed,
In the specific state, when the specific combination is determined as an internal winning combination,
If it is a notification period, the specific procedure is notified by the notification means, and the right can be granted when the specific symbol combination is displayed,
If it is not the notification period, the specific procedure is not notified by the notification means, and the specific state is ended when the predetermined symbol combination is displayed,
In the specific state, when a predetermined combination different from the specific combination (for example, other than “7 lip” in RT4) is determined as an internal winning combination, the specific state is set regardless of whether or not it is the notification period. Continue,
When the specific state continues for a predetermined period (for example, for 9 games), the right can be further granted.
When the specific state ends without continuing for the predetermined period, the intermediate period is held until the next specific state, and in the next specific state, the predetermined period is changed from the held intermediate period. It can be characterized by being resumed.

  In the gaming machine having the above-described configuration, in a specific state (for example, a special RUSH state) where a right related to a gaming period in an advantageous state (for example, an ART state) can be granted, a specific combination (for example, “7 Lip” in RT4) is won. Sometimes, in the notification period, the right is granted in response to the specific notification being performed. On the other hand, if it is not the notification period, the specific state ends without performing the specific notification. Otherwise, when a predetermined combination (for example, other than “7 Lip” in RT4) is won, the specific state continues. And when a specific state continues for a predetermined period (for example, between 9 games), the said right is separately provided. In addition, even if the specific state ends without continuing for a predetermined period, the midway continuation period is maintained until the next specific state, and in the next specific state, the predetermined period starts from the held midway continuation period. Configured to resume. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

In the gaming machine of the second or third invention,
If the specific state continues for the predetermined period after the specific state continues for the predetermined period, the right can be further granted.

  The gaming machine configured as described above is configured such that each time a specific state continues for a predetermined period, a right related to the game period is granted, so that a plurality of rights are granted according to the period during which the specific state continues. There is a case. That is, even if it is not the notification period, for example, when the predetermined combination continues to win and the specific state continues, there are cases where many of the rights can be obtained. Therefore, it is possible to further improve the expectation of granting rights in a specific state.

  In order to achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following fourth to sixth inventions can be provided.

The gaming machine of the fourth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, battle state) that can be granted a right related to the advantageous game period,
The specific state control means includes
It is possible to control to the specific state for a predetermined period (for example, 8 games),
Points can be awarded within the predetermined period,
The right can be granted when the points granted within the predetermined period are equal to or greater than a first value (eg, “10”),
When the right is granted, if the points granted within the predetermined period are equal to or greater than a second value (eg, “15”) greater than the first value, the points are granted within the predetermined period. Compared with the case where the point is equal to or more than the first value and less than the second value, the degree of advantage related to the grant of the right can be increased.

  In the gaming machine configured as described above, points given within a predetermined period (for example, 8 games) are specified in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. The right may be granted when the number of points is exceeded, and the degree of advantage regarding the granting of the right may differ depending on the range within the specified points or more. Specifically, when the given point is equal to or greater than a second value (for example, “15”), it is equal to or greater than the first value (for example, “10”) and less than the second value. The degree of advantage related to the granting of the right is higher than the case where the right is granted. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

In the gaming machine of the fourth invention,
In the predetermined period, when a predetermined number of unit games (for example, 8 games) are executed, or before the predetermined number of unit games are executed, a third value (for example, “20”) that is larger than the second value. ) It ends when the above points are awarded,
The right may always be granted when the points awarded within the predetermined period are equal to or greater than the first value.

  In the gaming machine configured as described above, the degree of advantage related to the granting of rights may vary depending on the range of points granted or greater, but if the score is greater than or equal to the prescribed point, the right is granted. It is configured to be granted. Therefore, the gameability in a specific state can be varied without impairing the player's sense of expectation for granting rights.

The gaming machine of the fifth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, battle state) that can be granted a right related to the advantageous game period,
The specific state control means includes
It is possible to control to the specific state for a predetermined period (for example, 8 games),
Points can be awarded for each game within the predetermined period,
If the points granted within the predetermined period are equal to or greater than a first value (eg, “10”), the right can be granted when the predetermined period ends,
When granting the right, the degree of advantage regarding the grant of the right may vary depending on the points granted within the predetermined period,
The point includes the first value, a second value greater than the first value (eg, “15”), and a third value greater than the second value (eg, “20”). Can be added within a predetermined range including
When the points awarded within the predetermined period are equal to or greater than the third value, the degree of advantage related to the granting of the rights is higher than when the predetermined period ends less than the third value. Can be characterized.

  In the gaming machine configured as described above, points given within a predetermined period (for example, 8 games) are specified in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. The right may be granted when the number of points is exceeded, and the degree of advantage regarding the granting of the right may differ depending on the range within the specified points or more. Specifically, when the given point is greater than or equal to a third value (for example, “20”) when the predetermined period ends, it is less than the third value. Rather, the degree of advantage related to the granting of the right is increased. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

In the gaming machine of the fifth invention,
The predetermined range to which the right can be granted includes a first range that includes the first value and does not include the second value and the third value, and the second value. And a second range that does not include the first value and the third value, and a third range that includes the third value and does not include the first value and the second value. And include
When granting the right,
The degree of advantage related to the grant of the right is higher in the case where the points given in the predetermined period are in the second range than in the case where the points are in the first range,
The advantage regarding the granting of the right can be increased when the point awarded within the predetermined period is in the third range than in the case where the point is in the second range.

  The gaming machine having the above-described configuration is configured such that the degree of advantage relating to the granting of rights increases sequentially in accordance with which range the given points are within a predetermined point or more. Therefore, the expectation regarding the granting of rights in a specific state can be sequentially increased, and the interest of the game can be improved.

The gaming machine of the sixth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, battle state) that can be granted a right related to the advantageous game period,
The specific state control means includes
It is possible to control to the specific state for a predetermined period (for example, 8 games),
Points can be awarded for each game within the predetermined period,
If the points granted within the predetermined period are greater than or equal to a specified point, the right can be granted when the predetermined period ends,
When granting the right, the degree of advantage regarding the grant of the right may vary depending on the points granted within the predetermined period,
For each game within the predetermined period, it is an advantageous game (for example, damage expectation “high”) to which points are easily awarded, or a disadvantaged game (for example, damage expectation “low”) to which points are difficult to be awarded. Can be determined in advance,
It further comprises specific notification means (for example, the display device 11) capable of notifying a player whether the current game in the specific state is the granted advantageous game or the disadvantaged game. can do.

  In the gaming machine configured as described above, points given within a predetermined period (for example, 8 games) are specified in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. The right may be granted when the number of points is exceeded, and the degree of advantage regarding the granting of the right may differ depending on the range within the specified points or more. Further, in a specific state, it is determined in advance whether the game is easy to give points (for example, damage expectation “high”) or difficult to receive points (for example, damage expectation “low”). The game is informed of which game it is. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  In order to achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following seventh to ninth inventions can be provided.

The gaming machine of the seventh invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, battle state) that can be granted a right related to the advantageous game period,
The specific state control means includes
It is possible to control to the specific state for a predetermined period (for example, 8 games),
Points can be awarded within the predetermined period,
The right can be granted when the points granted within the predetermined period become specified points,
The specific state can be controlled to a first specific state (for example, “normal pattern”) or a second specific state (for example, “special pattern”),
In the case where the specified state ends without the points granted within the predetermined period being the specified points, the second points are not carried over within the predetermined period if the first specific state is reached. If it is in a specific state, the points given within the predetermined period are carried over.

  In the gaming machine configured as described above, points given within a predetermined period (for example, 8 games) are specified in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. In the case of a point, the right is granted. On the other hand, if the granted point does not become a specified point, the right is not granted. In this case, however, the second specific state (for example, “special” Pattern "), the assigned points are carried over to a specific state after the next time. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

The gaming machine of the eighth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, battle state) that can be granted a right related to the advantageous game period,
The specific state control means includes
It is possible to control to the specific state for a predetermined period (for example, 8 games),
Points can be awarded within the predetermined period,
The right can be granted when the points granted within the predetermined period become specified points,
The specific state can be controlled to a first specific state (for example, “normal pattern”) or a second specific state (for example, “special pattern”),
In the case where the specified state ends without the points granted within the predetermined period being the specified points, the second points are not carried over within the predetermined period if the first specific state is reached. If it is in a specific state, carry over the points granted within the predetermined period,
When the second specific state is finished and then the specific state is started, the control unit is controlled to the second specific state and resumed from the point where the second specific state is carried over. Can do.

  In the gaming machine configured as described above, points given within a predetermined period (for example, 8 games) are specified in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. In the case of a point, the right is granted. On the other hand, if the granted point does not become a specified point, the right is not granted. In this case, however, the second specific state (for example, “special” If “pattern”), the second specific state can be performed from the previous time the next time the specific state is started. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

The gaming machine of the ninth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, battle state) that can be granted a right related to the advantageous game period,
The specific state control means includes
It is possible to control to the specific state for a predetermined period (for example, 8 games),
Points can be awarded for each game within the predetermined period,
If the points granted within the predetermined period are greater than or equal to a specified point, the right can be granted when the predetermined period ends,
In the case of granting the right, the content of the right is changed according to the points given within the predetermined period,
When the point granted within the predetermined period becomes the maximum value of the specified point, the right that is most advantageous for the player can be granted,
The specific state can be controlled to a first specific state (for example, “normal pattern”) or a second specific state (for example, “special pattern”),
In the case where the specified state ends without the points granted within the predetermined period being the specified points, the second points are not carried over within the predetermined period if the first specific state is reached. If it is in a specific state, the points given within the predetermined period are carried over.

  In the gaming machine configured as described above, points given within a predetermined period (for example, 8 games) are specified in a specific state (for example, battle state) in which a right related to a gaming period in an advantageous state (for example, ART state) can be granted. When the number of points is exceeded, the right is granted. On the other hand, when the granted point does not become the specified point, the right is not granted. In this case, however, the second specific state (for example, “ In the case of “special pattern”), the assigned points are carried over to a specific state after the next time. And in a specific state, it is comprised so that the said right of the more advantageous content may be provided, so that there are many points provided. That is, even if the right is not granted in a specific state, if the granted points are carried over, it is expected that the right with more advantageous contents will be granted in the specific state after the next time. The degree will increase. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

  In order to achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following tenth to twelfth inventions can be provided.

The gaming machine of the tenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Right granting means (for example, main CPU 101) capable of granting a right related to the advantageous game period,
The right granting means is:
A first right (for example, CZ stock which is a subordinate privilege) that can be used to determine whether or not to extend the advantageous gaming period;
A second right to decide to extend the advantageous gaming period (for example, a RUSH stock that is an upper privilege), and
The second right can be granted when the first right number reaches a predetermined number (for example, three).

  In the gaming machine having the above-described configuration, the first right (for example, a lower-order privilege) that can be used to determine whether or not to extend the advantageous game period as a right regarding the gaming period in the advantageous state (for example, ART state). CZ stock) and a second right (for example, RUSH stock, which is a higher-order privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, three) In such a case, the second right is granted. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state, and to improve the interest of the game.

An eleventh aspect of the gaming machine is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Right granting means (for example, main CPU 101) capable of granting a right related to the advantageous game period,
The right granting means is:
A first right (for example, CZ stock which is a subordinate privilege) that can be used to determine whether or not to extend the advantageous gaming period;
A second right to decide to extend the advantageous gaming period (for example, a RUSH stock that is an upper privilege), and
The second right can be granted when the first right number reaches a predetermined number (for example, three), and the second right is also given when other grant conditions are satisfied. Can be granted,
When the second right is granted by the right granting means, it further comprises grant notifying means (for example, display device 11) capable of notifying that the first number of rights has increased by the predetermined number. Can be a feature.

  In the gaming machine having the above-described configuration, the first right (for example, a lower-order privilege) that can be used to determine whether or not to extend the advantageous game period as a right regarding the gaming period in the advantageous state (for example, ART state). CZ stock) and a second right (for example, RUSH stock, which is a higher-order privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, three) The second right is granted when the other right conditions are met, and at this time, the player is informed that the first right number has increased by a predetermined number. Has been. That is, even when the upper privilege is given, it is converted into a lower privilege and notified. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state and to improve the interest of the game. In addition, it is possible to provide highly interesting notifications by utilizing the rule of privilege provision based on game play.

In addition, the gaming machine of the twelfth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Right granting means (for example, main CPU 101) capable of granting a right related to the advantageous game period,
The right granting means is:
A first right (for example, CZ stock which is a subordinate privilege) that can be used to determine whether or not to extend the advantageous gaming period;
A second right to decide to extend the advantageous gaming period (for example, a RUSH stock that is an upper privilege), and
When the first right number reaches a predetermined number (for example, three), the second right can be granted;
In the advantageous state, it may further include provision state notifying means (for example, sub display device 18) for notifying the first number of rights.

  In the gaming machine having the above-described configuration, the first right (for example, a lower-order privilege) that can be used to determine whether or not to extend the advantageous game period as a right regarding the gaming period in the advantageous state (for example, ART state). CZ stock) and a second right (for example, RUSH stock, which is a higher-order privilege) that decides to extend the advantageous game period, and the first right number is a predetermined number (for example, three) The second right is granted. In the advantageous state, the first right number is notified. That is, the number of lower-order benefits that can be converted into higher-order benefits is indicated to the player. Therefore, it is possible to make a variety of games related to the continuation of the advantageous state and to improve the interest of the game. In addition, it is possible to provide highly interesting notifications by utilizing the rule of privilege provision based on game play.

Moreover, in the gaming machines of the tenth to twelfth inventions,
The advantageous state control means includes:
When the advantageous gaming period has elapsed,
When the second right has been granted, it is possible to shift to a specific state (for example, RUSH state) to which the advantageous gaming period can be granted,
When the first right is granted, a special state (for example, pullback) in which a lottery can be performed as to whether or not the state can be shifted to the specific state for a period corresponding to the first right number. It is possible to make a state capable of shifting to (state).

  In the gaming machine having the above-described configuration, even when the advantageous game period has elapsed without the first right number being a predetermined number, the advantageous state withdrawal lottery is performed in the period corresponding to the first right number. Is configured to be performed. In other words, even when the second right (upper privilege) is not granted, the granted first right (lower privilege) is not wasted. Therefore, even if it is not determined to extend the advantageous game period, it is possible to suppress a decrease in the interest of the game and thereby maintain the player's expectation.

[Amusement machines of thirteenth to fifteenth inventions]
2. Description of the Related Art Conventional gaming machines are known that have a plurality of modes having different transition probabilities of advantageous states (for example, bonus games) that are advantageous to the player (see, for example, JP-A-2005-287880).

  However, it is considered that there is room for further improvement in the playability using such a plurality of modes (lottery states).

  The thirteenth to fifteenth inventions have been made based on such a background, and provide a gaming machine having a plurality of lottery states related to an advantageous state, which can improve the interest of the game. The purpose is to do.

  In order to achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following thirteenth to fifteenth inventions can be provided.

The gaming machine of the thirteenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A lottery state control having a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition Means (for example, main CPU 101);
A preferential state in which the lottery state transition control by the lottery state control means is preferential (for example, a specific mode) and a non-preferential state that is not the preferential state (for example, a non-specific mode), and a specific transition condition Preferential state control means (for example, the main CPU 101) capable of transition control between the preferential state and the non-preferential state based on
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means And determining means (for example, the main CPU 101).

  In the gaming machine having the above-described configuration, it is controlled to a preferential state (for example, a specific mode) in which transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

In addition, the gaming machine of the fourteenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A lottery state control having a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition Means (for example, main CPU 101);
A preferential state in which the lottery state transition control by the lottery state control means is preferential (for example, a specific mode) and a non-preferential state that is not the preferential state (for example, a non-specific mode), and a specific transition condition Preferential state control means (for example, the main CPU 101) capable of transition control between the preferential state and the non-preferential state based on
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means Determining means (for example, main CPU 101),
The advantageous state provision determining means includes:
When the lottery state transferred by the lottery state control means is the lower lottery state (for example, the normal mode “0” to “2”), the specific combination (for example, “F_RB”) is used as the internal winning combination. It is possible to decide to give said advantageous state if it is decided;
When the lottery state transferred by the lottery state control means is the upper lottery state (for example, the normal mode “3” and “4”), when the other than the specific combination is determined as the internal winning combination Can be characterized in that it can be determined to give the advantageous state.

  In the gaming machine having the above-described configuration, it is controlled to a preferential state (for example, a specific mode) in which transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. In the lower lottery state (for example, the normal mode “0” to “2”), the advantageous state is not given unless the specific combination (for example, “F_RB”) is won, but the upper lottery state (for example, the normal mode “ 3 ”and“ 4 ”) are configured such that an advantageous state may be given without winning the specific combination. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

A fifteenth aspect of the gaming machine is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
A lottery state control having a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition Means (for example, main CPU 101);
A preferential state in which the lottery state transition control by the lottery state control means is preferential (for example, a specific mode) and a non-preferential state that is not the preferential state (for example, a non-specific mode), and a specific transition condition Preferential state control means (for example, the main CPU 101) capable of transition control between the preferential state and the non-preferential state based on
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means Determining means (for example, main CPU 101),
The lottery state control means includes
In the non-preferential state, it is possible to determine that the lottery state is shifted to the more advantageous lottery state, and it is also possible to determine that the lottery state is shifted to the more disadvantageous lottery state,
In the preferential state, it is possible to determine to shift the lottery state to the more advantageous lottery state, and it is not possible to determine to shift the lottery state to the more unfavorable lottery state. be able to.

  In the gaming machine having the above-described configuration, it is controlled to a preferential state (for example, a specific mode) in which transition control of a plurality of lottery states (for example, a normal mode) relating to an advantageous state (for example, an ART state) advantageous to the player is preferential. In addition, in this preferential state, not only the transition control of the lottery state is preferential, but also an advantageous state is given based on the current lottery state as in the non-preferential state (for example, non-specific mode). Whether or not to be performed is determined. In the preferential state, the lottery state may be more advantageous but may not be more disadvantageous. Therefore, in the gaming machine having a plurality of lottery states related to the advantageous state, the interest of the game can be improved.

Moreover, in the gaming machines of the thirteenth to fifteenth inventions,
The preferential state control means is capable of determining whether or not to shift to the preferential state when the lottery state control means does not determine to shift the lottery state in the non-preferential state. can do.

  The gaming machine having the above configuration is configured to determine whether or not to shift to the preferential state when the lottery state shift control is not performed in the non-preferential state. Therefore, even if the lottery state does not shift, it can be suppressed that the interest of the game is lowered.

[Amusement machines of the sixteenth to eighteenth inventions]
In a conventional gaming machine, for each unit game in an advantageous state (for example, ART) advantageous to a player, an additional lottery is performed to determine whether or not to continue the advantageous state. There is known one that continues the advantageous state by a certain number (see, for example, JP 2013-17520 A).

  However, in the gaming machine shown in JP2013-17520A, it is determined whether or not the advantageous state continues depending on whether or not the extra lottery is won, so that the gaming property regarding the continuation of the advantageous state becomes monotonous, It can be considered that there is room for improvement in the production performed for the continuation of the advantageous state.

  The sixteenth to eighteenth aspects of the invention are based on such a background, and provide a gaming machine that can improve the interest of the game by devising the effect performed in relation to the continuation of the advantageous state. For the purpose.

  In order to achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following sixteenth to eighteenth inventions can be provided.

The gaming machine of the sixteenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, RUSH state) capable of granting a right related to the advantageous gaming period,
The specific state control means includes
Perform a predetermined lottery (for example, additional notification period lottery) for each predetermined opportunity in the specific state,
When the predetermined lottery is won, a predetermined right (for example, the number of notifications) is given, and the predetermined lottery is continued.
If the predetermined lottery is not won, the predetermined lottery is not granted and the predetermined lottery is terminated.
Start notifying means (for example, display device 11) capable of notifying that the predetermined lottery has been started;
Continuation notification means (for example, the lamp group 21) for determining whether or not to perform continuous notification when the predetermined lottery is won, and performing the continuous notification when it is determined to perform the continuous notification; It may be characterized by having.

  In the gaming machine having the above-described configuration, a predetermined lottery (for example, an additional notification period lottery) is provided for each predetermined opportunity in a specific state (for example, a RUSH state) in which a right related to a gaming period in an advantageous state (for example, an ART state) can be granted. When a win is made, a predetermined right (for example, the number of notifications) is given and the predetermined lottery is continued. On the other hand, when not winning, the predetermined right is not given and the predetermined lottery ends. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only when it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues, and even when the notification is not performed, the predetermined lottery may continue. Therefore, it is possible to make a player play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

The gaming machine of the seventeenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, RUSH state) capable of granting a right related to the advantageous gaming period,
The specific state control means includes
Perform a predetermined lottery (for example, additional notification period lottery) for each game in the specific state,
When the predetermined lottery is won, a predetermined right (for example, the number of notifications) is given, and the predetermined lottery is continued.
If the predetermined lottery is not won, the predetermined lottery is not granted and the predetermined lottery is terminated.
Start notifying means (for example, display device 11) capable of notifying that the predetermined lottery has been started;
It is determined whether or not to continue notification for each game won in the predetermined lottery, and when it is determined to perform the continued notification, continuous notification means for performing the continuous notification in the game (for example, lamp group 21) And further comprising.

  In the gaming machine having the above-described configuration, a predetermined lottery (for example, additional notification period lottery) is performed for each game in a specific state (for example, RUSH state) in which a right relating to a gaming period in an advantageous state (for example, ART state) can be granted. If the player wins, a predetermined right (for example, the number of notifications) is given and the predetermined lottery continues. On the other hand, if the player does not win, the predetermined right is not given and the predetermined lottery ends. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only in a game for which it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues, and even when the notification is not performed, the predetermined lottery may continue. Therefore, it is possible to make a player play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

The gaming machine of the eighteenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Specific state control means (for example, main CPU 101) for controlling a specific state (for example, RUSH state) capable of granting a right related to the advantageous gaming period,
The specific state control means includes
Perform a predetermined lottery (for example, additional notification period lottery) for each game in the specific state,
When the predetermined lottery is won, a predetermined right (for example, the number of notifications) is given, and the predetermined lottery is continued.
If the predetermined lottery is not won, the predetermined lottery is not granted and the predetermined lottery is terminated.
Start notifying means (for example, display device 11) capable of notifying that the predetermined lottery has been started;
Continuation notification means (for example, a lamp group 21) for determining whether or not to perform continuous notification when the predetermined lottery is won, and performing the continuous notification when it is determined to perform the continuous notification; Prepared,
The predetermined right is a specific notification for notifying that a stop operation is performed in a specific procedure when the internal winning combination determining means determines a specific combination (for example, “7 lip” in RT4) in the specific state. Is the right to be done once,
The specific state control means can grant a specific right (for example, an ART period) in response to the specific notification when the specific winning combination is determined by the internal winning combination determination means in the specific state. It can be characterized by being.

  In the gaming machine having the above-described configuration, a predetermined lottery (for example, additional notification period lottery) is performed for each game in a specific state (for example, RUSH state) in which a right relating to a gaming period in an advantageous state (for example, ART state) can be granted. In the event of winning, a predetermined right (for example, the number of notifications) to be given once is given and a predetermined lottery is continued, while in the case of not winning, a predetermined right is granted. The predetermined lottery is finished. In the specific state, a specific right (for example, an ART period) is granted in response to the specific notification. The start of the predetermined lottery is notified, but the continuation of the predetermined lottery is configured to be notified only when it is determined to perform the notification. That is, when the notification is performed, the player can recognize that the predetermined lottery continues and the number of times that the specific notification can be performed, and even if the notification is not performed, the player can recognize the predetermined lottery. Since there are cases where the game continues, it is possible to cause the player to play a game with expectation. Therefore, it is possible to improve the interest of the game by devising the effect performed regarding the continuation of the advantageous state.

[Amusement machines of the 19th to 21st inventions]
A conventional gaming machine is known that can generate a precursor state of an advantageous state (for example, a bonus game) that is advantageous to a player (see, for example, JP 2009-261548 A).

  However, it is considered that there is room for further improvement in the production in such a precursor state.

  The nineteenth to twenty-first aspects of the invention have been made based on such a background, and an object thereof is to provide a gaming machine that can improve its interest with respect to the performance in the precursor state of the advantageous state. .

  To achieve the above object, according to the gaming machine of the present embodiment, the gaming machines of the following nineteenth to twenty-first inventions can be provided.

The gaming machine of the nineteenth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Value determining means (for example, main CPU 101) capable of determining the value (for example, RUSH type) of the advantageous state;
When it is determined by the advantageous state control means that the advantageous state is controlled, the precursor state control means (main CPU 101) capable of controlling the precursor state;
When the precursor state ends, the preparation state control means (for example, the main CPU 101) that can be controlled to the preparation state (for example, the RUSH preparation state);
A precursor effect determining means (for example, a sub CPU 201) capable of determining a precursor effect (for example, an effect stage) in the precursor state based on the value determined by the value determining means,
The advantageous state control means can be controlled to the advantageous state when the preparation state ends,
The precursor effect determination means
When the value determined by the value determining means is low, it is easy to determine the first precursor effect (for example, the effect stage “1”),
When the value determined by the value determining means is high, it is easy to determine a second precursor effect (for example, an effect stage “3”),
When the value determined by the value determining means is high and the first precursor effect is determined, it is possible to further determine to perform a special precursor effect (for example, a special precursor) in the preparation state It can be characterized by.

  In the gaming machine configured as described above, when the value (for example, the RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value is high. In this case, it is easy to determine the second precursor effect in the precursor state, but when the value of the advantageous state is high and the first precursor effect is performed, further, after the end of the precursor state In the preparation state (for example, the RUSH preparation state), a special sign effect (for example, a special sign) is performed. That is, even when a precursor effect with a relatively low degree of expectation is performed, it is possible to expect that the value of the advantageous state is high when the special precursor effect is performed in the preparation state. In addition, the interest of the sign production itself, including special sign production, can be dramatically improved. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

In addition, the gaming machine of the twentieth invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Value determining means (for example, main CPU 101) capable of determining the value (for example, RUSH type) of the advantageous state;
When it is determined by the advantageous state control means that the advantageous state is controlled, the precursor state control means (main CPU 101) capable of controlling the precursor state;
When the precursor state ends, the preparation state control means (for example, the main CPU 101) that can be controlled to the preparation state (for example, the RUSH preparation state);
Based on the value determined by the value determining means, a precursor effect determining means (for example, the sub CPU 201) capable of determining a precursor effect (for example, an effect stage) in the precursor state;
When the preparation state starts, notification effect determining means (for example, determining whether or not to perform a notification effect for notifying that it is determined to be controlled to the advantageous state by the advantageous state control means (for example, Sub CPU 201)
The advantageous state control means can be controlled to the advantageous state when the preparation state ends,
The precursor effect determination means
When the value determined by the value determining means is low, it is easy to determine the first precursor effect (for example, the effect stage “1”),
When the value determined by the value determining means is high, it is easy to determine a second precursor effect (for example, an effect stage “3”),
If the value determined by the value determining means is high, and the first precursor effect is determined, and if the notification effect is not performed, a special precursor effect (e.g., It can be characterized that it is possible to decide to perform a special sign.

  In the gaming machine configured as described above, when the value (for example, the RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value is high. In this case, it is easy to determine the second precursor effect in the precursor state, but when the value of the advantageous state is high and the first precursor effect is performed, the notification effect of transition to the advantageous state is performed. If it is not performed, a special sign effect (for example, a special sign) is further performed in a preparation state (for example, a RUSH preparation state) after the sign state ends. In other words, even when a precursor effect with a relatively low degree of expectation is performed, when the special precursor effect is performed in the preparation state without performing the notification effect, it is expected that the value of the advantageous state is high. In addition, it is possible to dramatically improve the interest of the sign production itself, including the special sign production. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

In addition, the gaming machine of the 21st invention is
A gaming machine (for example, pachislot 1) that variably displays a plurality of symbols on a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination (for example, internal lottery processing by the main CPU 101);
When a start operation is performed by the player, symbol variation start control means (for example, reel rotation start processing by the main CPU 101) that starts symbol variation display;
When a stop operation is performed by the player, symbol variation stop control means (for example, reel stop control processing by the main CPU 101) that stops the symbol variation display based on the internal symbol combination determined by the internal symbol combination determination unit. When,
Advantageous state control means (for example, main CPU 101) for controlling an advantageous state (for example, ART state) advantageous for the player;
Value determining means (for example, main CPU 101) capable of determining the value (for example, RUSH type) of the advantageous state;
When it is determined by the advantageous state control means that the advantageous state is controlled, the precursor state control means (main CPU 101) capable of controlling the precursor state;
When the precursor state ends, the preparation state control means (for example, the main CPU 101) that can be controlled to the preparation state (for example, the RUSH preparation state);
A precursor effect determining means (for example, a sub CPU 201) capable of determining a precursor effect (for example, an effect stage) in the precursor state based on the value determined by the value determining means,
The advantageous state control means can be controlled to the advantageous state when the preparation state ends,
The precursor effect determination means
When the value determined by the value determining means is low, it is easy to determine the first precursor effect (for example, the effect stage “1”),
When the value determined by the value determining means is high, it is easy to determine a second precursor effect (for example, an effect stage “3”),
When the value determined by the value determining means is high and the first precursor effect is determined, it is possible to further determine to perform a special precursor effect (for example, a special precursor) in the preparation state And
The special precursor effect can be performed until the preparation state is completed.

  In the gaming machine configured as described above, when the value (for example, the RUSH type) of the advantageous state (for example, ART state) advantageous to the player is low, the first precursor effect is easily determined in the precursor state, and the value is high. In this case, it is easy to determine the second precursor effect in the precursor state, but when the value of the advantageous state is high and the first precursor effect is performed, further, after the end of the precursor state In the preparation state (for example, the RUSH preparation state), a special sign effect (for example, a special sign) is performed until the preparation state ends. That is, even when a precursor effect with a relatively low degree of expectation is performed, it is possible to expect that the value of the advantageous state is high when the special precursor effect is performed in the preparation state. In addition, the interest of the sign production itself, including special sign production, can be dramatically improved. Therefore, the interest can be improved with respect to the production in the precursor state of the advantageous state.

In the 19th to 21st gaming machines,
It further comprises notification means (for example, display device 11) for notifying the procedure of the stop operation that is advantageous for the player,
The advantageous state is a state in which notification by the notification unit is performed,
The notification means may perform notification even in the preparation state.

  The gaming machine having the above-described configuration is configured such that, in the preparation state in the advantageous state, the notification of the stop operation procedure advantageous to the player is started, but there is a case where the signage state remains in effect. That is, it is possible to give a surprise to the player as if the notification of the procedure of the stop operation that was advantageous in the sign state was suddenly started. Therefore, the interest can be improved with respect to the effect performed before the start of the advantageous state in which the procedure of the stop operation advantageous to the player is notified.

[The gaming machine of the 22nd invention]
In a conventional gaming machine, there is known a gaming machine that obtains a checksum of data stored in a RAM at the time of power interruption, and performs a checksum determination process obtained at the time of power interruption when the power is restored (for example, JP 2009-011375). In the gaming machine disclosed in Japanese Patent Application Laid-Open No. 2009-011375, in the checksum determination process at the time of power restoration, an error notification is performed when the checksum obtained at the time of power restoration does not match the checksum obtained at the time of power interruption.

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and there is a demand for capacity reduction of processing programs and tables other than the game management managed by the main control circuit.

  The twenty-second aspect of the invention is made to solve the above-mentioned problem, and its purpose is to reduce the capacity of processing programs and tables other than the playability managed by the main control circuit and to reduce the capacity of the ROM of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space and enhancing the playability by using the free space of the ROM corresponding to the increased space.

  In order to solve the above problems, according to a twenty-second invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Power supply means for supplying a power supply voltage (for example, the power supply substrate 53b and the switching regulator 94);
Starting means for outputting a starting signal to the arithmetic processing means when the power supply voltage exceeds a predetermined starting voltage value (for example, 10V) (for example, reset signal output processing of the power management circuit 93);
When the power supply voltage falls below a predetermined power failure voltage value (for example, 10.5 V), a power failure means for outputting a power failure signal to the arithmetic processing means (for example, output of a power failure detection signal of the power management circuit 93) Processing), and
The arithmetic processing means includes:
A flag register (eg, flag register F) that stores data corresponding to the result of the arithmetic processing;
When the power failure means outputs the power failure signal, the sum value is calculated by accumulating all the information stored in a predetermined storage area (for example, the game RAM area) in the second storage means. Sum value calculation means (for example, checksum generation processing);
A sum value that sequentially subtracts the information stored in the predetermined storage area from the sum value generated by the sum value calculation means at the time of the most recent power interruption when the activation means outputs the activation signal. Subtraction means (for example, S122 to S131 during the sum check process);
When the subtraction processing by the sum value subtracting unit is completed for all information stored in the predetermined storage area, the subtraction result set in the predetermined bit area (for example, zero flag) in the flag register is displayed. A gaming machine comprising sum value determination means (for example, S134 during sum check processing) for determining whether or not an abnormality has occurred based on corresponding data.

In the gaming machine of the 22nd invention,
The sum value calculation means executes a specific instruction (for example, a POP instruction) when adding the information stored in the predetermined storage area, thereby acquiring information stored for 2 bytes continuously. And updating the information of the read start address of the information by 2 bytes,
The sum value subtracting means executes the specific instruction when subtracting the information stored in the predetermined storage area from the sum value generated at the time of occurrence of power interruption, thereby continuously storing 2 While acquiring and subtracting information for bytes, the information of the read start address of the information may be updated for two bytes.

Furthermore, in the gaming machine of the 22nd invention,
The arithmetic processing means has a stack pointer capable of setting an address of the predetermined storage area of the second storage means,
The specific instruction executed when the sum value calculation means adds the information stored in the predetermined storage area may be a dedicated instruction (for example, a POP instruction) for operating the stack pointer. Good.

  According to the gaming machine of the twenty-second invention, the capacity of processing programs and tables other than game play is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the ROM for the increased capacity It is possible to improve the playability by using the free space.

[Amusement machines of the 23rd to 26th inventions]
In a conventional gaming machine, there has been proposed a gaming machine equipped with a main control device that processes numerical data by using a stack pointer in an operation command (see, for example, JP-A-2005-237737).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twenty-third to twenty-sixth aspects of the present invention have been made to solve the above-described problems. The object of the twenty-third to twenty-sixth aspects is to reduce the capacity of processing programs and tables managed by the main control circuit and to free up ROM in the main control circuit. An object of the present invention is to provide a gaming machine capable of increasing the capacity and enhancing the game playability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above problems, according to a twenty-third aspect, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means executes a predetermined instruction (for example, a “BITQ” instruction, a “SETQ” instruction, an “LDQ” instruction, etc.) that can perform address designation in the second storage means by using the extension register. A gaming machine characterized by being capable.

  In the gaming machine of the twenty-third invention, a part of the address that can be specified by the extension register may be a higher-order address value constituting the address.

  In order to solve the above-mentioned problems, in the twenty-fourth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The arithmetic processing means includes:
In the process of checking the stop state of the display column,
A predetermined read instruction (for example, an “LDQ” instruction) capable of performing addressing in the second storage means by using the extension register is executed, and the predetermined stored in the second storage means Read the information indicating the status of the variable display in the display column
Next, a predetermined OR operation instruction (for example, an “ORQ” instruction) that can perform addressing in the second storage means is executed using the extension register, and is stored in the second storage means Reading information indicating the state of the variable display of the other one display column, and performing an OR operation on the information and information indicating the state of the variable display of the predetermined display column,
Thereafter, the execution of the predetermined logical sum operation instruction is repeated, and the logical sum operation of the result of the logical sum operation and the information indicating the change display state of each remaining display column is repeated, and the logical sum for all the display columns is performed. A game machine, characterized in that it is determined whether or not all display columns are in a stopped state based on a result of an arithmetic sum operation obtained when the operation is completed.

  In the gaming machine according to the twenty-fourth aspect, a part of the address that can be designated by the extension register may be an upper address value constituting the address.

  In order to solve the above-described problems, in the twenty-fifth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the internal winning combination determining operation by the internal winning combination determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
A dedicated register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
The internal winning combination determined by the internal winning combination determining means includes an internal winning combination for each setting whose winning probability changes in accordance with a setting value for adjusting an expected value for determining an internal winning combination related to the granting of a privilege. Is provided,
The arithmetic processing means includes:
In the process of determining the internal winning combination,
By setting a predetermined addition instruction (for example, “ADDQ” instruction) capable of performing address designation in the second storage means using the extension register, setting of the internal winning combination by setting to be a lottery target Add the current setting value to the top address of the area where the lottery value for each value is stored, and specify the address where the lottery value of the internal winning combination for each setting associated with the current setting value is stored, A gaming machine characterized by acquiring the lottery value.

  In the gaming machine of the twenty-fifth aspect, a part of the address that can be specified by the extension register may be a higher-order address value that constitutes the address.

  In order to solve the above-mentioned problems, the twenty-sixth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the variable display of the plurality of display columns is stopped by the stop control means, the symbol corresponding to the internal winning combination relating to the payout of the game medium on the determination line set across the plurality of display columns Bonus granting determination means (for example, winning search process) for determining whether or not the combination of is stopped and displayed,
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the privilege grant determination means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
The arithmetic processing means includes:
In the process of determining whether or not a combination of symbols corresponding to an internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line,
The game that can be given when a combination of symbols corresponding to an internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line by executing a predetermined read command (for example, “LDIN” command) It is characterized by simultaneously acquiring data on the number of paid-out media and determination data indicating the type of combination of symbols corresponding to the internal winning combination related to the payout of the game media, which is associated with the data on the number of paid-out To play.

  In the gaming machine of the twenty-sixth aspect of the invention, the calculation processing means determines whether or not a combination of symbols corresponding to an internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line. , Executing a predetermined determination instruction (for example, “JSLAA” instruction) that can execute a determination instruction, a process jump destination address designation instruction, and a process jump operation instruction with one instruction. It may be determined whether or not a combination of symbols corresponding to the internal winning combination is stopped and displayed.

  According to the gaming machines of the twenty-third to twenty-sixth aspects, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to improve the playability by utilizing the free space of the ROM for the capacity.

[Game machines of the 27th and 28th inventions]
In the conventional gaming machine, when an abnormality occurs in the data stored in the RAM of the main control unit, it is controlled to the RAM abnormality error state, the progress of the game is disabled, and the mode shifts to the setting change mode. There has been proposed a gaming machine in which when a set value is newly selected and set based on a setting change operation, the game progress disabled state is canceled and the game progress is enabled (for example, JP, A 2007-209810 publication).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twenty-seventh and twenty-eighth inventions have been made in order to solve the above-described problems, and an object of the invention is to reduce the capacity of processing programs and tables managed by the main control circuit, thereby freeing up ROM in the main control circuit. An object of the present invention is to provide a gaming machine capable of increasing the capacity and enhancing the game playability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above problems, according to a twenty-seventh aspect, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Data transmission means for transmitting command data related to the gaming operation (for example, S904 (communication data transmission processing) during interrupt processing);
A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for determining an internal winning combination related to the privilege grant;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the setting value changing operation or checking operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A start command generation means for generating first command data at the start of the setting value change process or the setting value confirmation process (for example, S43 during the setting change confirmation process);
An end-time command generation means for generating second command data at the end of the setting value change process or the setting value confirmation process (for example, S57 during the setting change confirmation process);
The generation process of the first command data executed by the start time command generation means and the generation process of the second command data executed by the end time command generation means are shared. A featured gaming machine.

In the gaming machine of the 27th invention,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
The arithmetic processing means includes:
When generating the first command data, a first value (for example, “005H”) is set in a predetermined register (for example, the L register) of the general-purpose register, and the generation process is executed.
When generating the second command data, a second value (for example, “004H”) may be set in a predetermined register of the general-purpose register, and the generation process may be executed.

  In order to solve the above-described problems, the twenty-eighth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Data transmission means for transmitting command data related to the gaming operation (for example, S904 (communication data transmission processing) during interrupt processing);
Communication data generation means for creating the command data (for example, setting change command generation storage processing and communication data storage processing);
A setting change confirmation means (for example, a setting change confirmation process) capable of executing a setting value change process and a setting value confirmation process for adjusting an expected value for determining an internal winning combination related to the privilege grant;
Arithmetic processing means (for example, the main CPU 101) that performs arithmetic processing for controlling command data generation operation by the communication data generation means and setting value change operation or confirmation operation by the setting change confirmation means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
At the start of the setting value change process or the setting value confirmation process, start command generation means for generating start command data (for example, S43 during the setting change confirmation process);
End-time command generation means (for example, S57 during the setting change confirmation process) that generates end-time command data at the end of the setting value change process or the setting value confirmation process;
The start command data generation process executed by the start command generation means and the end command data generation process executed by the end command generation means are shared,
The arithmetic processing means has a plurality of general-purpose registers in which a plurality of types of data are respectively stored when the arithmetic processing is executed by the arithmetic processing means.
The arithmetic processing means includes:
In the command data generation process,
Among a plurality of types of communication parameters constituting the command data, a communication parameter to be used is set in a corresponding general-purpose register among the plurality of general-purpose registers,
Storing the communication parameters used in the general-purpose register in a predetermined storage area (for example, a communication data temporary storage area) in the second storage unit;
If there is a communication parameter that is not used among the plurality of types of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter when the command data is generated is used as the communication parameter. Stored in the storage area of
A gaming machine characterized in that a sum value of the command data is generated based on data stored in the general-purpose register associated with a communication parameter.

  In the gaming machine of the twenty-eighth aspect, in the command data generation process, the value stored in the general-purpose register associated with the communication parameter is added to the value stored in the accumulator of the general-purpose register. Thus, the sum value of the command data may be generated, and the generated sum value may be stored in the predetermined storage area.

  According to the gaming machines of the twenty-seventh and twenty-eighth aspects, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit. The playability can be improved by utilizing the free space.

[Game machines of the 29th and 30th inventions]
In a conventional gaming machine, there is known a gaming machine that transmits a command from a gaming control board (main control circuit) to an effect control board (sub control circuit) (see, for example, JP-A-2002-360766).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The twenty-ninth and thirtieth inventions have been made to solve the above problems, and the object of the invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the ROM of the main control circuit. It is an object of the present invention to provide a gaming machine capable of increasing the free space and enhancing the playability by using the free space in the ROM for the increased capacity.

  In order to solve the above problems, in a twenty-ninth aspect of the invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Data transmission means for transmitting communication data relating to gaming operations (for example, S904 (communication data transmission processing) during interrupt processing);
Communication data generation and storage means (for example, communication data storage processing and communication) for creating the communication data and storing the generated communication data in a communication data storage area provided in a predetermined address range in the second storage means Data pointer update processing), and
The communication data generation storage means
When the communication data is sequentially stored in the communication data storage area from the storage area of the start address of the predetermined address range to the storage area of the last address, an update instruction, an upper limit determination instruction, and a determination branch instruction are combined. By executing a predetermined update instruction (for example, “ICPLD” instruction) that can be executed by one instruction, the current value of the communication data pointer, which is a parameter for addressing in the communication data storage area, and the last address And the communication data pointer is added and updated if the current communication data pointer is less than the upper limit, and the current communication data pointer is updated to the upper limit value. If it is above, the communication data pointer is below the communication data pointer corresponding to the head address. Gaming machine and changing the value.

  In the gaming machine according to a twenty-ninth aspect of the invention, the communication data generation and storage means stores the communication data pointer in the communication data storage area when the communication data pointer is changed to a lower limit value of the communication data pointer corresponding to the head address. The transmitted communication data may be invalidated.

  In order to solve the above problems, in the thirtieth aspect, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
In a counting process (for example, a medal payout number check process) of a predetermined data value related to the progress of a game operation,
When updating the value of the predetermined data, by executing a predetermined update instruction (for example, “DCPLD” instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, The predetermined data value is compared with the lower limit value of the predetermined data value, and if the current predetermined data value is greater than the lower limit value of the predetermined data value, the predetermined data value The game machine is characterized in that if the current value of the predetermined data is less than or equal to the lower limit value of the predetermined data value, the predetermined data value is held at the lower limit value.

  In the gaming machine of the thirtieth aspect, the predetermined data may be the number of payouts of the game medium.

  According to the gaming machines of the 29th and 30th inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to improve the playability by utilizing the free space of the ROM for the capacity.

[The gaming machine of the 31st invention]
In a conventional gaming machine, a gaming machine controlled by a timer subtraction process by software is known (see, for example, Japanese Patent Application Laid-Open No. 2004-041261).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  A thirty-first aspect of the present invention has been made to solve the above-described problems. The object of the thirty-first aspect is to reduce the capacity of processing programs and tables managed by the main control circuit and increase the free space in the ROM of the main control circuit. Another object of the present invention is to provide a gaming machine capable of enhancing the gameability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above-described problems, the thirty-first invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
In the count process (for example, timer update process) of the number of soft timers,
By executing a predetermined update instruction (for example, “DCPWLD” instruction) that can execute the update instruction, the lower limit determination instruction, and the determination branch instruction with one instruction, the current timer number of the soft timer and the lower limit of the timer number When the current timer number of the soft timer is larger than the lower limit value, the soft timer timer number is subtracted and updated, and if the current soft timer timer number is less than or equal to the lower limit value, A gaming machine, wherein the number of timers of the soft timer is held at the lower limit value.

  In a gaming machine according to a thirty-first aspect, the soft timer may be a 2-byte soft timer.

In the gaming machine of the thirty-first invention,
The arithmetic processing means includes fixed-cycle processing means (for example, interrupt processing that is repeatedly executed at a cycle of 1.1172 msec) that performs processing at a constant cycle.
The counting process of the number of timers by the soft timer is executed by the periodic processing means,
The elapsed time of the soft timer may be determined based on a cycle in which the periodic processing unit performs processing and the number of timers.

  Furthermore, in the gaming machine of the thirty-first aspect, the processing by the fixed period processing means is executed based on an interrupt signal generated by a timer function (for example, timer circuit 113) built in the arithmetic processing means. It may be.

  According to the gaming machine of the thirty-first invention, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit, and the increased capacity It is possible to provide a gaming machine capable of improving the game performance by using the free space of the ROM.

[Game machines of the thirty-second and thirty-third inventions]
In a conventional gaming machine, there is known a gaming machine that displays an internal lottery result with a 7-segment LED under the control of a main control circuit (see, for example, JP 2008-237337 A).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The thirty-second and thirty-third inventions have been made in order to solve the above-described problems, and an object of the invention is to reduce the capacity of processing programs and tables managed by the main control circuit and to free up the ROM of the main control circuit. An object of the present invention is to provide a gaming machine capable of increasing the capacity and enhancing the game playability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above problems, in a thirty-second invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
A plurality of 7-segment LEDs for notifying specific information about the game;
7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, 7-segment LED drive processing);
LED drive control means for controlling the drive operation of the plurality of 7-segment LEDs by the 7-segment LED drive means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The LED drive control means includes
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (eg, “LDW” command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by that.

In the gaming machine of the thirty-second invention,
The arithmetic processing means includes fixed-cycle processing means (for example, interrupt processing that is repeatedly executed at a cycle of 1.1172 msec) that performs processing at a constant cycle.
The periodic processing means is:
Count the number of executions of processing by the periodic processing means,
When the counted value is an even number, the control process by the LED drive control means may be executed.

  In order to solve the above-described problems, the thirty-third invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
An indication display (for example, an indication monitor) including a plurality of 7-segment LEDs for informing information related to a stop operation of the variable display of the plurality of display rows;
7-segment LED driving means for driving the plurality of 7-segment LEDs (for example, 7-segment LED drive processing);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the driving operation of the plurality of 7-segment LEDs by the 7-segment LED driving means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Dynamic drive control is performed on the plurality of 7-segment LEDs, a predetermined read command (eg, “LDW” command) is executed, and common selection data and cathode data are simultaneously output to the plurality of 7-segment LEDs. A gaming machine characterized by that.

In the gaming machine of the 33rd invention,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing unit executes the arithmetic processing, and that can specify a part of the address in the second storage unit by the stored data;
The arithmetic processing means executes a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means by using the extension register, thereby causing the second storage means to And an address of a stop operation instruction information storage area (for example, a navigation data storage area) that stores information related to the stop operation of the variable display of the plurality of display columns, and a variable display of the plurality of display columns Information regarding the stop operation may be stored in the stop operation instruction information storage area.

  According to the gaming machines of the thirty-second and thirty-third inventions, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM (first storage means) of the main control circuit. It is possible to improve the playability by utilizing the free space of the ROM for the capacity.

[Amusement machine of the 34th invention]
In a conventional gaming machine, a gaming machine in which a gaming control board (main control board) controls a reel unit is known (see, for example, Japanese Patent Laid-Open No. 2012-034914).

  By the way, in the rotation control of the reel (rotor), the lack of a sense of stability of the rotation operation of the reel may cause discomfort for the player (especially an expert), and the interest of the game may be cut off from the discomfort. There is. In this case, it is disadvantageous for the game store and may affect the sales of the game machine itself.

  A thirty-fourth aspect of the invention has been made to solve the above-described problems, and an object of the thirty-fourth aspect is to suppress a lack of a sense of stability of the rotation operation of the reel so as not to make the player uncomfortable. Is to provide a unique gaming machine.

  In order to solve the above problems, in a thirty-fourth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
A setting switch (for example, a setting key type switch 54) for initializing a predetermined area of the second storage means,
The arithmetic processing means includes:
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
The input state of the input port and the output state of the output port at the time of power failure at the time of power recovery are set, and if the display row is changing at the time of power failure, it is stored in the second storage means The game return that clears the variation control management information (for example, reel control management information) of the display row at the time of occurrence of power interruption, and sets information instructing the start of variation of the display row to the variation control management information of the display row And a means (for example, a game return process).

  In the gaming machine of the thirty-fourth invention, the arithmetic processing means executes processing by the game return means when the setting switch is in an off state, and when the setting switch is in an on state. The predetermined area of the second storage means may be initialized without executing the processing by the game return means.

  According to the gaming machine of the thirty-fourth aspect, it is possible to suppress the lack of stability of the reel rotation operation (display row change display operation) and to prevent the player from feeling uncomfortable.

[Game machine of the 35th invention]
In a conventional gaming machine, gaming machines that can display setting values (1 to 6) by operating a setting change switch are known (for example, JP 2008-245704 A and JP 2013-042870 A). See the official gazette).

  By the way, conventionally, while a game is being played in a game state advantageous to the player, such as during a bonus game or an ART game, a gaming machine in which the set value cannot be confirmed is mainly used. In such a gaming machine, if a bonus game or an ART game is started immediately after an illegal act called “Goto”, the illegal act cannot be confirmed, which may cause a disadvantage to the game store. is there.

  A thirty-fifth aspect of the invention is made to solve the above-mentioned problems, and its purpose is to provide information such as set values even while a game is being played in a game state advantageous to the player. It is to provide a gaming machine that can be confirmed and capable of suppressing illegal acts such as goto.

  In order to solve the above problems, in a thirty-fifth aspect of the invention, a gaming machine having the following configuration is provided.

A setting switch arranged at a predetermined position inside the gaming machine body;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Based on the internal winning combination determined by the internal winning combination determining means, advantageous gaming means (for example, bonus game described later) for executing a gaming state advantageous to the player;
A setting change confirmation means (for example, S233 during the medal acceptance / start check process) capable of changing or confirming a setting value related to the probability that an internal winning combination is determined according to the operation of the setting switch;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Game start determining means (for example, medal reception / start check processing) for determining whether or not the game can be started,
The setting change confirmation means can change a setting value related to a probability that an internal winning combination is determined according to an operation of the setting switch at power-on,
When it is determined by the game start determining means that the game can be started and the setting switch is operated, a setting value related to the probability that an internal winning combination is determined regardless of the gaming state is confirmed as the setting change. A gaming machine characterized in that it can be confirmed by processing by means.

  In the gaming machine of the thirty-fifth aspect, the setting change confirmation means initializes a predetermined storage area of the second storage means when the gaming machine is powered on with the setting switch being operated. The setting value may be changed, and the changed setting value may be stored in the second storage unit.

  According to the gaming machine of the thirty-fifth aspect of the invention, information such as a set value is confirmed even while a game is being played in a gaming state advantageous to the player, such as during a bonus game or an ART game. And can deter fraudulent acts such as Goto.

[Game machines of thirty-sixth and thirty-seventh inventions]
In a conventional gaming machine, a gaming machine having a display device for displaying the number of inserted medals is known (see, for example, JP-A-1999-178983).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The thirty-sixth and thirty-seventh inventions have been made in order to solve the above-described problems, and an object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the space in the ROM of the main control circuit. An object of the present invention is to provide a gaming machine capable of increasing the capacity and enhancing the game playability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above problems, in a thirty-sixth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Game medium detecting means (for example, medal sensor) for detecting the reception state of the game medium (for example, medal sensor input state);
Based on the reception state of the game medium detected in the previous process, whether or not the change state of the current reception state of the game medium detected by the game medium detection means is normal is determined by calculation processing. A gaming machine reception state determination means (for example, S255 to S258 during the medal insertion check process).

  In a gaming machine according to a thirty-sixth aspect of the invention, the gaming medium reception state determination means logically calculates a normal value of the gaming medium reception state that can be detected in the current process based on the gaming medium reception state detected in the previous process. It may be calculated by calculation, and the normal value may be compared with the current reception state of the game medium to determine whether or not the change mode of the reception state of the game medium is normal.

  In the gaming machine of the thirty-sixth aspect of the invention, the game medium reception state determination means determines whether or not the change state of the reception state of the game medium is normal based on 2 bits in 1-byte information. May be.

  In order to solve the above problems, in a thirty-seventh aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Display means (for example, a first LED to a third LED) for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media;
Arithmetic processing means (for example, main CPU 101, medal insertion processing) for performing arithmetic processing for controlling the notification operation by the display means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
Illumination control data for notifying information indicating the number of inserted game media in a display mode corresponding to the number of inserted game media is generated by logical operation processing based on the number of inserted game media. To play.

  In the gaming machine of the thirty-seventh aspect, in the logical operation process, the lighting control data of the game medium may be generated from 3-bit data of information in one byte.

  According to the gaming machines of the thirty-sixth and thirty-seventh inventions, the capacity of the processing program and table managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit. The playability can be improved by utilizing the free space.

[Game machines of the thirty-eighth and thirty-ninth inventions]
In a conventional gaming machine, a gaming machine in which a main board (main control board) and a sub board (sub control board) are connected by communication and a command is transmitted from the main board to the sub board is known (for example, a patent) No. 5725590).

  By the way, conventionally, communication between the main control board that performs control related to the game and the sub control board that performs control related to the effect is one-way communication from the main control board to the sub control board. There is a large gap between the start time of the main control board and that of the sub control board. Therefore, there is a possibility that the communication connection between the main control board and the sub-control board when the power is turned on becomes unstable.

  The thirty-eighth and thirty-ninth inventions have been made to solve the above-mentioned problems, and the purpose thereof is communication between the main control board (main control means) and the sub-control board (sub-control means) when the power is turned on. It is an object of the present invention to provide a gaming machine capable of stably operating the game machine.

  In order to solve the above problems, according to the thirty-eighth aspect, a gaming machine having the following configuration is provided.

Comprising main control means (for example, main control circuit 90) for transmitting communication data relating to gaming operations;
The main control means includes
During the control process by the main control means, an interrupt process is executed at a predetermined cycle, and when there is no communication data related to the game operation at the time of executing the interrupt process, an interrupt process execution means for transmitting a no-operation command (for example, , Interrupt processing)
Power recovery processing execution means (for example, power-on processing) for executing a predetermined power recovery processing at the time of power recovery,
The power recovery process execution means waits until the interrupt process execution means can execute the interrupt process after starting the power recovery process (for example, S7 and S8 during the power-on process). Done
The game machine characterized in that the interrupt process execution means executes the interrupt process and transmits the no-operation command to the sub-control means at the end of the standby by the power recovery process execution means.

In the gaming machine of the thirty-eighth invention,
The main control means includes
A timer circuit (for example, timer circuit 113) that measures the predetermined period;
An interrupt circuit (for example, an interrupt controller 112) that generates an interrupt signal for executing the interrupt processing based on a timeout signal of the timer circuit,
The power recovery processing execution means is
After setting the initial setting for generating the timeout signal in the predetermined cycle in the timer circuit, performing a process of waiting until the interrupt process can be executed by the interrupt process execution means,
The end of the standby may be determined based on whether or not the timer circuit has generated the timeout signal.

  In order to solve the above-described problems, the thirty-ninth invention provides a gaming machine having the following configuration.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
Communication data generation means for creating command data related to gaming operations (for example, setting change command generation storage processing and communication data storage processing);
During the control process by the arithmetic processing means, an interrupt process is executed at a predetermined cycle, and when there is no command data related to a game operation at the time of executing the interrupt process, an interrupt process execution means for transmitting a no-operation command (for example, , Interrupt processing)
Power recovery processing execution means (for example, power-on processing) for executing a predetermined power recovery processing at the time of power recovery;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The power recovery process execution means waits until the interrupt process execution means can execute the interrupt process after starting the power recovery process (for example, S7 and S8 during the power-on process). Done
The interrupt process execution means executes the interrupt process and transmits the no-operation command at the end of the standby by the power recovery process execution means,
The arithmetic processing means includes:
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing unit performs the arithmetic processing;
The command data includes a command type, a plurality of communication parameters, and a sum value.
The plurality of communication parameters are respectively assigned to the plurality of general purpose registers,
The communication data generating means
In accordance with the command type of the command data, after setting the communication parameter in the general-purpose register assigned to the communication parameter, the communication parameter set in the general-purpose register is stored in a predetermined storage in the second storage means Stored in an area (for example, a temporary communication data storage area)
Even if there is a communication parameter that is not used based on the command type of the command data among the plurality of communication parameters, the data stored in the general-purpose register associated with the unused communication parameter is used as the communication parameter. Stored in the predetermined storage area as
A gaming machine that generates a sum value of the command data based on the command type and data stored in the general-purpose register assigned to a communication parameter.

In the gaming machine of the thirty-ninth invention,
Power supply monitoring means (for example, a power supply monitoring port) for monitoring the state of the power supply voltage is provided,
The arithmetic processing means includes:
If the state of the power supply voltage is not stable, wait until the state of the power supply voltage is stable,
After initializing the timer circuit, serial communication circuit and random number circuit of the arithmetic processing means on condition that the state of the power supply voltage is stable, the predetermined area of the second storage means is used to 2 Check whether the storage means is normal,
The no-operation command may be transmitted on condition that the second storage means is normal.

  According to the gaming machine of the thirty-eighth and thirty-ninth inventions, communication between the main control board and the sub control board can be stably operated when the power is turned on.

[Game machines of the 40th and 41st inventions]
In a conventional gaming machine, the reel symbol variable display stop control is performed based on the internal winning combination and the player's stop operation, the winning determination is performed based on the combination of symbols, and the hopper (medal payout device) is determined based on the winning determination result. ) To control the medal payout (see Japanese Patent Application Laid-Open No. 2008-119498, for example).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The forty-first and forty-first inventions have been made in order to solve the above-mentioned problems, and an object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit to reduce the ROM of the main control circuit. An object of the present invention is to provide a gaming machine capable of increasing the capacity and enhancing the game playability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above-described problems, in a fortieth aspect, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the second storage means by the stored data;
By executing a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means by using the extension register, the detection result of the stop operation by the stop operation detecting means is obtained. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired;
When a stop operation of a player for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, it is arranged in the second storage means and the predetermined display row Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL) in FIG. 139)” for designating the address of the stop control data storage area for storing the variable display stop control data; A gaming machine characterized by comprising:

  In the gaming machine according to the 40th aspect, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  In order to solve the above-described problems, the forty-first invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the stop operation of the display row by the stop control means and the determination operation of the combination of symbols to be stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the second storage means by the stored data;
By executing a predetermined read instruction (for example, “LDQ” instruction) that can perform address designation in the second storage means by using the extension register, the detection result of the stop operation by the stop operation detecting means is obtained. Stop operation detection result acquisition means (for example, S714 during reel stop control processing) to be acquired;
When a stop operation of a player for a predetermined display row is detected by the stop operation detecting means, by executing the predetermined read command, it is arranged in the second storage means and the predetermined display row Stop control data storage area setting means (for example, source code “LDQ IX, wR1_CTRL- (wR2_CTRL-wR1_CTRL)” in FIG. 139) for designating the address of the stop control data storage area for storing the variable display stop control data;
In the process of preferentially determining the combination of symbols to be stopped and displayed on the determination line by the priority stop symbol determination means, a comparison determination command, a process jump destination address designation command, and a process jump operation command By executing a predetermined determination instruction (for example, “JCP” instruction) executable by the instruction, a combination of symbols corresponding to the internal winning combination to be determined is added to a specific display sequence (for example, currently determined) In addition, it is determined whether or not a predetermined symbol combination (for example, “ANY” combination) in which the stop symbol on the determination line in the right reel 3R) is arbitrary is included, and the internal winning combination to be determined When it is determined that the predetermined symbol combination is included in the corresponding symbol combination, a stop display of the symbol combination corresponding to the internal winning combination to be determined is displayed. Gaming machine, characterized in that it comprises any combination corresponding processing means for locking (e.g., S683 in attraction priority acquisition processing), the.

  In the gaming machine of the forty-first invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

  According to the gaming machines of the forty and forty-first aspects of the invention, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free capacity of the ROM of the main control circuit. The playability can be improved by utilizing the free space.

[Amusement machines of the 42nd to 44th inventions]
In a conventional gaming machine, there is known a gaming machine that performs symbol stop control using a pull-in priority table during symbol stop control (see, for example, JP 2007-175450 A).

  By the way, conventionally, as a restriction peculiar to the gaming machine described above, the program capacity of the main control circuit is restricted to a small capacity by a rule. Further, in recent years, the ROM capacity of the main control circuit has been squeezed due to the complexity of the game, and the capacity of processing programs and tables managed by the main control circuit is required to be reduced.

  The forty-second to forty-fourth aspects of the present invention have been made to solve the above-described problems. The object of the present invention is to reduce the capacity of processing programs and tables managed by the main control circuit and to free up ROM in the main control circuit. An object of the present invention is to provide a gaming machine capable of increasing the capacity and enhancing the game playability by utilizing the ROM free space corresponding to the increased capacity.

  In order to solve the above problems, in a forty-second invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and that can specify a part of the address in the second storage means by the stored data; ,
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing addressing in the second storage means using the extension register, the internal memory is arranged in the second storage means and the internal A winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) for specifying an address of a winning flag data storage area (for example, a hit request flag storage area) for storing the winning flag data corresponding to the winning combination;
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area specifying means (for example, S686 during the drawing priority order acquisition process) for specifying an address of the winning action flag storage area);
A gaming machine comprising: AND operation means (for example, S686 during the drawing priority order acquisition process) that performs an AND operation between the winning flag data and the corresponding winning flag data.

In the gaming machine of the forty-second invention,
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determination means, a combination of symbols corresponding to the internal winning combination to be determined is added to a specific display sequence (for example, currently being determined) When a predetermined symbol combination (for example, “ANY” role) is included in which the stop symbol on the determination line in the right reel 3R) is arbitrary,
The arithmetic processing means includes: an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, and the AND operation The AND operation processing by the means may not be executed.

  In order to solve the above-described problems, the forty-third invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When a plurality of types of internal winning combinations are determined by the internal winning combination determining means, if the combinations are of a plurality of types corresponding to the plurality of types of internal winning combinations, they are set across the plurality of display columns. A priority stop symbol determination means (for example, a drawing priority order acquisition process) for determining a combination of symbols to be stopped and displayed preferentially on the determined determination line;
Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling the determination operation of the combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and can specify a part of the address in the first storage means or the second storage means by the stored data ) And
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determining means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing addressing in the second storage means using the extension register, the internal memory is arranged in the second storage means and the internal A winning flag storage area specifying means (for example, S686 during the pull-in priority acquisition process) for specifying an address of a winning flag data storage area (for example, a hit request flag storage area) for storing the winning flag data corresponding to the winning combination;
By executing the predetermined read command, a winning flag data storage area for storing winning flag data corresponding to a combination of symbols arranged in the second storage means and stopped and displayed on the determination line (for example, A winning flag storage area specifying means (for example, S686 during the drawing priority order acquisition process) for specifying an address of the winning action flag storage area);
AND operation means for performing an AND operation between the winning flag data and the corresponding winning flag data (for example, S686 during the drawing priority acquisition process);
Priority data table acquisition means (for example, pull-in priority) that acquires a data table that defines the priority of the combination of symbols to be stopped and displayed among the combinations of the plurality of types of symbols by executing the predetermined read command S687) during the acquisition process.

In the gaming machine of the 43rd invention,
In the process of determining a combination of symbols to be preferentially stopped and displayed by the priority stop symbol determination means, a combination of symbols corresponding to the internal winning combination to be determined is added to a specific display sequence (for example, currently being determined) When a predetermined symbol combination (for example, “ANY” role) is included in which the stop symbol on the determination line in the right reel 3R) is arbitrary,
The arithmetic processing means includes: an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, an address specifying process for the winning flag data storage area by the winning flag storage area specifying means, and the AND operation The AND operation processing by the means may not be executed.

  In order to solve the above-mentioned problems, the forty-fourth invention provides a gaming machine having the following configuration.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
Error detection means for determining whether or not an illegal hit error has occurred (for example, an illegal hit check process);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the determination operation by the error detecting means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A general-purpose register in which data is stored when the arithmetic processing unit executes the arithmetic processing;
An extension register (for example, a Q register) that stores data when the arithmetic processing means executes the arithmetic processing, and that can specify a part of the address in the second storage means by the stored data; ,
In the process of determining whether or not an illegal hit error has occurred by the error detection means,
The arithmetic processing means includes:
By executing a predetermined read instruction (for example, “LDQ” instruction) capable of performing address designation in the second storage means by using the extension register, the plurality of instructions are arranged in the second storage means and the plurality A winning flag that specifies an address of a winning flag data storage area (for example, a winning action flag storage area) that stores winning flag data corresponding to a combination of symbols stopped and displayed on the determination line set across the display line Storage area designating means (for example, S781 during illegal hit check processing);
AND operation means for performing an AND operation between the winning flag data stored in the winning flag data storage area and the corresponding winning flag data indicating the internal winning combination (for example, S784 during illegal hit check processing) When,
Error determination means (for example, S785 during the illegal hit check process) for determining whether or not an illegal hit error has occurred based on the calculation result by the logical product calculation means;
A gaming machine, wherein the structure of a winning flag data storage area (for example, a winning request flag storage area) in which the winning flag data is stored is the same as that of the winning flag data storage area.

  In the gaming machine according to the 44th aspect of the invention, a part of the address that can be specified by the extension register may be an upper address value constituting the address.

Furthermore, in the gaming machine of the 44th invention,
The arithmetic processing means includes error processing means for performing error processing when the error detection means determines that there is an illegal hit error.
The error processing means may notify the illegal hit error in a visually recognizable manner and stop the game until the illegal hit error is canceled.

  According to the gaming machines of the forty-second to forty-fourth aspects, the capacity of processing programs and tables managed by the main control circuit is reduced to increase the free space in the ROM of the main control circuit. The playability can be improved by utilizing the free space.

[The gaming machine of the 45th invention]
In conventional gaming machines, gaming machines that transmit command data from a gaming control board (main control board) to an effect control board (sub-control board) are known (for example, Japanese Patent Application Laid-Open No. 2013-027655 and Japanese Patent Application Laid-Open No. 2014). -033751).

  By the way, in recent years, with diversification of game playability, there is a tendency that processing related to game play increases in effect control by the sub control circuit. For this reason, an illegal act called “Goto” that tampers communication data transmitted from the main control circuit to the sub-control circuit has occurred, causing damage to the game shop. On the other hand, conventionally, as proposed in, for example, the above-mentioned Japanese Patent Application Laid-Open No. 2014-033751 and the like, countermeasures for performing anti-going processing on transmission data in the main control circuit have also been implemented. However, there is a problem that the program capacity of the main control circuit is compressed by the addition of such anti-going processing.

  The forty-fifth aspect of the invention is made to solve the above-described problem, and its object is to suppress fraud without performing fraud prevention processing on transmission data and to perform main control by fraud prevention processing. It is an object of the present invention to provide a gaming machine that can eliminate the pressure on the circuit program capacity.

  In order to solve the above problems, in a forty-fifth aspect of the invention, a gaming machine having the following configuration is provided.

Data transmission means (for example, main control circuit 90) for transmitting communication data relating to the gaming operation;
Communication data generation means for generating the communication data (for example, communication data storage processing);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling communication data generating operation by the communication data generating means;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
The arithmetic processing means includes:
A plurality of general-purpose registers each storing a plurality of types of data when the arithmetic processing unit performs the arithmetic processing;
The arithmetic processing means includes:
In the communication data generation process by the communication data generation means,
A plurality of types of communication parameters constituting the communication data are assigned to the plurality of general purpose registers, respectively.
Among a plurality of types of communication parameters constituting the communication data, a communication parameter is set in a corresponding general-purpose register among the plurality of general-purpose registers based on the type of the communication data,
Storing the communication parameters set in the general-purpose register in a predetermined storage area (communication data temporary storage area) in the second storage means;
Among the plurality of types of communication parameters, data stored in a general-purpose register associated with an unused communication parameter when generating communication data is stored as a communication parameter in the predetermined storage area,
A gaming machine that generates a sum value of the communication data based on data set in the plurality of general-purpose registers according to the plurality of types of communication parameters.

  In the gaming machine of the forty-fifth aspect of the present invention, the communication data generating means sets the communication parameters set in the plurality of general purpose registers when there is no free space in the predetermined storage area in the second storage means. You may make it complete | finish the production | generation process of communication data, without storing in the predetermined storage area in the said 2nd memory | storage means.

  According to the gaming machine of the forty-fifth aspect of the present invention, fraudulent acts can be suppressed without performing fraud prevention processing on transmission data (communication data), and pressure on the program capacity of the main control circuit due to fraud prevention processing is also eliminated. be able to.

[The gaming machine of the 46th invention]
In a conventional gaming machine, a gaming machine having a function of updating the number of credits in accordance with the number of medals paid out by control of a main control circuit is known (see, for example, JP 2009-079777 A). ).

  Conventionally, in games during ART or bonuses, medals are often paid out. At this time, the payout interval for each medal is often controlled uniformly (fixed). In this case, useless waiting time occurs in the medal payout period. Therefore, for example, in a long-time game such as ART, the game period becomes uselessly long, which may be a mental burden on the player.

  A forty-sixth aspect of the invention has been made to solve the above-described problem, and an object thereof is a gaming machine capable of reducing useless waiting time and reducing a player's mental burden during a medal payout period. Is to provide.

  In order to solve the above problems, in a forty-sixth aspect of the invention, a gaming machine having the following configuration is provided.

A loading operation detecting means (for example, a BET switch 77) for detecting a gaming medium loading operation;
A start operation detecting means (for example, a start switch 79) for detecting a start operation by the player after the input operation is detected by the input operation detecting means;
Internal winning combination determining means (for example, internal lottery processing) for determining an internal winning combination with a predetermined probability based on detection of the start operation by the start operation detecting means;
Fluctuation display means (for example, three reels 3L, 3C, 3R) that includes a plurality of display rows and variably displays symbols provided in each display row based on detection of the start operation by the start operation detection means;
Stop operation detecting means (for example, stop switch board 80) for detecting stop operation by the player;
Stop control means (for example, reel stop control process) for stopping the change display of the symbol based on the determination result of the internal winning combination determining means and detection of the stop operation by the stop operation detecting means;
When the variable display of the plurality of display columns is stopped by the stop control means, the symbol corresponding to the internal winning combination relating to the payout of the game medium on the determination line set across the plurality of display columns Bonus granting determination means (for example, winning search process) for determining whether or not the combination of is stopped and displayed,
A game medium payout means for paying out the game medium when the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line by the bonus grant determination means (for example, , Winning check / medal payout processing),
Game medium storage means for storing the game medium (for example, a credit function);
Arithmetic processing means (for example, main CPU 101) for performing arithmetic processing for controlling the game medium payout operation by the game medium payout means,
The arithmetic processing means includes:
The game medium determined by the bonus granting determination means that the combination of symbols corresponding to the internal winning combination relating to the payout of the game medium is stopped and displayed on the determination line, and stored in the game medium storage means If the storage number of the game medium is less than the upper limit value, game medium addition means for adding 1 to the number of storage of the game medium (for example, S805 during the winning check / medal payout process);
After the game medium is added to the number of stored game media by the game medium adding means, the combination of symbols corresponding to the internal winning combination related to the payout of the game medium is stopped and displayed. A payout end determination means for determining whether or not the payout of the total payout number of game media has ended (for example, S807 during the winning check / medal payout process);
When the payout end determination means determines that the payout of the total payout amount of the game medium has not ended, a weight generation means (for example, a prize check A game machine having a medal payout process (S808).

In the gaming machine of the 46th invention,
The arithmetic processing means has interrupt processing execution means for executing interrupt processing at a predetermined cycle,
The interrupt processing by the interrupt processing execution means may be executed a predetermined number of times with the weight where the operation related to the game by the weight generation means is invalid.

  According to the gaming machine of the forty-sixth aspect, in the medal (game medium) payout period, it is possible to reduce useless waiting time and reduce the mental burden on the player.

[The gaming machine of the 47th invention]
In a conventional gaming machine, a program and a table are arranged in predetermined areas in a ROM mounted on a main control board (see, for example, JP 2012-110635 A).

  By the way, as in the gaming machine described in JP 2012-110635 A, the programs and tables that can be arranged in the ROM of the main control board are limited by the rules of the gaming machine industry, and the ROM of the main control board The program and table expandability is extremely poor.

  The forty-seventh aspect of the invention has been made to solve the above-described problems, and an object of the invention is to provide a gaming machine capable of enhancing the expandability of the program and table in the ROM of the main control board. .

  In order to solve the above problems, according to a 47th aspect of the invention, a gaming machine having the following configuration is provided.

Arithmetic processing means (for example, the main CPU 101) for performing arithmetic processing for controlling game operations;
First storage means (for example, main ROM 102) in which information necessary for execution of the arithmetic processing by the arithmetic processing means is stored;
Second storage means (for example, main RAM 103) for storing information necessary for execution of the arithmetic processing by the arithmetic processing means,
In the first storage means, a game storage area (for example, a game ROM area) in which information necessary for executing a process related to the game performance of a game executed by a player is stored, and the game storage An unspecified storage area (for example, an unspecified ROM area) in which information necessary for execution of processing that is arranged in an area different from the area and is not related to the game performance of the game executed by the player is provided. A gaming machine characterized by

In the gaming machine of the 47th invention,
In the second storage means,
A game temporary storage area (for example, a game RAM area) including a game work area and a game stack area in which information necessary for execution of processing related to the game playability of the game executed by the player is temporarily stored. )When,
The non-regulated work area and the non-regulated work area which are arranged in an area different from the game temporary storage area and temporarily store information necessary for execution of a process which is not related to game playability performed by the player An unspecified temporary storage area including a stack area (for example, an unspecified RAM area) may be provided.

Furthermore, in the gaming machine of the 47th invention,
The arithmetic processing means includes:
Has a stack pointer as a dedicated register,
The arithmetic processing means includes:
When executing the program stored in the non-standard storage area of the first storage unit, the address of the non-standard stack area of the second storage unit is set in the stack pointer,
When the program stored in the non-specified storage area of the first storage means is to be terminated, the game of the second storage means saved when the program stored in the non-standard storage area is executed An address of the stack area may be set in the stack pointer to return to the program stored in the game storage area of the first storage area.

  According to the gaming machine of the 47th aspect, the expandability of the program and table in the ROM of the main control board can be improved.

  DESCRIPTION OF SYMBOLS 1 ... Pachislot, 3L, 3C, 3R ... Reel, 4 ... Reel display window, 6 ... Information indicator, 11 ... Display device, 17L, 17C, 17R ... Stop button, 18 ... Sub display device, 71 ... Main control board, 72 ... Sub-control board, 90 ... Main control circuit, 91 ... Microprocessor, 101 ... Main CPU, 102 ... Main ROM, 103 ... Main RAM, 107 ... Arithmetic circuit, 114 ... First serial communication circuit, 115 ... Second serial Communication circuit 200 ... sub control circuit 201 ... sub CPU 201 301 ... first interface board 302 ... second interface board

Claims (2)

A gaming machine that variably displays a plurality of symbols in a plurality of display rows,
An internal winning combination determining means for determining an internal winning combination;
When a start operation is performed by the player, a symbol variation start control means for starting symbol variation display;
When a stop operation is performed by the player, on the basis of the internal winning combination determined by the internal winning combination determining means, symbol variation stop control means for stopping the variation display of the symbol,
Lottery state control means having a plurality of lottery states relating to an advantageous state advantageous to the player and capable of transition control between the plurality of lottery states based on a predetermined transition condition;
A preferential state in which the lottery state transition control by the lottery state control means is preferential, and a non-preferential state that is not the preferential state, the preferential state and the non-preferential state based on a specific transition condition Preferential state control means capable of transition control between,
Regardless of whether it is the preferential state or the non-preferential state, it is possible to determine whether or not to give the advantageous state based on the lottery state subjected to transition control by the lottery state control means A determination means,
The lottery state control means includes
In the non-preferential state, it is possible to determine that the lottery state is shifted to the more advantageous lottery state, and it is also possible to determine that the lottery state is shifted to the more disadvantageous lottery state,
In the preferential state, it is possible to determine to shift the lottery state to the more advantageous lottery state, and it is not possible to determine to shift the lottery state to the more unfavorable lottery state. Gaming machine.   The preferential state control means is capable of determining whether or not to shift to the preferential state when the lottery state control means does not determine to shift the lottery state in the non-preferential state. The gaming machine according to claim 1.

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