JP2018195970A - Digital filter, signal processing device and communication instrument - Google Patents

Abstract

To provide a digital filter, a signal processing device and a communication instrument that can remove a direct current component and a low frequency component while maintaining signal quality of a rectangular wave signal due to ΔΣ modulation.SOLUTION: A digital filter, a signal processing device and a communication instrument comprise: an up-sampler 21 that performs up-sampling of a bandpass ΔΣ modulated signal to a predetermined sample rate by inserting 0 between samples of a signal and that generates an up-sampling signal by inserting 0 between samples of the signal; and a delay unit 22 and a subtracter 23 that attenuate a direct current component and a frequency band near the direct current component by subtracting between the up-sampling signal at the present time obtained from the up-sampler 21 and the up-sampling signal before odd number samples.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a digital filter used when processing a digital signal, a signal processing device using the digital filter, and a communication device.

  A D / A converter that converts a digital signal into an analog signal has a high operation speed and is more expensive as a component having a larger quantization bit. For this reason, it is effective to reduce the D / A converter in order to reduce the cost of the apparatus and to make it popular. A ΔΣ (delta sigma) modulator is known as one of the techniques for generating various signals without using a dedicated component for performing D / A conversion (see, for example, Patent Document 1).

  When ΔΣ modulation is used, a desired wave signal can be converted into a simple rectangular wave. Therefore, a desired wave signal can be generated from output circuits of various digital circuits such as a switch circuit that can express only binary values, such as a general-purpose output port of a microcomputer and a high-speed SERDES (serializer / deserializer) output port. . In addition, the noise level in the band around the desired wave can be selectively attenuated by noise shaping. For this reason, it is possible to restore the signal while maintaining a good signal-to-noise ratio by using an appropriate filter circuit that passes only the desired wave band.

JP 2012-60568 A

  However, when using the ΔΣ modulation described above, there are the following problems. The bandpass type ΔΣ modulator is used when the frequency of the desired wave signal is relatively high with respect to the sampling frequency in ΔΣ modulation. However, in the band-pass ΔΣ modulator, a DC component or a low-frequency signal close to DC appears frequently in the converted rectangular wave signal.

  For this reason, in the band-pass type ΔΣ modulation, when a rectangular wave signal is amplified by an amplifier before the transmission path of the switch circuit and the filter circuit or before the filter circuit, between the switch circuit and the amplifier and between the amplifier and the filter circuit It is necessary to use a circuit capable of transmitting direct current and a band in the vicinity of direct current for the transmission line. Due to this restriction, an AC coupling circuit that can propagate a high-speed signal while maintaining the signal quality cannot be used, which hinders application to generation of a radio transmission signal.

  An object of the present invention is to provide a digital filter, a signal processing device, and a communication device capable of solving the above-described problems and removing DC and low-frequency components while maintaining the signal quality of a rectangular wave signal by ΔΣ modulation. It is in.

  In order to solve the above-mentioned problem, the invention of claim 1 generates an up-sampled signal by up-sampling a band-pass ΔΣ modulated signal to a predetermined sample rate by inserting 0 between signal samples. The up-sampling unit, the current up-sampling signal from the up-sampling unit, and the sub-sampling of the up-sampling signal before the odd-numbered sample, and the DC component of the band-pass ΔΣ modulated signal and the frequency band near the DC And a calculating means for attenuating the digital filter.

  In the invention of claim 1, the digital filter includes an upsampling unit and a calculation means. The up-sampling unit up-samples the band-pass ΔΣ modulated signal to a predetermined sample rate by inserting 0 between signal samples. The arithmetic means subtracts the signal of the current sample from the upsampling unit and the signal before the odd sample, and attenuates the direct current component of the band-pass ΔΣ modulated signal and the frequency band near the direct current.

  According to a second aspect of the present invention, in the digital filter according to the first aspect, the computing means includes a delay unit that delays the upsampling signal from the upsampling unit by an odd number of samples, and the upsampling signal from the upsampling unit. And an arithmetic unit for performing subtraction based on the delayed upsampling signal from the delay unit and attenuating a DC component of the band-pass ΔΣ modulated signal and a frequency band in the vicinity of the DC. .

  According to a third aspect of the present invention, in the digital filter according to the second aspect, the computing unit subtracts the upsampling signal delayed by the delay unit from the upsampling signal of the upsampling unit. .

  According to a fourth aspect of the present invention, a bandpass ΔΣ modulation of the input signal and a signal subjected to the bandpass ΔΣ modulation from the conversion unit are inserted to a predetermined sample rate by inserting 0 between signal samples. A band-pass ΔΣ-modulated signal obtained by subtracting an up-sampling signal that generates an up-sampling signal by sampling, a current up-sampling signal from the up-sampling part, and an up-sampling signal before an odd number of samples. A signal processing device comprising: an arithmetic means for attenuating a direct current component and a frequency band near the direct current.

  In the invention of claim 4, the digital filter of claim 1 is applied to the signal processing device. That is, the band-pass ΔΣ modulated signal from the conversion unit is added to the upsampling unit.

  According to a fifth aspect of the present invention, there is provided an up-sampling unit that generates an up-sampling signal by inserting a 0 between signal samples and up-sampling a signal subjected to bandpass ΔΣ modulation to a predetermined sample rate, and the up-sampling Calculating means for attenuating the DC component of the band-pass ΔΣ modulated signal and the frequency band in the vicinity of the DC by subtracting the current up-sampling signal from the unit and the up-sampling signal before the odd sample; And an analog unit that extracts an analog signal from the signal from the means.

  In the invention of claim 5, the digital filter of claim 1 is applied to the communication device. That is, the analog unit extracts an analog signal from the signal of the arithmetic means.

  According to the invention of claim 1, by performing up-sampling by inserting 0 into a signal subjected to bandpass ΔΣ modulation, and further subtracting the up-sampling signal and the up-sampling signal before odd samples, It is possible to remove DC and low frequency components contained in the bandpass ΔΣ modulated signal.

  According to the second and third aspects of the invention, upsampling is performed on the band-pass ΔΣ modulated signal by zero insertion by the upsampling unit, and the upsampling signal is further processed by the delay unit and the arithmetic unit. By performing the delay and the subtraction, it is possible to remove the DC and low frequency components included in the signal subjected to the bandpass ΔΣ modulation.

  According to the fourth aspect of the present invention, the band-pass ΔΣ modulated signal from the conversion unit is subjected to up-sampling by inserting 0, and further, subtraction between the up-sampling signal and the up-sampling signal before the odd-numbered samples is performed. To do. As a result, the DC and low-frequency components included in the bandpass ΔΣ modulated signal are removed, so that the DC offset is eliminated and the circuit can be operated normally. Furthermore, it is possible to suppress the deterioration of the SN ratio (signal to noise ratio) and the occurrence of distortion.

  According to the fifth aspect of the present invention, before the signal is output to the analog unit, the band-pass ΔΣ modulated signal is up-sampled by inserting 0, and the up-sampling signal and the odd-number sample up-sampling are performed. Subtract from the sampling signal. As a result, the DC and low-frequency components included in the band-pass ΔΣ modulated signal are removed. As a result, when rectangular wave transmission is performed in the analog unit, an ultra-high bandwidth circuit can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the signal processing apparatus by Embodiment 1 of this invention. It is a figure which shows the modulation signal by band pass delta-sigma modulation. It is a block diagram which shows a digital filter. It is a figure which shows the process in a digital filter. It is a figure which shows the order of a differentiation circuit, and the characteristic of a digital filter. It is a block diagram which shows the radio | wireless machine by Embodiment 2 of this invention.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
An example of the signal processing apparatus according to this embodiment is shown in FIG. The signal processing apparatus includes a bandpass (BP) ΔΣ (delta sigma) converter 10 and a digital filter (HPF) 20.

  The bandpass ΔΣ converter 10 performs bandpass ΔΣ modulation on the n-bit (bit) input signal to generate a bandpass ΔΣ modulation signal composed of a 1-bit pulse train. The band-pass ΔΣ modulation can secure a large SNR (Signal to Noise Ratio) and a band with an output of 1 bit (or at most several bits), and can simplify the circuit. The bandpass ΔΣ converter 10 sends the generated bandpass ΔΣ modulation signal to the digital filter 20.

  The digital filter 20 is a multirate high pass filter (Multirate High Pass Filter). The digital filter 20 uses the bandpass ΔΣ modulation signal from the bandpass ΔΣ converter 10 as an input signal. As described above, the modulation signal subjected to the bandpass ΔΣ modulation can secure a large SNR and band, and can simplify the circuit configuration. However, in the bandpass ΔΣ modulation, as shown in FIG. 2, the levels of DC (direct current) and low frequency components close to DC increase. Therefore, the digital filter 20 removes DC and low frequency components included in the bandpass ΔΣ modulation signal.

  For this purpose, the digital filter 20 includes an upsampler 21, a delay device 22, and a subtractor 23, as shown in FIG.

  The upsampler 21 is a bandpass ΔΣ modulation signal from the preceding bandpass ΔΣ converter 10 and receives as input a bandpass ΔΣ modulation signal sampled at the sampling frequency fs. The upsampler 21 performs the following processing on this bandpass ΔΣ modulation signal. First, the up-sampler 21 up-samples the band-pass ΔΣ modulation signal with an up-sampling frequency m · fs obtained by increasing the sampling frequency fs of the band-pass ΔΣ modulation signal by an integer m. In this embodiment, the integer m is 2 and the upsampling frequency is 2fs.

That is, the upsampler 21 inserts 0 (zero) into the A signal by upsampling with the upsampling frequency 2fs as shown in FIG. 4 with respect to the sample of the sampling frequency fs. In FIG. 4, the A signal (FIG. 3) is an input signal input to the upsampler 21, that is, a modulation signal subjected to bandpass ΔΣ modulation. X ₁ , X ₂ and X ₃ of the A signal represent each sample sampled at the sampling frequency fs, and the sample value is 0 or 1. A B signal (FIG. 3) is an upsampling signal output from the upsampler 21 and represents a state in which the upsampler 21 has inserted 0 (zero) by upsampling.

Thus, the upsampler 21 inserts 0 (zero) between samples by upsampling the sampling frequency fs with the upsampling frequency 2fs. As a result, as shown in FIG. 4, 0 (zero) is inserted after samples X ₁ , X ₂ , and X ₃ .

  The delay device 22 delays and outputs the upsampling signal from the upsampler 21. The delay amount by the delay device 22 is set to an odd sample time. As a result, the delay unit 22 delays the B signal, which is an upsampling signal, by an odd number of sample times and sends the delayed signal to the subtracter 23. In this embodiment, the delay amount is 3 samples. That is, the delay device 22 delays the upsampling signal from the upsampler 21 by 3 samples and generates a delayed signal. Thereby, the delay device 22 generates a delay signal such that one of the up-sampling signal from the up-sampler 21 and the generated delay signal becomes zero.

The subtracter 23 forms an odd-order differentiation circuit together with the delay unit 22. The subtracter 23 performs subtraction, that is, differentiation, by subtracting the delay signal from the delay device 22 from the upsampling signal (B signal) from the upsampler 21. This state is shown in the C signal of FIG. The C signal is for explaining the processing in the subtracter 23. The delayed signal from the delay unit 22 input to the subtracter 23 is delayed by 3 samples when the signal is input to the subtractor 23. Accordingly, the subtraction indicated by the arrow C1, the point of input of signals from the up-sampler 21, i.e. the signal sample at the present time is X _3. At the same time, since it is 3 samples before the signal from the delayer 22 0 (zero) is input to the subtracter 23 at the present time, D signal indicating the subtraction result is 1bit become X _3. Further, the subtraction of the arrow C2, since the current is 0 is (zero) 3 samples ago _{X 2,} D signal indicating the subtraction result is 1bit become -X _2.

  Such a differentiation circuit is an HPF (High Pass Filter) that can be realized with the simplest configuration in a discrete-time filter. Here, the order of the subtracter 23 and the characteristics of the digital filter 20 are shown in FIG. The sampling frequency fs is the sampling frequency of the input signal. Since the upsampling 21 in the previous stage performs double upsampling, the frequency characteristic is accompanied by a Sinc function characteristic such that the level becomes 0 (zero) at 2 fs. In this embodiment, since the center frequency of the desired wave band is fs / 4, it is necessary to reduce the attenuation of this band as much as possible. In addition, the odd-order differentiation circuit composed of the delay unit 22 and the subtracter 23 cannot make the output equal to the number of bits of the input signal unless it is of odd order. Therefore, the order of the most basic odd-order differentiation circuit applicable to the bandpass ΔΣ modulator to be created is 3. If the analog front-end circuit is more advantageous, the orders can be increased to the fifth and seventh orders.

  In this way, an odd-order differentiating circuit composed of the delay device 22 and the subtractor 23 is an odd number in the up-sampling signal in which 0 (zero) is inserted between the samples of the input signal and up-sampled to the double sampling rate. Perform the following differentiation. That is, in this embodiment, the third order differentiation is performed by subtracting the signal input three samples ahead and the signal input at the present time. As a result, one of the computation targets in the subtracter 23 is always 0 (zero), so that the number of bits of the output signal from the subtracter 23 can be made equal to the number of bits of the input signal to the subtracter 23. . The subtractor 23 sends the signal generated by such differentiation, that is, the signal from which the DC and low frequency components are removed while maintaining the signal quality of the bandpass ΔΣ modulation signal to the next stage as an output signal.

  The above is the configuration of the signal processing device. Next, the operation of this signal processing device will be described. In this signal processing apparatus, the bandpass ΔΣ converter 10 performs bandpass ΔΣ conversion on the input signal and sends a bandpass ΔΣ modulation signal to the digital filter 20.

  In the digital filter 20, an odd-order differentiation circuit is formed, in which the first stage includes a secondary upsampler 21 and the second stage includes a delay device 22 and a subtractor 23. The upsampler 21 upsamples the input signal at a sampling rate twice, and outputs a signal in which 0 (zero) is inserted between samples.

  The subtractor 23 and the delay unit 22 perform odd-order differentiation on the signal from the upsampler 21 in which 0 (zero) is inserted. As a result, since one of the computation targets is always 0 (zero), the number of bits of the output signal can be made equal to the number of bits of the input signal. The subtracter 23 sends a signal obtained by removing DC and low frequency components from the bandpass ΔΣ modulation signal to the next stage as an output signal.

  Thus, according to this embodiment, since the DC and low frequency components are removed from the bandpass ΔΣ modulation signal, it is possible to prevent the generation of a long pulse waveform and to set the number of bits of the output signal to the input signal. It can be equal to the number of bits. Further, the DC offset is eliminated and the AC coupling circuit can be operated normally. Furthermore, it is possible to suppress the deterioration of the SN ratio (signal to noise ratio) and the occurrence of distortion.

(Embodiment 2)
An example of the radio device 50 according to this embodiment is shown in FIG. The radio device 50 includes a signal generation unit 51, a bandpass ΔΣ converter (BPΔΣ) 52, a digital filter (HPF) 53, an analog unit 54, and an antenna 55.

  The signal generation unit 51 generates a signal transmitted by the wireless device 50. The signal generation unit 51 converts the transmission signal into an n-bit parallel signal and sends it to the bandpass ΔΣ converter 52.

  The bandpass ΔΣ converter 52 is the same as the bandpass ΔΣ converter 10 of the first embodiment. That is, the bandpass ΔΣ converter 52 performs bandpass ΔΣ modulation on the n-bit signal from the signal generation unit 51 to generate a bandpass ΔΣ modulation signal composed of a 1-bit pulse train. The bandpass ΔΣ converter 52 sends the generated bandpass ΔΣ modulation signal to the digital filter 53.

  The digital filter 53 is the same as the digital filter 20 of the first embodiment. That is, in the band-pass ΔΣ modulation signal from the digital filter 53, the level of DC and a low frequency component close to DC increases. Therefore, the digital filter 53 removes DC and low frequency components included in the bandpass ΔΣ modulation signal. Then, the digital filter 53 sends the same 1-bit signal as the input bandpass ΔΣ modulation signal to the analog unit 54.

  The analog unit 54 performs power amplification of the signal from the digital filter 53, filter processing using a bandpass filter, and the like, and generates a desired wave signal. Then, the analog unit 54 sends the generated desired wave signal to the antenna 55. When the antenna 55 receives the desired wave signal, the antenna 55 transmits the desired wave.

  Thus, according to this embodiment, the low-frequency component is removed by the digital filter 53 before output to the analog unit 54. Therefore, in the analog front-end circuit, when performing rectangular wave transmission, an ultra-high band circuit is used. It can be made unnecessary.

  As mentioned above, although each embodiment of this invention has been described in detail, the specific configuration is not limited to this embodiment, and even if there is a design change or the like without departing from the scope of this invention, It is included in this invention.

10 Bandpass ΔΣ Converter (Conversion Unit)
20 Digital filter 21 Upsampler (Upsample part)
22 Delay device
23 Subtractor (Calculation unit / Calculation means)
50 Radio equipment (communication equipment)
51 Signal Generator 52 Bandpass ΔΣ Converter 53 Digital Filter 54 Analog Unit 55 Antenna

Claims (5)

An up-sampling unit for generating an up-sampling signal by inserting a band-pass ΔΣ modulated signal into a predetermined sample rate by inserting 0 between signal samples;
Arithmetic means for subtracting the current up-sampling signal from the up-sampling unit and the up-sampling signal before the odd sample to attenuate the DC component of the band-pass ΔΣ modulated signal and the frequency band near the DC; ,
A digital filter comprising: The computing means is
A delay unit that delays the upsampling signal from the upsampling unit by an odd number of samples;
Subtraction based on the upsampling signal from the upsampling unit and the delayed upsampling signal from the delay unit to attenuate the DC component of the bandpass ΔΣ modulated signal and the frequency band near the DC And
The digital filter according to claim 1, further comprising: The arithmetic unit subtracts the delayed upsampling signal of the delay unit from the upsampling signal of the upsampling unit,
The digital filter according to claim 2. A converter that performs bandpass ΔΣ modulation of the input signal;
An up-sampling unit that generates an up-sampling signal by inserting 0 between signal samples and up-sampling a signal subjected to bandpass ΔΣ modulation from the conversion unit to a predetermined sample rate;
Arithmetic means for subtracting the current up-sampling signal from the up-sampling unit and the up-sampling signal before the odd sample to attenuate the DC component of the band-pass ΔΣ modulated signal and the frequency band near the DC; ,
A signal processing apparatus comprising: An up-sampling unit for generating an up-sampling signal by inserting a band-pass ΔΣ modulated signal into a predetermined sample rate by inserting 0 between signal samples;
Arithmetic means for subtracting the current up-sampling signal from the up-sampling unit and the up-sampling signal before the odd sample to attenuate the DC component of the band-pass ΔΣ modulated signal and the frequency band near the DC; ,
An analog unit for extracting an analog signal from the signal from the arithmetic means;
A communication device comprising:

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