JP2018195773A - Wiring board - Google Patents

Abstract

To provide a circuit board capable of suppressing an increase in transmission loss when single-ended transmission is performed using a differential output.SOLUTION: A signal transmitting/receiving circuit is connected to one end of a first transmission line, and the other end is terminated with a terminating resistor. A signal transmitting/receiving circuit is connected to one end of a second transmission line. The second transmission line includes a parallel running portion which runs parallel to the first transmission line and constitutes a differential transmission line at an end portion side connected to the signal transmission/reception circuit and includes a non-parallel running portion that does not run parallel to the first transmission line between the other end portion and the parallel running portion. An impedance matching structure for matching the characteristic impedance between the parallel running portion and the non-parallel running portion is provided.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a wiring board on which a transmission line is formed.

  As interface standards used in the in-vehicle market, standards called SerDes such as “FPD-LinkIII” and “GMSL” have been proposed. Non-Patent Document 1 below is a description of an evaluation board for FPD-LinkIII, which is one of SerDes circuit modules that mutually convert serial data and parallel data. The peripheral circuit of the serializer (serialized IC) is disclosed on page 21 of Non-Patent Document 1, and the peripheral circuit of the deserializer (parallelized IC) is disclosed on page 25. The signal transmitted from the serializer is transmitted through the coaxial cable and received by the deserializer. Further, power for driving the serializer circuit module is supplied from the deserializer circuit module to the serializer circuit module through a coaxial cable.

  The output from the serializer is a two-line differential output, and a single-core coaxial line is used for the cable. For this reason, single-ended transmission is performed by passing one of the operation outputs from the serializer through a coaxial line and terminating the other output at 50Ω.

DS90UB913A-CXEVM & DS90UB914A-CXEVM User's Guide (http://www.tij.co.jp/en/lit/ug/snlu135b/snlu135b.pdf)

  Transmission loss occurs when a differential signal is converted into a single-ended signal. An object of the present invention is to provide a circuit board capable of suppressing an increase in transmission loss when single-ended transmission is performed using a differential output.

A wiring board according to a first aspect of the present invention provides:
A first transmission line in which a signal transmitting / receiving circuit is connected to one end and the other end is terminated with a termination resistor;
The signal transmission / reception circuit is connected to one end, and includes a parallel running part that forms a differential transmission path in parallel with the first transmission path on the end connected to the signal transmission / reception circuit, A second transmission line including a non-parallel running part that does not run parallel to the first transmission path between an end of the parallel running part and the parallel running part;
An impedance matching structure for matching characteristic impedances of the parallel running portion and the non-parallel running portion;

  By impedance matching between the parallel portion and the non-parallel portion by the impedance matching structure, reflection of the signal transmitted through the second transmission path is suppressed. By suppressing reflection, an increase in transmission loss can be suppressed.

In addition to the configuration of the wiring board according to the first aspect, the wiring board according to the second aspect of the present invention includes:
The width of the non-parallel portion is wider than the width of the parallel portion, and the impedance matching structure is realized by the difference in width between the non-parallel portion and the parallel portion.

  The characteristic impedance of the parallel running portion is affected by the first transmission path that runs parallel to the parallel running portion. On the other hand, the characteristic impedance of the non-parallel running portion is hardly affected by the first transmission path. If the conditions other than the presence / absence of the first transmission path running in parallel are the same, the characteristic impedance of the non-parallel portion becomes higher than the characteristic impedance of the parallel portion. If the width of the non-parallel portion is increased, the parasitic capacitance of the non-parallel portion increases and the parasitic inductance decreases. As a result, the characteristic impedance of the non-parallel running portion is reduced. By reducing the characteristic impedance of the non-parallel portion, it is possible to match the characteristic impedance of the parallel portion.

In addition to the configuration of the wiring board according to the second aspect, the wiring board according to the third aspect of the present invention includes:
An interval between the parallel running portion and the first transmission path is constant;
The non-parallel running part includes a part in which the distance from the first transmission path is widened in a part of a region continuous to the parallel running part as the distance from the end connected to the signal transmission / reception circuit increases. Has characteristics.

  Since the distance between the non-parallel running portion and the first transmission path increases as the distance from the end connected to the signal transmission / reception circuit increases, the relative positions of the first transmission path and the second transmission path with respect to each other The relationship changes gradually. This makes it easy to match the characteristic impedance between the non-parallel running portion and the parallel running portion of the second transmission path.

In addition to the configuration of the wiring board according to the first aspect, the wiring board according to the fourth aspect of the present invention includes:
In addition, it has a ground plane,
The distance from the non-parallel portion to the ground plane is different from the distance from the parallel portion to the ground plane, the distance from the non-parallel portion to the ground plane, and the distance from the parallel portion to the ground plane. The impedance matching structure is realized by the difference from the distance up to.

  The characteristic impedance can be adjusted by changing the distance from the transmission line to the ground plane. Signal reflection can be suppressed by adjusting the distance to the ground plane so that the characteristic impedance of the non-parallel portion matches the characteristic impedance of the parallel portion.

  By impedance matching between the parallel portion and the non-parallel portion by the impedance matching structure, reflection of the signal transmitted through the second transmission path is suppressed. By suppressing reflection, an increase in transmission loss can be suppressed.

FIG. 1 is a schematic equivalent circuit diagram of a serializer circuit module, a deserializer circuit module, and a coaxial cable that connects the serializer circuit module and the serializer circuit module mounted on the wiring board according to the first embodiment. FIG. 2A is a schematic plan view of a wiring board according to a first reference example, and FIG. 2B is a schematic plan view of a wiring board according to a second reference example. 3A is a schematic plan view of the wiring board according to the first embodiment, and FIGS. 3B and 3C are cross-sectional views taken along one-dot chain line 3B-3B and one-dot chain line 3C-3C in FIG. 3A, respectively. FIG. 4 is a schematic plan view of the wiring board according to the second embodiment. 5A is a schematic plan view of the wiring board according to the third embodiment, and FIGS. 5B and 5C are cross-sectional views taken along one-dot chain line 5B-5B and one-dot chain line 5C-5C in FIG. 5A, respectively. 6A is a schematic plan view of a wiring board according to a fourth embodiment, and FIG. 6B is a cross-sectional view taken along one-dot chain line 6B-6B in FIG. 6A. 7A is a schematic plan view of a wiring board according to a fifth embodiment to be simulated, FIG. 7B is a cross-sectional view taken along one-dot chain line 7B-7B in FIG. 7A, and FIG. 7C is a wiring according to the first comparative example. FIG. 7D is a schematic plan view of a wiring board according to a second comparative example. FIG. 8 is a graph showing the calculation result of the characteristic impedance of the transmission path of the wiring board according to the fifth embodiment.

[First embodiment]
The circuit module according to the first embodiment will be described with reference to FIGS. 1 to 3C.

  FIG. 1 is a schematic equivalent circuit diagram of an apparatus including a serializer circuit module 10, a deserializer circuit module 30, and a coaxial cable 50 connecting the serializer circuit module 10 and the serializer circuit module 30 mounted on the wiring board according to the first embodiment. A serializer circuit module 10 on which the serializer 11 and its peripheral circuits are mounted and a deserializer circuit module 30 on which the deserializer 31 and its peripheral circuits are mounted are connected via a coaxial cable 50.

  A parallel signal is input from the image sensor 60 to the serializer 11. The serializer 11 converts the input parallel signal into a serial signal. This serial signal is input to the deserializer 31 through the coaxial cable 50. The deserializer 31 converts the input serial signal into a parallel signal and transmits the parallel signal to an electronic component 61 such as an electronic control unit (ECU) or a display.

  The serializer circuit module 10 and the deserializer circuit module 30 have the same basic circuit configuration, although the mounted signal transmitting / receiving element is the serializer 11 or the deserializer 31. Hereinafter, the configuration of the serializer circuit module 10 will be described, and redundant description of the configuration of the deserializer circuit module 30 will be omitted.

  The serializer circuit module 10 includes a wiring board, a serializer 11 mounted on the wiring board, and other peripheral circuit components. A ground plane 20, a first transmission path 21, a second transmission path 22, and a power supply line 23 are provided on the wiring board. The serializer 11 converts the input parallel signal into a serial signal and outputs a differential signal from the data output terminals D1 and D2. One data output terminal D1 is connected to the ground plane 20 via the first transmission path 21 and the termination resistor R1. The other data output terminal D2 is connected to the inner conductor 51 of the coaxial cable 50 via the second transmission path 22. Capacitors C1 and C2 are inserted in series in the first transmission path 21 and the second transmission path 22, respectively. Capacitors C1 and C2 cut direct current and pass high-frequency signals.

  One differential signal output from the data output terminal D <b> 2 is transmitted to the inner conductor 51 of the coaxial cable 50 via the second transmission path 22. The other operation signal output from the data output terminal D1 is transmitted through the first transmission path 21. Since the first transmission path 21 is terminated by the termination resistor R1, signal reflection hardly occurs.

  An outer conductor 52 of the coaxial cable 50 is connected to the ground plane 20. A second transmission path 22 between the inner conductor 51 of the coaxial cable 50 and the capacitor C2 is connected to the power supply line 23 via the inductor L1. The inductor L1 cuts the high frequency signal and passes the direct current.

  Power is supplied from a DC power supply 55 to the power supply line 43 of the deserializer circuit module 30. The power supply line 43 of the deserializer circuit module 30 is connected to the power supply line 23 of the serializer circuit module 10 via the inner conductor 51 of the coaxial cable 50 with a low impedance in a direct current manner. The ground plane 40 of the deserializer circuit module 30 is connected to the ground plane 20 of the serializer circuit module 10 via the outer conductor 52 of the coaxial cable 50 with a low impedance. Power is supplied from the DC power supply 55 to the serializer circuit module 10 via the deserializer circuit module 30 and the coaxial cable 50.

FIG. 2A is a schematic plan view of a wiring board according to a first reference example. In the first reference example, the first transmission path 21 and the second transmission path 22 respectively connected to the data output terminals D1 and D2 of the serializer 11 constitute a differential transmission path. The differential signal output from the serializer 11 is differentially transmitted through the first transmission path 21 and the second transmission path 22. The characteristic impedance Z ₀ of the second transmission path 22 is the parasitic inductance of the second transmission path 22, between the second transmission path 22 and the ground plane 20, and the first transmission line adjacent to the second transmission path 22. It is determined by the parasitic capacitance with the transmission line 21. When the inductance per unit length of the second transmission path 22 is represented by L and the parasitic capacitance per unit length is represented by C, the characteristic impedance Z ₀ is represented by the following equation.

  FIG. 2B is a schematic plan view of a wiring board according to a second reference example. In the second reference example, one differential signal output from one data output terminal D2 is transmitted to the coaxial cable via the second transmission path 22, and is transmitted single-ended through the coaxial cable. The first transmission path 21 through which the other differential signal output from the other data output terminal D1 is transmitted is terminated with a termination resistor R1. Capacitors C1 and C2 are inserted in series in the first transmission path 21 and the second transmission path 22, respectively.

  The second transmission path 22 includes a portion (hereinafter referred to as a parallel running portion) 22A that runs parallel to the first transmission path 21 and a portion (hereinafter referred to as a non-parallel running portion) 22B that does not run parallel. The Parasitic capacitance C is generated between the parallel running portion 22 </ b> A and the ground plane 20 and between the first transmission path 21. However, in the non-parallel portion 22 </ b> B, the parasitic capacitance between the first transmission path 21 and the first transmission line 21 is almost negligible, and the parasitic capacitance C is generated substantially only between the ground plane 20. For this reason, the parasitic capacitance per unit length of the non-parallel portion 22B is smaller than the parasitic capacitance per unit length of the parallel portion 22A.

Assuming that the parasitic inductance L per unit length of the second transmission path 22 is constant in the length direction, the characteristic impedance Z ₀ of the non-parallel portion 22B is reduced due to the parasitic capacitance C being reduced. greater than the characteristic impedance _{Z 0} of 22A. Since the parallel running portion 22A and the characteristic impedance Z ₀ in the non-parallel running portion 22B is not matched, defects such as reflection of the signal occurs at both boundaries.

  FIG. 3A is a schematic plan view of the wiring board according to the first embodiment. One end of the second transmission path 22 is connected to a data output terminal D2 of a signal transmission / reception circuit such as the serializer 11. The other end of the second transmission path 22 is connected to, for example, the inner conductor 51 of the coaxial cable 50 (FIG. 1). One end of the first transmission path 21 is connected to a data output terminal D1 of a signal transmission / reception circuit such as the serializer 11, and the other end is connected to the ground plane 20 (see FIG. 5) via a termination resistor R1 and a through hole 27. 1).

  The second transmission path 22 includes a parallel running portion 22A and a non-parallel running portion 22B. The parallel running portion 22 </ b> A is connected to the serializer 11 and runs parallel to the first transmission path 21. The non-parallel portion 22B is disposed between the end connected to the coaxial cable 50 (FIG. 1) and the parallel portion 22A, and does not run parallel to the first transmission path 21. The distance between the parallel portion 22A of the second transmission path 22 and the first transmission path 21 is constant, and a differential transmission path is configured by both. The wiring board according to the first embodiment has an impedance matching structure that matches the characteristic impedance of the parallel running portion 22A and the non-parallel running portion 22B. Here, “matching the characteristic impedance” does not necessarily mean that the characteristic impedance is completely matched, but means that the degree of mismatch of the characteristic impedance is reduced.

  Hereinafter, the impedance matching structure will be described. The non-parallel running portion 22B of the second transmission path 22 is thicker than the parallel running portion 22A. The non-parallel running portion 22B includes a tapered portion 22C whose width gradually decreases toward the parallel running portion 22A at a location connected to the parallel running portion 22A. The impedance matching structure is realized by the structure in which the width of the non-parallel portion 22B is different from the width of the parallel portion 22A, more specifically, the structure in which the non-parallel portion 22B is thicker than the parallel portion 22A. .

  3B and 3C are cross-sectional views taken along one-dot chain line 3B-3B and one-dot chain line 3C-3C in FIG. 3A, respectively. The wiring board includes a dielectric substrate 25, parallel running portions 22A and non-parallel running portions 22B of the second transmission path 22 formed on the upper surface, the first transmission path 21 and the ground plane 20 formed on the back surface. Including. As shown in FIG. 3B, a parasitic capacitance Ca is generated between the parallel portion 22A of the second transmission path 22 and the ground plane 20, and a parasitic capacitance is generated between the parallel portion 22A and the first transmission path 21. Cb is generated. A parasitic capacitance Cc is generated between the first transmission path 21 and the ground plane 20. As shown in FIG. 3C, a parasitic capacitance Cd is generated between the non-parallel portion 22 </ b> B of the second transmission path 22 and the ground plane 20. There is almost no parasitic capacitance between the non-parallel portion 22B and the first transmission path 21.

  Next, the reason why impedance can be matched by the impedance matching structure will be described.

  The combined parasitic capacitance between the parallel running portion 22A and the ground plane 20 is larger than the parasitic capacitance Ca. When the non-parallel portion 22B has the same width as the parallel portion 22A, the parasitic capacitance Cd generated in the non-parallel portion 22B is approximately equal to the parasitic capacitance Ca between the parallel portion 22A and the ground plane 20. Since the parasitic capacitance Ca is smaller than the combined parasitic capacitance of the parallel portion 22A, from the equation (1), the characteristic impedance of the non-parallel portion 22B having the same width as the parallel portion 22A is larger than the characteristic impedance of the parallel portion 22A. End up.

ここで、μ_０は伝送路を構成する材料の透磁率であり、ｗは伝送路の幅であり、ａは伝送路の長さであり、ｔは伝送路とグランドプレーンとの間隔である。伝送路の幅ｗを広げると、寄生インダクタンスＬが小さくなることがわかる。従って、非並走部分２２Ｂの寄生インダクタンスは並走部分２２Ａの寄生インダクタンスより小さい。 In the first embodiment, since the non-parallel portion 22B is thicker than the parallel portion 22A, the parasitic capacitance Cd of the non-parallel portion 22B is larger than the parasitic capacitance Ca of the parallel portion 22A. Further, the parasitic inductance L of the microstrip line can be expressed by the following equation.

Here, μ ₀ is the magnetic permeability of the material constituting the transmission line, w is the width of the transmission line, a is the length of the transmission line, and t is the distance between the transmission line and the ground plane. It can be seen that the parasitic inductance L decreases when the width w of the transmission line is increased. Therefore, the parasitic inductance of the non-parallel portion 22B is smaller than the parasitic inductance of the parallel portion 22A.

  As described above, when the width of the non-parallel portion 22B is increased, the parasitic capacitance is increased and the parasitic inductance is reduced as compared with the transmission path before being expanded. From the equation (1), the characteristic impedance of the non-parallel portion 22B is lower than the characteristic impedance of the transmission line before the width is increased. For this reason, by making the non-parallel portion 22B thicker than the parallel portion 22A, the characteristic impedance of the non-parallel portion 22B and the characteristic impedance of the parallel portion 22A are compared with the case where the non-parallel portion 22B has the same thickness as the parallel portion 22A. It becomes possible to approach. That is, the characteristic impedance of the non-parallel portion 22B can be matched with the characteristic impedance of the parallel portion 22A.

Next, the excellent effect of the wiring board according to the first embodiment will be described.
In the first embodiment, by matching the characteristic impedance of the non-parallel portion 22B of the second transmission path 22 to the characteristic impedance of the parallel portion 22A, the high frequency at the boundary between the parallel portion 22A and the non-parallel portion 22B. Signal reflection can be reduced. Thereby, an increase in transmission loss can be suppressed. A preferable widening amount of the width of the non-parallel portion 22B relative to the parallel portion 22A can be determined by simulation, an actual evaluation experiment, or the like.

  When the widths of the parallel running portion 22A and the non-parallel running portion 22B are discontinuously changed at the boundary between the two, noise is likely to be generated at the discontinuous portion. In the first embodiment, since the taper portion 22C is provided and the width is gradually and continuously changed, generation of noise can be suppressed.

[Second Embodiment]
Next, the wiring board according to the second embodiment will be described with reference to FIG. Hereinafter, the description of the configuration common to the wiring board according to the first embodiment will be omitted.

  FIG. 4 is a schematic plan view of the wiring board according to the second embodiment. In the first embodiment, after the first transmission path 21 (FIG. 3A) has run parallel to the parallel running portion 22A of the second transmission path 22, the first transmission path 21 is bent at a substantially right angle and terminated. The second transmission path 22 had a shape along one straight line. In the second embodiment, the distance G from the first transmission path 21 gradually increases as the non-parallel portion 22B moves away from the end connected to the serializer 11 in a part of the region that is continuous with the parallel portion 22A. A portion (hereinafter, referred to as an interval expanding portion) 22D that expands is included.

  The first transmission path 21 includes a spacing extension portion 21 </ b> D corresponding to the spacing extension portion 22 </ b> D of the second transmission path 22. The interval spreading portion 22D and the interval spreading portion 21D are line symmetric with respect to the axis of symmetry CL between the parallel running portion 22A and the first transmission path 21 running parallel thereto. The space spreading portions 22D and 21D are arranged obliquely so as to be separated from the symmetry axis CL as the distance from the parallel running portion 22A increases.

  The interval widening portion 22D gradually becomes thicker as it moves away from the parallel running portion 22A. The non-parallel running portion 22B in a region farther from the interval spreading portion 22D when viewed from the parallel running portion 22A is parallel to the symmetry axis CL, thicker than the parallel running portion 22A, and its width is constant. In the second embodiment, the impedance matching structure is realized by the configuration in which the gap extending portions 22D and 21D and the non-parallel running portion 22B are thicker than the parallel running portion 22A.

  Next, the excellent effect of the wiring board according to the second embodiment will be described. Also in the second embodiment, the characteristic impedance of the non-parallel portion 22B can be matched with the characteristic impedance of the parallel portion 22A by the impedance matching structure. In addition, since the interval spreading portions 22D and 21D are provided, the relative positions of the second transmission path 22 and the first transmission path 21 with respect to the length direction of the first transmission path 21 and the second transmission path 22 are described. The relationship changes gradually. As a result, an effect of facilitating impedance matching is obtained.

[Third embodiment]
Next, a wiring board according to a third embodiment will be described with reference to FIGS. 5A to 5C. Hereinafter, the description of the configuration common to the wiring board according to the first embodiment will be omitted.

  FIG. 5A is a schematic plan view of a wiring board according to a third embodiment. In the first embodiment, the first transmission path 21 and the second transmission path 22 (FIGS. 3B and 3C) are configured by microstrip lines, but in the third embodiment, the first transmission path 21 and The second transmission path 22 is constituted by a coplanar line. In FIG. 5A, the area where the ground plane 20 is arranged is hatched.

  The parallel running portion 22A and the non-parallel running portion 22B of the second transmission path 22 have the same thickness. The parallel transmission portion 22A and the first transmission path 21 constitute a differential transmission path, and ground planes 20 are disposed on both sides thereof. The ground plane 20 is also arranged on both sides of the non-parallel running portion 22B of the second transmission path 22. The first transmission path 21 is connected to the ground plane 20 via a termination resistor R1 at one end thereof.

  The distance GB from the non-parallel portion 22B to the ground plane 20 is different from the distance GA from the parallel portion 22A to the ground plane 20. The distance from the second transmission path 22 to the ground plane 20 gradually changes in the boundary region 26 between the parallel running portion 22A and the non-parallel running portion 22B. Outside the boundary region 26, the distance GA and the distance GB are constant.

5B and 5C are cross-sectional views taken along one-dot chain line 5B-5B and one-dot chain line 5C-5C in FIG. 5A, respectively. As shown in FIG. 5B, a parasitic capacitance Ce is generated between the non-parallel portion 22 </ b> B and one ground plane 20. The combined parasitic capacitance between the non-parallel portion 22B and the ground planes 20 on both sides is twice the parasitic capacitance Ce. As shown in FIG. 5C, a parasitic capacitance Cf is generated between the parallel portion 22A and the ground plane 20, and a parasitic capacitance Cg is generated between the parallel portion 22A and the first transmission path 21. A parasitic capacitance Ch is generated between the transmission line 21 and the ground plane 20. The combined parasitic capacitance Cc between the parallel running portion 22A and the ground plane 20 is expressed by the following equation using these parasitic capacitances Cf, Cg, and Ch.

  Further, the inductance per unit length of the non-parallel portion 22B and the inductance per unit length of the parallel portion 22A depend on the distance GB and the distance GA, respectively.

  The characteristic impedance of the non-parallel portion 22B is obtained from the combined parasitic capacitance and parasitic inductance per unit length. Similarly, the characteristic impedance of the parallel running portion 22A is also obtained from the combined parasitic capacitance and parasitic inductance per unit length. The distance GA and the distance GB are set so that the characteristic impedance of the non-parallel portion 22B matches the characteristic impedance of the parallel portion 22A. By setting the distance GA and the distance GB in this way, reflection of high-frequency signals at the boundary between the non-parallel portion 22B and the parallel portion 22A can be suppressed.

  Further, in the wiring board according to the third embodiment, since the width of the second transmission path 22 is constant, the pattern of the conventional transmission path at the connection point between the second transmission path 22 and the coaxial cable susceptor. It is possible to divert the design.

[Fourth embodiment]
Next, a wiring board according to a fourth embodiment will be described with reference to FIGS. 6A and 6B. Hereinafter, the description of the configuration common to the wiring board according to the first embodiment will be omitted.

  FIG. 6A is a schematic plan view of a wiring board according to a fourth embodiment. In the first embodiment, the non-parallel running portion 22B of the second transmission path 22 is thicker than the parallel running section 22A, but in the fourth embodiment, the width of the second transmission path 22 is constant. That is, the width of the non-parallel running portion 22B is equal to the width of the parallel running portion 22A.

  6B is a cross-sectional view taken along one-dot chain line 6B-6B in FIG. 6A. A second transmission path 22 is formed on the upper surface of the dielectric substrate 25. A ground plane 20A is disposed on the back surface of the dielectric substrate 25, and another ground plane 20B is disposed on the inner layer. The inner-layer ground plane 20B is disposed immediately below the non-parallel running portion 22B, but is not disposed directly below the parallel running portion 22A. The ground plane 20A and the ground plane 20B are connected to each other by via conductors for interlayer connection. The ground planes 20 </ b> A and 20 </ b> B act as the ground plane 20 with respect to the second transmission path 22.

  The distance GB from the non-parallel portion 22B to the ground plane 20B is shorter than the distance GA from the parallel portion 22A to the ground plane 20A. By making the distance GB shorter than the distance GA, a reduction in parasitic capacitance due to the fact that the first transmission path 21 does not run parallel to the non-parallel running portion 22B is compensated. Thereby, the characteristic impedance of the parallel running portion 22A and the non-parallel running portion 22B can be matched. In the fourth embodiment, an impedance matching structure is realized by a structure in which the distance GB is narrower than the distance GA.

[Fifth embodiment]
Next, a wiring board according to a fifth embodiment will be described with reference to FIGS. 7A to 8. Hereinafter, the description of the configuration common to the wiring board according to the first embodiment will be omitted. In the fifth embodiment, it is confirmed by simulation that the characteristic impedance can be matched.

  FIG. 7A is a schematic plan view of a wiring board according to a fifth embodiment to be simulated. In the first embodiment, the parallel running portion 22A of the second transmission path 22 and the first transmission path 21 (FIG. 3A) have the same width. In the fifth embodiment, the width W1 of the parallel running portion 22A and the width W of the first transmission path 21 are slightly different in order to match the characteristic impedance of the second transmission path 22 to 50Ω.

  The length LA of the parallel running portion 22A was 25 mm, the length LB of the non-parallel running portion 22B was 25 mm, and the length LC of the tapered portion 22C was 0.3 mm. The tapered portion 22C is included in the non-parallel running portion 22B. The width W of the first transmission path 21 was 0.083 mm, the width W1 of the parallel running portion 22A was 0.11 mm, and the width W2 of the non-parallel running portion 22B was 0.155 mm. The distance S between the parallel running portion 22A and the first transmission path 21 was 0.0327 mm.

  7B is a cross-sectional view taken along one-dot chain line 7B-7B in FIG. 7A. The thickness t of the first transmission path 21 and the second transmission path 22 is 0.02 mm, and the distance h from the first transmission path 21 and the second transmission path 22 to the ground plane 20 is 0.1 mm. . The relative dielectric constant εr of the dielectric substrate 25 was set to 4.4.

For comparison, a simulation was also performed for the wiring boards according to the two comparative examples.
FIG. 7C is a schematic plan view of a wiring board according to a first comparative example. In the first comparative example, the second transmission path 22 and the first transmission path 21 constitute a differential transmission path. The length LX of the first transmission path 21 and the second transmission path 22 was 50 mm. The width W of the first transmission path 21 and the second transmission path 22 was set to 0.083 mm. The distance S between the first transmission path 21 and the second transmission path 22 is the same as the distance S between the parallel running portion 22A of the wiring board according to the fifth embodiment and the first transmission path 21. The dimensions in the thickness direction of the wiring board and the relative dielectric constant are the same as those in the fifth embodiment.

  FIG. 7D is a schematic plan view of a wiring board according to a second comparative example. In the second comparative example, the widths of the parallel running portion 22A and the non-parallel running portion 22B of the second transmission path 22 are the same. The length LA of the parallel running portion 22A and the length LB of the non-parallel running portion 22B are the same as those lengths LA and LB of the wiring board according to the fifth embodiment. The widths W of the first transmission path 21 and the second transmission path 22 are the same as those widths W of the wiring board according to the first comparative example. The distance S between the parallel running portion 22A and the first transmission path 21 is the same as the distance S in the wiring board according to the fifth embodiment. The dimensions in the thickness direction of the wiring board and the relative dielectric constant are the same as those in the fifth embodiment.

  Using a three-dimensional electromagnetic field analysis tool, the time domain reflection (TDR) characteristics of the second transmission path 22 of the wiring board according to the fifth example, the first comparative example, and the second comparative example are obtained by simulation, and the simulation result From which the characteristic impedance was obtained.

  FIG. 8 is a graph showing the obtained characteristic impedance. The horizontal axis represents the elapsed time until the reflected waveform is observed in the unit “ns”. On the upper horizontal axis, the length of the transmission line corresponding to the elapsed time is shown in the unit “mm”. The vertical axis represents the characteristic impedance in the unit “Ω”. In FIG. 8, a thick solid line 7A, a broken line 7C, and a thin solid line 7D are a wiring board according to the fifth embodiment (FIG. 7A), a wiring board according to the first comparative example (FIG. 7C), and a wiring board according to the second comparative example, respectively. The characteristic impedance of the 2nd transmission line 22 of (Drawing 7D) is shown.

  It was confirmed that the characteristic impedance of the second transmission line 22 of the first comparative example (FIG. 7C) was matched to approximately 50Ω. The characteristic impedance of the parallel portion 22A of the second transmission line 22 of the second comparative example (FIG. 7D) is matched to approximately 50Ω, but the characteristic impedance of the non-parallel portion 22B is greater than 50Ω. It can be seen that sufficient impedance matching is not obtained.

  The characteristic impedance of the parallel portion 22A of the second transmission line 22 of the fifth embodiment (FIG. 7A) is matched to approximately 50Ω. Although the characteristic impedance of the non-parallel portion 22B is slightly deviated from 50Ω, it can be seen that the amount of deviation from 50Ω is small compared to the second comparative example (FIG. 7D).

  From the simulation results of the wiring board according to the fifth example, the first comparative example, and the second comparative example, it was confirmed that the characteristic impedance can be matched by incorporating the impedance matching structure into the wiring board.

  Each of the above-described embodiments is an exemplification, and needless to say, partial replacement or combination of the configurations shown in the different embodiments is possible. About the same effect by the same composition of a plurality of examples, it does not refer to every example one by one. Furthermore, the present invention is not limited to the embodiments described above. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

DESCRIPTION OF SYMBOLS 10 Serializer circuit module 11 Serializer 20, 20A, 20B Ground plane 21 1st transmission path 21D Spacing extension part 22 2nd transmission path 22A Parallel running part 22B Non-parallel running part 22C Taper part 22D Spacing spreading part 23 Power supply line 25 Dielectric Body board 26 Boundary region 27 Through hole 30 Deserializer circuit module 31 Deserializer 40 Ground plane 43 Power line 50 Coaxial cable 51 Internal conductor 52 External conductor 55 DC power supply 60 Image sensor 61 Electronic component

Claims (4)

A first transmission line in which a signal transmitting / receiving circuit is connected to one end and the other end is terminated with a termination resistor;
The signal transmission / reception circuit is connected to one end, and includes a parallel portion that forms a differential transmission path in parallel with the first transmission path on the one end side, and the other end and the A second transmission path including a non-parallel running section that is not parallel to the first transmission path between the parallel running sections;
A wiring board having an impedance matching structure for matching characteristic impedances of the parallel running portion and the non-parallel running portion.   The wiring board according to claim 1, wherein a width of the non-parallel portion is wider than a width of the parallel portion, and the impedance matching structure is realized by a difference in width between the non-parallel portion and the parallel portion. An interval between the parallel running portion and the first transmission path is constant,
The non-parallel portion includes a portion where a distance from the first transmission path is widened as the distance from the end connected to the signal transmission / reception circuit increases in a partial region continuous to the parallel portion. Item 3. The wiring board according to Item 2. In addition, it has a ground plane,
The distance from the non-parallel portion to the ground plane is different from the distance from the parallel portion to the ground plane, the distance from the non-parallel portion to the ground plane, and the distance from the parallel portion to the ground plane. The wiring board according to claim 1, wherein the impedance matching structure is realized by a difference from the distance up to.

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