JP2018190915A - Electronic component and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To miniaturize a laminate body and uniform a thickness of a terminal.SOLUTION: A diplexer 100 comprises: a laminate body 10 to which a plurality of dielectric layers is laminated and which has an upper surface and a lower surface; a plurality of conductive patterns provided into the laminate body; a first terminal that is included in a plurality of terminals 20 provided onto the lower surface of the laminate body, and includes a first metal layer and a second metal layer provided to the side opposite to the laminate body of the first metal layer; third metal layers that are included in the plurality of terminals, that are provided so as not to be conducted in a DC current with another terminal of the plurality of terminals through any of the conductive patterns and conducted in the DC current with each other through at least one of the plurality of conductive patterns, and each of which is thinner than the first metal layer; a fourth metal layer that is provided to the side opposite to the laminate body of the third metal layer, and is thicker than the second metal layer and is made of the material similar to the second metal layer; and a plurality of second terminals of which an area of a sum is larger than that of the first terminal.SELECTED DRAWING: Figure 7

Description

  The present invention relates to an electronic component and a manufacturing method thereof, for example, an electronic component in which a plurality of dielectric layers are stacked and a manufacturing method thereof.

  2. Description of the Related Art As electronic parts used for wireless communication terminals such as smart phones and mobile phones, electronic parts having a laminate in which a plurality of conductive patterns are laminated and dielectric layers are laminated are known. It is known to use an LGA (Land Grid Array) having a terminal (land electrode) on the lower surface of a laminated body for downsizing of electronic components. In order to make the thickness of the terminal uniform, it is known that a plating electrode connected to a part of the terminal in a direct current (DC) manner is provided on the surface of the laminate (for example, Patent Document 1).

JP 2016-39334 A

  However, the plating electrode interferes with the surrounding conductor pattern at a high frequency. In order to suppress such interference, a space is secured between the plating electrode and the conductor pattern. This increases the size of the electronic component.

  The present invention has been made in view of the above problems, and aims to reduce the size of the laminate and make the thickness of the terminals uniform.

  The present invention provides a laminate having a plurality of dielectric layers laminated, having an upper surface and a lower surface, a plurality of conductor patterns provided in the laminate, and a plurality of terminals provided on the lower surface of the laminate. The first metal layer and the laminate of the first metal layer are provided so as not to be electrically connected to other terminals among the plurality of terminals through a direct current through any of the plurality of conductor patterns. And a second metal layer provided on the opposite side of the first terminal, and the second terminal included in the plurality of terminals, and the other terminal among the plurality of terminals through any of the plurality of conductor patterns A third metal layer that is not conductive by a direct current and is conductive by a direct current through at least one of the plurality of conductor patterns, each being thinner than the first metal layer; and the third metal layer Provided on the opposite side of the laminate, and A fourth metal layer thicker than two metal layers and made of the same material as the second metal layer, and a plurality of second terminals having a total area larger than the area of the first terminal. .

  In the above configuration, the second metal layer and the fourth metal layer may include a metal layer having a melting point lower than that of the first metal layer and the third metal layer.

  The said structure WHEREIN: The difference of the thickness of the said 1st terminal and the said 2nd terminal can be set as the structure smaller than the difference of the thickness of the said 2nd metal layer and the said 4th metal layer.

  In the above-described configuration, it is included in the plurality of terminals, and is provided so as not to be conducted with a direct current to other terminals among the plurality of terminals through any of the plurality of conductor patterns. A fifth metal layer that is provided so as to conduct with a direct current through at least one of the conductor patterns, each being thinner than the first metal layer and thicker than the third metal layer, and the laminated layer of the fifth metal layer A sixth metal layer which is provided on the opposite side of the body and is thicker than the second metal layer and thinner than the fourth metal layer and made of the same material as the second metal layer and the fourth metal layer, and has a total area Can be configured to include one or more third terminals that are larger than the area of the first terminals and smaller than the total area of the plurality of second terminals.

  In the above-mentioned configuration, it comprises one or more inductors formed from at least one of the plurality of conductor patterns, and one or more capacitors formed from at least one of the plurality of conductor patterns, At least one terminal of the first terminal and the plurality of second terminals is provided so as not to be electrically connected to other terminals of the plurality of terminals by direct current through at least one of the one or more capacitors, The plurality of second terminals may be configured to be electrically connected to each other with a direct current through at least one of the one or more inductors.

  In the above configuration, a filter having at least one of the one or more inductors and at least one of the one or more capacitors may be provided.

  In the above configuration, a first filter having at least one of the one or more inductors and at least one of the one or more capacitors, at least one other of the one or more inductors and the 1 Or it can be set as the structure provided with the multiplexer containing the 2nd filter which has another at least 1 among several capacitors.

  The said structure WHEREIN: The said laminated body is a rectangular parallelepiped shape, The short side and long side of the largest surface among the said rectangular parallelepiped can be set as the structure which is 0.8 mm or less and 1.6 mm or less, respectively.

  The said structure WHEREIN: It can be set as the structure by which the terminal which mounts another electronic component is not provided in the said upper surface of the said laminated body.

  The present invention includes a step of forming the laminate in which a plurality of conductor patterns are provided in a laminate having an upper surface and a lower surface, and a plurality of dielectric layers are laminated, and a plurality of layers provided on the lower surface of the laminate. A first metal layer that is included in the terminal and is a part of a first terminal provided so that a direct current is not conducted to other terminals among the plurality of terminals through any of the plurality of conductor patterns; , Included in the plurality of terminals, through which any of the plurality of conductor patterns does not conduct direct current to other terminals of the plurality of terminals and through at least one of the plurality of conductor patterns. Forming a third metal layer that is provided so that direct currents are conducted to each other, the total area being a part of a plurality of second terminals larger than the area of the first terminal, and being thinner than the first metal layer; The first metal layer and the front After forming the third metal layer, a second metal layer on the opposite side of the stacked body of the first metal layer, and a fourth thicker than the second metal layer on the opposite side of the stacked body of the third metal layer. Forming a metal layer at the same time using a barrel plating method.

  In the above configuration, after the step of forming the first metal layer and the third metal layer, the step of dividing the laminate, and the step of firing the laminate after the step of dividing And the step of forming the second metal layer and the fourth metal layer includes the second metal layer including a metal layer having a melting point lower than the firing temperature of the step of firing the separated laminate. The fourth metal layer can be formed at the same time using a barrel plating method.

  The present invention provides a laminate having a plurality of dielectric layers laminated, having an upper surface and a lower surface, a plurality of conductor patterns provided in the laminate, and a plurality of terminals provided on the lower surface of the laminate. Included, and does not conduct with other DC terminals among the plurality of terminals by DC current through any of the plurality of conductor patterns, and conducts by DC current with each other through at least one of the plurality of conductor patterns. A plurality of first terminals each including a first metal layer and a second metal layer provided on the opposite side of the stacked body of the first metal layer, and included in the plurality of terminals. The conductive patterns are not connected to the other terminals of the plurality of terminals by a direct current through any of the plurality of conductive patterns, and are connected to each other by a direct current through at least one of the plurality of conductive patterns. Each of the above A third metal layer that is thinner than the metal layer, and a fourth metal layer that is provided on the opposite side of the laminate of the third metal layer and that is thicker than the second metal layer and made of the same material as the second metal layer. And a plurality of second terminals having a total area larger than a total area of the plurality of first terminals.

  According to the present invention, it is possible to reduce the size of the laminate and make the thickness of the terminals uniform.

FIG. 1 is a circuit diagram of a diplexer according to the first embodiment. FIG. 2A and FIG. 2B are a perspective view and a BB cross-sectional view of the diplexer according to the first embodiment. FIG. 3 is a disassembled perspective view (No. 1) of the laminate in the first embodiment. FIG. 4 is a disassembled perspective view (No. 2) of the laminate in the first embodiment. FIG. 5 is a flowchart illustrating the manufacturing method of the diplexer according to the first embodiment. 6A and 6B are cross-sectional views of a diplexer according to Comparative Example 1. FIG. FIG. 7A and FIG. 7B are cross-sectional views of the diplexer according to the first embodiment. FIG. 8A to FIG. 8C are cross-sectional views illustrating a method for forming the metal layer 21 in the first embodiment. FIGS. 9A to 9C are cross-sectional views showing another method for forming the metal layer 21 in the first embodiment. FIG. 10 is a circuit diagram of a diplexer according to the second embodiment. FIG. 11 is a perspective view of the diplexer according to the second embodiment. 12A and 12B are cross-sectional views of the diplexer according to the second embodiment. FIG. 13 is a circuit diagram of a diplexer according to the third embodiment. FIG. 14 is a perspective view of the diplexer according to the third embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  A diplexer will be described as an example of the electronic component. FIG. 1 is a circuit diagram of a diplexer according to the first embodiment. As shown in FIG. 1, in the diplexer 100, an LPF (low-pass filter) 24 is connected between a common terminal Ta and a terminal T1. An HPF (High Pass Filter) 26 is connected between the common terminal Ta and the terminal T2. The ground sides of the LPF 24 and the HPF 26 are connected to the ground terminal Tg.

  The LPF 24 includes inductors L11 and L12 and capacitors C11 to C13. The inductors L11 and L12 are connected in series between the common terminal Ta and the terminal T1. The capacitor C11 is connected in parallel with the inductor L12. The capacitors C12 and C13 are respectively connected between the node N1 and the ground terminal Tg and between the node N2 and the ground terminal Tg.

  The HPF 26 includes an inductor L21 and capacitors C21 to C23. The capacitors C21 and C23 are connected in series between the common terminal Ta and the terminal T2. The capacitor C22 and the inductor L21 are connected in series between the node N3 between the capacitors C21 and C23 and the ground terminal Tg.

For example, the inductance of each inductor is as follows.
L11: 7nH, L12: 4nH, L21: 6nH
The capacitance of each capacitor is as follows.
C11: 2pF, C12: 4pF, C13: 2.5pF
C21: 2.5 pF, C22: 5 pF, C23: 3 pF
The pass band of each filter is set to include the following frequency bands, for example.
LPF24: 669MHz to 960MHz
HPF26: 1710MHz-2690MHz

  The LPF 24 suppresses the signal in the pass band of the HPF 26 by passing the signal in the pass band among the high-frequency signals input to the common terminal Ta (or terminal T1) to the terminal T1 (or common terminal Ta). The HPF 26 passes a signal in the pass band of the high-frequency signal input to the common terminal Ta (or terminal T2) to the terminal T2 (or common terminal Ta), and suppresses the signal in the pass band of the LPF 24. For example, an antenna is connected to the common terminal Ta. For example, a low frequency band duplexer and a high frequency band duplexer are connected to the terminals T1 and T2 through high frequency switches, for example.

  FIG. 2A and FIG. 2B are a perspective view and a BB cross-sectional view of the diplexer according to the first embodiment. FIG. 2A shows the terminal electrode 20 through the laminate 10. The same applies to the following perspective views. As shown in FIGS. 2A and 2B, the terminal electrode 20 is provided on the lower surface of the laminate 10. The terminal electrode 20 includes a common terminal Ta, terminals T1 and T2, and a ground terminal Tg. The terminal electrode 20 is an LGA land electrode and is a terminal for connection to a mother board 30 (circuit board or wiring board) as shown in FIG. For this reason, all the terminals are provided on the lower surface of the laminate 10. The terminal electrode 20 includes a metal layer 21 provided on the lower surface of the stacked body 10 and a metal layer 22 provided on the opposite side of the stacked body 10 of the metal layer 21.

The size and area of the terminal electrode 20 are as follows, for example.
Common terminal Ta: 180 μm × 125 μm, 22,500 μm ²
Terminal T1: 180 μm × 400 μm, 72000 μm ²
Terminal T2: 180 μm × 400 μm, 72000 μm ²
Ground terminal Tg: 180 μm × 125 μm, 22,500 μm ²

  The common terminal Ta and the terminal T1 are connected in a DC manner via inductors L11 and L12 as shown in FIG. 1 (solid line 52 in FIG. 2A). The capacitor C12, C13, or C22 is connected between the terminal T2 and the ground terminal Tg between the other terminals, and is not connected to the other terminals in a direct current manner.

  3 and 4 are exploded perspective views of the laminated body in Example 1. FIG. As shown in FIGS. 3 and 4, a plurality of dielectric layers 11a to 11i are stacked. Conductor patterns 12b to 12i are formed between the dielectric layers 11b to 11i. A terminal electrode 20 is formed on the lower surface of the dielectric layer 11i. The terminal electrode 20 corresponds to the common terminal Ta, the terminals T1 and T2, and the ground terminal Tg.

  The conductor patterns 12b to 12i form an inductor coil 14 and a capacitor electrode 15. The conductor patterns 12b to 12i are connected by a via wiring 13. Connection of the via wiring 13 is indicated by a vertical broken line. In this example, the inductors L11 and L21 are formed by the conductor patterns 12b and 12c, and the inductor L12 is formed by the conductor patterns 12d and 12e. Capacitors C11 and C22 are formed by conductor patterns 12f and 12g. The capacitor C12 is formed by the conductor patterns 12f to 12h. Capacitors C21 and C23 are formed by conductor patterns 12g to 12i. A capacitor C13 is formed by the conductor patterns 12h and 12i.

  The capacitor electrode 15 and the coil 14 included in the LPF 24 and the capacitor electrode 15 and the coil 14 included in the HPF 26 do not overlap in plan view. Thereby, interference with LPF24 and HPF26 can be suppressed.

  The film thicknesses of the dielectric layers 11a to 11i are, for example, 35 μm, 15 μm, 80 μm, 15 μm, 75 μm, 10 μm, 10 μm, 10 μm, and 35 μm.

  FIG. 5 is a flowchart illustrating the manufacturing method of the diplexer according to the first embodiment. As shown in FIG. 5, a sheet-like dielectric layer 11 is formed (step S10). The dielectric layer 11 is produced using, for example, a doctor blade method. The dielectric layer 11 is a ceramic material containing an oxide such as Al, Si and / or Ca.

  A via wiring 13 penetrating the dielectric layer 11 is formed (step S12). For example, a via hole penetrating the dielectric layer 11 is formed by laser light irradiation. Via wiring 13 is formed in the via hole using a squeegee method or the like.

  Conductive pattern 12 is formed on the surface of dielectric layer 11 (step S14). The conductor pattern 12 is formed using, for example, a screen printing method or a transfer method. The conductor pattern 12 and the via wiring 13 are metal layers such as Ag, Pd, Pt, Cu, Ni, Au, Au—Pd alloy, or Ag—Pt alloy.

  The metal layer 21 of the terminal electrode 20 is formed on the lower surface of the lowermost dielectric layer 11i of the dielectric layers 11 (step S16). The metal layer 21 is formed using, for example, a screen printing method or a transfer method. The metal layer 21 is a metal layer such as Ag, Cu, or Au.

  The dielectric layer 11 is laminated and pressure-bonded (step S18). For the lamination of the dielectric layer 11, for example, heat pressing or an adhesive is used. Thereby, a laminated body is formed.

  The laminate is cut into individual pieces (step S20). The laminated body is cut by, for example, pressing using a blade. Since the laminate is before firing, it can be easily cut off.

  The laminate is fired (step S22). The firing temperature is 700 ° C. or higher. Thereby, the dielectric layer 11 becomes a sintered body. Since the firing temperature is lower than the melting point of the conductor pattern 12 and the metal layer 21, the conductor pattern 12 and the metal layer 21 are not melted.

  A metal layer 22 is formed on the lower surface of the metal layer 21 using a plating method (step S24). For example, barrel plating is used to form the metal layer 22. In the barrel plating method, the laminate 10 and conductive metal particles (media) are immersed in a plating solution. An electric current is passed through the plating solution while stirring the plating solution. Thereby, the plating metal is deposited on the surface of the metal layer 21. The current flows when the media contacts the electrode of the laminate 10, and the plated metal is deposited. When the area of the metal layer 21 is large, the probability that the metal layer 21 contacts the media increases. This increases the amount of plating metal deposited. As described above, the amount of plating metal deposited depends on the area of the metal layer 21. The metal layer 22 is, for example, a Ni film and a Sn film from the metal layer 21 side. The Sn film is a solder layer for mounting electronic components on a mother board or the like, and the Ni film is a barrier layer for suppressing mutual diffusion between the solder layer and the metal layer 21.

  The characteristics of the electronic component are inspected (step S26). Thus, the diplexer according to the first embodiment is completed.

  The step of cutting and stacking the laminate in step S20 is preferably before the firing step in step S22. This is because, when the laminate is fired, the laminate becomes hard and cannot be cut off, and an expensive dicing process or the like is performed. The formation of the metal layer 22 in step S24 is preferably after the firing step in step S22. This is because if a solder having a melting point lower than the firing temperature is used as the metal layer 22, it will melt in the firing step. In step S <b> 24, barrel plating is used to form the metal layer 22 on the separated laminate 10.

  As shown in FIG. 2A, the common terminal Ta and the ground terminal Tg are smaller than the areas of the terminals T1 and T2. The reason why the common terminal Ta and the ground terminal Tg are small is to reduce the size. The different areas within the terminal electrode 20 are due to requirements when mounted on the mother board 30. In particular, when the terminal electrode 20 is an LGA, the terminal electrode 20 is provided only on the lower surface of the surface of the multilayer body 10. When trying to reduce the size of the diplexer, the area of the lower surface of the laminate 10 is reduced. Therefore, the arrangement of the terminal electrode 20 can be restricted, and a part of the terminal electrode 20 is reduced in area.

  In step S24 in FIG. 5, the amount of plating metal deposited is substantially proportional to the area of the terminal electrode 20 (ie, the metal layer 21). That is, the thickness of the metal layer 22 is substantially proportional to the area of the terminal electrode 20. The film thickness of the metal layer 22 in the terminal electrode 20 connected in a direct current manner via the conductor pattern is proportional to the total area of the connected terminal electrodes 20. For example, the common terminal Ta and the terminal T1 are connected in a direct current manner via inductors L11 and L12 (via conductor patterns 12b to 12i). For this reason, the substantial area of the common terminal Ta and the terminal T1 when performing barrel plating is the total area of the common terminal Ta and the terminal T1.

  6A and 6B are cross-sectional views of the diplexer 110 according to the first comparative example. 6A and 6B correspond to the AA cross section and the BB cross section of FIG. 2A, respectively. As shown in FIGS. 6A and 6B, the film thickness t1 of the metal layer 21 is constant, for example, 10 μm. The film thicknesses of the metal layers 22 at the terminals T1, T2, the common terminal Ta, and the ground terminal Tg are t12, t22, ta2, and tg2, respectively.

The film thickness of the metal layer 22 at each terminal of the diplexer 110 in Comparative Example 1 is proportional to the area of each terminal (when connected in a direct current manner, the total area of the connected terminals). When the minimum film thickness of the metal layer 22 is 3 μm, the substantial area of each terminal electrode 20 (the total area of the terminal electrodes 20 connected in a DC manner) and the film thickness of the metal layer 22 are, for example, as follows. .
Common terminal Ta: 94500 μm ² , ta2 = 12.6 μm
Terminal T1: 94500 μm ² , t12 = 12.6 μm
Terminal T2: 72000 μm ² , t22 = 9.6 μm
Ground terminal Tg: 22500 μm ² , tg2 = 3 μm

  The terminal T2 and the ground terminal Tg are thinner than the common terminal Ta and the terminal T1. Thereby, the coplanarity of the diplexer 110 is deteriorated. Therefore, when the diplexer 110 is mounted on the mother board 30, there is a possibility that the connection between the terminal T1 and the ground terminal Tg and the mother board 30 is weakened.

FIG. 7A and FIG. 7B are cross-sectional views of the diplexer according to the first embodiment. FIG. 7A and FIG. 7B correspond to the AA and BB sections in FIG. 2A, respectively. In the diplexer 100 of the first embodiment, the film thickness of the metal layer 21 is varied for each terminal. The film thicknesses of the metal layers 21 at the terminals T1, T2, the common terminal Ta, and the ground terminal Tg are t11, t21, ta1, and tg1, respectively. The film thickness of the metal layers 21 and 22 of each terminal electrode 20 is, for example, as follows.
Common terminal Ta: ta1 = 10 μm, ta2 = 12.6 μm
Terminal T1: t11 = 10 μm, t12 = 12.6 μm
Terminal T2: t21 = 13 μm, t22 = 9.6 μm
Ground terminal Tg: tg1 = 19.6 μm, tg2 = 3 μm
As a result, the film thickness of each terminal electrode 20 is approximately 22.6 μm. Thus, the film thickness of the terminal electrode 20 can be made uniform, and coplanarity can be improved.

  In the method of Patent Document 1, although coplanarity is improved, a plating electrode connected to the conductor pattern is provided on the surface of the laminate. Thereby, it interferes with other conductor patterns in high frequency. If it is going to suppress interference, the relationship of arrangement | positioning of the electrode for plating and a conductor pattern will be restrict | limited. Thereby, an electronic component will enlarge. In Example 1, since there is no restriction | limiting of such arrangement | positioning of a conductor pattern, an electronic component can be reduced in size.

  The example of the formation method of the metal layer 22 in step S24 of FIG. 5 is demonstrated. FIG. 8A to FIG. 8C are cross-sectional views illustrating a method for forming the metal layer 21 in the first embodiment. As shown in FIG. 8A, a metal layer 21a is formed on the dielectric layer 11 (corresponding to the lower surface of the laminate). As shown in FIG. 8B, a metal layer 21 b is formed on the dielectric layer 11. As shown in FIG. 8C, a metal layer 21 c is formed on the dielectric layer 11. The metal layers 21a to 21c are formed using, for example, a screen printing method or a transfer method. In this way, the metal layers 21a to 21c may be formed with different thicknesses. The order of forming the metal layers 21a to 21c is not limited, but it is preferable to form the metal layers 21a to 21c in order from the thin metal layer 21a. Thereby, it can suppress that the metal layer formed previously becomes an obstacle of the formation process of the subsequent metal layer.

  FIGS. 9A to 9C are cross-sectional views showing another method for forming the metal layer 21 in the first embodiment. As shown in FIG. 9A, a metal layer 21 d that is a part of the metal layers 21 b and 21 c is formed on the dielectric layer 11. As shown in FIG. 9B, a metal layer 21 e that becomes a part of the metal layer 21 c is formed on the dielectric layer 11. As shown in FIG. 9C, a metal layer 21 f that is a part of the metal layers 21 a to 21 c is formed on the dielectric layer 11. A metal layer 21a is formed by the metal layer 21f. A metal layer 21b is formed by the metal layers 21d and 21f. A metal layer 21c is formed by the metal layers 21d to 21f. The metal layers 21d to 21f are formed using, for example, a screen printing method or a transfer method.

  The metal layers 21a to 21c may be formed using an inkjet method other than the screen printing method and the transfer method.

  Thus, the metal layers 21a to 21c may be formed by laminating one or a plurality of metal layers 21d to 21f. The order in which the metal layers 21a to 21c are formed is not limited, but it is preferable to form the metal layers 21d to 21f in order from the thin metal layer 21d. Thereby, it can suppress that the metal layer formed previously becomes an obstacle of the formation process of the subsequent metal layer. When the film thickness of the metal layers 21b and 21c exceeds the film thickness that can be formed at a time using the screen printing method or the transfer method, the method for forming the metal layer 21 shown in FIGS. 9A to 9C is used. It is preferable.

  FIG. 10 is a circuit diagram of a diplexer according to the second embodiment. As shown in FIG. 10, in the diplexer 102, three ground terminals Tg are provided. Other configurations are the same as those of the first embodiment shown in FIG.

FIG. 11 is a perspective view of the diplexer according to the second embodiment. As shown in FIG. 11, in the diplexer 102, the terminal electrode 20 is provided on the lower surface of the multilayer body 10. The terminal electrode 20 includes a common terminal Ta, terminals T1 and T2, and three ground terminals Tg. The terminal electrodes 20 have the same size, and each terminal electrode 20 has a size of 180 μm × 125 μm and an area of 22,500 μm ² .

  The common terminal Ta and the terminal T1 are connected in a DC manner via inductors L11 and L12 as shown in FIG. 10 (solid line 52 in FIG. 11). The three ground terminals Tg are connected in a direct current manner (dotted line 54 in FIG. 15). The capacitor C23 is connected between the terminal T2 and another terminal, and is not connected to the other terminal in a direct current manner. Other configurations are the same as those of the first embodiment, and the description thereof is omitted.

  12A and 12B are cross-sectional views of the diplexer according to the second embodiment. FIG. 12A and FIG. 12B correspond to the AA cross section and the BB cross section of FIG. 11, respectively. In the diplexer 102 according to the second embodiment, the common terminal Ta and the terminal T1 are connected in a DC manner, and the three ground terminals Tg are connected in a DC manner. Therefore, the substantial area ratio of the common terminal Ta and the terminals T1, T2, and the three ground terminals Tg is 2: 1: 3.

When the minimum film thickness of the metal layer 22 is 4 μm, the film thicknesses of the metal layers 21 and 22 of each terminal electrode 20 are, for example, as follows.
Common terminal Ta: ta1 = 14 μm, ta2 = 8 μm
Terminal T1: t11 = 14 μm, t12 = 8 μm
Terminal T2: t21 = 18 μm, t22 = 4 μm
Ground terminal Tg: tg1 = 10 μm, tg2 = 12 μm
The film thickness of each terminal electrode 20 is approximately 22 μm. Thus, the film thickness of the terminal electrode 20 can be made uniform, and coplanarity can be improved.

  FIG. 13 is a circuit diagram of a diplexer according to the third embodiment. As shown in FIG. 13, in the diplexer 104, two ground terminals Tg are provided. A dummy terminal Td that is not connected to the inductor and the capacitor is provided. Other configurations are the same as those of the second embodiment shown in FIG.

  FIG. 14 is a perspective view of the diplexer according to the third embodiment. As shown in FIG. 14, in the diplexer 104, the terminal electrode 20 includes a common terminal Ta, terminals T1 and T2, two ground terminals Tg, and a dummy terminal Td. The dummy terminal Td is not electrically connected to the conductor pattern in the stacked body 10 and is a terminal for mechanically connecting to the mother board 30.

  The substantial area ratio of the common terminal Ta, the terminal T1, the terminal T2, the two ground terminals Tg, and the dummy terminal Td is 2: 1: 2: 1. Similar to the first and second embodiments, the thickness of the metal layer 21 is made different for each terminal electrode 20. Thereby, the film thickness of the terminal electrode 20 can be made uniform, and coplanarity can be improved. Other configurations are the same as those of the second embodiment, and the description thereof is omitted.

  Examples 1 to 3 are summarized below. A plurality of terminal electrodes 20 provided on the lower surface of the multilayer body 10 are divided into a plurality of terminal groups A to C and considered. No direct current is conducted to the other terminal electrode 20 through any of the conductor patterns 12b to 12i in the laminated body 10, and at least one of the plurality of conductor patterns 12b to 12i is not provided. One or a plurality of terminal electrodes 20 provided so that direct currents are conducted to each other are defined as terminal groups A to C.

Table 1 summarizes the terminal groups A to C in the first embodiment. In Example 1, the terminal T1 and the common terminal Ta are the terminal group A, the ground terminal Tg is the terminal group B, and the terminal T2 is the terminal group C as shown in Table 1 and FIG.

Table 2 summarizes the terminal groups A to C in the second embodiment. In Example 2, as shown in Table 2 and FIG. 11, the three ground terminals Tg are the terminal group A, the terminal T1 and the common terminal Ta are the terminal group B, and the terminal T2 is the terminal group C.

  As shown in Tables 1 and 2, the terminal group A has the largest total area and the metal layer 22 has the largest thickness. For this reason, the metal layer 21 of the terminal group A is made the thinnest. The terminal group C has the smallest total area and the metal layer 22 is the thinnest. For this reason, the metal layer 21 of the terminal group C is made thickest. The total area in the terminal group B is smaller than the terminal group A and larger than the terminal group C. The metal layer 22 of the terminal group B is thinner than the terminal group A and thicker than the terminal group C. For this reason, the metal layer 21 of the terminal group B is made thicker than the terminal group A and thinner than the terminal group C.

  For example, the total area of the terminal group A (one or more second terminals) is larger than the terminal group B (one or more first terminals). At this time, the metal layer 21 (third metal layer) of the terminal group A is thinner than the metal layer 21 (first metal layer) of the terminal group B. The metal layer 22 (fourth metal layer) of the terminal group A is thicker than the metal layer 22 (second metal layer) of the terminal group B. The relationship between the terminal group A and the terminal group C and the relationship between the terminal group B and the terminal group C are the same as the relationship between the terminal group A and the terminal group B.

  Thus, even if the metal layer 22 of the terminal group A having a large total area is thicker than the terminal group B, the metal layer 21 of the terminal group A is made thinner than the terminal group B. Thereby, the thickness of the terminal electrode 20 can be made uniform. When the electrode for plating connected to a part of the conductor pattern is formed as in Patent Document 1, the laminate 10 is enlarged in order to suppress interference between the conductor pattern and the electrode for plating. In Examples 1 to 3, since it is not necessary to provide a plating electrode connected to the conductor patterns 12b to 12i, the stacked body 10 can be downsized.

  The difference in thickness of the terminal electrode 20 between the terminal group A and the terminal group B is smaller than the difference in thickness between the metal layer 22 of the terminal group A and the metal layer 22 of the terminal group B. Thus, the thickness of the terminal electrode 20 can be made uniform by adjusting the thickness of the metal layer 21. The thicknesses of the terminal electrodes 20 of the terminal groups A to C are preferably substantially the same.

  As in the terminal group A and the terminal group B of the second embodiment, one or more first terminals and one or more second terminals may be plural. As in the terminal group A and terminal group B of the first embodiment, the terminal group A and terminal group C or the terminal group B and terminal group C of the second embodiment, one or more first terminals and one or more second terminals. One of the terminals may be plural, and the other terminal may be 1. As in the terminal group B and the terminal group C of the first embodiment, each of the one or more first terminals and the one or more second terminals may be one.

  The terminal group A may be one or more first terminals, and the terminal group C may be one or more second terminals. The terminal group B may be one or more third terminals. The total area of the terminal group B is larger than the total area of the terminal group C and smaller than the total area of the terminal group A. At this time, the metal layer 21 of the terminal group B is thicker than the metal layer 21 of the terminal group A and thinner than the metal layer 21 of the terminal group C. The metal layer 22 of the terminal group B is thinner than the metal layer 21 of the terminal group A and thicker than the metal layer 21 of the terminal group C. Thus, the terminal electrode 20 may have three or more terminal groups.

  As in the first and second embodiments, all the terminal electrodes 20 may be connected to at least one of the conductor patterns 12b to 12i. Like the dummy terminal Td of the third embodiment, some of the terminal electrodes 20 of the terminal electrode 20 may not be connected to any of the conductor patterns 12b to 12i. For the terminal electrode 20 that does not affect the mounting and the coplanarity is not a problem, the film thickness of the metal layer 21 may not be adjusted.

  As shown in FIGS. 3 and 4, one or more inductors are formed from at least one of the plurality of conductor patterns 12b to 12i, and one or more capacitors are formed from at least a part of the plurality of conductor patterns 12b to 12i. Is formed. As shown in FIGS. 1 and 10, each of the terminal groups A to C is provided so that a direct current does not conduct with other terminals via at least one of one or a plurality of capacitors. Further, from the same terminal group A, a plurality of terminal electrodes 20 in C are connected to each other through a direct current through at least one of one or a plurality of inductors. Thus, the inductor and the capacitor may be formed by the conductor patterns 12b to 12i.

  As shown in FIGS. 1 and 10, the multilayer body 10 may be formed with a filter (LPF 24 and HPF 26) having at least one of one or more inductors and at least one of one or more capacitors. The number and connection relationship of capacitors and inductors in each filter can be arbitrarily designed. The filter may be a band pass filter or a band stop filter. A coupler may be formed in the laminate 10.

  The LPF 24 (first filter) has at least one of one or more inductors and at least one of one or more capacitors. The HPF 26 (second filter) has at least another one of one or more inductors and at least one other of one or more capacitors. The electronic component may be a multiplexer having LPF 24 and HPF 26. In addition to the diplexer, the multiplexer may be a duplexer, a triplexer, a quadplexer, or the like.

  The metal layer 22 is formed using a barrel plating method. When the barrel plating method is used, the metal layer 22 of the terminal group A having a large total area becomes thicker than the terminal group B. Therefore, it is preferable to make the metal layer 21 of the terminal group A thinner than the terminal group B. Thereby, the thickness of the terminal electrode 20 can be made uniform.

  After forming the metal layer 21 in step S16 of FIG. 5, the laminated body 10 is separated into pieces as in step S20. Thereby, the singulation process can be performed by a simple method such as pressing. After the separation, as in step S24, the metal layer 22 of the terminal group A and the terminal group B including the metal layer having a melting point lower than the firing temperature is simultaneously formed on the separated laminated body 10 using the barrel plating method. To do. The metal layer 22 having a melting point lower than the firing temperature can be formed on the separated laminate 10 by barrel plating.

  In the first to third embodiments, the dielectric filter in which the terminals for mounting other electronic components are not provided on the upper surface of the multilayer body 10 has been described as an example. However, the multilayer body 10 is a circuit board, Other electronic components may be mounted. When using the laminated body 10 as a dielectric filter, it is preferable that the short side and the long side of the largest surface among the rectangular parallelepiped shapes of the laminated body 10 are 0.8 mm or less and 1.6 mm or less, respectively. The short side and the long side are more preferably 0.7 mm or less and 1.5 or less.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

10 Laminated body 11, 11a-11i Dielectric layer 12, 12b-12j Conductor pattern 13, 13a, 13b Via wiring 14 Coil 15 Electrode 20 Terminal electrode 24 LPF
26 HPF

Claims (12)

A laminate in which a plurality of dielectric layers are laminated and having an upper surface and a lower surface;
A plurality of conductor patterns provided in the laminate;
Included in a plurality of terminals provided on the lower surface of the multilayer body, and provided so as not to be electrically connected to other terminals of the plurality of terminals by a direct current through any of the plurality of conductor patterns; A first terminal comprising: one metal layer; and a second metal layer provided on the opposite side of the laminate of the first metal layer;
The plurality of terminals are included in the plurality of conductor patterns and do not conduct with other terminals among the plurality of terminals with a direct current and are connected to each other via at least one of the plurality of conductor patterns. A third metal layer thinner than the first metal layer, and provided on the opposite side of the stacked body of the third metal layer, and thicker than the second metal layer. A fourth metal layer made of the same material as the two metal layers, and a plurality of second terminals having a total area larger than the area of the first terminal;
An electronic component comprising:   The electronic component according to claim 1, wherein the second metal layer and the fourth metal layer include a metal layer having a melting point lower than that of the first metal layer and the third metal layer.   The electronic component according to claim 1, wherein a difference in thickness between the first terminal and the second terminal is smaller than a difference in thickness between the second metal layer and the fourth metal layer.   It is included in the plurality of terminals, and is provided so as not to conduct with a direct current to other terminals among the plurality of terminals through any of the plurality of conductor patterns. A fifth metal layer that is thinner than the first metal layer and thicker than the third metal layer, and is opposite to the stacked body of the fifth metal layer. And a sixth metal layer that is thicker than the second metal layer and thinner than the fourth metal layer and made of the same material as the second metal layer and the fourth metal layer, and has a total area of the first metal layer 5. The electronic component according to claim 1, further comprising one or a plurality of third terminals that are larger than a terminal area and smaller than a total area of the plurality of second terminals. One or more inductors formed from at least one of the plurality of conductor patterns;
One or more capacitors formed from at least one of the plurality of conductor patterns;
Comprising
The plurality of second terminals are provided so as not to be electrically connected to other terminals among the plurality of terminals through a direct current through at least one of the one or more capacitors.
The plurality of terminals of at least one of the first terminal and the plurality of second terminals are provided so as to be electrically connected to each other by a direct current through at least one of the one or the plurality of inductors. The electronic component as described in any one.   The electronic component according to claim 5, further comprising a filter having at least one of the one or more inductors and at least one of the one or more capacitors. A first filter having at least one of the one or more inductors and at least one of the one or more capacitors;
The electronic component according to claim 7, further comprising: a multiplexer that includes at least one other of the one or more inductors and a second filter having at least one other of the one or more capacitors.   8. The electron according to claim 1, wherein the stacked body has a rectangular parallelepiped shape, and a short side and a long side of the largest surface of the rectangular parallelepiped are 0.8 mm or less and 1.6 mm or less, respectively. parts.   The electronic component according to any one of claims 1 to 9, wherein a terminal for mounting another electronic component is not provided on the upper surface of the stacked body. Forming a laminate in which a plurality of conductor patterns are provided in a laminate having an upper surface and a lower surface, and a plurality of dielectric layers are laminated;
A first terminal that is included in the plurality of terminals provided on the lower surface of the multilayer body, and is configured so that a direct current is not conducted to another terminal among the plurality of terminals through any of the plurality of conductor patterns; The first metal layer that is a part of the terminal, and included in the plurality of terminals, the direct current is not conducted to other terminals among the plurality of terminals through any of the plurality of conductor patterns, and The first metal layer is provided such that direct currents are conducted to each other through at least one of the plurality of conductor patterns, the total area being a part of the plurality of second terminals larger than the area of the first terminal, Forming a thinner third metal layer;
After forming the first metal layer and the third metal layer, the second metal layer on the opposite side of the stacked body of the first metal layer and the second metal layer on the opposite side of the stacked body of the third metal layer. Forming a fourth metal layer thicker than two metal layers simultaneously using a barrel plating method;
Of electronic parts including After the step of forming the first metal layer and the third metal layer, the step of separating the laminate;
After the step of dividing into pieces, a step of firing the laminate,
Including
In the step of forming the second metal layer and the fourth metal layer, the second metal layer and the fourth metal including a metal layer having a melting point lower than a firing temperature of the firing step in the singulated laminate. The method of manufacturing an electronic component according to claim 10, wherein the layer is a step of simultaneously forming a layer using a barrel plating method. A laminate in which a plurality of dielectric layers are laminated and having an upper surface and a lower surface;
A plurality of conductor patterns provided in the laminate;
The plurality of terminals are included in the plurality of terminals provided on the lower surface of the multilayer body, and do not conduct with other terminals among the plurality of terminals with a direct current through any of the plurality of conductor patterns, and the plurality of conductors. A first metal layer and a second metal layer provided on a side of the first metal layer opposite to the stacked body, the first metal layer and the second metal layer provided on the opposite side of the stacked body. A plurality of first terminals;
The plurality of terminals are included in the plurality of conductor patterns and do not conduct with other terminals among the plurality of terminals with a direct current and are connected to each other via at least one of the plurality of conductor patterns. The second metal layer is provided so as to be conductive by a direct current, and is provided on the opposite side of the third metal layer from the first metal layer and the stacked body of the third metal layer, and is thicker than the second metal layer. A fourth metal layer made of the same material as the metal layer, and a plurality of second terminals having a total area larger than the total area of the plurality of first terminals,
An electronic component comprising:

Images