JP2018190796A - Solid state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device that performs efficient electron multiplying operation.SOLUTION: A solid-state imaging device (100) is so configured that, when a voltage for driving the solid-state imaging device is applied to a second gate group (34) connected to a multiplied horizontal CCD channel (4), a first N-type region (20), a second P-type region (14), and the multiplied horizontal CCD channel punch through, and well concentration of a second P type region is so set that charge is not injected from the first N type region into the multiplied horizontal CCD channel.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state image sensor, and more particularly to a solid-state image sensor having an electron multiplication function.

  Several proposals have been made for increasing the sensitivity of solid-state imaging devices. For example, improvements to on-chip microlenses to improve the light collection rate of solid-state imaging devices, proposals to deepen the light receiving unit to improve quantum efficiency, and improvements to the output circuit to improve amplifier gain Has been made. In addition, as one of the solid-state imaging devices, there is a solid-state imaging device having an electron multiplication function that realizes high sensitivity by photoelectrically converting light received by the light receiving unit and multiplying the signal charge after conversion. It is disclosed as Patent Document 1.

  The electron multiplication function means that a high gate application voltage is applied to a specific gate of a transfer unit where a solid-state imaging device transfers a signal charge, and the signal charge is avalanche amplified by a strong electric field generated according to the voltage. The function of amplifying signal charges. However, in avalanche amplification, there is a problem that noises other than signal charges are also amplified, and there is a problem that the insulating film is deteriorated by a high gate applied voltage and the electron multiplication factor changes with time.

  There are several prior arts to solve the above problems. For example, Patent Document 2 discloses that a P-type impurity concentration in a P-type well region that forms a multiplication register is higher than a P-type impurity concentration in a P-type epitaxial layer in which the well region is formed. A solid-state imaging device with a built-in electron multiplication function is disclosed. The solid-state imaging device disclosed in Patent Document 2 suppresses unnecessary carriers (charges) from being mixed into the transfer unit by using a high-resistance epitaxial layer. Patent Document 3 discloses that a semiconductor region under a high-voltage electrode that causes charge multiplication has a higher deficiency than a region under the electrode on the front side of the high-voltage electrode in a series of electrodes. A CCD device is disclosed that is doped to have a density. The CCD element of Patent Document 2 suppresses the deterioration of gain performance by preventing electrons in the semiconductor from encountering the surface of the semiconductor.

Japanese Patent Laid-Open No. 7-176721 (published July 14, 1995) JP 2010-177588 A (released on August 12, 2010) JP 2008-535231 A (released on August 28, 2008)

  However, all of the solid-state imaging devices using the above-described conventional technology have a problem of consuming a lot of power because they require a high gate application voltage. Further, there are problems of dark voltage deterioration due to heat generation of the solid-state imaging device, and performance deterioration and reliability due to deterioration of the insulating film.

  An object of one embodiment of the present invention is to realize a solid-state imaging device that is driven by a low gate application voltage and performs an efficient electron multiplication operation.

  In order to solve the above-described problem, a solid-state imaging device according to one embodiment of the present invention uses a vertical CCD to convert an electrical signal generated by photoelectric conversion from received light by a third N-type region that functions as a light receiving unit. Transfer to the second N-type region forming the channel, the normal horizontal CCD channel, and the multiplication horizontal CCD channel, and further output from the output unit. The third N-type region is the first N-type which is a substrate The multiplication horizontal CCD channel is formed on the first N-type region of the second N-type region. The multiplication horizontal CCD channel is formed on the first N-type region. A second gate group for applying a voltage to the multiplied horizontal CCD channel is connected to the normal horizontal CCD channel. Of the second N-type region, the first N-type region A solid-state image pickup device connected to a third gate group for applying a voltage to the normal horizontal CCD channel. When the voltage at the time of driving the solid-state imaging device is applied to the second gate group, the first N-type region, the second P-type region, and the multiplication horizontal CCD channel punch through, In addition, the well concentration of the second P-type region is set so that charges are not injected from the first N-type region into the multiplication horizontal CCD channel.

  According to the above configuration, there is an effect that it is possible to provide a solid-state imaging device that is driven by a low gate applied voltage and performs an efficient electron multiplication operation.

It is a top view of the solid-state image sensing device concerning Embodiment 1 of the present invention. It is a schematic diagram which shows the gate structure of the solid-state image sensor which concerns on Embodiment 1 of this invention, and the potential for every gate. It is a figure which shows the relationship between the potential difference between the channel under an adjacent gate among the multiplication horizontal CCD channels of a solid-state image sensor, and an electron multiplication factor. It is sectional drawing of the solid-state image sensor which concerns on Embodiment 1 of this invention. The solid-state imaging device according to the first embodiment of the present invention shows the relationship between the well concentration of the P-type region adjacent to the CCD channel and the gate voltage causing punch-through between the CCD channel and the substrate under a constant substrate potential. FIG. It is a figure which shows the relationship between the gate application voltage applied to the multiplication horizontal CCD channel of the solid-state image sensor which concerns on Embodiment 1 of this invention, and channel potential. It is a figure which shows the relationship between the gate application voltage applied to the multiplication horizontal CCD channel of the solid-state image sensor which concerns on Embodiment 1 of this invention, and channel potential. It is a figure which shows the relationship between the gate application voltage applied to the multiplication horizontal CCD channel of the solid-state image sensor which concerns on this invention and Embodiment 1, and the board | substrate electric potential which raise | generates the charge injection to a channel. In the solid-state imaging device according to the first embodiment of the present invention, it is a diagram showing the relationship between the well concentration of the first P-type region, the substrate voltage for optimal OFD suppression, and the substrate voltage necessary for the shutter operation. 6 is a flowchart illustrating an example of processing for setting a well concentration of a second P-type region in the solid-state imaging device according to the first embodiment of the present invention. It is a figure which shows the relationship between the gate applied voltage applied to a normal horizontal CCD channel of the solid-state image sensor which concerns on Embodiment 2 of this invention, and channel potential. It is a figure which shows the relationship between the gate applied voltage applied to a normal horizontal CCD channel of the solid-state image sensor which concerns on Embodiment 2 of this invention, and channel potential. It is a flowchart which shows an example of the process which sets the well density | concentration of a 3rd P type area | region in the solid-state image sensor which concerns on Embodiment 2 of this invention.

Embodiment 1
Hereinafter, Embodiment 1 of the present invention will be described in detail with reference to FIGS.

(Configuration of solid-state image sensor)
The configuration of the solid-state imaging device 100 according to the present embodiment will be described below with reference to FIG. FIG. 1 is a plan view showing an overview of the solid-state image sensor 100.

  The solid-state imaging device 100 includes a light receiving unit 1, a vertical CCD channel 2, a normal horizontal CCD channel 3, a multiplication horizontal CCD channel 4, and an output unit 5, as in the conventional solid-state imaging device. The solid-state imaging device 100 can output a signal charge obtained by photoelectrically converting the light received by the light receiving unit 1 via the vertical CCD channel 2 and the normal horizontal CCD channel 3. When the solid-state imaging device 100 applies a voltage higher than the voltage applied to the normal horizontal CCD channel 3 to one of the electrodes constituting the multiplication horizontal CCD channel 4, the solid-state image pickup device 100 transmits the signal charges to the vertical CCD channel 2 and the normal horizontal CCD channel. 3 is transferred to the multiplying horizontal CCD channel 4. The solid-state imaging device 100 can output the signal charge from the output unit 5 after multiplying the signal charge by avalanche amplification in the multiplication horizontal CCD channel 4.

  The light receiving unit 1 can generate a signal charge (electric signal) by photoelectric conversion from the received light. The light receiving unit 1 can transfer the converted signal charge to the vertical CCD channel 2. In the illustrated example, the light receiving units 1 are configured as photodiodes (PDs), and are arranged in a matrix in the solid-state imaging device 100. Further, a large number of light receiving sections 1 arranged in a matrix are connected to the vertical CCD channel 2 for each column. As a result, the light received by the entire number of light receiving units 1 is transferred to the corresponding vertical CCD channel 2 for each column of the light receiving units 1. That is, one light receiving unit 1 corresponds to one pixel in the solid-state imaging device 100.

  The vertical CCD channel 2 can transfer the signal charge transferred from the light receiving unit 1 to the normal horizontal CCD channel 3. In the illustrated example, a plurality of vertical CCD channels 2 are arranged, and a plurality of light receiving portions 1 corresponding to one column are connected to each vertical CCD channel 2. The plurality of vertical CCD channels 2 simultaneously transfer the signal charges transferred from the plurality of light receiving portions 1 corresponding to one row among the light receiving portions 1 arranged in a matrix to the normal horizontal CCD channel 3. To do. That is, the signal charges photoelectrically converted by each of the light receiving units 1 arranged in a matrix are transferred to the vertical CCD channel 2 in columns and then transferred to the normal horizontal CCD channel 3 in rows.

  The normal horizontal CCD channel 3 can output the signal charges corresponding to one row transferred from the vertical CCD channel 2. The normal horizontal CCD channel 3 is composed of a plurality of electrodes, and signal charges from the vertical CCD channel 2 are transferred by controlling a voltage applied to a third gate group described later. When the normal horizontal CCD channel 3 is applied with a voltage higher than the voltage applied to the third gate group 33 connected to the normal horizontal CCD channel 3 to one of the electrodes constituting the multiplication horizontal CCD channel 4. The signal charge is transferred to the multiplying horizontal CCD channel 4.

  The multiplication horizontal CCD channel 4 can amplify the signal charge transferred from the normal horizontal CCD channel 3 by avalanche amplification and transfer it to the output unit 5. The multiplying horizontal CCD channel 4 is composed of a plurality of electrodes, and controls the transfer of signal charges from the normal horizontal CCD channel 3 by controlling the voltage applied to the second gate group described later.

  The output unit 5 is electrically connected to the multiplication horizontal CCD channel 4 and can output the signal charge transferred from the multiplication horizontal CCD channel 4. The output unit 5 may be an amplifier that further amplifies and outputs signal charges, for example.

(Gate configuration and potential of solid-state image sensor)
The gate configuration of the solid-state imaging device 100 according to the present embodiment and the potential at each gate will be described with reference to FIG. FIG. 2 is a schematic diagram showing the gate configuration of the solid-state imaging device 100 and the potential for each gate. In the illustrated example, the solid-state imaging device 100 is driven by power supplied from a power source indicated as VDD. Further, in the drawing, the portions where the potential is indicated by the solid line portion and the dotted line portion indicate the fluctuation range of the potential in the transfer of the signal charge or the like. In addition, VDD and FDA whose potentials are indicated by hatched portions are a power source and an amplifier, respectively, and not a gate.

  A signal charge generated by photoelectric conversion from light received by a plurality of light-receiving units 1 indicated as PDs is a vertical CCD channel 2 constituted by channels connected to four types of gates indicated as ΦV1 to ΦV1-4. Forwarded to The signal charge is further transferred to a normal horizontal CCD channel 3 constituted by a channel to which two types of gates ΦH1 and ΦH2 are connected. When electron multiplication is not performed, signal charges are output as they are from ΦH1 and ΦH2.

  The multiplication horizontal CCD channel 4 is composed of channels to which four types of gates of EM1, EM2, DC1, and DC2 are connected. In the illustrated example, electron multiplication is performed in a channel to which the gates indicated by EM1 and EM2 are connected. The signal charge after the electron multiplication is transferred to the output unit 5.

  The output unit 5 includes two types of gates, OG and ΦR, and further includes an FDA that functions as an amplifier. The output unit 5 amplifies the signal charge received from the multiplying horizontal CCD channel 4 by OG and outputs it by FDA.

(Relationship between potential difference between channels under adjacent gates and electron multiplication factor)
FIG. 5 is a diagram illustrating a relationship between a potential difference between adjacent under-gate channels of a multiplication horizontal CCD channel and an electron multiplication factor in a solid-state imaging device having a general electron multiplication function including the solid-state imaging device 100 according to the present embodiment. 3 will be described. FIG. 3 is a diagram showing the relationship between the potential difference between adjacent under-gate channels and the electron multiplication factor in the multiplication horizontal CCD channel of the solid-state imaging device.

  In the example shown in the figure, the “channel potential difference between channels under adjacent gates (multiplier horizontal CCD channel)” is the channel connected to the gate indicated by EM1 in FIG. 2 and the channel connected to the gate adjacent to EM1. Shows the potential difference between. “Electron multiplication factor” indicates the multiplication factor when the signal charge is multiplied before and after passing through the gate indicated by EM1.

  Now, when two potential differences where a, b> 0 and a> b are considered, the electron multiplication factor with respect to the potential difference a is lower than the electron multiplication factor with respect to the potential difference b as in the illustrated example. Become. In other words, in order to realize a solid-state imaging device having a high electron multiplication factor, it is preferable to set the potential difference between the gates to be large in the multiplication horizontal CCD channel.

  However, if the gate applied voltage applied to EM1 is set large, for example, in order to increase the potential difference between the gates, problems such as deterioration of the insulating film occur. An imaging device such as a camera using a solid-state imaging device having an electron multiplication function that is currently used is used in a high-end field for special applications. Therefore, it is configured to drive at a high driving voltage without considering the cost and life of the solid-state imaging device. Therefore, in order to reduce the cost and extend the life of the solid-state imaging device, there is a demand for a solid-state imaging device that can maintain a high electron multiplication factor and can be driven with a lower gate applied voltage than conventional ones. . The inventor has newly found a method for setting these concentration conditions and the like.

(Layer structure of solid-state image sensor)
A layer structure of the solid-state imaging device 100 according to the present embodiment will be described with reference to FIG. 4 is a cross-sectional view of the solid-state imaging device 100 according to the present embodiment taken along the line AA ′ of FIG.

  In the illustrated example, the solid-state imaging device 100 further includes a first P-type region 11, a third P-type region 13, a second P-type region 14, a first one in addition to the configuration described in FIG. N-type region 20, first gate group 32, third gate group 33, and second gate group 34. In the illustrated example, the light receiving unit 1 is configured as a third N-type region, and the vertical CCD channel 2, the normal horizontal CCD channel 3, and the multiplication horizontal CCD channel 4 are used as the second N-type region. Is formed.

  In the illustrated example, the solid-state imaging device 100 is configured by stacking various regions on a first N-type region 20 that is a substrate.

  The first N-type region 20 is a region that conducts electricity by electrons, and is, for example, a silicon substrate. In the following description, the first N-type region 20 may be referred to as a substrate, and the potential of the first N-type region 20 may also be referred to as a substrate potential.

  The light receiving unit 1 is formed on the first P-type region 11. The first P-type region 11 is a region that conducts electricity by holes, and the well concentration in the region is limited by the well concentration condition P1. The first P-type region 11 is formed on the first N-type region 20. That is, the light receiving unit 1, the first P-type region 11, and the first N-type region 20 form a layer structure in this order. For example, the first P-type region 11 is preferably formed at a position where the depth from the surface of the solid-state imaging device 100 is 5 to 8 μm.

  The vertical CCD channel 2 is disposed on the surface of the solid-state imaging device 100, and the first gate group 32 is connected to the upper side. The vertical CCD channel 2 is formed on the P-type region. The first gate group 32 includes four types of gates ΦV1 to ΦV4.

  Usually, the horizontal CCD channel 3 is arranged at a position adjacent to the surface of the solid-state imaging device 100 and the vertical CCD channel 2. The normal horizontal CCD channel 3 is formed on the third P-type region 13 with the third gate group 33 connected to the upper side.

  The third gate group 33 is connected to the normal horizontal CCD channel 3, and a voltage can be applied to each channel of the normal horizontal CCD channel 3. In the illustrated example, the third gate group 33 is represented by two types of gates ΦH1 and ΦH2.

  The third P-type region 13 is a region that conducts electricity by holes, and the well concentration in the region is limited by the well concentration condition H3. In the illustrated example, the third P-type region 13 is formed on the first N-type region 20. For example, the third P-type region 13 is preferably formed at a position where the depth from the surface of the solid-state imaging device 100 is 5 to 7 μm.

  The multiplying horizontal CCD channel 4 is disposed on the surface of the solid-state imaging device 100 and at a position adjacent to the normal horizontal CCD channel 3. The multiplication horizontal CCD channel 4 has a second gate group 34 connected to the upper side and is formed on the second P-type region 14.

  The second gate group 34 can apply a voltage to each channel of the multiplication horizontal CCD channel 4. In the illustrated example, the second gate group 34 is represented by four types of gates of EM1, EM2, DC1, and DC2.

  The second P-type region 14 is a region that conducts electricity by holes, and the well concentration in the region is limited by the well concentration condition H2. In the illustrated example, the second P-type region 14 is formed on the first N-type region 20 and at a position adjacent to the third P-type region 13. The second P-type region 14 is preferably formed at a position where the depth from the surface of the solid-state imaging device 100 is 5 to 7 μm, for example.

(Relationship between well concentration in P-type region and gate applied voltage causing punch-through)
The solid-state imaging device needs to punch through the CCD channel and the substrate in an operation such as reading signal charges. FIG. 5 shows the relationship between the well concentration in the P-type region adjacent to the CCD channel and the gate application voltage that causes punch-through between the CCD channel and the substrate in the solid-state imaging device 100 according to this embodiment. More specifically, the well concentration in the second P-type region 14 and the application to the second gate group 34 necessary for punch-through between the multiplying horizontal CCD channel 4 and the first N-type region 20 occur. The relationship with the voltage to be shown is shown.

  In the illustrated example, when the substrate potential is an arbitrary constant value, the well concentration in the P-type region and the gate applied voltage are in a directly proportional relationship. That is, it can be seen that in order to realize a solid-state imaging device driven by a low gate applied voltage, the well concentration of the P-type region in contact with the CCD channel may be set low.

(Relationship between gate application voltage and channel potential to multiplication horizontal CCD channel)
FIG. 6 shows the relationship between the voltage applied to the second gate group 34 connected to the multiplication horizontal CCD channel 4 and the potential of the multiplication horizontal CCD channel 4 in the solid-state imaging device 100 according to the present embodiment. FIG. 6 is a diagram showing the relationship between the gate application voltage applied to the multiplying horizontal CCD channel 4 and the channel potential in the solid-state imaging device 100 according to the present embodiment.

  The illustrated example shows the difference in channel potential when three kinds of well concentrations of NH1> NH2> NH3 are applied to the well concentration conditions for setting the well concentration of the second P-type region 14 respectively. Yes. Further, when the increase amount of the channel potential exceeds the increase amount of the voltage applied to the second gate group 34, the multiplication horizontal CCD channel 4 and the first N-type region 20 cause punch through. Is shown.

  When the second P-type well concentration is NH1, punch-through does not occur between the multiplying horizontal CCD channel 4 and the first N-type region 20 in the range shown.

  When the well concentration is 2, punch-through occurs between the multiplying horizontal CCD channel 4 and the first N-type region 20 in a region where the voltage applied to the second gate group 34 is somewhat higher than 0V.

  When the well concentration is NH 3, punch-through occurs between the multiplication horizontal CCD channel 4 and the first N-type region 20 from a region where the voltage applied to the second gate group 34 is less than 0V.

  From the example shown in the figure, the channel potential is low when the well concentration of the second P-type region 14 is high, the channel potential is high when the well concentration of the second P-type region 14 is low, and punch-through occurs in a wide region. I understand that.

(Relationship between well concentration and potential difference)
With respect to the solid-state imaging device 100 according to the present embodiment, a difference in potential difference between adjacent gates of the second gate group 34 due to a difference in well concentration in the second P-type region 14 will be described with reference to FIG. . FIG. 7 is a diagram showing the relationship between the gate application voltage applied to the multiplying horizontal CCD channel 4 and the channel potential of the solid-state imaging device 100. In the illustrated example, description will be given using NH1 and NH2 among the well concentrations NH1 to NH3 shown in FIG.

  Consider a case where voltages applied to two adjacent gates in the second gate group 34 connected to the multiplication horizontal CCD channel 4 are 0V and 15V, respectively. That is, consider a case where the driving voltage of the multiplying horizontal CCD channel 4 is 15V. At this time, from the illustrated example, the potential difference when the well concentration of the second P-type region 14 is NH1 is ΔVe1, and the potential difference when the well concentration is NH2 is ΔVe2. Further, ΔVe1 <ΔVe2. That is, even if the voltage applied to the second gate group 34 is the same, the lower the well concentration, the greater the potential difference between the channels under the adjacent gates. Therefore, the electron multiplication factor in the multiplication horizontal CCD channel 4 can be set higher when the well concentration in the second P-type region 14 is lower.

(Relationship between gate application voltage to CCD channel and substrate potential)
From the results of FIGS. 6 and 7, punch-through is more likely to occur when the well concentration of the second P-type region 14 of the solid-state imaging device 100, i.e., the well concentration of the second P-type region 14, is further reduced. It was shown that can be set high.

  However, the well concentration of the second P-type region 14 needs to be set in consideration of the relationship with other members. For example, when charge injection from the substrate to the multiplying horizontal CCD channel 4 occurs when the multiplying horizontal CCD channel 4 causes punch through, the injected charge becomes noise and affects the transfer of the original signal charge. There is a risk of giving. For this reason, it is preferable to set the well concentration of the second P-type region 14 to be low within a range where charge injection does not occur. Alternatively, it is preferable to prevent charge injection from the substrate to the multiplying horizontal CCD channel 4 by setting the substrate potential high.

  FIG. 8 shows the relationship between the P-type region well concentration and the substrate potential in the solid-state imaging device 100 according to the present embodiment. FIG. 8 is a diagram showing the relationship between the gate application voltage applied to the gate group connected to the CCD channel of the solid-state imaging device 100 and the substrate potential causing charge injection into the channel. The well concentrations NH1 to NH3 in the figure are the same as the well concentrations NH1 to NH3 shown in FIG. 8 can be applied not only to the multiplication horizontal CCD channel 4, but also to the normal horizontal CCD channel 3. In the following description, the second gate group 34 connected to the multiplication horizontal CCD channel 4 is used. The relationship between the gate application voltage applied to the substrate and the substrate potential will be described.

  From the example shown in the figure, when the voltage applied to the second gate group 34 applied to the second gate group 34 increases, charge injection from the first N-type region 20 to the multiplication horizontal CCD channel 4 does not occur. It is understood that the substrate potential needs to be increased. It can also be seen that when the well concentration is low, the substrate potential causing charge injection is high when the voltage applied to the same second gate group 34 is applied.

  That is, if the well concentration of the second P-type region 14 is set low so that punch-through is likely to occur and the electron multiplication factor becomes high, charge injection from the first N-type region 20 into the multiplication horizontal CCD channel 4 It is necessary to set the substrate potential high so that noise does not occur.

(Well concentration of first P-type region and substrate voltage)
From the result of FIG. 8, it was shown that if the well concentration of the second P-type region 14 is lowered, the substrate potential needs to be set higher accordingly.

  However, the substrate potential needs to be set in consideration of the relationship between the substrate and other members. For example, the driving voltage required for the overflow drain (OFD) operation and the shutter operation of the solid-state imaging device 100 needs to be set according to the substrate potential and the well concentration of the first P-type region 11 in contact with the light receiving unit 1. .

  In order to suppress the blooming phenomenon that occurs when the light receiving unit 1 receives strong light, the solid-state imaging device 100 needs to perform an OFD operation. The OFD operation is for discharging (overflowing) an excessive amount of signal charges generated in the light receiving unit 1 by controlling the substrate potential to the substrate. Therefore, the drive voltage (overflow drain voltage: OFD voltage) necessary for the OFD operation increases correspondingly when the substrate potential is increased.

  Further, in order to set the amount of light received by the light receiving unit 1 to an appropriate amount, the solid-state imaging device 100 needs to perform a shutter operation. In the shutter operation, all charges generated in the light receiving unit 1 are discharged to the substrate by controlling the substrate potential. Therefore, when the substrate potential is set high, the shutter operation voltage required for the shutter operation increases accordingly. .

  The relationship between the well concentration of the first P-type region 11 and the substrate potential necessary for the OFD voltage and the shutter operation voltage will be described with reference to FIG.

  As shown in the figure, as the well concentration increases, the substrate potential and the shutter operating voltage for optimal OFD suppression both increase. Conversely, when the substrate potential is set high, the well concentration in the first P-type region also increases.

  The results of FIGS. 6 and 7 indicate that punch-through is likely to occur, and that the well concentration of the second P-type region 14 is preferably set low in order to set the electron multiplication factor high. . Further, the result of FIG. 8 indicates that the substrate potential needs to be set higher when the well concentration of the second P-type region 14 is lowered. From the result of FIG. 9, when the substrate potential is set high, it is necessary to set the OFD voltage and shutter operating voltage high, and the well concentration of the first P-type region 11 needs to be set high. It has been shown. In other words, it is necessary to set the well concentration of the second P-type region 14 in balance with the substrate potential. For example, it is preferable to set the substrate potential according to the specifications of the power supplied to the camera using the solid-state imaging device 100 and set the well concentration of the second P-type region 14 according to the set substrate potential. is there. The well concentration in the first P-type region 11 is set based on the OFD voltage set according to the substrate potential and the driving voltage for the shutter operation.

(Method for setting well concentration in second P-type region)
In the solid-state imaging device 100 according to the present embodiment, an example of a method for setting the well concentration of the second P-type region 14 will be described with reference to FIG. FIG. 10 is a flowchart illustrating an example of a method for setting the well concentration of the second P-type region 14 in the solid-state imaging device 100. In the illustrated example, the flowchart is shown as three steps, but is not limited thereto.

  First, the well concentration of the first P-type region 11 and the potential (substrate potential) of the first N-type region 20 are set according to the assumed OFD voltage and shutter operating voltage (S1). The setting is performed so as to satisfy the relationship shown in FIG. 9, for example. In that case, the substrate voltage for optimal OFD suppression and the substrate voltage necessary for the shutter operation with respect to the substrate potential (drive potential) during normal operation is the minimum of the total displacement amount from the original substrate potential. Thus, the substrate potential during normal operation and the well concentration of the first P-type region 11 are set.

  Next, from the information indicating the relationship between the substrate potential causing charge injection, the well concentration of the second P-type region 14, and the voltage applied to the second gate group 34, the well concentration of the second P-type region 14 Information indicating the relationship between the voltages applied to the second gate group 34 is obtained (S2). The information indicating the relationship between the well concentration of the second P-type region 14 and the voltage applied to the second gate group 34 corresponds to, for example, a straight line set for each well concentration shown in FIG. More specifically, in FIG. 8, when the potential of the first N-type region (substrate potential) set in S1 is applied, the second P-type region 14 in a range where charge injection does not occur. A combination of the well concentration and the voltage applied to the second gate group 34 is extracted.

  Then, the well concentration of the second P-type region 14 is set according to the assumed voltage applied to the second gate group 34 (S3). For example, in contrast to the straight line set for each well concentration shown in FIG. 8, when the voltage applied to the second gate group 34 is an assumed value, a straight line indicating a well concentration condition that does not cause charge injection is shown. decide. This can be realized by setting the well concentration corresponding to the straight line as the well concentration of the second P-type region 14.

By the above method, when a voltage assumed when the solid-state imaging device 100 is driven is applied to the second gate group 34, the second P in which charge injection from the substrate to the multiplication horizontal CCD channel 4 does not occur. The well concentration of the mold region 14 can be set. For example, when the voltage applied to the second gate group 34 is 13 V or more and 18 V or less, the well concentration of the second P-type region 14 is set to 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁵ cm ⁻³ or less. Can be set. At this time, the solid-state imaging device 100 maintains the electron multiplication factor in the multiplication horizontal CCD channel 4 high, and does not generate noise due to charge injection from the first N-type region 20 to the multiplication horizontal CCD channel 4. Efficient electron multiplication operation can be performed.

As described above, when the well concentration of the second P-type region 14 is set, the well concentration and the substrate potential of the first P-type region 11 are also set. For example, when the substrate potential is 8 V or more and 10 V or less, the well concentration of the first P-type region 11 can be set to 0.3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁵ cm ⁻³ or less. At this time, the solid-state imaging device 100 can be set and driven with an OFD voltage of 6 V or more and 10 V or less.

[Embodiment 2]
A second embodiment of the present invention will be described with reference to FIGS.

(Configuration of solid-state image sensor)
The configuration of the solid-state imaging device 100 according to the present embodiment is the same as that of the first embodiment except for some configurations. In the present embodiment, the solid-state imaging device 100 includes a first N-type region 20, a third P-type region 13, and a normal horizontal CCD channel 3 punched through, and a normal horizontal CCD from the first N-type region 20. In this configuration, charge is not injected into the channel 3.

(Relationship between well concentration condition and potential difference)
Regarding the solid-state imaging device 100 according to this embodiment, FIG. 11 and FIG. 12 show the difference in potential difference between adjacent gates of the third gate group 33 due to the difference in well concentration conditions of the third P-type region 13. It explains using. FIG. 11 is a diagram showing the relationship between the gate application voltage applied to the normal horizontal CCD channel 3 and the channel potential of the solid-state imaging device 100. FIG. 11 shows the case where FIG. 7 is applied to the normal horizontal CCD channel 3, and the well concentrations NH1 and NH2 in the figure are the same as those shown in FIG. FIG. 12 shows a configuration similar to that in FIG. 11, but compares well concentrations NH1 and NH3. The well concentration NH3 is the same as that shown in FIG.

Since the signal charge is not multiplied in the normal horizontal CCD channel 3, the potential difference between the channels under the two adjacent gates may be smaller than that in the multiplied horizontal CCD channel 4. However, the signal charge transfer efficiency (TE) in the normal horizontal CCD channel 3 is determined by TE = f (E _min , L) ∝ΔV / L ⁴ . Here, E _min is the minimum fringe electric field, and ΔV is the adjacent gate potential difference. That is, if the adjacent gate potential difference is large, the signal charge transfer efficiency in the normal horizontal CCD channel 3 can be increased, so that the potential difference is preferably large.

  Consider a case where voltages applied to two adjacent gates in the third gate group 33 connected to the normal horizontal CCD channel 3 are 0 V and 3 V, respectively. This is because the normal horizontal CCD channel 3 is driven by a gate application voltage lower than that of the multiplication horizontal CCD channel 4 and generally a drive voltage of about 3V is used. At this time, from FIG. 11, the potential difference when the well concentration condition of the third P-type region 13 is NH1 is ΔVh1, and the potential difference when the well concentration condition is NH2 is ΔVh2. Further, ΔVh1 <ΔVh2. That is, even if the voltage applied to the third gate group 33 is the same, the lower the well concentration, the larger the potential difference between the channels under the adjacent gates. Therefore, the transfer efficiency in the normal horizontal CCD channel 3 can be set higher when the well concentration of the third P-type region 13 is lower.

  From FIG. 12, the potential difference when the well concentration condition of the third P-type region 13 is NH3 is ΔVh3. Then, ΔVh1 (<ΔVh2) <ΔVh3. Therefore, when the well concentration condition of the third P-type region 13 is NH3, the potential difference can be maximized, and therefore the transfer efficiency in the normal horizontal CCD channel 3 can be set high.

(Method for setting well concentration of third P-type region 13)
In the solid-state imaging device 100 according to the present embodiment, an example of a method for setting the well concentration of the third P-type region 13 will be described with reference to FIG. FIG. 13 is a flowchart illustrating an example of processing for setting the well concentration of the third P-type region 13 in the solid-state imaging device 100. In the illustrated example, it is assumed that the potential (substrate potential) of the first N-type region 20 has been set by, for example, the method shown in FIG.

  First, from the information indicating the relationship between the substrate potential causing charge injection, the well concentration of the third P-type region 13, and the voltage applied to the third gate group 33, the well concentration of the third P-type region 13 and the first concentration Information indicating the relationship between the voltages applied to the three gate groups 33 is obtained (S11). The information indicating the relationship between the well concentration of the third P-type region 13 and the voltage applied to the third gate group 33 corresponds to, for example, a straight line set for each well concentration shown in FIG. More specifically, FIG. 8 shows the well concentration of the third P-type region 13 in a range where charge injection does not occur when the potential (substrate potential) of the first N-type region that has been set is applied. And a combination of voltages to be applied to the third gate group 33 are extracted.

  Then, the well concentration of the third P-type region 13 is set according to the voltage applied to the assumed third gate group 33 (S12). For example, in contrast to the straight line set for each well concentration shown in FIG. 8, when the voltage applied to the third gate group 33 is an assumed value, a straight line indicating a well concentration condition that does not cause charge injection is shown. decide. This can be realized by setting the well concentration corresponding to the straight line as the well concentration of the third P-type region 13.

According to the above method, the third P-type in which charge injection from the substrate to the normal horizontal CCD channel 3 does not occur when a voltage assumed when driving the solid-state imaging device 100 is applied to the third gate group 33. The well concentration of the region 13 can be set. For example, when the voltage applied to the third gate group 33 is 3 V or more and 5 V or less, the well concentration of the third P-type region 13 is set to 0.3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁵ cm ^−3. It can be set as: At this time, with respect to the solid-state imaging device 100 in which noise due to charge injection from the first N-type region 20 to the multiplication horizontal CCD channel 4 does not occur while maintaining the electron multiplication factor in the multiplication horizontal CCD channel 4 high, the normal horizontal The transfer efficiency in the CCD channel 3 can be increased.

[Modification]
[Summary]
In the solid-state imaging device (100) according to the first aspect of the present invention, the third N-type region functioning as the light receiving unit (1) generates an electrical signal generated by photoelectric conversion from the received light. ), The normal horizontal CCD channel (3), and the second horizontal N-type region forming the multiplication horizontal CCD channel (4), and further output from the output unit (5). The multiplication horizontal CCD channel is provided on the first P-type region (11) formed on the first N-type region (20) which is the substrate. Among the regions, the region is provided on the second P-type region (14) formed on the first N-type region, and is used for applying a voltage to the multiplication horizontal CCD channel. 2 gate groups (34) are connected, and the normal horizontal CCD channel is Of the second N-type region, the region is provided on a third P-type region (13) formed on the first N-type region, and a voltage is applied to the normal horizontal CCD channel. A solid-state imaging device to which a third gate group (33) for application is connected, and when the voltage at the time of driving the solid-state imaging device is applied to the second gate group, the first N The second region, the second P-type region, and the multiplying horizontal CCD channel are punched through, and charge is not injected from the first N-type region into the multiplying horizontal CCD channel. In this configuration, the well concentration of the P-type region is set.

  According to the above-described configuration, when a voltage is applied to the solid-state imaging device for driving, the first N-type region, the second P-type region, and the multiplication horizontal CCD channel are punched through, and the first N-type region is driven. No charge is injected from the mold region into the multiplying horizontal CCD channel. At this time, the gates adjacent to the second gate group in the multiplication horizontal CCD channel are connected to each other within a range in which noise due to charge injection from the first N-type region to the multiplication horizontal CCD channel does not occur. The potential difference between channels can be set large. Further, the gate application voltage applied to the second gate group can be set low according to the well concentration of the second P-type region. Therefore, a low gate that does not generate noise due to charge injection from the first N-type region to the multiplication horizontal CCD channel while maintaining a high electron multiplication factor in the multiplication horizontal CCD channel according to the potential difference between the channels. There is an effect that it is possible to provide a solid-state imaging device that is driven by an applied voltage and performs an efficient electron multiplication operation.

  The solid-state imaging device (100) according to the second aspect of the present invention is the first N-type when the voltage at the time of driving the solid-state imaging device is applied to the third gate group (33) in the first aspect. The region (20), the third P-type region (13), and the normal horizontal CCD channel (3) are punched through, and charge is not injected from the first N-type region into the normal horizontal CCD channel. Further, the well concentration of the third P-type region may be set.

  According to the above-described configuration, when a voltage is applied to the solid-state imaging device and driven, the first N-type region, the third P-type region, and the normal horizontal CCD channel punch through, and the first N-type region There is no charge injected from the region into the normal horizontal CCD channel. As a result, between the channels connected to the adjacent gates of the third gate group in the normal horizontal CCD channel, as long as noise due to charge injection from the first N-type region to the normal horizontal CCD channel does not occur. The potential difference can be set large. Accordingly, by reducing the charge transfer time in the normal horizontal CCD channel according to the potential difference between the channels, the transfer efficiency in the normal horizontal CCD channel is maintained high, while the normal horizontal CCD channel is changed from the first N-type region. There is an effect that it is possible to provide a solid-state imaging device that efficiently transfers charges without generating noise due to charge injection.

  In the solid-state imaging device (100) according to aspect 3 of the present invention, in the aspect 1 or 2, an excess charge of the signal charge generated in the third N-type region is transferred to the first N-type region (20). The well concentration of the first P-type region (11) may be set so that the first N-type region overflows and no charge is injected from the first N-type region to the third N-type region.

  According to the above configuration, the solid-state imaging device performs an overflow drain operation for discharging the excess charge generated in the third N-type region to the first N-type region, and performs the third drain operation from the first N-type region. A state in which no charge is injected into the N-type region is achieved. Thus, there is an effect that it is possible to provide a solid-state imaging device that performs an efficient electron multiplication operation within a range in which noise due to charge injection from the first N-type region to the third N-type region does not occur. .

A solid-state imaging device (100) according to an aspect 4 of the present invention is the solid-state imaging device (100) according to the aspect 1, wherein the substrate has a potential of 6V to 10V when the solid-state imaging device is driven, and the second gate group ( 34) The voltage applied to 34) is not less than 13V and not more than 18V, and the well concentration of the second P-type region (14) is not less than 1 × 10 ¹⁵ cm ^{−3 and not} more than 5 × 10 ¹⁵ cm ^−3. It is good.

  According to the above configuration, the solid-state imaging device is driven at a substrate potential of 6 V or more and 10 V or less, and a voltage applied to the multiplication horizontal CCD channel via the second gate group is 13 V or more and 18 V or less. . At this time, the solid-state imaging device punches through between the first N-type region, the second P-type region, and the multiplication horizontal CCD channel, but from the first N-type region to the multiplication horizontal CCD channel. The charge does not move. Furthermore, the voltage applied to the multiplying horizontal CCD channel is a lower value compared to 25 to 50 V in the case of a conventional solid-state imaging device having an electron multiplying function. Therefore, it is possible to provide a solid-state imaging device that reduces the load during driving and has a long lifetime.

The solid-state imaging device (100) according to aspect 5 of the present invention is the solid-state imaging element (100) according to aspect 4, wherein the voltage applied to the third gate group (33) is 3V or more and 5V or less when the solid-state imaging element is driven. The well concentration of the third P-type region (13) may be not less than 0.3 × 10 ¹⁵ cm ^{−3 and not} more than 2 × 10 ¹⁵ cm ⁻³ .

  According to the above configuration, when the voltage applied to the normal horizontal CCD channel through the third gate group is 3 V or more and 5 V or less, the solid-state imaging device has the first N-type region and the third P-type. Punch-through occurs between the region and the normal horizontal CCD channel, but it is possible to prevent the charge from moving from the first N-type region to the normal horizontal CCD channel.

In the solid-state imaging device (100) according to the sixth aspect of the present invention, in the fifth aspect, the well concentration of the first P-type region (11) is 0.3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁵ cm. ^-3 or less.

  According to the above configuration, no charge is injected from the first N-type region to the third N-type region when the solid-state imaging device is driven. Therefore, there is an effect that it is possible to provide a solid-state imaging device that performs an efficient electron multiplication operation in a range in which noise due to charge injection from the first N-type region to the third N-type region does not occur.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, a new technical feature can be formed by combining the technical means disclosed in each embodiment.

DESCRIPTION OF SYMBOLS 1 Light-receiving part 2 Vertical CCD channel 3 Normal horizontal CCD channel 4 Multiplication horizontal CCD channel 5 Output part 11 1st P-type area | region 13 3rd P-type area | region 14 2nd P-type area | region 20 1st N-type area | region 32 First gate group 33 Third gate group 34 Second gate group 100 Solid-state imaging device

Claims (6)

A third N-type region functioning as a light-receiving unit forms a vertical CCD channel, a normal horizontal CCD channel, and a multiplying horizontal CCD channel by using a second N-type electric signal generated by photoelectric conversion from the received light. Transfer to the area, and further output from the output unit,
The third N-type region is provided on a first P-type region formed on the first N-type region which is a substrate,
The multiplication horizontal CCD channel is an area provided on a second P-type area formed on the first N-type area in the second N-type area. A second gate group for applying a voltage to the horizontal CCD channel is connected;
The normal horizontal CCD channel is an area provided on a third P-type area formed on the first N-type area in the second N-type area. A solid-state imaging device to which a third gate group for applying a voltage to a channel is connected,
When a voltage at the time of driving the solid-state imaging device is applied to the second gate group, the first N-type region, the second P-type region, and the multiplication horizontal CCD channel punch through, and A solid-state imaging device, wherein a well concentration of the second P-type region is set so that charges are not injected from the first N-type region into the multiplication horizontal CCD channel. When a voltage at the time of driving the solid-state imaging device is applied to the third gate group, the first N-type region, the third P-type region, and the normal horizontal CCD channel punch through, and 2. The solid-state imaging device according to claim 1, wherein a well concentration of the third P-type region is set so that charges are not injected from the first N-type region into the normal horizontal CCD channel. The excess charge of the signal charge generated in the third N-type region overflows into the first N-type region, and no charge is injected from the first N-type region into the third N-type region. The solid-state imaging device according to claim 1, wherein a well concentration of the first P-type region is set. At the time of driving the solid-state image sensor,
The substrate has a potential of 6V to 10V, and
The voltage applied to the second gate group is not less than 13V and not more than 18V;
2. The solid-state imaging device according to claim 1, wherein a well concentration of the second P-type region is 1 × 10 ¹⁵ cm ⁻³ or more and 5 × 10 ¹⁵ cm ⁻³ or less. At the time of driving the solid-state image sensor,
The voltage applied to the third gate group is 3 V or more and 5 V or less;
5. The solid-state imaging device according to claim 4, wherein a well concentration of the third P-type region is 0.3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁵ cm ⁻³ or less. 6. The solid-state imaging device according to claim 5, wherein a well concentration of the first P-type region is 0.3 × 10 ¹⁵ cm ⁻³ or more and 2 × 10 ¹⁵ cm ⁻³ or less.

Images