JP2006073609A - Solid state imaging element, solid state imaging device, and imaging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make the easiness of charge transfer and the securement of a dynamic range compatible, in a solid state imaging element. <P>SOLUTION: The solid state imaging element comprises a photodiode in a pixel. The photodiode is so formed as to comprise the first impurity region of a second conductive type which is formed on the semiconductor substrate of a first conductive type, and the second impurity region of the first conductive type. The first impurity region has a plurality of impurity concentration peaks. At least such a first impurity concentration peak C1 which is close to the second impurity region is in a range of 3×10<SP>15</SP>≤C1≤2×10<SP>17</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device, and more particularly to a well structure in which a photodiode that receives light and performs photoelectric conversion is formed.

  There are a CCD type and a CMOS type solid-state imaging device. Recently, a demand for a CMOS type solid-state imaging device which is attractive for low cost and low power consumption has increased. As a prior art of the CMOS area sensor, the well layer of the photodiode was formed by performing thermal diffusion after ion implantation, and thus the concentration distribution in the substrate depth direction was generally gradually lowered. . As a result, the structure has no potential barrier in the substrate depth direction, and a part of the optical carriers generated in the well is lost in the substrate direction and does not contribute as an optical signal. Therefore, the quantization efficiency of the sensor is lowered, and the image quality is significantly deteriorated as the pixel size is reduced.

As a means for improving the quantization efficiency of the sensor, there is a structure having a carrier profile as described in Patent Document 1 (FIG. 6). This structure has an impurity diffusion region 6A having a high concentration in a deep region in the substrate, and has the effect of increasing the efficiency of extracting charges generated by light absorbed in the well to the surface side and improving the sensitivity.
US Pat. No. 6,483,129

  However, in such a structure, reducing the concentration on the substrate surface side causes a disadvantage in characteristics other than sensitivity due to the structure of the photodiode. Since the concentration of the well immediately below the charge storage portion of the photodiode becomes thin, there is a problem that the depletion voltage becomes high when the charge storage portion is sufficiently depleted and reset, especially when it is completely depleted. This point will be described in more detail.

  As a method for removing the reset noise of the photodiode, a reset operation for completely depleting the inside of the photodiode at the time of resetting and at the time of charge reading is particularly effective in reducing noise, and has been practically used. In order to realize this, the voltage for fully (preferably completely) depleting the photodiode needs to be lower than the reset voltage, and is sufficiently within the constraint range of the ON voltage of the transfer gate. Charge transfer needs to be done. From the viewpoint of ease of charge transfer, it is necessary to design the depletion voltage of the photodiode as low as possible. On the other hand, in order to secure a sufficient dynamic range, that is, a sufficient saturation charge number of the photodiode, it is desirable that the concentration of the charge storage region of the photodiode is higher. Therefore, reducing the concentration of the charge storage region is not preferable from the viewpoint of securing the dynamic range, although it has the effect of reducing the depletion voltage.

  Therefore, a solid-state imaging device that satisfies both the requirements of easy charge transfer and securing a dynamic range is desired.

In view of the above problems, the present invention is a solid-state imaging device having a photodiode in a pixel, wherein the photodiode is a second conductivity type first impurity formed on a first conductivity type semiconductor substrate. And a first impurity type second impurity region, the first impurity region having a plurality of impurity concentration peaks, and at least the second impurity region. The first impurity concentration peak in the vicinity of is in the range of 3 × 10 ¹⁵ to 2 × 10 ¹⁷ cm ⁻³ , thereby providing a solid-state imaging device.

  According to the present invention, since the extension of the depletion layer of the photodiode can be suppressed, the depletion voltage can be suppressed, and the number of saturated charges can be improved without increasing the power supply voltage. It is possible to provide a solid-state imaging device having a wide dynamic range with low voltage and low power consumption.

According to the present invention, a photodiode has a second conductivity type first impurity region (well) formed on a first conductivity type semiconductor substrate, and a first conductivity type second impurity region (charge storage region). ) At least, and the first impurity region has a plurality of impurity concentration peaks, and the first impurity concentration peak adjacent to the second impurity region is 3 × 10 ¹⁵ to 3 × 10 ¹⁵ . It is characterized by setting in the range of 2 × 10 ¹⁷ cm ⁻³ .

  In this way, by designing the concentration peak of the impurity region (region having the first impurity concentration peak) adjacent to the charge accumulation region to be higher than before, the spread of the depletion layer extending to the well side is suppressed, and as a result The present inventor has found a technique for maintaining the saturation charge while lowering the depletion voltage of the photodiode.

Specifically, in the carrier profile described in Patent Document 1 described above, the concentration in the vicinity of the surface of the well adjacent to the accumulation region and the region under the accumulation region is about 1 × 10 ¹⁵ cm ^−3. The depletion layer extends to the well side by about 1 μm. According to the actual measurement by the present inventor, in this case, the depletion voltage that does not contribute to the saturation charge and is wasted is about 1V. On the other hand, in the present invention, the depletion voltage can be greatly reduced by defining the concentration of the impurity region under the accumulation region.

  Further, the impurity concentration peak (third impurity concentration peak) of the intermediate region 109 formed below the first impurity concentration peak (in the depth direction of the substrate) is set to 1 of the concentration of the first impurity concentration peak. / 4 or more, and 1/3 or less of the peak concentration of the deep impurity region 110 (concentration of the second impurity concentration peak). According to such a configuration, carriers that have been lost to the substrate side in the past can be taken in as signal charges, and the quantization efficiency can be improved.

  The pixel structure of the present invention is preferably used for a structure having an amplifying element for amplifying photoelectrically converted charges in the pixel.

  Hereinafter, the present invention will be described in detail with specific examples.

(First embodiment)
FIG. 1 is a cross-sectional view for explaining the first embodiment. Reference numeral 101 denotes an n-type silicon substrate (semiconductor substrate). A p-type well (first impurity region) including a region having an impurity concentration peak of 108 to 110 is formed in the n-type silicon substrate 101, and an element is formed on the substrate surface. The isolation region 102, the transfer transistor gate electrode 103, the readout region 104, the photodiode storage region 105 (second impurity region), the photodiode surface p region 106 (third impurity region), and 111 are p-type wells. Is formed. The light shielding layer 107 has an opening to shield light to a region other than the photodiode. In this figure, wiring layers other than the light shielding layer are omitted. In FIG. 1, the first impurity region to be a well is divided into three regions for different purposes. In FIG. 1, an impurity region 108 having a first impurity concentration peak close to the surface of the photodiode storage region 105 is disposed near the surface. The impurity region 108 has a function of suppressing the width of the depletion layer at the junction with the storage region 105 of the photodiode. Due to this effect, the depletion voltage of the photodiode can be lowered, the photodiode can be reset without increasing the potential for resetting the readout region 104, and transfer efficiency can be improved, more preferably complete transfer.

  In addition, the transfer gate voltage required for resetting and transferring the photodiode, that is, the ON voltage applied to the gate electrode 103 of the transfer transistor can be reduced, and a dynamic range can be secured without causing an increase in the power supply voltage. It becomes.

  Further, the impurity region 110 having the second impurity concentration peak disposed deeper than the impurity region 108 can be formed by, for example, boron ion implantation. When implanted with acceleration energy of 2 MeV, approximately from the silicon surface. It can be formed to a depth of 3 μm. Although optical carriers generated at a deeper position than the impurity region 110 are damaged in the silicon substrate, optical carriers generated at a portion shallower than the peak 110 can be collected on the photodiode side. Reference numeral 109 denotes an intermediate region of the retrograde well, which is formed at a lower concentration than the impurity region 110 in order to diffuse light carriers generated near the impurity region 110 to the surface side. Further near the surface is an impurity region 108 close to the photodiode storage region 105. This has a function of forming a higher impurity concentration than the intermediate region 109 and suppressing the width of the depletion layer at the junction with the storage region 105 of the photodiode. By this effect, the depletion voltage of the photodiode can be lowered, and the photodiode can be completely reset and transferred without increasing the potential for resetting the readout region 104. In addition, the transfer gate voltage required for resetting and transferring the photodiode, that is, the ON voltage applied to the gate electrode 103 of the transfer transistor can be reduced, and a dynamic range can be secured without causing an increase in the power supply voltage. It becomes.

  FIG. 2 is an explanatory diagram of the concentration profile in the vertical direction of the photodiode portion. Reference numeral 206 denotes a concentration profile of the surface p region of the photodiode, which corresponds to 106 in FIG. 206 can be formed by implantation of boron or boron fluoride. Reference numeral 205 denotes a concentration profile of the accumulation region of the photodiode, which corresponds to 105 in FIG. 205 can be formed by implantation of phosphorus or arsenic. Reference numeral 208 denotes a concentration profile of the impurity region adjacent to the accumulation region 205, which corresponds to 108 in FIG. Reference numerals 209 and 209 ′ denote density profiles in the intermediate region, which correspond to 109 in FIG. In FIG. 2, the intermediate region is formed with two steps of peaks. As described above, the present invention is also effective in the case of forming by a plurality of stages of ion implantation in accordance with a desired structure. 209 and 209 ′ can be formed by two injections of boron or boron fluoride having different acceleration energies. Reference numeral 210 denotes a concentration profile of the impurity region located deeper than 208 and 209, and corresponds to 110 in FIG. 111 is omitted.

  Here, a means for achieving both improvement in sensitivity and improvement in saturation charge, which are the objects of the present invention, will be described below.

Whether or not an electron becomes a potential barrier when thermally diffusing can be roughly expressed by the following equation.
Vb = (kT / q) · ln (N1 / N2) <kT / q
Here, Vb is a barrier, k is a Boltzmann constant, T is a temperature, q is an elementary charge, N1 is a peak concentration of the barrier, and N2 is a concentration before the barrier. In the region indicated by the inequality sign, the charge can overcome the barrier by thermal excitation. That is, when N1 / N2 <e (approximately 3 or less), the barrier can be overcome. Accordingly, the present invention proposes a configuration in which the potential formed by 210 functions as a barrier, and the potential formed by the well region 208 adjacent to the accumulation region 205 does not serve as a barrier. Specifically, as described above,
(1) The concentration of the impurity region 210 is at least three times the peak concentration of the intermediate regions 209 and 209 ′.
(2) The peak concentration of the impurity region 208 adjacent to the accumulation region 205 is not more than four times the peak concentration of the intermediate regions 209 and 209 ′.

Regarding (2), the reason why the value is set to 4 times or less is that the well region 208 adjacent to the accumulation region 205 has a relationship of canceling each other as the Net concentration. Therefore, when focusing only on the well (boron) concentration, it is about 4 times. This is because even if it is a concentration, the effective Net concentration is actually reduced. Further, a specific example of the concentration relationship satisfying such a condition shows that the peak concentration of the impurity region 208 adjacent to the accumulation region 205 is 3 × 10 ¹⁵ to 2 × 10 ¹⁷ cm ⁻³ , and the intermediate regions 209 and 209 ′. It is effective that the peak concentration is 1 × 10 ^{15 to} 5 × 10 ¹⁶ cm ⁻³ and the concentration of the impurity region 210 is 3 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ⁻³ .

Next, means for suppressing the depletion voltage of the photodiode will be described. As an ideal design according to the present invention, it is important to keep the depletion layer spread within the adjacent impurity region 208. In the depletion layer, considering that the electric lines of force starting from a positive fixed charge start from a negative fixed charge, the total number of fixed charges in the accumulation region 205 is the number of fixed charges in the surface p region 206 in the depletion layer. It is equal to the sum of the fixed charge number and the fixed charge number in the depletion layer in the adjacent well 208. Considering that the surface p region 206 has a higher impurity concentration than 208, the majority of the fixed charges can be handled by the surface p region 206. Even if the concentration of the adjacent impurity concentration 208 is ½ or less that of the accumulation region 205, It can be a solution. According to the experiments and studies of the present inventors, the peak concentration of the accumulation region 205 is 3 × 10 ¹⁶ ≦ peak concentration of the accumulation region 205 ≦ 8 × 10 ¹⁷ cm ⁻³ , and the peak concentration of the adjacent impurity region 208 is 3 × 10 6. The effect of the present embodiment can be obtained when ¹⁵ cm ⁻³ ≦ peak concentration of the impurity region 208 ≦ peak concentration of the accumulation region 205. More preferably, the effect is high when it is ¼ or more of the accumulation region 205. More preferably, the peak concentration of the storage region 205 is 5 × 10 ¹⁶ ≦ peak concentration of the storage region 205 ≦ 2 × 10 ¹⁷ cm ⁻³ , and the peak concentration of the adjacent impurity region 208 is 1 × 10 ¹⁶ cm ⁻³ ≦ impurity. It is preferable that the peak concentration of the region 208 ≦ the peak concentration of the storage region 205 and the upper limit be the concentration of the storage region.

Further, it is more effective that the depth of each concentration peak has the following relationship. When the depth of the concentration peak of the accumulation region is V1, and the depth of the concentration peak of the adjacent impurity region 208 is V2, V1 <V2 <2 × V1.
With this relationship, the effect of the present embodiment can be obtained more effectively.

(Second Embodiment)
FIG. 3 is an explanatory diagram of the second embodiment. 301 to 311 correspond to 101 to 111 in FIG. In this embodiment, the impurity region 308 adjacent to the storage region 305 of the photodiode is not formed on the entire surface of the pixel, but is formed only in a portion below the storage region 305. The advantages of such a structure are as follows.
(1) [Structural advantage] Charges overflowing from adjacent pixels can be sucked into the readout region 304, so that there is an effect of preventing blooming, smearing and color mixing. The influence of the density design of 308 on the characteristics of the transistor in the pixel and outside the pixel region (not shown) is reduced, and the degree of freedom in design is increased. The junction capacitance in the readout region is reduced and the signal to noise ratio is improved by increasing the gain. And so on.
(2) [Process Advantage] The adjacent impurity region 308 can be formed using the same photoresist as the accumulation region 305 or the same as the surface p region 306. Although it is theoretically possible to form the impurity region 310 with the same resist, it is necessary to form a thick resist that can secure a blocking performance against deep ion implantation, and it is difficult to deal with fine patterns. It is also possible to form the impurity region 310 by buried Epi. In such a case, the impurity region 308 adjacent to the storage region 305 is made of the same photoresist as the storage region 305 or the same as the surface p region 306. Thus, the effect of the present embodiment can be obtained without increasing the number of steps.

(Third embodiment)
FIG. 4 is a top view of the pixel structure according to the third embodiment. Reference numeral 401 denotes an active region, 402 denotes a transfer gate electrode, 403 denotes a photodiode region, and 404 denotes a readout region. The length in the direction parallel to the channel width of the transistor is Dy1 and Dy2, which indicates the width of the photodiode region. In general, the depletion voltage becomes high in a wide portion, and therefore, if a layout having a narrow width on the side close to the transfer gate 402 as shown in FIG. 4 is used, there arises a problem that complete transfer becomes difficult. That is, at the time of resetting or transferring, there is a problem that the Dy1 portion is completely depleted before the Dy2 portion, charges remain in the Dy2 portion, and reset noise occurs. This problem occurs because the depletion voltage has size dependence due to the influence of the spread of the depletion layer from the lateral direction (the length direction of Dy1 and Dy2). Specifically, when the concentration near the surface of the retrograde well is designed to be thin and the depletion layer extends widely in the depth direction, this becomes a particularly significant problem. In the present embodiment, as a result of suppressing the expansion of the depletion layer in the depth direction, restrictions on the layout are reduced, and even if the layout shown in FIG. 4 is performed, no reset noise is generated. The reason will be described with reference to FIG. FIG. 5 is a schematic diagram showing a cross section along Dy1 and Dy2 in FIG. Reference numeral 405 denotes a depletion layer region extending to the photodiode and the well, and its depth is indicated by Dz. Reference numeral 406 denotes a neutral region remaining at the end immediately before complete depletion. Reference numeral 407 indicates a state of a depletion layer extending in the depth direction, and reference numeral 408 indicates a state of a depletion layer extending in the lateral direction (length direction of Dy1 and Dy2). In the case of complete depletion due to the effect of the depletion layer spreading in the depth direction as shown in this figure, Dy1 and Dy2 have the same depletion voltage regardless of the layout, and complete reset and complete transfer of the photodiode are possible. In the case where Dy1 is narrower than this figure and the structure having a large depletion layer spread 407 in the depth direction, the depletion voltage is Dy1 because Dy1 is completely depleted by the influence of the lateral depletion layer spread 408. It becomes smaller depending on the width. In view of the above problems, the present embodiment adopts the following structure in order to equalize the depletion voltages of the Dy1 portion and the Dy2 portion.

  In a pixel having a layout where Dy2> Dy1, the well concentration is set so that the expansion width of the depletion layer in the depth direction is suppressed and Dy1> Dz.

  In the structure of this embodiment, the depletion voltage can be made the same at any location on the planar layout of the photodiode, high-speed operation is possible, and deterioration in image quality due to reset noise can be suppressed. Is possible.

  In addition, a plurality of solid-state imaging devices according to each embodiment can be used as an area sensor (solid-state imaging device) arranged in two dimensions. In addition, the readout region described in each embodiment can be used in an amplification type solid-state imaging device (Active Pixel Sensor) in which the gate is connected to the gate of an insulated gate transistor and the charge voltage is converted and read out.

(Application to imaging system)
FIG. 6 shows an example of a circuit block when the solid-state imaging device according to the present invention is applied to a camera. A shutter 1001 is provided in front of the taking lens 1002 and controls exposure. The amount of light is controlled by the diaphragm 1003 as necessary, and an image is formed on the solid-state imaging device 1004. A signal output from the solid-state imaging device 1004 is processed by a signal processing circuit 1005 and converted from an analog signal to a digital signal by an A / D converter 1006. The output digital signal is further processed by a signal processing unit 1007. The processed digital signal is stored in the memory 1010 or sent to an external device through the external I / F 1013. The solid-state imaging device 1004, the imaging signal processing circuit 1005, the A / D converter 1006, and the signal processing unit 1007 are controlled by a timing generation unit 1008, and the entire system is controlled by an overall control unit / arithmetic unit 1009. In order to record an image on the recording medium 1012, the output digital signal is recorded through a recording medium control I / F unit 1011 controlled by the overall control unit / arithmetic unit.

Sectional drawing for demonstrating 1st Embodiment The figure which represented the density profile by 1st Embodiment typically Sectional drawing for demonstrating 2nd Embodiment Top view for explaining the third embodiment Sectional drawing for demonstrating 3rd Embodiment Block diagram for explaining an imaging system

Explanation of symbols

101, 301 Semiconductor substrate 102, 302 Element isolation region 103, 303 Gate electrode 104, 304 Read region 105, 305 Charge storage region 106, 306 Surface region 107, 307 Light shielding film 108, 308 Region having first impurity concentration peak 109 , 309 Region having the second impurity concentration peak 110, 310 Region having the third impurity concentration peak 205 Impurity concentration in the charge storage region 206 Impurity concentration in the surface region 208 Impurity concentration in the region having the first impurity concentration peak 209 209 ′ Impurity concentration in the region having the second impurity concentration peak 210 Impurity concentration in the region having the third impurity concentration peak 401 Active region 402 Gate electrode 403 Photodiode region 404 Read-out region 1001 Shutter 1002 Lens 1003 aperture 1004 solid-state imaging device 1005 signal processing circuit 1006 A / D converter 1007 signal processing section 1008 timing generator 1009 control unit and arithmetic operation unit 1010 memory unit 1011 interface unit 1012 a recording medium

Claims (12)

A solid-state imaging device having a photodiode in a pixel, wherein the photodiode has a first conductivity type first impurity region formed on a first conductivity type semiconductor substrate, and a first conductivity type first impurity region. The first impurity region has a plurality of impurity concentration peaks, and at least the first impurity concentration peak C1 adjacent to the second impurity region is 3 ×. A solid-state imaging device having a range of 10 ¹⁵ ≦ C1 ≦ 2 × 10 ¹⁷ cm ⁻³ .   The solid-state imaging device according to claim 1, further comprising a third conductivity region of a second conductivity type on the second impurity region.   The plurality of impurity concentration peaks are a second impurity concentration peak C2 formed at a position deeper in the substrate than the first impurity concentration peak and a third impurity concentration peak located between the first and second impurity concentration peaks. The solid-state imaging device according to claim 1, wherein the solid-state imaging device has an impurity concentration peak C3.   The solid-state imaging device according to claim 3, wherein the second impurity concentration peak and the third impurity concentration peak satisfy C2 ≧ 3 × C3.   5. The solid-state imaging device according to claim 3, wherein the first impurity concentration peak and the third impurity concentration peak satisfy C 3 <C 1 ≦ 4 × C 3. The impurity concentration peak C4 of the second impurity region is in the range of 3 × 10 ¹⁶ ≦ C4 ≦ 8 × 10 ¹⁷ cm ⁻³ , and the first impurity concentration peak is 3 × 10 ¹⁵ cm ⁻³ ≦ C1 ≦ C4. The solid-state imaging device according to claim 1, wherein   The solid-state imaging device according to claim 6, wherein the first impurity concentration peak C1 and the impurity concentration peak C4 of the second impurity region satisfy C4 / 4 ≦ C1 ≦ C4.   The first impurity concentration peak is disposed under the second impurity region, and is not disposed under at least a part of the transistor and readout region disposed in the pixel. Item 8. The solid-state imaging device according to any one of Items 1 to 7.   2. The depth (V1) of the impurity concentration peak of the second impurity region and the depth (V2) of the first impurity concentration peak satisfy V1 <V2 <2 × V1. The solid-state image sensor of any one of -8.   Further, the pixel includes a transfer transistor, and the length of the photodiode in the direction substantially parallel to the channel width of the transfer transistor has at least two values, Dy1 and Dy2, and the Dy1 portion Is closer to the gate electrode of the transfer transistor than the Dy2 portion, and when the width in the depth direction of the depletion layer at the time of resetting the photodiode is Dz, the relationship is Dy2> Dy1> Dz. Item 10. The solid-state imaging device according to any one of Items 1 to 9.   A solid-state imaging device comprising a plurality of the solid-state imaging elements according to claim 1. 12. An imaging system comprising: the solid-state imaging device according to claim 11; an optical system that focuses light on the solid-state imaging device; and a signal processing circuit that processes an output signal from the solid-state imaging device. .

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