JP2018183426A - Ultrasonic imaging apparatus, ultrasonic transducer, and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMUT having flexibility and curved surface followability while maintaining performance of the CMUT.SOLUTION: An ultrasonic transducer includes a plurality of semiconductor chips CHP1 formed with cells performing reception of the ultrasonic wave and a flexible substrate FS which is in close contact with the plurality of semiconductor chips CHP1. Here, in a case where attention is paid to the mutually-adjacent semiconductor chip CHP1a and semiconductor chip CHP1b among the plurality of semiconductor chips CHP1, the semiconductor chip CHP1a includes a side surface S1 and the semiconductor chip CHP1b includes a side surface S2 facing the side surface S1. A first portion of the side surface S1 is s cleavage plane, and the second portion of the side surface S2 facing the first portion is also a cleavage plane.SELECTED DRAWING: Figure 11

Description

  The present invention relates to an ultrasonic imaging apparatus, an ultrasonic transducer, and a manufacturing technique thereof. For example, the present invention relates to an ultrasonic transducer manufactured by a MEMS (Micro Electro Mechanical Systems) technique and a technique effective when applied to the manufacturing technique.

  Japanese Patent Laying-Open No. 2005-295553 (Patent Document 1) describes a technique for suppressing acoustic crosstalk between adjacent ultrasonic transducers by forming a trench between adjacent ultrasonic transducers. Yes.

JP 2005-295553 A

  Ultrasonic transducers are used in various applications such as diagnosis of tumors in the human body and inspection of cracks generated in buildings by transmitting and receiving ultrasonic waves.

  Up to now, ultrasonic transducers using the vibration of piezoelectric materials have been used, but due to the recent advancement of MEMS technology, a capacitive detection type ultrasonic transducer (CMUT: Capacitive) in which a vibration part is fabricated on a silicon substrate. Micromachined Ultrasonic Transducer) has been actively developed for practical use.

  CMUT has advantages such as a wider frequency band of ultrasonic waves that can be used or higher sensitivity than ultrasonic transducers using piezoelectric materials. In addition, since it can be manufactured using LSI processing technology, there is an advantage that fine processing is possible.

  When the surface of the subject to be subjected to ultrasonic examination has a curved surface or uneven shape, the conventional ultrasonic probe is not flexible and cannot follow the curved surface or uneven surface of the subject surface. It was difficult to obtain a good inspection image. Even when the CMUT is used as an ultrasound probe, if the surface of the subject has a curved surface or an uneven shape, it is necessary to devise the CMUT with flexibility and curved surface followability while maintaining the performance of the CMUT. The

  An object of the present invention is to provide a CMUT having flexibility and curved surface followability while maintaining the performance of the CMUT.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An ultrasonic transducer in one embodiment includes a plurality of semiconductor chips on which cells for receiving ultrasonic waves are formed, and a flexible member that is in close contact with the plurality of semiconductor chips. Here, when attention is paid to the first semiconductor chip and the second semiconductor chip adjacent to each other among the plurality of semiconductor chips, the first semiconductor chip includes the first side surface, and the second semiconductor chip includes the first side surface. And a second side surface opposite to the first side surface. And the 1st part of the 1st side is a cleavage plane, and the 2nd part which is the 2nd part of the 2nd side and opposes the 1st part is also a cleavage plane.

  According to one embodiment, it is possible to provide a CMUT having flexibility and curved surface followability while maintaining the performance of the CMUT.

It is a block diagram which shows the structure of the ultrasonic imaging device in embodiment. It is a block diagram which shows the structure of the ultrasonic probe in embodiment. It is sectional drawing which shows the fundamental sectional structure of one cell. It is a schematic diagram which shows the example which uses a flexible ultrasonic probe. It is a schematic diagram explaining the example of application of CMUT which has curved surface followability. It is a figure explaining the related technique which affixes a some fine semiconductor chip on a flexible substrate. It is a figure which shows the ideal state which affixes a several fine semiconductor chip on a flexible substrate at equal intervals. It is a figure which shows the realistic state which affixes a several fine semiconductor chip on the flexible substrate at the space | interval which varied. (A) And (b) is a graph which shows intensity distribution at the time of superimposing the ultrasonic wave output from each of the some semiconductor chip which comprises CMUT. It is a perspective view which shows the external appearance structure of CMUT in embodiment. It is sectional drawing which shows typically a part of CMUT in embodiment. It is a schematic diagram which shows the structure which affixed CMUT in embodiment to the curved surface member. It is sectional drawing which shows typically the state which affixed CMUT on the curved surface member. It is sectional drawing which shows typically the state which affixed CMUT on the curved surface member. It is a figure which shows the manufacturing process of CMUT in embodiment. FIG. 16 is a diagram illustrating a CMUT manufacturing process subsequent to FIG. 15, and a plan view of the chip array; FIG. 16 is a diagram illustrating a manufacturing step of the CMUT following FIG. 15, and is a cross-sectional view of the chip array. FIG. 18 is a diagram showing a CMUT manufacturing process following FIG. 17. It is a figure which shows the manufacturing process of CMUT following FIG. FIG. 20 is a diagram illustrating manufacturing steps of CMUT subsequent to FIG. 19. FIG. 21 is a plan view showing a CMUT manufacturing process following FIG. 20; It is sectional drawing cut | disconnected by the AA line of FIG. FIG. 22 is a plan view showing a CMUT manufacturing process following FIG. 21; It is sectional drawing cut | disconnected by the AA line of FIG. FIG. 18 is a plan view illustrating a modification example of the CMUT manufacturing process subsequent to FIG. 17. It is sectional drawing cut | disconnected by the AA line of FIG. It is a figure which shows the manufacturing process of CMUT in a modification. FIG. 28 is a diagram illustrating manufacturing steps of CMUT subsequent to FIG. 27. FIG. 29 is a diagram illustrating a manufacturing step of the CMUT subsequent to FIG. 28.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

<Configuration of ultrasonic imaging apparatus>
First, a configuration example and the role of the ultrasonic imaging apparatus according to the present embodiment will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of an ultrasonic imaging apparatus 1000 according to the present embodiment. In FIG. 1, an ultrasonic imaging apparatus 1000 according to the present embodiment includes a main body and an ultrasonic probe 1001. The main body includes a transmission / reception separation unit 1002, a transmission unit 1003, a bias unit 1004, a reception unit 1005, and an adjustment unit. A phase addition unit 1006, an image processing unit 1007, a display unit 1008, a control unit 1009, and an operation unit 1010 are included.

  The ultrasonic probe 1001 is a device that transmits and receives ultrasonic waves to and from a subject by making contact with the subject, and is manufactured using the CMUT in this embodiment. An ultrasonic wave is transmitted from the ultrasonic probe 1001 to the subject, and a reflected echo signal from the subject is received by the ultrasonic probe 1001. The ultrasonic probe 1001 is electrically connected to a transmission / reception separating unit 1002 described later.

  The transmission unit 1003 and the bias unit 1004 have a function of supplying a drive signal to the ultrasonic probe 1001 in order to transmit ultrasonic waves from the ultrasonic probe 1001.

  The receiving unit 1005 has a function of receiving a reflected echo signal output from the ultrasonic probe 1001. The receiving unit 1005 further performs signal processing such as analog-digital conversion (AD conversion) on the received reflected echo signal.

  The transmission / reception separating unit 1002 electrically connects the ultrasonic probe 1001 and the transmission unit 1003 when transmitting ultrasonic waves, while electrically connecting the ultrasonic probe 1001 and the reception unit 1005 when receiving ultrasonic waves. Has a function of switching the connection path so as to be connected. That is, the transmission / reception separating unit 1002 switches between transmission and reception so as to pass a drive signal from the transmission unit 1003 to the ultrasonic probe 1001 during transmission and to pass a reception signal from the ultrasonic probe 1001 to the reception unit 1005 during reception. Have the function of separating.

  The phasing addition unit 1006 has a function of adding a reflection echo signal output from the focus point in consideration of a time difference received by each CMUT cell. That is, the phasing addition unit 1006 has a function of adding (phasing addition) in consideration of the phase difference of the reflected echo signal.

  The image processing unit 1007 has a function of forming an inspection image based on the reflection echo signal subjected to phasing addition. The display unit 1008 is a display device that displays the image processed inspection image.

  The control unit 1009 has a function of controlling each component constituting the main body, and the control unit 1009 controls transmission / reception of ultrasonic waves of the ultrasonic probe 1001.

  The operation unit 1010 is a device that gives an instruction to the control unit 1009, and the operation unit 1010 includes, for example, an input device such as a trackball, a keyboard, or a mouse. As described above, the ultrasonic imaging apparatus according to the present embodiment is configured.

<Configuration of ultrasonic probe>
Next, the configuration of the ultrasonic probe 1001 will be described. FIG. 2 is a block diagram showing a configuration of the ultrasound probe 1001 in the present embodiment. As shown in FIG. 2, the ultrasound probe 1001 in the present embodiment includes a CMUT 100, and the CMUT 100 is composed of a plurality of semiconductor chips CHP1. A plurality of cells CL are formed in each of the plurality of semiconductor chips CHP1. In this way, the ultrasonic probe 1001 in the present embodiment is configured.

<Configuration and operation of CMUT cell>
Subsequently, the device structure of the cells constituting the CMUT will be described.

  FIG. 3 is a cross-sectional view showing a basic cross-sectional structure of one cell. A lower electrode BE is formed over the substrate SUB via an insulating film IF1, and a cavity CAV surrounded by the insulating film IF2 is formed over the lower electrode BE. The membrane MB is disposed by the upper insulating film IF2 and the upper electrode UE in the cavity CAV.

  When a DC voltage and an AC voltage are superimposed between the upper electrode UE and the lower electrode BE, an electrostatic force works between the upper electrode UE and the lower electrode BE, and the membrane MB vibrates at the frequency of the AC voltage applied. Send ultrasound. At this time, an ultrasonic wave can be transmitted efficiently by applying an alternating voltage having a frequency close to the resonance frequency of the membrane MB.

  When receiving ultrasonic waves, the membrane MB vibrates due to the pressure of the ultrasonic waves reaching the surface of the membrane MB. Then, since the distance between the upper electrode UE and the lower electrode BE changes, ultrasonic waves can be detected as a change in capacitance. Also at this time, ultrasonic waves having a frequency close to the resonance frequency of the membrane MB can be received efficiently. As described above, the cell according to the present embodiment is configured.

<Future uses of CMUT>
As one of the future developments of CMUT, it is assumed that the ultrasonic probe including CMUT will be flexible. For example, development of an ultrasonic imaging apparatus using a flexible ultrasonic probe is desired. . FIG. 4 is a schematic diagram illustrating an example in which a flexible ultrasonic probe is used. As shown in FIG. 4, for example, by applying a flexible ultrasonic probe 1001 to the elbow of a human arm ARM, an ultrasonic image of the bending elbow can be acquired. Based on this ultrasonic image, A diagnosis by a doctor can be realized.

  FIG. 5 is a schematic diagram for explaining an application example of the CMUT 100 having curved surface followability. In FIG. 5, a catheter CT is inserted into the blood vessel BV, and a CMUT 100 having a curved surface following property is provided following the curved surface shape of the catheter CT. In this configuration, light is emitted from the catheter CT. Irradiate toward the inner wall of the blood vessel BV. At this time, if the plaque PQ is attached to the inner wall of the blood vessel BV, the plaque PQ is irradiated with light. When the plaque PQ is irradiated with light, the plaque PQ is warmed by the energy of the irradiated light. As a result, the plaque PQ expands and ultrasonic waves are output from the plaque PQ. Therefore, the state of the plaque PQ on the inner wall of the blood vessel BV can be confirmed by receiving the ultrasonic wave generated from the plaque PQ by the CMUT provided on the surface of the catheter CT. In this way, by providing the CMUT with flexibility and curved surface followability, the application range of the CMUT is expanded.

  Here, an important point is that it is necessary to devise in order to give the CMUT flexibility and curved surface followability while maintaining the device performance of the CMUT.

  This point will be described below. For example, as a method of giving CMUT flexibility and curved surface followability, first, there is a method of directly manufacturing a device structure on a flexible substrate. However, in this method, as a result of using a flexible substrate generally made of an organic material, temperature restrictions are added in the manufacturing process of the device structure, and it is difficult to manufacture a CMUT having good device characteristics. To do. That is, the method of directly manufacturing the device structure on the flexible substrate is not an appropriate method from the viewpoint of realizing a structure that gives the CMUT flexibility and curved surface followability while maintaining the device performance of the CMUT. is there.

  Next, for example, a method of attaching a plurality of fine semiconductor chips on a flexible substrate is conceivable. In this method, since the gap between the semiconductor chips has flexibility, the CMUT can have flexibility and curved surface followability. However, since there is room for improvement in this method, the room for improvement existing in this method will be described below with reference to the drawings.

<Examination of improvement>
FIG. 6 is a diagram for explaining a related technique for attaching a plurality of fine semiconductor chips on a flexible substrate. As shown in FIG. 6, the CMUT 100 according to the related art includes semiconductor chips CHP1a to CHP1g each having a cell CL formed on a flexible substrate FS. At this time, as shown in FIG. 6, the individual semiconductor chips CHP1a to CHP1g are arranged on the flexible substrate FS by a mechanical handling mechanism. As a result, the gaps between the semiconductor chips vary. Then, the device performance of the CMUT deteriorates due to variations in the gap between the semiconductor chips.

  Specifically, FIG. 7 is a diagram showing an ideal state in which a plurality of fine semiconductor chips are pasted on the flexible substrate at prescribed equal intervals. In FIG. 7, on the flexible substrate FS, semiconductor chips CHP1a to CHP1g each having a cell CL are arranged at equal intervals. Here, in the CMUT 100, the resolution of the CMUT 100 can be improved by concentrating the ultrasonic waves output from each of the semiconductor chips CHP1a to CHP1g at the focus point. In particular, at the focus point, the ultrasonic waves output from each of the semiconductor chips CHP1a to CHP1g are superimposed. At this time, in order to increase the intensity of the ultrasonic wave at the focus point, it is necessary to superimpose the ultrasonic waves output from the semiconductor chips CHP1a to CHP1g so as to strengthen each other at the focus point. In other words, the phases of the ultrasonic waves output from each of the semiconductor chips CHP1a to CHP1g need to be aligned at the focus point. Here, as shown in FIG. 7, the distance from each of the semiconductor chips CHP1a to CHP1g arranged on the flexible substrate FS to the focus point is different. Therefore, for example, in FIG. 7, when ultrasonic waves are output from the semiconductor chips CHP1a to CHP1g at the same time, the distance from each of the semiconductor chips CHP1a to CHP1g to the focus point is different, which causes the semiconductor chips CHP1a to CHP1g. The phases of the ultrasonic waves output from each of these are not aligned at the focus point. This means that superimposing superposition of ultrasonic waves cannot be realized at the focus point. This means that the reflected echo signal from the focus point is weakened, which means that the sensitivity of the CMUT 100 cannot be improved.

  Therefore, in CMUT 100, the ultrasonic waves are not output from each of the semiconductor chips CHP1a to CHP1g at the same time, but are strengthened at the focus point according to the distance from each of the semiconductor chips CHP1a to CHP1g to the focus point. As described above (so that the phases are aligned), the time for outputting the ultrasonic waves is adjusted.

  In this regard, for example, as shown in FIG. 7, when a plurality of fine semiconductor chips CHP1a to CHP1g are attached on the flexible substrate FS at regular intervals, the focus point is changed from one semiconductor chip. The distance from the semiconductor chip adjacent to the semiconductor chip to the focus point can be calculated in advance. That is, the difference in distance from each of the adjacent semiconductor chips to the focus point can be calculated. Therefore, in this case, it is possible to cope with the difference in the calculated distance by advancing the output time of the ultrasonic wave in the semiconductor chip arranged at a long distance among the adjacent semiconductor chips. . Specifically, for example, as shown in FIG. 7, the semiconductor chips CHP1a to CHP1g are attached at a regular interval (chip interval d), and the semiconductor chip is on the normal line from the focus point to the surface of the CMUT 100. The output time of the ultrasonic wave from the CHP 1d is “T”. At this time, the distance from each of the semiconductor chip CHP1c and the semiconductor chip CHP1e to the focus point can be calculated using the distance from the semiconductor chip CHP1d to the focus point and the chip interval d. The semiconductor chip CHP1c and the semiconductor chip The output time of the ultrasonic waves from each of the CHPs 1e can be set to “T−Δt1”. Similarly, the distance from each of the semiconductor chip CHP1b and the semiconductor chip CHP1f to the focus point is the distance from the semiconductor chip CHP1d to the focus point, and the chip interval “2 × d” from the semiconductor chip CHP1d to the semiconductor chips CHP1b and CHP1f. The output time of the ultrasonic waves from each of the semiconductor chip CHP1b and the semiconductor chip CHP1f can be “T−Δt2”. Further, as the distance from the semiconductor chip CHP1a and the semiconductor chip CHP1g to the focus point, the distance from the semiconductor chip CHP1d to the focus point and the chip interval “3 × d” from the semiconductor chip CHP1d to the semiconductor chips CHP1a and CHP1g are used. Therefore, the output time of the ultrasonic wave from each of the semiconductor chip CHP1a and the semiconductor chip CHP1g can be set to “T−Δt3”. That is, as shown in FIG. 7, when a plurality of fine semiconductor chips CHP1a to CHP1g are affixed at an equal interval on the flexible substrate FS, the time when ultrasonic waves are output from each of the semiconductor chips CHP1a to CHP1g Can be adjusted easily. That is, in the case where a plurality of fine semiconductor chips CHP1a to CHP1g are pasted on the flexible substrate FS at specified regular intervals, ultrasonic waves are output in advance from each semiconductor chip using the specified intervals. Since the time to be adjusted can be adjusted, the time can be easily adjusted.

  On the other hand, FIG. 8 is a diagram showing a realistic state in which a plurality of fine semiconductor chips are pasted on the flexible substrate at different intervals that cannot be defined in advance. In FIG. 8, on the flexible substrate FS, semiconductor chips CHP1a to CHP1g each having a cell CL formed thereon are arranged at intervals d1 to d6. In this case, the distances from the semiconductor chips adjacent to each other to the focus point cannot be calculated because the intervals d1 to d6 are not defined in advance. Therefore, in a realistic configuration in which a plurality of fine semiconductor chips are pasted on the flexible substrate FS at different intervals, the time at which the ultrasonic waves are output is adjusted as in the configuration in which they are arranged at specified intervals. Therefore, it is very difficult to adjust the output time of the ultrasonic wave in the semiconductor chip. This is because the variation in the interval between the semiconductor chips in a certain CMUT and the variation between the semiconductor chips in another CMUT have no regularity and randomness. That is, since the error due to the mechanical handling mechanism occurs at random, the variations of the semiconductor chips CHP1a to CHP1g are also different for each CMUT, accurately reflecting the variations in the interval between the semiconductor chips (intervals d1 to d6), This is because it is almost impossible to adjust the time for outputting the ultrasonic waves.

  Therefore, in a realistic configuration in which a plurality of fine semiconductor chips CHP1a to CHP1g are attached to the flexible substrate FS at different intervals, it is difficult to realize superimposing superposition of ultrasonic waves at the focus point. This means that the focus point is blurred. As a result, in a realistic configuration in which a plurality of fine semiconductor chips CHP1a to CHP1g are attached to the flexible substrate FS at different intervals, the sensitivity of the CMUT 100 is reduced. In other words, in the related technique of attaching a plurality of fine semiconductor chips CHP1a to CHP1g on the flexible substrate FS, it is difficult to provide the CMUT 100 with flexibility and curved surface followability while maintaining the performance of the CMUT 100. Recognize.

  Further, in this related technology, as described above, the CMUT performance is deteriorated due to the variation in the interval between the semiconductor chips, and the use of the mechanical handling mechanism causes the adjacent semiconductor chips to be adjacent to each other. The fact that the interval cannot be narrowed also leads to a decrease in CMUT performance. This point will be described below.

  FIG. 9A and FIG. 9B are graphs showing the intensity distribution when superposing the ultrasonic waves output from each of the plurality of semiconductor chips constituting the CMUT. 9A and 9B, the horizontal axis indicates the angle, and the vertical axis indicates the directivity coefficient corresponding to the intensity. 9A and 9B, the peak appearing at an angle of 0 degrees indicates the main lobe (0th order diffracted light), and the peak appearing on both sides of the main lobe is the grating lobe (first order diffracted light). It is. Here, the main lobe corresponds to a real image, while the grating lobe corresponds to a virtual image caused by interference. Then, the more the grating lobe appears near the main lobe, the worse the quality of the ultrasonic image. This is because, as the grating lobe appears closer to the main lobe, the real image is more likely to be adversely affected by the virtual image.

  Here, FIG. 9A shows the result when using ultrasonic waves having a frequency of 15 MHz (wavelength: 102 μm) and setting the pitch between the semiconductor chips to 112 μm. On the other hand, FIG. 9B shows the results when using ultrasonic waves having a frequency of 15 MHz (wavelength is 102 μm) and the pitch between the semiconductor chips is 132 μm. At this time, assuming that the sizes of the semiconductor chips are the same, a large pitch between the semiconductor chips means that the interval between the semiconductor chips is large. From this, it can be seen from FIGS. 9A and 9B that the grating lobe is closer to the main lobe as the distance between the semiconductor chips is larger. This means that the larger the interval between the semiconductor chips, the more easily the real image is affected by the virtual image. Therefore, there is room for improvement from the viewpoint of improving the quality of the ultrasonic image in the related technology in which the interval between adjacent semiconductor chips cannot be narrowed due to the use of a mechanical handling mechanism. Recognize.

  In the related art, the plurality of semiconductor chips CHP1a to CHP1g are arranged on the flexible substrate FS by a mechanical handling mechanism. When the curved surface followability with a smaller curvature is given to the CMUT, the related technology requires that a finer semiconductor chip be used. In this case, since it becomes necessary to handle a fine semiconductor chip, handling characteristics are deteriorated. In other words, there is room for improvement in the related technology from the viewpoint of improving handling characteristics.

  From the above, in the related art, a synergistic factor between the fact that the interval between the semiconductor chips varies and the point where the interval between the semiconductor chips cannot be narrowed causes a decrease in the performance of the CMUT and a smaller curvature. If the size of the semiconductor chip is reduced in order to ensure the curved surface followability, there is room for improvement in that the handling characteristics are deteriorated.

  Therefore, a device is required to make the CMUT flexible and curved surface tracking while maintaining the device performance of the CMUT. For this reason, in this Embodiment, the device for giving flexibility and curved surface followability to CMUT is given, maintaining the device performance of CMUT. Hereinafter, the technical idea of the present embodiment in which this device is applied will be described with reference to the drawings.

<Composition of CMUT>
FIG. 10 is a perspective view showing an external configuration of CMUT 100A in the present embodiment. As shown in FIG. 10, the CMUT 100A in the present embodiment has a flexible substrate FS and a plurality of semiconductor chips CHP1 mounted on the flexible substrate FS. For example, as shown in FIG. 10, the planar size of the flexible substrate FS is larger than the combined planar size of the plurality of semiconductor chips CHP1, and the plurality of semiconductor chips CHP1 are included in the flexible substrate FS in plan view. Has been.

  Here, in the present embodiment, the flexible substrate FS having flexibility is given as an example, but the present invention is not limited to this, and a flexible film may be used. That is, in this embodiment, the member on which the plurality of semiconductor chips CHP1 are mounted may be a flexible member having flexibility.

  As shown in FIG. 10, a plurality of cells CL are formed in each of the plurality of semiconductor chips CHP1. The cell CL has a function of transmitting / receiving ultrasonic waves, and has, for example, a device structure shown in FIG.

  At this time, the plurality of semiconductor chips CHP1 are separated by the trench DIT and the cleavage plane CVS formed on the side surfaces of the semiconductor chips CHP1 adjacent to each other.

  FIG. 11 is a cross-sectional view schematically showing a part of CMUT 100A in the present embodiment. In FIG. 11, three semiconductor chips CHP1a to CHP1c mounted on the flexible substrate FS are illustrated. In FIG. 11, for example, when attention is given to the semiconductor chip CHP1a and the semiconductor chip CHP1b adjacent to each other, the semiconductor chip CHP1a includes the side surface S1, while the semiconductor chip CHP1b includes the side surface S2 that faces the side surface S1 of the semiconductor chip CHP1a. Contains. Then, the side surface S1 of the semiconductor chip CHP1a includes a part that constitutes a part of the groove DIT and a part that constitutes the cleavage plane CVS. Similarly, the side surface S2 of the semiconductor chip CHP1b includes a portion constituting a part of the trench DIT and a portion constituting a cleavage plane CVS. At this time, the site | part (1st part) in which cleavage plane CVS is formed in side surface S1, and the site | part (2nd part) in which cleavage plane CVS is formed in side surface S2 mutually oppose. Yes. That is, it can be said that the first portion of the side surface S1 of the semiconductor chip CHP1a and the second portion of the side surface S2 of the semiconductor chip CHP1b have a shape that matches when they are brought into close contact with each other.

  In other words, as shown in FIG. 11, the side surface S1 of the semiconductor chip CHP1a has a first protruding side surface that protrudes toward the semiconductor chip CHP1b, and the side surface S2 of the semiconductor chip CHP1b includes the semiconductor chip CHP1a. A second projecting side surface projecting to the side; The first portion (cleavage surface) of the side surface S1 of the semiconductor chip CHP1a is a first protruding side surface, and the second portion (cleavage surface) of the side surface S2 of the semiconductor chip CHP1b is a second protruding side surface.

  As shown in FIG. 11, the semiconductor chip CHP1a has three cells, the semiconductor chip CHP1b also has three cells, and the semiconductor chip CHP1c also has three cells. . At this time, nine cells including three cells formed in the semiconductor chip CHP1a, three cells formed in the semiconductor chip CHP1b, and three cells formed in the semiconductor chip CHP1c are equal to each other. Arranged at intervals. As shown in FIG. 11, the semiconductor chip CHP1a includes an outer edge cell ECL1 formed at a position closest to the semiconductor chip CHP1b, and an adjacent cell ACL1 adjacent to the outer edge cell ECL1. Similarly, the semiconductor chip CHP1b includes an outer edge cell ECL2 formed at a position closest to the semiconductor chip CHP1a, and an adjacent cell ACL2 adjacent to the outer edge cell ECL2. At this time, in the present embodiment, the distance between the outer edge cell ECL1 and the outer edge cell ECL2 is equal to the distance between the outer edge cell ECL1 and the adjacent cell ACL1, and between the outer edge cell ECL2 and the adjacent cell ACL2. Is equal to the distance.

  In the CMUT 100A according to the present embodiment, the maximum distance between the side surface S1 of the semiconductor chip CHP1a and the side surface S2 of the semiconductor chip CHP1b (also referred to as the width of the groove DIT) is smaller than the wavelength of the ultrasonic wave to be used. ing.

  As described above, the CMUT 100A in the present embodiment is configured.

<CMUT mounting configuration on curved surface member>
Next, a configuration example in which the CMUT 100A according to the present embodiment is mounted on the curved surface member CSM will be described. FIG. 12 is a schematic diagram showing a configuration in which the CMUT 100A according to the present embodiment is attached to the curved surface member CSM. As shown in FIG. 12, a flexible substrate FS having flexibility is attached exactly to the curved surface of the curved member CSM, and a plurality of semiconductor chips CHP1 are mounted on the flexible substrate FS attached to the curved surface of the curved member CSM. Is installed. That is, each of the plurality of semiconductor chips CHP1 has a front surface and a back surface located on the opposite side of the front surface, and the flexible substrate FS (flexible member) is in close contact with the back surface of the semiconductor chip CHP1 and has a curved surface. It arrange | positions so that the curved surface of member CSM may be followed.

  FIG. 13 is a cross-sectional view schematically showing a state in which the CMUT 100A is attached to the curved surface of the curved surface member CSM. As shown in FIG. 13, a flexible substrate FS having flexibility is attached to the surface of the curved surface member CSM so as to follow the curved surface, and a plurality of semiconductor chips CHP1 are respectively formed on the flexible substrate FS. Arranged at different angles. That is, the plurality of semiconductor chips CHP1 are arranged at different inclination angles with respect to the cleavage plane CVS, and thereby, the plurality of semiconductor chips CHP1 are arranged on the flexible substrate FS so as to follow the curved surface of the curved surface member CSM. The CMUT 100A including the semiconductor chip CHP1 is attached to the curved surface member CSM. Thereby, for example, an ultrasonic probe including the curved member CSM and the CMUT 100A attached to the curved member CSM is configured.

  Note that FIG. 13 illustrates a configuration example in which the flexible substrate FS is disposed so as to be sandwiched between the surface of the curved surface member CSM and the back surfaces of the plurality of semiconductor chips CHP1. The technical idea is not limited to this. For example, as shown in FIG. 14, a configuration in which the flexible substrate FS is arranged so as to be in close contact with the surfaces of the plurality of semiconductor chips CHP1 is also possible.

<Manufacturing method of CMUT>
The CMUT 100A in the present embodiment is configured as described above. Hereinafter, a manufacturing method thereof will be described with reference to the drawings.

  First, as shown in FIG. 15, a silicon wafer (semiconductor substrate) WF having a plurality of chip regions CR in which cells for transmitting and receiving ultrasonic waves are formed is prepared. The silicon wafer WF has a substantially disk shape and has a plurality of chip regions CR on the surface. A chip array area CAR is formed from a predetermined number of chip areas CR. At this time, for example, the surface of the silicon wafer WF is a (100) plane of silicon, and cells are formed on the (1000) plane.

  Subsequently, by dicing the silicon wafer WF, a chip array CA including a predetermined number of chip regions CR is obtained as shown in FIG. Specifically, in FIG. 16, for example, a chip array CA including three chip regions CR is illustrated. FIG. 17 is a cross-sectional view of a chip array CA composed of three chip regions. As shown in FIG. 17, the chip array CA includes a plurality of cells CL formed above a substrate (silicon substrate) SUB. Specifically, in FIG. 17, assuming that three cells are formed in one chip area, the chip array CA includes nine cells because the chip array CA includes three chip areas. These nine cells are arranged at equal intervals.

  Next, as shown in FIG. 18, a flexible substrate FS having flexibility is attached to the back surface of the chip array CA. In other words, the chip array CA is bonded on the surface of the flexible substrate FS having flexibility. At this time, for example, as shown in FIG. 18, the size of the flexible substrate FS is larger than the size of the chip array CA.

  Subsequently, the chip array CA disposed on the flexible substrate FS is separated into a predetermined number (for example, three) of semiconductor chips. Specifically, in the present embodiment, first, as shown in FIG. 19, in the chip array CA arranged on the flexible substrate FS, the trench DIT is formed along the boundary of the chip area included in the chip array CA. Form. That is, as shown in FIG. 19, in the thickness direction of the semiconductor substrate SUB, grooves DIPT corresponding to a plurality of cuts that stop in the middle of the semiconductor substrate SUB are formed in the chip array CA. The groove DIT can be formed by using, for example, a photolithography technique and an etching technique, or can be formed by half dicing using a dicer (cutting blade). Thereafter, as shown in FIG. 20, a predetermined number (for example, three) of semiconductor chips CHP1 bonded to the flexible substrate FS are obtained by cleaving using a plurality of grooves DIT corresponding to a plurality of cuts as starting points. At this time, when the cell is formed on the (100) plane of silicon, the cleavage from the trench DIT is likely to be performed along the boundary line of the chip region.

  Subsequently, a wiring for supplying power to each divided semiconductor chip CHP1 is connected. FIG. 21 is a top view of the CMUT 100A in which the respective semiconductor chips CHP1 and the flexible substrate FS are connected by wires, and FIG. 22 is a cross-sectional view taken along line AA in FIG.

  In this case, a flexible printed circuit board on which a wiring pattern is formed can be used as the flexible circuit board FS. A wire bonding pad CBP is formed on the semiconductor chip CHP1 in which cells for transmitting and receiving ultrasonic waves are formed, while a wire bonding pad FBP is formed on the flexible substrate FS. The pad CBP formed on the semiconductor chip CHP1 and the pad FBP formed on the flexible substrate FS are connected by a bonding wire BW.

  Here, the wire bonding pad CBP formed on the semiconductor chip CHP1 is connected to the electrode of the cell CL (not shown). On the other hand, the wire bonding pad FBP formed on the flexible substrate FS is electrically connected to the connector CNC for connecting the flexible substrate FS and an external electric terminal by the wiring FIC formed on the flexible substrate FS. It is connected. Therefore, power can be supplied to each semiconductor chip CHP1 from the outside of the CMUT 100A via the connector CNC.

  Subsequently, as shown in FIGS. 23 and 24, the pad CBP, the pad FBP, and the bonding wire BW are covered with an insulating resin RSN. Thereby, the pad CBP, the pad FBP, and the bonding wire BW are protected by the resin RSN.

  At this time, for example, the three resins RSN shown in FIG. 23 may be connected on the CMUT 100A, but from the viewpoint of not reducing the flexibility of the CMUT 100A, as shown in FIG. It is preferable that the flexible substrate FS is separated from the region where the flexible substrate FS bends, starting from the groove DIT and the cleavage plane CVS.

  In the present embodiment, the example in which the wire bonding process is performed after the chip array CA is cleaved into the semiconductor chip CHP1 has been described. However, the wire bonding process is performed on the back surface of the chip array CA with a flexible substrate having flexibility. After the FS is pasted, it may be performed before the chip array CA is cleaved into the semiconductor chip CHP1.

  21 and 22 show the case where one power supply is required for the semiconductor chip CHP1, the necessary number of pads CBP are formed on the semiconductor chip CHP1 even when two or more power supplies are required. At the same time, by forming the required number of pads FBP on the flexible substrate FS, the corresponding pads CBP and the pads FBP can be connected by bonding wires BW.

  Further, power can be supplied to each of the divided semiconductor chips CHP1 by using a through hole TSV penetrating the substrate SUB of the semiconductor chip CHP1 instead of wire bonding. In this case, in the step shown in FIG. 18, the flexible substrate FS and the chip array CA are electrically connected. A top view of the CMUT 100A in this case is shown in FIG. 26 is a cross-sectional view taken along line AA in FIG. In this case, a flexible printed circuit board on which a wiring pattern is formed can also be used as the flexible circuit board FS.

  As shown in FIG. 26, after connecting the bottom surface of the through hole TSV formed in the substrate SUB of the semiconductor chip CHP1 and the bump electrode BMP formed on the flexible substrate FS, an underside is formed between the flexible substrate FS and the substrate SUB. Fill material UF is embedded. The through hole TSV formed in the semiconductor chip CHP1 is connected to the electrode of the cell CL (not shown). On the other hand, the bump electrode BMP is electrically connected to a connector CNC for connecting the flexible substrate FS and an external electric terminal by a wiring FIC formed on the flexible substrate FS. Therefore, power can be supplied to each semiconductor chip CHP1 from the outside of the CMUT 100A via the connector CNC. Subsequent processes can manufacture CMUT100A through the process similar to the process shown in FIG. 19 and FIG.

  FIGS. 25 and 26 show the case where one power supply is required for the semiconductor chip CHP1, but the necessary number of through holes TSV are formed in the semiconductor chip CHP1 even when two or more power supplies are required. In addition, the necessary number of bump electrodes BMP can be formed on the flexible substrate FS, and the corresponding through holes TSV and the bump electrodes BMP can be connected to each other.

  As described above, it is possible to manufacture the CMUT 100A according to the present embodiment including the plurality of semiconductor chips CHP1 mounted on the flexible substrate FS.

<Features in Embodiment>
Next, feature points in the present embodiment will be described. For example, as shown in FIGS. 15 to 20, the feature point in the present embodiment is a plurality of cuts that stop in the middle of the semiconductor substrate SUB in the chip array CA attached to the flexible substrate (flexible member) FS. Then, the chip array CA is divided into a plurality of semiconductor chips CHP1 by cleaving using the plurality of cuts as starting points. Thereby, according to this Embodiment, the 1st advantage shown below can be acquired. That is, according to the feature point in the present embodiment, since the chip array CA mounted on the flexible substrate FS is separated into a plurality of semiconductor chips CHP1 by cleavage, the interval between the semiconductor chips CHP1 separated from each other is separated. Can be suppressed. This is because, according to the present embodiment, for example, unlike the related art, the semiconductor chips CHP1 separated in advance are not arranged on the flexible substrate FS one by one by a mechanical handling mechanism, but in advance. This is because a configuration is adopted in which the chip array CA is collectively separated into a plurality of semiconductor chips CHP1 by cleavage with the chip array CA mounted on the flexible substrate FS. Thus, according to the present embodiment, a plurality of fine semiconductor chips CHP1 are pasted on the flexible substrate FS at regular intervals, and from each of the adjacent semiconductor chips to the focus point. Can be calculated in advance. As a result, according to the present embodiment, it is possible to adjust the output time of ultrasonic waves in each semiconductor chip. That is, according to the feature point in the present embodiment, since a plurality of fine semiconductor chips CHP1 are attached on the flexible substrate FS at regular intervals, the time for outputting ultrasonic waves is adjusted in advance. Therefore, the time can be easily adjusted. That is, according to the present embodiment, the CMUT can have flexibility and curved surface followability while maintaining the device performance of the CMUT.

  Next, the second advantage obtained by the feature points in the present embodiment will be described. In the present embodiment, as described above, the semiconductor chip CHP1 singulated in advance is not arranged on the flexible substrate FS one by one by a mechanical handling mechanism, but the chip array CA is preliminarily arranged on the flexible substrate FS. In a state of being mounted on the chip array CA, the chip array CA is collectively separated into a plurality of semiconductor chips CHP1 by cleavage. As a result, according to the present embodiment, the interval between adjacent semiconductor chips can be reduced. This means that the grating lobe can be prevented from approaching the main lobe according to the present embodiment. That is, according to the present embodiment, as a result of the interval between the semiconductor chips CHP1 being narrowed, the real image (corresponding to the main lobe) is less likely to be adversely affected by the virtual image (corresponding to the grating lobe). Therefore, in the related technology, the use of a mechanical handling mechanism cannot reduce the interval between adjacent semiconductor chips, and as a result, the quality of the ultrasonic image cannot be improved. In the embodiment, due to the use of cleavage for the separation between the semiconductor chips CHP1, the interval between the adjacent semiconductor chips can be narrowed, so that the quality of the ultrasonic image can be improved.

  Furthermore, in the present embodiment, the interval between the adjacent semiconductor chips CHP1 can be narrowed, so that the CMUT having a configuration in which a plurality of semiconductor chips CHP1 are arranged on the flexible substrate FS can be reduced. That is, according to the feature point in the present embodiment, as a result of being able to narrow the interval between the adjacent semiconductor chips CHP1, it is possible to improve the quality of the ultrasonic image and improve the device performance of the CMUT, The CMUT can be downsized. That is, the feature point in the present embodiment is useful in that the CMUT can be provided with flexibility and curved surface followability while realizing both improvement in device performance of the CMUT and downsizing of the CMUT.

  Next, the third advantage obtained by the feature point in the present embodiment will be described. For example, in the related art, the semiconductor chips CHP1 separated in advance are arranged one by one on the flexible substrate FS by a mechanical handling mechanism. For this reason, in the related art, it is necessary to handle the fine semiconductor chip CHP1, and the handling property is deteriorated. On the other hand, in the feature point in the present embodiment, since a large-sized chip array CA including a predetermined number of chip regions may be handled on the flexible substrate FS, handling properties can be improved. In other words, the feature point in the present embodiment is only useful in that the CMUT can be provided with flexibility and curved surface followability while realizing both improvement of the device performance of the CMUT and miniaturization of the CMUT. In addition, since the handling property during the manufacturing process can be ensured, it can be seen that this is an excellent technical idea in that the manufacturing yield of CMUT can be improved.

  Further, the fourth advantage obtained by the feature point in the present embodiment will be described. In this embodiment, for example, as shown in FIGS. 19 to 20, after forming a plurality of cuts (grooves DIT) that stop in the middle of the semiconductor substrate SUB, the plurality of cuts (grooves DIT) are used as starting points. By the cleavage, the chip array CA is separated into a plurality of semiconductor chips CHP1. As a result, the chip array CA can be easily separated into a plurality of semiconductor chips CHP1 by cleaving, compared to the case where the notches (grooves DIT) are not formed. This is because it is desirable to have a starting point in order to realize cleavage. That is, if the cleavage is performed in the state where there is no starting point, the cleavage direction is not determined, and there is a high possibility that the cleavage proceeds in an unintended direction. On the other hand, if the starting point (cut) is formed in advance, the cleavage direction can be guided to the intended direction.

  Thereby, according to the feature point in the present embodiment, the cleavage direction can be controlled by forming a plurality of cuts (grooves DIT), and thus the cleavage proceeds in an unintended direction. It can be effectively suppressed. In particular, in the present embodiment, the surface of the silicon wafer WF is the (100) surface of silicon, so that the cleavage is easily progressed in the intended direction.

<Modification>
Next, a modification of the embodiment will be described. In this modification, a CMUT manufacturing method that is partially different from the CMUT manufacturing method according to the embodiment will be described. First, as shown in FIG. 27, a silicon wafer (semiconductor substrate) WF having a plurality of chip regions CR in which cells for transmitting and receiving ultrasonic waves are formed is prepared. The silicon wafer WF has a substantially disk shape and has a plurality of chip regions CR on the surface. A chip array area CAR is formed from a predetermined number of chip areas CR. Then, as shown in FIG. 27, a substantially disk-shaped flexible substrate FS having the same size as the silicon wafer WF is prepared. Thereafter, the flexible substrate FS is attached to the back surface of the silicon wafer WF. Subsequently, as shown in FIG. 28, a chip array CA including a predetermined number of chip regions is obtained by dicing the silicon wafer WF to which the flexible substrate FS is attached. At this time, a flexible substrate FS having flexibility is bonded to the back surface of the chip array CA. Thereafter, the semiconductor chip CHP1 including a plurality of semiconductor chips CHP1 mounted on the flexible substrate FS as shown in FIG. 29 and adjacent to each other through almost the same process as the CMUT manufacturing process in the embodiment. The CMUT 100B in which the groove DIT and the cleavage surface CVS are formed on the side surface of the CHP 1 can be manufactured.

In this case, the electrical connection for supplying power from the outside is performed by a substantially disk-shaped flexible substrate FS.
If a wiring pattern is formed in advance, for example, it is possible to connect to the flexible substrate FS using the through hole TSV (through hole TSV formed in the substrate SUB of the semiconductor chip CHP1) shown in FIG. Then, the wiring of the substantially disc-shaped flexible substrate FS is opposed to the surface (front surface) to which the silicon wafer WF of the substantially disc-shaped flexible substrate FS is attached through another through hole formed in the flexible substrate FS. By drawing around the surface (back surface), power can be supplied from the bottom surface of the CMUT 100B shown in FIG.

  Here, in the present modification, for example, as shown in FIG. 29, the planar size of the flexible substrate FS is substantially equal to the combined planar size of the plurality of semiconductor chips CHP1, so that it is more than the CMUT 100A in the embodiment. The CMUT 100B can provide an advantage that the size can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The embodiment includes the following forms.

(Appendix 1)
A plurality of semiconductor chips on which cells for receiving ultrasonic waves are formed;
A flexible member in close contact with the plurality of semiconductor chips;
With
When focusing on the first semiconductor chip and the second semiconductor chip adjacent to each other among the plurality of semiconductor chips,
The first semiconductor chip includes a first side surface,
The second semiconductor chip includes a second side surface facing the first side surface,
The ultrasonic transducer, wherein the first portion of the first side surface and the second portion of the second side surface have a shape that matches when they are brought into close contact with each other.

(Appendix 2)
A plurality of semiconductor chips on which cells for receiving ultrasonic waves are formed;
A flexible member in close contact with the plurality of semiconductor chips;
With
Each of the plurality of semiconductor chips is formed with a plurality of cells.
When focusing on the first semiconductor chip and the second semiconductor chip adjacent to each other among the plurality of semiconductor chips,
The first semiconductor chip is
A first outer edge cell formed at a position closest to the second semiconductor chip;
A first adjacent cell adjacent to the first outer edge cell;
Including
The second semiconductor chip is
A second outer edge cell formed at a position closest to the first semiconductor chip;
A second adjacent cell adjacent to the second outer edge cell;
Including
The distance between the first outer edge cell and the second outer edge cell is equal to the distance between the first outer edge cell and the first adjacent cell, and the second outer edge cell and the second adjacent cell. Ultrasonic transducer, equal to the distance between.

(Appendix 3)
(A) preparing a semiconductor substrate having a plurality of chip regions in which cells are formed and bonded to a flexible member;
(B) obtaining a chip array including a predetermined number of chip regions;
(C) separating the chip array into the predetermined number of semiconductor chips;
A method of manufacturing an ultrasonic transducer comprising:
The step (c)
(C1) forming a plurality of cuts in the chip array that stop in the middle of the semiconductor substrate in the thickness direction of the semiconductor substrate;
(C2) After the step (c1), obtaining the predetermined number of the semiconductor chips bonded to the flexible member by cleaving using the plurality of cuts as starting points;
A method for manufacturing an ultrasonic transducer.

100A ultrasonic transducer (CMUT)
100B ultrasonic transducer (CMUT)
DESCRIPTION OF SYMBOLS 1000 Ultrasonic imaging device 1001 Ultrasonic probe 1002 Transmission / reception separation part 1003 Transmission part 1004 Bias part 1005 Reception part 1006 Phased addition part 1007 Image processing part 1008 Display part 1009 Control part 1010 Operation part ACL1 Adjacent cell ACL2 Adjacent cell BMP Bump Electrode BW Bonding wire CBP pad CHP1 Semiconductor chip CHP1a Semiconductor chip CHP1b Semiconductor chip CHP1c Semiconductor chip CHP1d Semiconductor chip CHP1e Semiconductor chip CHP1f Semiconductor chip CHP1g Semiconductor chip CL cell CNC connector CVS Cleavage surface DIT Edge cell L Flexible substrate RSN Resin S1 Side S2 Side TSV Through hole UF Underfill material

Claims (15)

An ultrasonic probe that is brought into contact with the subject and transmits / receives ultrasonic waves to / from the subject;
A transmitter for supplying a drive signal for transmitting ultrasonic waves to the ultrasonic probe;
A receiving unit for receiving a reflected echo signal output from the ultrasonic probe;
An image processing unit for generating an image based on the reflected echo signal;
When transmitting ultrasonic waves, the ultrasonic probe and the transmitting unit are electrically connected, while when receiving ultrasonic waves, the ultrasonic probe and the receiving unit are electrically connected. A transmission / reception separation unit for switching connection paths;
An ultrasonic imaging apparatus comprising:
The ultrasonic probe includes an ultrasonic transducer,
The ultrasonic transducer is
A plurality of semiconductor chips on which cells for transmitting and receiving ultrasonic waves are formed;
A flexible member in close contact with the plurality of semiconductor chips;
Have
When focusing on the first semiconductor chip and the second semiconductor chip adjacent to each other among the plurality of semiconductor chips,
The first semiconductor chip includes a first side surface,
The second semiconductor chip includes a second side surface facing the first side surface,
The first portion of the first side surface is a cleavage plane;
The ultrasonic imaging apparatus, wherein the second portion of the second side surface and the second portion facing the first portion is also a cleavage plane. A plurality of semiconductor chips on which cells for receiving ultrasonic waves are formed;
A flexible member in close contact with the plurality of semiconductor chips;
With
When focusing on the first semiconductor chip and the second semiconductor chip adjacent to each other among the plurality of semiconductor chips,
The first semiconductor chip includes a first side surface,
The second semiconductor chip includes a second side surface facing the first side surface,
The first portion of the first side surface is a cleavage plane;
The ultrasonic transducer, wherein the second portion of the second side surface and the second portion facing the first portion is also a cleavage plane. The ultrasonic transducer according to claim 2,
The first side surface has a first protruding side surface protruding to the second semiconductor chip side,
The second side surface has a second protruding side surface protruding toward the first semiconductor chip,
The first portion is the first protruding side surface;
The ultrasonic transducer, wherein the second portion is the second protruding side surface. The ultrasonic transducer according to claim 2,
The ultrasonic transducer, wherein the first portion and the second portion have a shape that matches when they are brought into close contact with each other. The ultrasonic transducer according to claim 2,
Each of the plurality of semiconductor chips is formed with a plurality of cells.
The first semiconductor chip is
A first outer edge cell formed at a position closest to the second semiconductor chip;
A first adjacent cell adjacent to the first outer edge cell;
Including
The second semiconductor chip is
A second outer edge cell formed at a position closest to the first semiconductor chip;
A second adjacent cell adjacent to the second outer edge cell;
Including
The distance between the first outer edge cell and the second outer edge cell is equal to the distance between the first outer edge cell and the first adjacent cell, and the second outer edge cell and the second adjacent cell. Ultrasonic transducer, equal to the distance between. The ultrasonic transducer according to claim 2,
The ultrasonic transducer, wherein a maximum distance between the first side surface and the second side surface is smaller than a wavelength of an ultrasonic wave to be used. The ultrasonic transducer according to claim 2,
Each of the plurality of semiconductor chips is
Surface,
A back surface located on the opposite side of the front surface;
Have
The flexible member is an ultrasonic transducer in close contact with the back surface. The ultrasonic transducer according to claim 2,
Each of the plurality of semiconductor chips is
Surface,
A back surface located on the opposite side of the front surface;
Have
The flexible member is an ultrasonic transducer in close contact with the surface. The ultrasonic transducer according to claim 2,
The flexible member is an ultrasonic transducer, which is a flexible substrate. The ultrasonic transducer according to claim 2,
The ultrasonic transducer, wherein the flexible member is a flexible film. The ultrasonic transducer according to claim 2,
The cell is an ultrasonic transducer, which is a capacitance type cell. (A) preparing a semiconductor substrate having a plurality of chip regions in which cells are formed;
(B) obtaining a chip array including a predetermined number of chip regions;
(C) bonding the chip array to a flexible member;
(D) separating the chip array into the predetermined number of semiconductor chips;
A method of manufacturing an ultrasonic transducer comprising:
The step (d)
(D1) forming a plurality of cuts in the chip array that stop in the middle of the semiconductor substrate in the thickness direction of the semiconductor substrate;
(D2) After the step (d1), obtaining the predetermined number of the semiconductor chips bonded to the flexible member by cleaving using the plurality of cuts as starting points;
A method for manufacturing an ultrasonic transducer. The method of manufacturing an ultrasonic transducer according to claim 12,
In the step (d1), an ultrasonic transducer manufacturing method using etching. The method of manufacturing an ultrasonic transducer according to claim 12,
In the step (d1), an ultrasonic transducer manufacturing method using dicing. The method of manufacturing an ultrasonic transducer according to claim 12,
The semiconductor substrate is a silicon wafer;
The method for manufacturing an ultrasonic transducer, wherein the cell is formed on a (100) surface of the silicon wafer.

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