JP2018182291A - Domain wall utilization type analog memory element, domain wall utilization type analog memory, nonvolatile logic circuit, and magnetic neuro element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a domain wall utilization type analog memory element capable of recording data with multiple values or analog and stably reading out the data.SOLUTION: A domain wall utilization type analog memory element according to the present invention includes a magnetization fixed layer whose magnetization is oriented in a first direction, a nonmagnetic layer provided on one surface of the magnetization fixed layer, a domain wall driving layer that includes a first region in which magnetization is oriented in the first direction, a second region in which magnetization is oriented in a second direction opposite to the first direction, a domain wall forming an interface between these regions and that is provided to sandwich the nonmagnetic layer with respect to the magnetization fixed layer, and current control means that causes a current to flow between the magnetization fixed layer and the second region at the time of reading.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a domain wall based analog memory device, a domain wall based analog memory, a non-volatile logic circuit and a magnetic neuro device.

  As a next-generation non-volatile memory replacing flash memory etc. which has seen limits in miniaturization, resistance change type memory which records data using resistance change type elements, for example, MRAM (MagnetroResistive Random Access Memory), ReRAM (Resistance Network) Attention has been focused on Random Access Memory (PC), Phase Change Random Access Memory (PCRAM), and the like.

  As a method of increasing the density of a memory (increasing the capacity), there is a method of multileveling recording bits per element constituting a memory in addition to a method of reducing an element constituting the memory itself. Methods have been proposed (for example, Patent Documents 1 to 3).

  Patent Document 4 and Patent Document 5 describe multi-value recording and analog recording using a domain wall utilizing MRAM. In the domain wall utilizing type MRAM, data writing is performed by flowing current in the in-plane direction of the domain wall driving layer (magnetization free layer) and reversing the magnetization of the ferromagnetic film in the direction according to the direction of the write current. The domain wall of the domain wall drive layer moves by the spin transfer effect by spin-polarized electrons.

  On the other hand, at the time of reading, in the domain wall utilizing type MRAM, the resistance value change of the magnetoresistive element, which changes in accordance with the relative relationship between the magnetization direction of the magnetization fixed layer and the average magnetization direction of the central region of the magnetization recording layer Read as The average magnetization direction of the central region of the magnetization recording layer changes in accordance with the magnetization state (the position of the domain wall) of the central region of the magnetization recording layer. Further, Patent Document 5 describes an example in which a domain wall utilizing type MRAM is used for a current reading circuit of a memory array. One end of the domain wall drive layer is grounded, and the current from the memory array is input to the other fixed magnetization region. The magnetization direction of the domain wall layer becomes parallel or antiparallel to the magnetization fixed layer depending on the direction of the current, thereby functioning as a current mode comparator.

JP, 2015-88669, A International Publication No. 2009/072213 JP, 2016-4924, A WO 2009/101827 U.S. Patent No. 9489618

  However, Patent Document 4 only describes reading data by a change in resistance value of the magnetoresistive element, and does not describe how to apply a read current. Therefore, the resistance value change which changes according to the magnetization state (the position of the domain wall) does not become linear, and it may not be possible to stably read the information written in multiple values. In Patent Document 5, the purpose is not to store information, but to detect the current of a bit line, and only provides the same function as reading of a conventional binary memory.

  The present invention has been made in view of the above circumstances, and provides a domain wall utilizing analog memory element, domain wall utilizing analog memory, non-volatile logic circuit and magnetic neuro device capable of stably reading analog recording data. The purpose is

  The present invention provides the following means in order to solve the above problems.

(1) In the domain wall utilizing type analog memory element according to the first aspect, there is provided a magnetization fixed layer whose magnetization is oriented in a first direction, a nonmagnetic layer provided on one surface of the magnetization fixed layer, and the first magnetic memory. The magnetization fixed, comprising a first region in which magnetization is oriented in one direction, a second region in which the magnetization is oriented in a second direction opposite to the first direction, and a domain wall forming an interface between these regions; And a current control means for causing an electric current to flow between the magnetization fixed layer and the second region at the time of reading.

(2) In the domain wall utilizing type analog memory element according to the above aspect, the first domain wall supplying layer is provided with first magnetization supplying means for supplying the domain oriented magnetization in the first direction and the domain oriented magnetization in the second direction. The device further includes a second magnetization supply unit, and at least one of the first magnetization supply unit and the second magnetization supply unit is in contact with the domain wall driving layer, and is oriented in the first direction or the second direction. The magnetization supply layer may have a different magnetization.

(3) In the domain wall utilizing type analog memory element according to the above aspect, the first domain wall supplying layer is provided with first magnetization supplying means for supplying the domain oriented magnetization in the first direction and the domain oriented magnetization in the second direction. The device further includes second magnetization supply means, and at least one of the first magnetization supply means and the second magnetization supply means is electrically insulated from the domain wall drive layer and intersects the domain wall drive layer. It may be a wire extending in the direction.

(4) In the domain wall utilization type analog memory element according to the above aspect, the first domain wall supplying layer is supplied with first magnetization supplying means for supplying the domain oriented magnetization in the first direction, and the domain magnetization using the second domain. The device further includes a second magnetization supply unit, and at least one of the first magnetization supply unit and the second magnetization supply unit is in contact with the domain wall drive layer and extends in a direction intersecting the domain wall drive layer. The spin track torque wiring may be used.

(5) In the domain wall utilization type analog memory element according to the above aspect, the first domain wall supplying layer is supplied with first magnetization supplying means for supplying the domain oriented magnetization in the first direction, and the domain is used for supplying the domain oriented magnetization. The voltage application unit may further include a second magnetization supply unit, and at least one of the first magnetization supply unit and the second magnetization supply unit may be a voltage application unit connected to the domain wall driving layer via an insulating layer. Good.

(6) In the domain wall utilization type analog memory element according to the above aspect, the current control means may be a potential control means for setting the potential of the second region lower than the potential of the magnetization fixed layer at the time of reading.

(7) In the domain wall utilizing analog memory device according to the above aspect, the current control means may be a rectifying device for controlling the flow direction of the current.

(8) The domain wall based analog memory according to the second aspect includes a plurality of domain wall based analog memory elements according to the above aspect.

(9) The nonvolatile logic circuit according to the third aspect includes the domain wall based analog memory according to the above aspect arranged in an array, and the STT-MRAM is provided in either the array or the array, and the storage function And a logic function, and includes the domain wall utilizing analog memory and the STT-MRAM as a memory function.

(10) A magnetic neuro device according to a fourth aspect comprises the domain wall utilizing type analog memory element according to the above aspect, wherein the domain wall drive layer comprises a first storage unit aligned in the longitudinal direction, and the first storage unit. The domain wall is sequentially moved so as to stay at least once in all the storage units of the first storage unit, the second storage unit, and the third storage unit, having a second storage unit and a third storage unit interposed therebetween. And a current source having a control circuit that controls the obtained write current.

  According to the domain wall utilizing analog memory device of the present invention, data can be recorded in multiple values or in an analog manner, and these data can be read stably.

It is a cross-sectional schematic diagram of an example of the magnetic wall utilization type analog memory element which concerns on 1st Embodiment. FIG. 7 is a diagram showing a write operation of the domain wall based analog memory element according to the first embodiment. FIG. 6 is a diagram showing a read operation of the domain wall utilizing type analog memory element according to the first embodiment. FIG. 7 schematically shows a part of the circuit at the time of data read-out. (A) is a magnetization of the magnetization fixed layer opposite in magnetization direction to the magnetization direction as in the domain wall utilizing type analog memory element according to the present embodiment. It is a circuit diagram at the time of sending a reading current in the existing direction, and (b) is a circuit diagram at the time of sending a reading current in the direction in which the magnetization of the magnetization fixed layer and the orientation direction are the same. FIG. 7 is a schematic perspective view of a domain wall based analog memory element according to a second embodiment; FIG. 16 is a schematic perspective view of another example of the domain wall based analog memory element according to the second embodiment. It is a perspective view schematic diagram of a domain wall utilization type analog memory element concerning a 3rd embodiment. It is a perspective view schematic diagram of a domain wall utilization type analog memory element concerning a 4th embodiment. FIG. 18 is a schematic perspective view of another example of the domain wall based analog memory element according to the fourth embodiment. It is the figure which showed typically an example of the circuit structure of the domain wall utilization type | mold analog memory concerning this embodiment. It is a cross-sectional schematic diagram of an example of the magnetic neuro device concerning this embodiment. It is a figure which shows the concept of the artificial brain using the magnetic neuro element concerning this embodiment. It is a product-sum operation circuit in which the magnetic neuro elements according to the present embodiment are arranged in an array.

  Hereinafter, the configuration of the present embodiment will be described using the drawings. In the drawings used in the following description, in order to make the features easy to understand, the features that are the features may be enlarged for the sake of convenience, and the dimensional ratio of each component is not necessarily the same as the actual. Further, the materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not limited thereto.

First Embodiment
(A domain wall type analog memory device)
FIG. 1 is a schematic cross-sectional view of an example of a domain wall based analog memory device according to the first embodiment. The domain wall utilizing type analog memory element shown in FIG. 1 comprises a magnetization fixed layer 1, a nonmagnetic layer 2, a domain wall drive layer 3, a first magnetization supply layer 4, a second magnetization supply layer 5 and a current control means ( Not shown).

  In FIG. 1, the stacking direction of each layer, that is, the direction orthogonal to the main surface of each layer (perpendicular direction) is defined as the Z direction. Each layer is formed in parallel to the XY plane orthogonal to the Z direction.

"Magnetic fixed layer"
The magnetization fixed layer 1 is a layer in which the magnetization M1 is oriented and fixed in the first direction. Here, that the magnetization is fixed means that the magnetization direction does not change (the magnetization is fixed) before and after the writing using the write current.

  In the example shown in FIG. 1, the magnetization fixed layer 1 is an in-plane magnetization film in which the magnetization M1 has in-plane magnetic anisotropy (in-plane magnetization easy axis). The magnetization fixed layer 1 is not limited to the in-plane magnetization film, and may be a perpendicular magnetization film having perpendicular magnetic anisotropy (perpendicular magnetization easy axis).

  If the magnetization fixed layer 1 is an in-plane magnetization film, it has a high MR ratio, is not easily affected by the spin transfer torque (STT) at the time of reading, and the read voltage can be increased. On the other hand, when it is desired to miniaturize the element, it is preferable to use a perpendicular magnetization film having a large magnetic anisotropy and a small demagnetizing field. The perpendicular magnetization film has high resistance to thermal disturbance, so that data is difficult to erase.

  A known material can be used for the magnetization fixed layer 1. For example, a metal selected from the group consisting of Cr, Mn, Co, Fe and Ni, and an alloy exhibiting one or more of these metals and exhibiting ferromagnetism can be used. Alternatively, an alloy containing these metals and at least one or more elements of B, C, and N can also be used. Specifically, Co-Fe and Co-Fe-B can be mentioned.

Further, a Heusler alloy such as Co ₂ FeSi can also be used for the magnetization fixed layer 1. The Heusler alloy contains an intermetallic compound having a chemical composition of X ₂ YZ, X is a transition metal element or noble metal element of Co, Fe, Ni, or Cu group on the periodic table, and Y is Mn, V , A transition metal of Cr or Ti group and can also take an element species of X, and Z is a typical element of Group III to V. For _example, Co 2 _FeSi, etc. Co 2 MnSi and _{Co 2 Mn 1-a Fe a} Al b Si 1-b can be mentioned.

  The magnetization fixed layer 1 may have a synthetic structure including an antiferromagnetic layer, a ferromagnetic layer, and a nonmagnetic layer. In the synthetic structure, the magnetization direction of the magnetization fixed layer 1 is strongly held by the antiferromagnetic layer. Therefore, the magnetization of the magnetization fixed layer 1 is less susceptible to the influence of the outside.

In order to orient the magnetization of the magnetization fixed layer 1 in the XY plane (make the magnetization fixed layer 1 an in-plane magnetization film), it is preferable to use, for example, NiFe. On the other hand, in the case of orienting the magnetization of the magnetization fixed layer 1 in the Z direction (making the magnetization fixed layer 1 a perpendicular magnetization film), it is preferable to use, for example, a Co / Ni laminated film or a Co / Pt laminated film. For example, the magnetization fixed layer 1 may be formed of [Co (0.24 nm) / Pt (0.16 nm)] ₆ / Ru (0.9 nm) / [Pt (0.16 nm) / Co (0.16 nm)] ₄ / Ta If 0.2 nm) / FeB (1.0 nm), then it becomes a perpendicular magnetization film.

"Nonmagnetic layer"
The nonmagnetic layer 2 is provided on one surface of the magnetization fixed layer 1. The domain wall utilizing analog memory element 100 reads out a change in the magnetization state of the domain wall drive layer 3 with respect to the magnetization fixed layer 1 as a change in resistance value via the nonmagnetic layer 2. That is, the magnetization fixed layer 1, the nonmagnetic layer 2 and the domain wall drive layer 3 function as a magnetoresistive effect element, and when the nonmagnetic layer 2 is made of an insulator, it has a configuration similar to a tunnel magnetoresistive (TMR) element When the nonmagnetic layer 2 is made of metal, it has a configuration similar to a giant magnetoresistive (GMR) element.

As a material of the nonmagnetic layer 2, known materials that can be used for the nonmagnetic layer of the magnetoresistive element can be used. When the nonmagnetic layer 2 is made of an insulator (in the case of a tunnel barrier layer), the material is Al ₂ O ₃ , SiO ₂ , MgO, MgAl ₂ O ₄ , ZnAl ₂ O ₄ , MgGa ₂ O ₄ , ZnGa ₂ O ₄ , MgIn ₂ O ₄ , ZnIn ₂ O ₄ , and multilayer films or mixed composition films of these materials can be used. Besides these materials, materials in which a part of Al, Si and Mg is substituted by Zn, Be and the like can also be used. Among these, MgO and MgAl ₂ O ₄ are materials that can realize coherent tunneling, so spins can be injected efficiently. On the other hand, when the nonmagnetic layer 2 is made of metal, Cu, Al, Ag or the like can be used as the material.

"Domain wall drive layer 3"
The domain wall drive layer 3 is a magnetization free layer made of a ferromagnetic material, and the direction of magnetization in the inside is reversible. The domain wall drive layer 3 has a first region 3a in which the magnetization M3a is oriented in the same first direction as the magnetization fixed layer 1, and a second region 3b in which the magnetization M3b is oriented in a second direction opposite to the first direction. And a domain wall DW forming an interface between these regions. The magnetization directions of the first region 3a and the second region 3b are opposite to each other across the domain wall DW. The domain wall DW moves by changing the composition ratio of the first region 3 a and the second region 3 b in the domain wall drive layer 3.

  The material of the domain wall drive layer 3 may be a known material that can be used for the magnetization free layer of the magnetoresistive element, and in particular, a soft magnetic material can be applied. For example, a metal selected from the group consisting of Cr, Mn, Co, Fe and Ni, an alloy containing one or more of these metals, and these metals and at least one or more elements of B, C, and N Alloys can be used. Specifically, Co-Fe, Co-Fe-B, and Ni-Fe can be mentioned as the material of the domain wall drive layer 3.

  A material with small saturation magnetization can also be used as the material of the domain wall drive layer 3. For example, when a material with small saturation magnetization such as MnGaAs or InFeAs is used, the domain wall DW of the domain wall drive layer 3 can be driven with a small current density. Further, when these materials are used, the driving speed of the domain wall DW becomes slow, and can be suitably used as an analog memory.

  In a material with weak magnetic anisotropy such as NiFe, the driving speed of the domain wall DW is high, and the domain wall DW operates at a speed of 100 m / sec or more. That is, the domain wall DW moves a distance of 1 μm with a pulse of 10 nsec. Therefore, when moving the domain wall drive layer 3 in an analog manner in the device, measures such as applying a minute pulse using an expensive semiconductor circuit or making the domain wall drive layer sufficiently long at the expense of integration degree are required. It will be necessary. On the other hand, in the case of a material with a slow driving speed of the domain wall DW, it is possible to form an analog memory even when applying a sufficiently long pulse current or when the length of the domain wall driving layer 3 is short.

It is preferable to use a perpendicular magnetization film made of a perpendicular magnetization film of Mn ₃ X (X = Ga, Ge) or a multilayer film of Co / Ni, Co / Pt or the like for the domain wall drive layer 3. These materials can drive the domain wall DW even if the current density for driving the domain wall is small.

  The length of the domain wall drive layer 3 extending in the X direction is preferably 60 nm or more. If it is less than 60 nm, it is likely to become a single magnetic domain, and it is difficult to form the domain wall DW in the domain wall driving layer 3.

  The thickness of the domain wall drive layer 3 is not particularly limited as long as it functions as a domain wall drive layer, but can be, for example, 2 to 60 nm. When the thickness of the domain wall drive layer 3 is 60 nm or more, the possibility of forming a domain wall in the stacking direction increases. However, whether or not the domain wall is formed in the stacking direction depends on the balance with the shape anisotropy of the domain wall drive layer 3. If the thickness of the domain wall drive layer 3 is less than 60 nm, it is unlikely that the domain wall DW can be produced.

  The domain wall drive layer 3 may have a domain wall pinning portion for stopping the movement of the domain wall DW on the side surface of the layer. For example, when the unevenness, groove, swelling, constriction, notch or the like is provided at the position where the movement of the domain wall DW of the domain wall driving layer 3 is to be stopped, the movement of the domain wall can be stopped (pinned). If the domain wall pinning portion is provided, the domain wall can not be moved further if a current equal to or higher than the threshold is supplied, and the output signal is not analog but is easily converted into multiple values.

  For example, the domain wall DW can be held more stably by forming the domain wall pinning portions at predetermined distances, enabling stable multi-level recording, and more stable multi-leveled output Allows to read out the signal.

"First magnetization supply layer, second magnetization supply layer"
The first magnetization supply layer 4 and the second magnetization supply layer 5 are an aspect of the magnetization supply means for supplying the magnetization to the domain wall drive layer 3. When a write current flows between the magnetization fixed layer 1 and the first magnetization supply layer 4 or the second magnetization supply layer 5, magnetization is generated from the first magnetization supply layer 4 or the second magnetization supply layer 5 to the domain wall drive layer 3. Supplied.

  Each of the first magnetization supply layer 4 and the second magnetization supply layer 5 is a layer (ferromagnetic layer) made of a ferromagnetic material in which the magnetization is fixed. The magnetization M4 of the first magnetization supply layer 4 is oriented in the same direction as the magnetization M3a of the first region 3a of the domain wall drive layer 3 in contact with the first magnetization supply layer 4. That is, the magnetization M4 of the first magnetization supply layer 4 is oriented in the same direction as the magnetization M1 of the magnetization fixed layer 1. On the other hand, the magnetization M5 of the second magnetization supply layer 5 is oriented in the same direction as the magnetization M3b of the second region 3b of the domain wall drive layer 3 in contact with the second magnetization supply layer 5. That is, the magnetization M5 of the second magnetization supply layer 5 is oriented in the opposite direction to the magnetization M1 of the magnetization fixed layer 1.

  In FIG. 1, the first magnetization supply layer 4 and the second magnetization supply layer 5 are disposed on the opposite side of the magnetization fixed layer 1 with respect to the domain wall drive layer 3. The first magnetization supply layer 4 and the second magnetization supply layer 5 may be disposed on the same plane as the magnetization fixed layer 1 with reference to the domain wall drive layer 3.

  When the first magnetization supply layer 4 and the second magnetization supply layer 5 are disposed on the opposite side of the magnetization fixed layer 1 with respect to the domain wall drive layer 3, the magnetization M1 of the magnetization fixed layer 1 is the first magnetization supply layer. The influence of the magnetization M4 of 4 and the magnetization M5 of the second magnetization supply layer 5 can be reduced. On the other hand, when the first magnetization supply layer 4 and the second magnetization supply layer 5 are disposed on the same plane side as the magnetization fixed layer 1 with reference to the domain wall drive layer 3, the first magnetization supply layer 4 and the There is no need to make the heights of the surfaces of the two magnetization supply layers 5 on which the domain wall drive layer 3 is formed the same, and the fabrication of the domain wall utilizing analog memory element 100 becomes easy.

  The direction of the magnetization of the portion in contact with the first magnetization supply layer 4 and the second magnetization supply layer 5 of the domain wall drive layer 3 is not rewritten in principle. This is because the first magnetization supply layer 4 and the second magnetization supply layer 5 and the domain wall drive layer 3 are magnetically coupled and stabilized. Therefore, when the first magnetization supply layer 4 and the second magnetization supply layer 5 are used as the magnetization supply means, even if the domain wall DW is moved, the domain wall DW is in contact with the first magnetization supply layer 4 and the second magnetization supply layer 5 There is no principle to move to the outside (X direction). By restricting the movable range of the domain wall DW, it is possible to suppress the domain wall DW from being lost during operation and to form a single magnetic domain.

  The same material as the magnetization fixed layer 1 can be used for the first magnetization supply layer 4 and the second magnetization supply layer 5. Orientation directions of the magnetization M4 of the first magnetization supply layer 4 and the magnetization M5 of the second magnetization supply layer 5 are set in advance by an external magnetic field or the like.

"Current control means"
The current control means is a control means that controls so that a current flows from the magnetization fixed layer 1 to the second region 3b side of the domain wall drive layer 3 at the time of reading.

  One of the current control means is a potential control means for adjusting the potentials of the magnetization fixed layer 1, the first region 3a and the second region 3b at the time of reading. For example, the magnetization fixed layer 1 and the first region 3 a are set to the same potential, and the potential of the second region 3 b is set lower than the potential of the magnetization fixed layer 1. With this setting, a current flows from the magnetization fixed layer 1 to the second region 3b at the time of reading.

  In addition to this, a rectifying element such as a diode may be used as the current control means. At the time of reading, control may be performed so that current flows from the magnetization fixed layer 1 to the second region 3b by using a diode or the like.

(Operation of domain wall type analog memory device)
Next, the operation principle of data writing and reading of the domain wall based analog memory device according to the present embodiment will be described.

"Write operation"
First, the write operation will be described. In the domain wall type analog memory element, writing is performed using a magnetoresistive effect such as a GMR (Giant Magneto Resistance) effect or a TMR (Tunnel Magneto Resistance) effect. In the magnetoresistive effect, for example, the resistance value state caused by the parallel or antiparallel magnetization directions of the two ferromagnetic layers stacked via the nonmagnetic layer is associated as “0” or “1”. Record with Since the direction of magnetization does not change without applying external force, data is recorded in a non-volatile manner.

  At the time of writing, data is recorded by changing the orientation direction of the magnetizations M3a and M3b of the domain wall drive layer 3 with respect to the magnetization M1 of the magnetization fixed layer 1. Therefore, the state of magnetization of the domain wall driving layer 3 is rewritten at the time of writing. The state of magnetization of the domain wall drive layer 3 is also rewritten by supplying a write current from one end of the domain wall drive layer 3 to the other end. When a current equal to or greater than the threshold value flows in the direction (X direction) penetrating the domain wall DW, a spin polarization current is generated in the domain (domain) of the domain wall drive layer 3 and conduction electrons are generated in the domain wall DW in the domain wall drive layer 3. Move in the flowing direction.

FIG. 2 is a diagram showing a write operation of the domain wall based analog memory device 100 according to the present embodiment.
For example, when the current I _W1 flows from the first magnetization supply layer 4 through the domain wall drive layer 3 to the second magnetization supply layer 5 in the direction shown by the dotted line in FIG. 2A, the conduction electron e ₁ is a current I Contrary to the direction of _W1 , it flows in the direction shown by the solid line. When conduction electrons e ₁ from the second magnetization supply layer 5 enters the wall driving layer 3, the conduction electrons e ₁ is the magnetization of the second magnetic supply layer 5 and the second magnetization supply layer 5 and the magnetic coupling domains of wall driving layer 3 It becomes spin-polarized electrons corresponding to the direction of M3b. When this spin-polarized electrons reach the domain wall DW, spin with spin-polarized electrons in a magnetic domain wall DW undergoes a spin-transfer against the domain wall DW, the domain wall DW is moved in the same direction as the flow of conduction electrons e _1. That is, the domain wall DW moves from left to right in FIG.

Similarly, when the current I _W2 flows from the second magnetization supply layer 5 to the first magnetization supply layer 4 via the domain wall drive layer 3 in the direction indicated by the dotted line in FIG. 2B, the conduction electron e ₂ is a current Contrary to the direction of I _W2 , it flows in the direction shown by the solid line. When the conduction electron e ₂ enters the domain wall drive layer 3 from the first magnetization supply layer 4, the conduction electron e ₂ is magnetized in the domain magnetically coupled to the first magnetization supply layer 4 of the first magnetization supply layer 4 and the domain wall drive layer 3. It becomes a spin polarization current corresponding to the direction of M3a. When the spin-polarized electrons reach the domain wall DW, the spins possessed by the spin-polarized electrons in the domain wall DW cause spin transfer to the domain wall DW, and the domain wall DW moves in the same direction as the conduction electrons e ₂ flow. That is, the domain wall DW moves from the right to the left in FIG.

  When the position of the domain wall DW changes, the magnetization state of the portion of the domain wall drive layer 3 in contact with the magnetization fixed layer 1 changes. For example, as shown in FIG. 2A, when the magnetization state of the portion in contact with the magnetization fixed layer 1 of the domain wall drive layer 3 is antiparallel to the magnetization M1 of the magnetization fixed layer 1, “0” is shown in FIG. The data can be recorded in binary values by setting the magnetization state of the portion of the domain wall drive layer 3 in contact with the magnetization fixed layer 1 parallel to the magnetization M 1 of the magnetization fixed layer 1 as “1” as shown in FIG. Further, in the case where the domain wall DW is in a portion in contact with the magnetization fixed layer 1 of the domain wall drive layer 3, a plurality of threshold values are provided for the resistance value which varies by changing the ratio of magnetization M3a and magnetization M3b in the domain wall drive layer 3. Data can be recorded in multiple values.

  Further, the moving amount (moving distance) of the domain wall DW can be variably controlled by adjusting the magnitude and time of the write current. For example, the amount of movement of the domain wall DW (the movement distance) may be set according to the number of pulses or the pulse width.

"Read operation"
Next, the data read operation will be described. FIG. 3 is a diagram showing the read operation of the domain wall based analog memory device 100 according to the present embodiment.

As shown in FIG. 3, when data is read, the electric current I _R between the second region 3b of the magnetization fixed layer 1 and the wall driving layer 3. The flow direction of the current I _R is controlled by current control means. Magnetization M1 and the alignment direction opposite magnetization M3b of the magnetization fixed layer 1 by flowing a current I _R in the direction in which the presence, the resistance value change of the magnetic wall-using the analog memory device 100 is a linear, data more precisely multi It can be read by value.

  The magnetization M 3 a of the first region 3 a of the domain wall drive layer 3 is oriented parallel to the magnetization M 1 of the magnetization fixed layer 1. On the other hand, the magnetization M 3 b of the second region 3 b of the domain wall drive layer 3 is oriented antiparallel to the magnetization M 1 of the magnetization fixed layer 1. That is, the interface between the magnetization fixed layer 1 and the first region 3a has a low resistance, and the interface between the magnetization fixed layer 1 and the second region 3b has a high resistance.

FIG. 4 is a view schematically showing a part of the circuit at the time of data reading, where (a) shows the magnetization M1 and orientation of the magnetization fixed layer 1 as in the domain wall utilizing type analog memory element according to the present embodiment. a circuit diagram of a case where the direction is flowing read current I _R in the direction in which there is an opposite magnetization M 3 b, read in the direction in which there is (b) the magnetization of the magnetization fixed layer 1 is M1 and the alignment is the same magnetization M3a it is a circuit diagram when a current flows I _R.

If the orientation direction as the magnetization M1 of the magnetization fixed layer 1 shed the read current I _R in the second area 3b side there are opposite magnetization M 3 b, as shown in FIG. 4 (a), the magnetization fixed layer 1 and the first region a current path _{I 3a} having a resistance _{R 3a} at the interface between 3a, a current path _{I 3b} having magnetization fixed layer 1 and a resistor _{R 3b} at the interface of the second region 3b, the parallel circuit having a are formed. Magnetization pinned layer 1 and the resistor R _3a and magnetization fixed layer 1 at the interface between the first region 3a resistor R _3b at the interface of the second region 3b is the position of the domain wall DW in the magnetic wall driving layer 3 in contact with magnetization fixed layer 1 It can be regarded as a changing variable resistance.

Further, since the read current I _R finally flows to the second region 3b side, the current flowing to the interface between the magnetization fixed layer 1 and the first region 3a is the domain wall DW between the first region 3a and the second region 3b. pass. That is, the current path _{I 3a} resistor _{R DW} in the domain wall DW interface is superimposed. The resistance _RD can be regarded as a fixed resistance because the domain wall DW only changes in position but does not greatly change the resistance state.

In contrast, even if flowing a read current I _R in the first region 3a side magnetization M1 and the alignment of the magnetization fixed layer 1 at which the identical magnetization M3a, as shown in FIG. 4 (b), the magnetization fixed layer 1 a parallel circuit having a current path _{I 3a} having a resistance _{R 3a} at the interface between the first region 3a, and a current path _{I 3b} having magnetization fixed layer 1 and a resistor _{R 3b} at the interface of the second region 3b is formed Be done. On the other hand, since the read current I _R finally flows to the first region 3a side, the current flowing to the interface between the magnetization fixed layer 1 and the second region 3b is the current between the first region 3a and the second region 3b. It is necessary to pass through the domain wall DW. That is, the resistance _{R DW} is superimposed in the domain wall DW interface in the current path _{I 3b.}

Here, as described above, the magnetization fixed layer 1 and the surface of the resistance R _3a of the first region 3a is a low-resistance than the resistance R _3b the interface of the magnetization fixed layer 1 and the second region 3b. As shown in FIG. 4 (b), when present in the current path _{I 3b} resistance _{R DW} at the interface of the domain wall DW is present a high resistance resistor _{R 3b,} the total resistance of the current path _{I 3b} is increased, the read current Many flow through the current path I _3a . Therefore, when passing a read current I _R in the first region 3a side orientation direction as the magnetization M1 of the magnetization fixed layer 1 at which the identical magnetization M3a, primarily from being read as a change in resistance of the magnetic wall-using the analog memory device 100 is the resistance value variation of the resistance R _3a at the interface of the magnetization fixed layer 1 and the first region 3a, the resistance value variation of the resistance R _3b of the magnetization fixed layer 1 and the interface of the second region 3b are not significantly contribute.

In contrast, as shown in FIG. 4 (a), when the resistance _{R DW} at the interface of the domain wall DW is present in a current path _{I 3a} to low-resistance resistor _{R 3a} is present, total resistance of the current path _{I 3a} increases , the distribution ratio of the read current flowing through the read current and the current path I _3b flowing through the current path I _3a are averaged. Therefore, when passing a read current I _R in the second area 3b side orientation direction as the magnetization M1 of the magnetization fixed layer 1 is present opposite magnetization M 3 b, the read current in any of the current paths I _3a and the current path I _3b Flow, the combination of the change in resistance of the resistance R _3a between the magnetization fixed layer 1 and the first region 3a and the change in resistance of the resistance R _3b between the magnetization fixed layer 1 and the second region 3b It is read as a change in resistance value of the analog memory element 100.

As described above, by controlling the flow direction of the current I _R at the time of reading by the current control means, the resistance value change of the two resistors R _3a and R _3b (variable resistors) on the circuit is controlled by the resistance of the domain wall utilizing analog memory element 100. It can be read out as a value change, and data can be read out more precisely.

  At the time of data reading, it is necessary to consider the spatial distribution of the current. In FIG. 3, the resistance between the magnetization fixed layer 1 and the domain wall drive layer 3 differs depending on the magnetization directions of the magnetization fixed layer 1 and the domain wall drive layer 3. In FIG. 3, the orientations of the first region 3a and the magnetization fixed layer 1 are parallel, and the resistance is low. The directions of the second region 3b and the magnetization fixed layer 1 are antiparallel, and the resistance is high. That is, the current easily flows into the first region 3a. The current that has flowed to the first region 3a flows to the second magnetization supply layer 5 through the second region 3b. However, when the current flows from the magnetization fixed layer 1 to the first magnetization supply layer 4, the current flowing to the first region 3 a flows directly to the first magnetization supply layer 4. The current flowing through the second magnetization supply layer 5 is reduced, and the high resistance region can not be sufficiently utilized as the resistance of the path. Therefore, rather than the current flowing from the magnetization fixed layer 1 to the first magnetization supply layer 4, the linearity of the read resistance against the movement of the domain wall in the case where the current flows from the magnetization fixed layer 1 to the second magnetization supply layer 5 Sex improves.

Note that part of the current I _R at the time of reading flows in the direction (X direction) which penetrates the domain wall DW. At this time, it is assumed that the domain wall DW moves and the write state changes at the time of reading, but the current I _R applied at the time of reading is smaller than the currents I _W1 and I _W2 applied at the time of writing. Therefore, the movement of the domain wall DW can be suppressed by adjusting the current I _R applied at the time of reading.

As described above, the domain wall utilizing analog memory element 100 according to the first embodiment adjusts the composition ratio of the first region 3a and the second region 3b in the portion of the domain wall driving layer 3 in contact with the magnetization fixed layer 1 at the time of writing. By moving the domain wall DW, data can be recorded in multiple values. Further, by controlling the flow direction of the current I _R at the time of reading by the current control means, the resistance value change of the domain wall utilizing type analog memory device 100 changes linearly due to domain wall driving, and the analog value can be measured more accurately.

(Other configuration)
A magnetic coupling layer may be provided between the domain wall drive layer 3 and the nonmagnetic layer 2. The magnetic coupling layer is a layer to which the magnetization state of the domain wall drive layer 3 is transferred. The main function of the domain wall drive layer 3 is to drive the domain wall, and it is not always possible to select a material suitable for the magnetoresistive effect generated through the magnetization fixed layer 1 and the nonmagnetic layer 2. In general, in order to cause a coherent tunneling effect using the nonmagnetic layer 2, it is known that the magnetization fixed layer 1 or the magnetic coupling layer is preferably a ferromagnetic material having a BCC structure. In particular, it is known that a large output can be obtained when a material having a composition of Co—Fe—B is prepared by sputtering as the material of the magnetization fixed layer 1 and the magnetic coupling layer.

  The thickness of the portion of the domain wall drive layer 3 overlapping the magnetization fixed layer 1 in plan view may be thicker than that of the other portions. When the domain wall DW moves in the lower part of the nonmagnetic layer 2, the cross-sectional area of the domain wall DW increases, so that the current density decreases and the moving speed of the domain wall DW becomes slow. When the moving speed of the domain wall DW becomes slow, it becomes easy to control the composition ratio of the first region 3a and the second region 3b in the portion in contact with the magnetization fixed layer 1 of the domain wall drive layer 3, and it becomes easy to read output data as an analog value.

  Such a structure can be manufactured by forming the magnetic domain drive layer 3, the nonmagnetic layer 2, and the magnetization fixed layer 1 by continuous film formation and scraping off unnecessary portions. When continuous film formation is performed, the coupling between the layers to be joined becomes strong, and more efficient magnetic coupling and output can be obtained.

  In addition to this, a configuration equivalent to the configuration used for the magnetoresistive effect element can be used. For example, each layer may be composed of a plurality of layers, or may be provided with another layer such as an antiferromagnetic layer for fixing the magnetization direction of the magnetization fixed layer 1.

"2nd Embodiment"
FIG. 5 is a schematic perspective view of a domain wall based analog memory device 101 according to the second embodiment. The domain wall based analog memory element 101 according to the second embodiment differs from the domain wall based analog memory element 100 according to the first embodiment in that the magnetization supply means is different. The other configuration is the same as that of the domain wall based analog memory device 100 according to the first embodiment, and the same configuration is denoted by the same reference numeral.

  In the domain wall utilizing type analog memory element 101 according to the second embodiment, the magnetization supplying means is electrically insulated from the domain wall driving layer 3 and extends in the direction intersecting with the domain wall driving layer 3. Wiring 15 is shown.

The domain wall based analog memory device 101 according to the second embodiment differs in magnetization supply means, so the operation at the time of writing is different. When writing magnetic domain wall-using the analog memory device 101, electric current _{I 14, I 15} and first wiring 14 on at least one of the second wiring 15. The first wiring 14 and second wiring 15, the current _{I 14,} when _{I 15} flows a magnetic field from Ampere's law _{M 14, M 15} is generated.

The directions of the current I ₁₄ flowing through the first wiring 14 and the current I ₁₅ flowing through the second wiring 15 are opposite to each other. By reversing the direction of the current, the directions of the magnetic fields M ₁₄ and M ₁₅ generated around the respective wires become opposite. Magnetic field _{M 14} of the first wiring 14 produces gives a magnetic field _{M 14} of + X in wall driving layer 3, a magnetic field _{M 15} of the second wiring 15 produces gives a magnetic field _{M 15} of -X to wall driving layer 3. That is, by flowing the first wiring 14 and the second wiring 15, the composition ratio of the first region 3a and the second region 3b of the domain wall driving layer 3 can be changed, and the position of the domain wall DW can move the movement. Can be recorded in multiple values.

  At the time of data reading, the flow direction of the current is controlled between the magnetization fixed layer 1 and the second region 3 b of the domain wall drive layer 3 as in the domain wall based analog memory device 100 according to the first embodiment. , Data can be read correctly.

  The material used for the first wiring 14 and the second wiring 15 is not particularly limited as long as it has excellent conductivity. For example, gold, silver, copper, aluminum or the like can be used.

When the magnetization directions of the magnetization fixed layer 1 and the domain wall driving layer 3 are oriented in the Z direction as in the domain wall utilizing type analog memory element 102 shown in FIG. 6, the first wiring 14 and the second wiring 15 are The position of the domain wall DW can be moved by adjusting the positional relationship and the direction in which the currents I _{14 and} I ₁₅ flow.

"3rd Embodiment"
FIG. 7 is a schematic perspective view of a domain wall based analog memory device 103 according to the third embodiment. The domain wall based analog memory device 103 according to the third embodiment differs from the domain wall based analog memory device 100 according to the first embodiment in that the magnetization supply means is different. The other configuration is the same as that of the domain wall based analog memory device 100 according to the first embodiment, and the same configuration is denoted by the same reference numeral.

  In the domain wall utilizing type analog memory element 103 according to the third embodiment, the magnetization supplying means is in contact with the domain wall driving layer 3 and extends in a direction intersecting the domain wall driving layer 3 with the first spin track torque wiring 24 and the second spin. Orbital torque wiring 25. Hereinafter, the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25 may be collectively referred to as a spin orbit torque.

The domain wall based analog memory device 103 according to the third embodiment differs in magnetization supply means, so the operation at the time of writing is different. When writing magnetic domain wall-using the analog memory device 103, electric current _{I 24, I 25} and the first spin-orbit torque wire 24 on at least one of the second spin-orbit torque wire 25.

When currents I _{24 and} I ₂₅ flow through the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25, spin derived from the spin orbit interaction is supplied to the domain wall driving layer 3. The spin derived from the spin-orbit interaction is generated by the spin Hall effect generated by current flow in the spin-orbit torque wiring and the interface Rashba effect between different element interfaces.

  The spin Hall effect is a phenomenon in which a pure spin current is induced in a direction perpendicular to the current direction based on spin-orbit interaction when a current flows in a material. When current flows in the extending direction of the spin orbit torque wiring, the first spins oriented in one direction and the second spins oriented in the opposite direction are bent in the direction orthogonal to the current, respectively. The ordinary Hall effect and the spin Hall effect are common in that moving (moving) charges (electrons) can bend the direction of movement (moving), but the ordinary Hall effect causes charged particles moving in a magnetic field to move the Lorentz force. In contrast to being able to receive and bend the direction of movement, the spin Hall effect is largely different in that the direction of movement is bent only by electron movement (only current flow) even though there is no magnetic field.

In nonmagnetic materials (materials that are not ferromagnetic materials), the number of electrons in the first spin and the number of electrons in the second spin are equal. Therefore, for example, the number of electrons of the first spin directed upward in the drawing is equal to the number of electrons of the second spin directed downward. The flow of the first spin electronic J _↑, the flow of the second spin electrons J _↓, to represent the spin current and _{J S,} is defined by _J S = _{J ↑} -J _↓. J _S is a current of electrons having a polarizability of 100%. That is, in the spin-orbit torque wiring, the current as the net flow of charge is zero, and the spin current without this current is particularly called pure spin current.

  When a spin orbit torque wiring in which a pure spin current is generated is joined to the domain wall drive layer 3, spins oriented in a predetermined direction are diffused and flow into the domain wall drive layer 3.

  The interface Rashba effect is a phenomenon in which spins are easily oriented in a predetermined direction under the influence of an interface between different elements, and spins oriented in a predetermined direction are accumulated in the vicinity of the interface.

  For example, in FIG. 7, the interface between the spin orbit torque wiring and the domain wall drive layer 3 corresponds to the interface between different elements. Therefore, the spins oriented in a predetermined direction are accumulated in the surface on the domain wall driving layer 3 side of the spin orbit torque wiring. The accumulated spins diffuse and flow into the domain wall drive layer 3 in order to obtain energetic stability.

The direction of the spins diffused and flowing into the domain wall driving layer 3 can be changed by the direction of the current flowing through the first spin orbit torque wire 24 and the second spin orbit torque wire 25. The first region 3a spin magnetization M _3a in the same direction to the wall driving layer 3, the second region 3b of the wall driving layer 3 is spin magnetization M _3b in the same direction, to be supplied.

As described above, by causing the current I _{24 and} I ₂₅ to flow in at least one of the first spin orbit torque wiring 24 and the second spin orbit torque wiring 25, spins in a predetermined direction can be supplied to the domain wall drive layer 3. . As a result, the composition ratio of the first region 3a and the second region 3b of the domain wall drive layer 3 is changed, and the position of the domain wall DW moves, whereby data can be recorded in multiple values.

  At the time of data reading, the flow direction of the current is controlled between the magnetization fixed layer 1 and the second region 3 b of the domain wall drive layer 3 as in the domain wall based analog memory device 100 according to the first embodiment. , Data can be read correctly.

  The spin orbit torque wiring is made of a material in which a pure spin current is generated by the spin Hall effect when current flows. The material constituting the spin orbit torque wiring is not limited to the material consisting of a single element, and is composed of a part composed of a material in which a pure spin current is generated and a part composed of a material in which a pure spin current is not generated Or the like.

  The spin track torque wiring may include nonmagnetic heavy metals. Here, heavy metal is used in the meaning of the metal which has specific gravity more than yttrium. The spin orbit torque wiring may be made of only nonmagnetic heavy metals.

  In this case, the nonmagnetic heavy metal is preferably a nonmagnetic metal having an atomic number of 39 or more, which has d electrons or f electrons in the outermost shell. Such nonmagnetic metals have a large spin-orbit interaction that causes the spin Hall effect. The spin orbit torque wiring may be made of only a nonmagnetic metal having a large atomic number of 39 or more, which has d electrons or f electrons in the outermost shell.

  Normally, when current flows in metal, all electrons move in the direction opposite to the current regardless of the direction of spin, while nonmagnetic metal with large atomic number having d electrons or f electrons in the outermost shell Since the spin-orbit interaction is large, the direction of electron movement depends on the direction of electron spin by the spin Hall effect, and a pure spin current is likely to occur. The spin track torque wiring is preferably a metal alloy. Since different metallic elements are present in one structure of the alloy, the symmetry of the crystal structure is reduced and pure spin current is likely to occur. It is further preferable that the atomic numbers of the metal elements constituting the alloy be sufficiently different. In this case, since the orbit of the metal element felt by the electrons is largely changed, a pure spin current is more easily generated.

  In addition, the spin track torque wiring may include magnetic metal. Magnetic metal refers to ferromagnetic metal or antiferromagnetic metal. If the nonmagnetic metal contains a trace amount of magnetic metal, the spin-orbit interaction is enhanced, and the spin current generation efficiency with respect to the current flowing through the spin-orbit torque wiring can be increased. The spin orbit torque wiring may be made of only antiferromagnetic metal.

  Since the spin-orbit interaction is caused by the intrinsic internal field of the material of the spin-orbit torque wiring material, a pure spin current is also generated in the nonmagnetic material. When a small amount of magnetic metal is added to the spin orbit torque wiring material, the spin current generation efficiency is improved because the magnetic metal itself scatters the electron spins flowing therethrough. However, if the addition amount of the magnetic metal is excessively increased, the generated pure spin current is scattered by the added magnetic metal, and as a result, the spin current decreases. Therefore, it is preferable that the molar ratio of the magnetic metal to be added be sufficiently smaller than the molar ratio of the main component of the spin track torque wiring. As a rule, the molar ratio of the magnetic metal added is preferably 3% or less.

  The spin track torque wiring may also include topological insulators. The spin track torque wiring may consist only of topological insulators. The topological insulator is a substance in which the inside of the substance is an insulator or a high resistance, but a spin-polarized metal state is generated on the surface thereof. There is something like an internal magnetic field called spin-orbit interaction in matter. Therefore, even if there is no external magnetic field, a new topological phase appears due to the effect of spin-orbit interaction. This is a topological insulator, and strong spin-orbit interaction and inversion symmetry breaking at the edge can generate pure spin current with high efficiency.

The topological insulators _{example, SnTe, Bi 1.5 Sb 0.5 Te} 1.7 Se 1.3, TlBiSe 2, Bi 2 Te 3, preferably such as _{(Bi 1-x Sb x)} 2 Te 3. These topological insulators can generate spin current with high efficiency.

"4th Embodiment"
FIG. 8 is a schematic perspective view of a domain wall based analog memory element 104 according to the fourth embodiment. The domain wall based analog memory element 104 according to the fourth embodiment differs from the domain wall based analog memory element 100 according to the first embodiment in that the magnetization supply means is different. The other configuration is the same as that of the domain wall based analog memory device 100 according to the first embodiment, and the same configuration is denoted by the same reference numeral.

  In the domain wall utilizing type analog memory element 104 according to the fourth embodiment, the magnetization supplying means is the first voltage applying terminal 34 and the second voltage applying terminal 35 connected to the domain wall driving layer 3 via the insulating layers 36 and 37. Hereinafter, the first voltage application terminal 34 and the second voltage application terminal 35 may be collectively referred to as a voltage application terminal.

  Since the magnetic wall utilizing analog memory element 104 according to the fourth embodiment differs in magnetization supply means, the operation at the time of writing is different. When writing the domain wall based analog memory element 104, a voltage is applied between the magnetization fixed layer 1 and the first voltage application terminal 34 or the second voltage application terminal 35.

For example, when a voltage is applied between the magnetization fixed layer 1 and the first voltage application terminal 34, a part of the magnetization M _3a of the first region 3a is affected by the voltage. When a voltage is applied as a pulse, part of the magnetization M _3a is oriented in the Z direction when the voltage is applied, and is oriented in the easy magnetization direction + X or −X direction at the timing when the voltage application is stopped. It is equally probability that the magnetization oriented in the Z direction falls in the + X direction or the −X direction, and part of the magnetization M _3a can be viewed from the + X direction by adjusting the timing, number, and period of applying the pulse voltage. It can be oriented in the X direction.

  As described above, by applying a voltage to the domain wall drive layer 3 as a pulse, it is possible to supply the domain wall drive layer 3 with spin in a predetermined direction. As a result, the composition ratio of the first region 3a and the second region 3b of the domain wall drive layer 3 is changed, and the position of the domain wall DW moves, whereby data can be recorded in multiple values.

  On the other hand, the insulating layers 36 and 37 inhibit the flow of current at the time of reading. Therefore, the presence of the insulating layers 36 and 37 may reduce the output characteristics of the domain wall utilizing analog memory device 104. In this case, as in the domain wall utilizing type analog memory device 104 shown in FIG. 9, a reading wire 38 through which a reading current flows may be provided.

  The embodiments of the present invention have been described in detail with reference to the drawings, but the respective configurations and the combinations thereof and the like in the respective embodiments are merely examples, and additions and omissions of configurations are possible within the scope of the present invention. , Permutations, and other modifications are possible.

  The magnetization supply means may be different from the means for supplying the magnetization to the first region 3a and the means for supplying the magnetization to the second region 3b. For example, the means for supplying the magnetization to the first region 3 a may be the first magnetization supply layer 4, and the means for supplying the magnetization to the second region 3 b may be the second wiring 15. Thus, the magnetization supply means according to the first to fourth embodiments may be combined and arranged. Further, as the magnetization supply means, the write current itself flowing through the domain wall drive layer 3 may be used as the spin polarization current.

(A domain wall type analog memory)
The domain wall based analog memory according to the present embodiment includes a plurality of domain wall based analog memory elements according to the above-described embodiment.

  FIG. 10 is a view schematically showing an example of a circuit structure of a domain wall based analog memory 200 according to the present embodiment. The domain wall utilization type analog memory 200 includes a plurality of domain wall utilization type analog memory elements 100, a first wiring 201, a first control element 202, a second wiring 203, a second control element 204, and a third wiring 205. , Cell selection control element 206.

  The first wiring 201 is connected to the magnetization fixed layer 1 of each domain wall utilizing analog memory element 100, and connects the magnetization fixed layer 1 and the first control element 202. The second wiring 203 is connected to the first magnetization supply layer 4 of each domain wall utilizing analog memory element 100, and connects the first magnetization supply layer 4 and the second control element 204. The third wiring 205 is connected to the second magnetization supply layer 5 of each domain wall utilizing analog memory element 100, and connects the first magnetization supply layer 4 and the cell selection control element 206 to each other.

  For the first wiring 201, the second wiring 203, and the third wiring 205, a material used as a material of a normal wiring can be used. For example, aluminum, silver, copper, gold or the like can be used.

  The first control element 202 controls the current flowing to the first wiring 201. The second control element 204 controls the current flowing through the second wiring 203. The cell selection control element 206 controls which domain wall utilizing analog memory element 100 a current flows at the time of writing and reading.

  As the first control element 202, the second control element 204, and the cell selection control element 206, known switching elements can be used. For example, a transistor element represented by a field effect transistor or the like can be used.

  When writing data in the domain wall based analog memory 200, the cell selection control element 206 connected to the second control element 204 and the domain wall based analog memory element 100 to which data is to be written is released. Thereby, the domain wall DW of the domain wall drive layer 3 of the predetermined domain wall based analog memory element 100 is moved, and data is written.

  When reading data from the domain wall based analog memory 200, the cell selection control element 206 connected to the first control element 202 and the domain wall based analog memory element 100 to which data is to be written is opened. Thereby, data of a predetermined domain wall utilizing analog memory element 100 is read out.

(Nonvolatile logic circuit)
In the nonvolatile logic circuit according to the present embodiment, the domain wall based analog memory elements according to the present embodiment are arranged in an array, STT-MRAM is provided in any of the arrays or other than the array, and the storage function and the logic function are provided. It has a domain wall based analog memory element and STT-MRAM as a storage function.
Since the domain wall based analog memory element and the STT-MRAM can be manufactured in the same process, cost can be reduced. In addition, by installing STT-MRAM, which is digital, in the same circuit as a domain-wall-based analog memory element arranged in an array, input / output can be digitized and logic that can be internally processed in analog It can be formed.

(Magnetic neuro device)
FIG. 11 is a schematic cross-sectional view of an example of the magnetic neuro device according to the present embodiment. The magnetic neuro device 300 according to the present embodiment includes the above-described domain wall utilizing analog memory device and a current source (not shown) having a control circuit. A first storage unit 301 and a second storage unit 302 and a third storage unit 303 sandwiching the first storage unit 301 are provided in the longitudinal direction of the domain wall driving layer 3 of the domain wall utilizing analog memory element. The control circuit supplies a write current that can sequentially move the domain wall so as to stay at least once in all of the first storage unit 301, the second storage unit 302, and the third storage unit 303.

  The first storage unit 301 is a portion overlapping the magnetization fixed layer 1 in a plan view of the domain wall drive layer 3. The second storage unit 302 is located in a portion between the portion overlapping with the magnetization fixed layer 1 and the second magnetization supply layer 5 in plan view (a portion not overlapping with any of the magnetization fixed layer 1 and the second magnetization supply layer 5). . In addition, the third storage unit 303 is a portion between the magnetization fixed layer 1 and the first magnetization supply layer 4 in a plan view (a portion not overlapping with any of the magnetization fixed layer 1 and the first magnetization supply layer 4). .

  The magnetic neuro element is an element that simulates synapse operation, and can be used as a magnetic neuro element by providing a control circuit in the domain wall based analog memory element according to the present embodiment.

  The synapse has a linear output with respect to an external stimulus, and outputs reversibly without hysteresis when reverse load is given. When the area of the portion in which the magnetization directions of the magnetization fixed layer 1 and the domain wall drive layer 3 are parallel is continuously changed by the driving (movement) of the domain wall DW, the magnetization directions of the magnetization fixed layer 1 and the domain wall drive layer 3 become the same. A parallel circuit is formed by the current path formed in the parallel portion and the current path formed in the antiparallel portion.

  When the domain wall DW of the domain wall drive layer 3 moves, the ratio of the area ratio of the portion in which the magnetization directions are parallel to the area ratio of the portion in which the magnetization directions are antiparallel changes, and a relatively linear resistance change is obtained. Also, the movement of the domain wall DW depends on the magnitude of the current and the time of the applied current pulse. As a result, the magnitude and direction of the current, and the time of the applied current pulse can be regarded as an external load.

(Early stage of memory)
For example, when the domain wall of the domain wall drive layer 3 moves to the maximum in the −X direction, the domain wall DW is stabilized at the end 302 a of the second magnetization supply layer 5 on the magnetization fixed layer 1 side. When current flows from the first magnetization supply layer 4 to the second magnetization supply layer 5, electrons flow from the second magnetization supply layer 5 to the first magnetization supply layer 4, and the inside of the second magnetization supply layer 5 and the domain wall drive layer 3 The spin-polarized electrons cause spin transfer, and the domain wall DW moves in the + X direction. Even if the domain wall DW moves until the domain wall DW reaches the end 302b of the magnetization fixed layer 1 on the second magnetization supply layer 5 side, the read resistance does not change. This state (when the domain wall DW is disposed in the second storage unit 302) is referred to as an initial stage of storage. Although the data is not recorded at the initial stage of storage, it is in a state of being ready for recording data.

(Main memory stage)
While the domain wall DW passes through the lower portion of the magnetization fixed layer 1 (the overlapping portion in the plan view, the first storage unit 301), the resistance at the time of reading changes. The flow of current from the first magnetization supply layer 4 to the second magnetization supply layer 5 can be used as an external load, and a linear change in resistance value proportional to the load can be read out. This is the main memory stage. That is, the case where the domain wall DW is disposed in the first storage unit 301 is referred to as a main storage stage of storage. A state in which the domain wall DW is outside the one end in the X direction of the magnetization fixed layer 1 is stored or defined as no memory, and a state in which the domain wall DW is outside the other end of the magnetization fixed layer 1 is not It defines as memory or memory. When the direction of the current flowing in the domain wall drive layer 3 is reversed, the reverse action is obtained.

(The deepening stage of memory)
When the domain wall DW reaches the end portion 303 b on the first magnetization supply layer 4 side of the magnetization fixed layer 1 and the domain wall DW moves in the direction away from the magnetization fixed layer 1, the read output does not change. However, after the domain wall DW is sufficiently separated from the magnetization fixed layer 1, the output at the time of reading does not change until the domain wall DW reaches the end portion 303 b of the magnetization fixed layer 1 even if a reverse load is applied. That is, when the domain wall DW is in the third storage unit 303, the storage is deepened without losing the storage even if an external load is applied. That is, the case where the domain wall DW is disposed in the third storage unit 303 is referred to as the deeping stage of storage.

  When the direction of the current flowing through the domain wall drive layer 3 is reversed, the correspondence between the initial stage of storage, the main storage stage and the deep storage stage of storage and each storage unit is reversed.

  As described above, in order to use the domain wall based analog memory as a magnetic neuro element that simulates synapse operation, it is necessary to move the domain wall DW sequentially through the initial stage of storage, the main storage stage, and the deep storage stage of storage. The movement of the domain wall DW is controlled by a current source that passes a write current. That is, the domain wall utilizing type analog memory is controlled to flow a write current capable of moving the domain wall sequentially so as to stay at least once in all the storage units of at least the first storage unit, the second storage unit and the third storage unit. By providing a current source (not shown) having a control circuit, it functions as a magnetic neuro device. The number of movements of each of the first storage unit 301, the second storage unit 302, and the third storage unit 303 determines how many times the domain wall passes through depending on the conditions of the write current.

(Memory oblivion phase)
Memory can be forgotten by moving the domain wall of the domain wall drive layer 3 in a non-memory state. In addition, the domain wall can also be driven or dissipated by applying an external magnetic field, heat, and physical distortion. In the domain wall based analog memory, storage and no storage are determined by definition because the output shows constant low resistance and high resistance values. In addition, since the domain wall is made to move or disappear by a method other than supplying current to the domain wall driving layer 3, the correlation of the information among the plurality of domain wall utilizing analog memories is lost. These are called the oblivion phase of memory.

(Artificial brain using magnetic neuro elements)
The magnetic neuro device according to the present embodiment is a memory that simulates synapse movement and can go through the initial stage of memory, the main memory stage, and the depth stage of memory. That is, it is possible to simulate a brain by installing domain wall utilizing analog memories on a plurality of circuits. It is possible to form a brain with a high degree of integration in an arrangement in which the vertical and horizontal arrays are uniformly arrayed as in a general memory.

  As shown in FIG. 12, by arranging a plurality of magnetic neuroelements having specific circuits as one mass and arranging them in an array, it is possible to form a brain having a different degree of recognition from an external load. FIG. 13 shows a product-sum operation circuit in which magnetic neuro elements are arrayed. In FIG. 13, data is simultaneously input to the respective wirings from the left direction in the drawing. The input data is output based on the weight (the initial stage of storage, the main storage stage, and the depthing stage of storage) recorded by the magnetic neuro element. Each data output from each magnetic neuro element is bundled in the column direction and output. The neuromorphic computer having the product-sum operation circuit shown in FIG. 13 can produce individualities such as a brain sensitive to color and a brain having a high level of language understanding like a brain. In other words, the information obtained from an external sensor is processed in the five sense areas optimized for vision, taste, touch, smell, and auditory recognition, and further, by judgment in the logical thinking area, It is possible to form a process of determining behavior. Furthermore, when the material of the domain wall driving layer 3 is changed, the driving speed of the domain wall to the load and the method of forming the domain wall are changed, so that it is possible to form an artificial brain having the change as individuality.

DESCRIPTION OF SYMBOLS 1 ... magnetization fixed layer, 2 ... nonmagnetic layer, 3 ... domain wall drive layer, 3a ... 1st area, 3b ... 2nd area, 4 ... 1st magnetization supply layer, 5 ... 2nd magnetization supply layer, 14 ... 1st Wiring 15 15 second wiring 24 first spin orbit torque wiring 25 second spin orbit torque wiring 34 first voltage application terminal 35 second voltage application terminal 36, 37 insulation layer 38 ... Readout wiring, 100, 101, 102 ... Domain wall utilization type analog memory device, 200 ... Domain wall utilization type analog memory, 201 ... First wiring, 202 ... First control element, 203 ... Second wiring, 204 ... Second control Element 205: Third wiring 206: Cell selection control element 300: Magnetic neuro element 301: First storage unit 302: Second storage unit 303: Third storage unit M1, M3a, M3b, M4, M5 ... _{magnetization, I W1, I W2, I} R _{I 14, I 15, I 24} , I 25 ... current, _{e 1, e} 2 _... conduction _{electrons, R 3a, R 3b, R} DW ... resistance, DW ... magnetic wall

Claims (10)

A fixed magnetization layer whose magnetization is oriented in a first direction,
A nonmagnetic layer provided on one side of the magnetization fixed layer;
It has a first region in which the magnetization is oriented in the first direction, a second region in which the magnetization is oriented in a second direction opposite to the first direction, and a domain wall forming an interface between these regions. A domain wall drive layer provided on both sides of the nonmagnetic layer with respect to the magnetization fixed layer;
And a current control unit for causing a current to flow between the magnetization fixed layer and the second region at the time of reading. The device further comprises a first magnetization supply means for supplying magnetization oriented in the first direction to the domain wall driving layer, and a second magnetization supply means for supplying magnetization oriented in the second direction,
At least one of the first magnetization supply unit and the second magnetization supply unit is a magnetization supply layer in contact with the domain wall drive layer and having magnetization oriented in the first direction or the second direction. A domain wall utilizing type analog memory device according to claim 1. The device further comprises a first magnetization supply means for supplying magnetization oriented in the first direction to the domain wall driving layer, and a second magnetization supply means for supplying magnetization oriented in the second direction,
At least one of the first magnetization supply means and the second magnetization supply means is a wire which is electrically insulated from the domain wall drive layer and extends in a direction intersecting the domain wall drive layer. The domain wall utilization type analog memory element of claim 1. The device further comprises a first magnetization supply means for supplying magnetization oriented in the first direction to the domain wall driving layer, and a second magnetization supply means for supplying magnetization oriented in the second direction,
At least one of the first magnetization supply unit and the second magnetization supply unit is a spin track torque wiring which contacts the domain wall drive layer and extends in a direction intersecting the domain wall drive layer. The domain wall utilization type analog memory element of 1. The device further comprises a first magnetization supply means for supplying magnetization oriented in the first direction to the domain wall driving layer, and a second magnetization supply means for supplying magnetization oriented in the second direction,
The domain wall utilizing type analog memory according to claim 1, wherein at least one of the first magnetization supplying means and the second magnetization supplying means is a voltage applying means connected to the domain wall driving layer via an insulating layer. element.   The domain wall utilizing analog memory device according to any one of claims 1 to 5, wherein the current control means is a potential control means for setting the potential of the second region lower than the potential of the magnetization fixed layer at the time of reading. .   The domain wall utilization type analog memory device according to any one of claims 1 to 5, wherein the current control means is a rectifying device for controlling the flow direction of current.   A domain wall utilizing analog memory comprising a plurality of domain wall utilizing analog memory elements according to any one of claims 1 to 7. The domain wall based analog memory element according to any one of claims 1 to 7 is arranged in an array.
An STT-MRAM is provided either in the array or other than the array,
A non-volatile logic circuit having a storage function and a logic function and including the domain wall utilizing analog memory element and the STT-MRAM as a storage function. A domain wall utilizing type analog memory device according to any one of claims 1 to 7, comprising:
The domain wall drive layer includes a first storage unit aligned in the longitudinal direction, and a second storage unit and a third storage unit sandwiching the first storage unit.
A current source having a control circuit for controlling a write current which can sequentially move the domain wall so as to stay at least once in all the storage units of the first storage unit, the second storage unit, and the third storage unit Magnetic neuro device.

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