JP2006270069A - Magnetoresistance effect element and high-speed magnetic recording device based on domain wall displacement by pulse current - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a magnetoresistance element capable of high-speed magnetization reversal and having low critical current density, and provide a solid memory. <P>SOLUTION: A magnetoresistance effect element comprises a first magnetization fixed layer, a magnetization free layer, and a second magnetization fixed layer. The first magnetization fixed layer is roughly anti-parallel to the second magnetization fixed layer. Both of transition regions between the first magnetization fixed layer and the magnetization free layer and between the second magnetization fixed layer and the magnetization free layer can trap magnetic domain walls, and there is provided a structure in which the magnetic domain wall exists in either one of them. Between the first and second magnetization fixed layers, pulse current having the DC current density with a pulse width of 1 ns that is a value not exceeding 10<SP>6</SP>A/cm<SP>2</SP>is supplied. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory using a magnetization reversal process due to low-current density and high-speed domain wall movement accompanying application of a pulse current, a solid-state memory element that reads using a magnetoresistive effect, and a device using these.

  The magnetoresistance effect is a phenomenon in which the electrical resistance changes when a magnetic field is applied to the magnetic material or when the magnetization state of the magnetic material changes. As a magnetoresistive effect element using this effect, a magnetic head and a magnetic sensor are conventionally known, and recently, a nonvolatile solid-state magnetic memory element (MRAM) or the like has been prototyped.

  The main form of the MRAM currently being prototyped has a matrix structure in which tunnel magnetoresistive (TMR) elements are arranged at the intersections of bit lines and word lines. Recording is performed by reversing the direction of magnetization of the TMR element by a synthetic magnetic field generated by a current flowing through each wiring. That is, the TMR element plays the role of a memory cell. In order to read the information of the memory cell, since there is a leak current from the memory cell, it is essential to select the cell by the MOS transistor. MRAMs having these structures have been pointed out because of their structures, the following disadvantages are the combination of process technologies and the following three defects that are not suitable for high density and large capacity. One is that the effective reversal magnetic field conditions are reduced by downsizing the memory cells. The other is the increase of the reversal magnetic field due to the thin film of the magnetic material, and the accompanying increase in wiring current and power consumption. The last is that it can be integrated only to the same extent as DRAM because it has MOS transistors for cell selection.

On the other hand, recently, spin torque, which is a magnetization reversal process that does not use a reversal magnetic field, has been proposed (Non-Patent Documents 1 and 2), and magnetization reversal by spin torque was actually confirmed (Non-Patent Documents 3 and 4). Writing to a memory cell has been proposed by this spin torque. However, magnetization reversal by spin torque currently has the following two technical problems. One is that the operating speed of the magnetization reversal process by spin torque is determined by the relaxation time. This is because the magnetization reversal process uses magnetization rotation in a quasi-steady state caused by magnetization relaxation (damping), and therefore cannot be applied to a solid-state memory that requires high-speed magnetization reversal. The other is that a critical current density as high as 10 ⁸ A / cm ² is required to generate spin torque that causes magnetization reversal.

Physical Review B39, 6995-7002 (1989) (Phys. Rev. B 39, 6995-7002 (1989)) Physical Review B 54, 9353-9358 (1996) (Phys. Rev. B 54, 9353-9358 (1996)) Physical Review Letters 84, 3149-3152 (2000) (Phys. Rev. Lett. 84, 3149-3152 (2000)) Applied Physics Letters 78, 3663-3665 (2001) (Appl. Phys. Lett. 78, 3663-3665 (2001))

  An object of the present invention is to provide a magnetoresistive element and a magnetic recording device having a low critical current density and a high-speed magnetization reversal process in writing to a memory cell by a magnetization reversal process that does not use a reversal magnetic field, as in spin torque magnetization reversal. It is to provide.

  In order to achieve the above object, a high-speed magnetic recording apparatus according to the present invention includes a first magnetization fixed layer, a magnetization free layer, and a second magnetization fixed layer, and the first magnetization fixed layer and the second magnetization fixed layer. And the transition region of both the first magnetization fixed layer and the magnetization free layer or the second magnetization fixed layer and the magnetization free layer can trap the domain wall, and one of them is the domain wall. And a pulse current having a sufficiently short pulse width in the range of 0.6 to 2.0 ns is supplied between the first and second magnetization fixed layers.

In the above configuration, the magnetization of the magnetization free layer can be reversed by moving the domain wall between the two transition regions with a DC current density of the pulse current not exceeding 10 ⁶ A / cm ² . The magnetic resistance due to the change in the relative magnetization direction of the transition region between the first and second magnetization fixed layers is detected by the magnetization reversal of the magnetization free layer.

  According to the magnetoresistive element of the present invention, it is possible to realize a magnetic storage device that has a low critical current density required for magnetization reversal and can be written at high speed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Example 1
(Application to solid-state memory devices)
FIG. 1 is a conceptual diagram for explaining the magnetoresistive effect element 10 of the present invention, and FIG. 2 is a diagram for explaining the characteristics of the magnetoresistive effect element 10 shown in FIG.

  A ferromagnetic fine wire made of Co having a width and thickness of 100 nm is formed by a normal electron beam lithography technique. Next, a region having a length of 200 nm from the end of the ferromagnetic fine wire is defined as a first ferromagnetic fine wire portion 11, and a first constriction portion 12 having a width, a thickness, and a length of 20 nm is adjacent to the first ferromagnetic fine wire portion 11. Adjacent to this, a ferromagnetic microregion part 13 having a width and thickness of 100 nm and a length of 10 nm, and adjoining this, a second constriction part 14 having a width, thickness and length of 20 nm, Is processed by a normal electron beam lithography technique so as to form a second ferromagnetic fine wire portion 15 having a width, a thickness, and a length of 100 nm.

  Here, the magnetization of one of the first and second ferromagnetic thin wire portions 11 and 15 is reversed (antiparallel) so that one of the magnetizations is reversed by the external magnetic field to form a magnetization fixed layer. . The ferromagnetic minute region 13 is a magnetization free layer. Hereinafter, paying attention to the function of each layer, the first and second ferromagnetic thin wire portions 11 and 15 are changed to the first and second magnetization fixed layers 11 and 15 and the ferromagnetic minute region portion 13 is changed to the magnetization free layer. 13 is called.

  Further, the first and second constriction portions 12 and 14 are made smaller in width, thickness, and length than the first and second magnetization fixed layers 11 and 15 and the magnetization free layer 13. The first and second constricted portions 12 and 14 are referred to as first and second transition regions. The first and second transition regions include not only the above-described Co, but also other examples of the thickness change portion (step) of a continuous magnetic material having a plurality of thicknesses, and the magnetic / insulator laminated structure. You may form by the insulator part or the pinhole etc. which are formed in the said insulator part. These can be processed by ordinary electron beam lithography techniques.

Electrodes that are in contact with the first and second magnetization fixed layers 11 and 15 in the magnetoresistive effect element 10 are provided outside, and electrodes are also provided outside the magnetization free layer 13. First, a DC power source for measurement 16 and a meter 17 for measurement are connected between the external electrodes of the first magnetization fixed layer 11 and the magnetization free layer 13 to measure a DC current for measurement (the magnitude is 0.3 × 10 ⁻⁴ A (= 0.03 mA)). Next, a direct current with a pulse width of 1 ns is supplied from the pulse current source 18 at a current of 1 × 10 ⁻⁴ A between the external electrodes on the magnetization fixed layer 11 side and the 15 side, and the polarity of the current is inverted at intervals of 30 s. Repeat. The current density when measured at the element input section is 10 ⁶ A / cm ² . 2 is observed between the external electrodes on the first magnetization fixed layer 11 side and the magnetization free layer 13 side.

  This is because, when the magnetization direction of one of the first and second magnetization fixed layers 11 and 15 is reversed, a domain wall is introduced into one of the first and second transition regions 12 and 14. It is considered that the magnetization direction of the magnetization free layer 13 has changed due to the domain wall moving by the pulse current applied between the first and second magnetization fixed layers 11 and 15. In other words, the domain wall runs through the magnetization free layer 13 within the time of the pulse current width of 1 ns. If the polarity of both the measurement current and the pulse current is reversed after waiting 30 seconds so that the domain wall that has ran completely does not return, it is said that the domain wall runs almost in the opposite direction. be able to.

The output signal in FIG. 2 is considered to be the magnetic resistance between the magnetization fixed layer 11 and the magnetization free layer 13 as described above, and is approximately 250% when converted to the magnetic resistivity. This is obtained as follows from the results of FIG. When the approximate value of the voltage obtained in FIG. 2 is estimated, the large voltage portion is about 550 mV, and the small portion is about 150 mV.
(550-150) /150=400/150=8/3=2.666666
It becomes. That is, about 250%. The characteristics shown in FIG. 2 were measured by connecting a DC power source 16 for measurement and a meter 17 for measurement between the external electrodes of the second magnetization fixed layer 15 and the magnetization free layer 13 to pass a DC current. Even if you get it the same way. However, the waveform of the output signal is inverted.

In the same measurement, when the current supplied between the external electrodes of the magnetization fixed layers 11 and 15 is simply a direct current, the magnitude equal to or larger than 10 ⁹ A / cm ² is observed in order to observe a result equivalent to FIG. It is necessary to supply a current having a current density of.

  That is, according to the present invention, it is possible to obtain a solid-state memory element that operates with a current that is three orders of magnitude smaller than that of driving with a simple direct current.

  Table 1 is a table showing the size of each part of the magnetoresistive effect element 10 shown in FIG. 1, that is, the magnetoresistance ratio when the magnetization fixed layers 11 and 15, the constriction parts 12 and 14 and the magnetization free layer 13 are variously changed. is there.

表１に示すケースは、第１の磁化固定層１１側と磁化自由層１３側の外部電極間に、測定用の直流電流０．０３ｍＡを流し、磁化固定層１１，１５間に１０^−４Ａレベルの電流でｎｓレベルのパルス幅の直流電流を供給し、３０ｓ間隔で電流の極性を反転させることを繰り返して上述のようにして得た磁気抵抗率を示すものである。表１のＮｏ．１のケースは、上述の例である。

In the case shown in Table 1, a measurement DC current of 0.03 mA is passed between the external electrodes on the first magnetization fixed layer 11 side and the magnetization free layer 13 side, and 10 ⁻⁴ A is applied between the magnetization fixed layers 11 and 15. The magnetic resistance obtained as described above is shown by repeatedly supplying a direct current with a pulse width of ns level at a level current and reversing the polarity of the current at intervals of 30 seconds. No. in Table 1 Case 1 is the example described above.

No. in Table 1 1-No. As can be seen from the result of FIG. 4, when the pulse current is 1 × 10 ⁻⁴ A and the first and second constriction portions 12 and 14 are 20 nm × 20 nm × 20 nm, the pulse width of the pulse current and the magnetization free The relationship with the length of the layer 13 shows a proportional relationship as shown in FIG. And it turns out that the magnetic resistivity obtained in the range shown in FIG. 3 is 200-250%.

  No. in Table 1 5 shows that the size of the first and second constrictions 12 and 14 is 40 nm × 40 nm × 40 nm, and other conditions are set to pulse No. 5. The result when it is the same as 1 is shown. As can be seen from this, when the first and second constrictions 12 and 14 are made larger, the magnetic resistivity is greatly lowered. In other words, it can be understood that the size of the first and second constrictions 12 and 14 needs to be 20 nm × 20 nm × 20 nm or less in order to obtain a large magnetic resistivity. It can be said that the smaller this is, the larger the magnetic resistivity can be obtained, but there is a limit from the manufacturing process.

(Example 2)
(Application to solid-state memory)
Next, an example of a solid state memory using the magnetoresistive effect element 10 shown in FIG. 1 will be described. FIG. 4 is a connection diagram showing an example in which the magnetoresistive effect element 10 shown in FIG. 1 is a memory element and a solid-state memory in the case of two columns and two columns is arranged as an example of an XY matrix arrangement. is there. In FIG. 4, the memory elements 300 ₁₁ , 300 ₁₂ , and 300 ₂₁ shown in FIG. 1 are crossed at bit lines 311 ₁ , 311 ₂ , read word lines 312 ₁ , 312 ₂ , and write word lines 313 ₁ , 313 ₂ . and _{300 22} are disposed. The bit lines 311 ₁ and 311 ₂ are each connected to the second magnetization fixed layer 15 of the memory element. A read word line 312 ₁ , 312 ₂ and a write word line 313 ₁ , 313 ₂ are provided for each of the memory elements, and are connected to the magnetization free layer 13 and the first magnetization fixed layer 11, respectively. Has been. Reference numeral 318 denotes a bit line decoder, and 319 ₁ denotes a decoder for the read word lines 312 ₁ and 312 ₂ . Reference numeral 319 ₂ denotes a decoder for the write word lines 313 ₁ and 313 ₂ . The decoder 318 selects one of the bit lines 311 ₁ and 311 _{2 in accordance with} the write or read addressing. The decoder 319 ₁ selects one of the word lines 312 ₁ and 312 ₂ corresponding to the read addressing. Decoder 319 ₂ corresponding to the address of the write, selects one of the word lines ₃₁₃ 1, 313 _2. Further, write data to the decoder 319 ₂ corresponding to the address of the write is also input.

The word line 312 ₁ and the word line 312 ₂ are selectively connected to the data line 314 by opening / closing the gates of the MOS-FET 316 ₁ and the MOS-FET 316 ₂ . The word line 313 ₁ and the word line 313 ₂ are selectively connected to the power supply lines 315 ₁ and 315 ₂ by opening / closing one of the gates of the MOS-FET 317 ₁₁ and the MOS-FET 317 ₁₂ , the MOS-FET 317 _21, and the MOS-FET 317 _22. Connected. The power supply lines 315 ₁ and 315 ₂ are positive and negative power supply lines for supplying the input pulse of FIG. Since the decoder 319 _{2 also} receives write data corresponding to the write addressing, depending on the data to be written to the magnetoresistive elements 300 ₁₁ , 300 ₁₂ , 300 ₂₁ and 300 ₂₂ , the power supply lines 315 ₁ and 315 ₂ Any one of the gates of the MOS-FET 317 ₁₁ , the MOS-FET 317 ₁₂ , the MOS-FET 317 _21, and the MOS-FET 317 ₂₂ is connected to a positive or negative power source, and a predetermined current is supplied.

For example, when writing data into the memory device _{300 11,} the bit line 311 _1, of 1ns at ¹⁰ 6 A / cm ² between the word line 313 ₁ is connected to one of the power lines 315 ₁ and 315 ₂ by supplying a current pulse width, moving the domain wall of the first transition region 12 or the first transition area 14 in the memory device 300 ₁₁ have the polarity of the supply current, or is held. That is, writing is performed by changing the magnetization direction of the magnetization free layer 13 in FIG. 1 as the domain wall moves. At this time, connect the word line 313 ₁ to one of the power lines 315 ₁ and 315 ₂ are selected by the data to be written. Meanwhile, reading, for example, the bit line 311 _1, by applying a voltage between the data lines 314 and selectively connected to the word line 312 _1, the magnetization fixed layer 11 in FIG. 1, the magnetization free layer 13 This is done by reading out the resistance depending on the relative direction of the magnetization of. The magnetoresistive effect element in FIG. 1 of the present invention has a magnetic resistivity of 250%, so that it is not necessary to perform cell selection with a MOS-FET during reading.

  FIG. 5 is a cross-sectional view schematically showing one memory element 110 in which the solid-state memory shown in FIG. 4 is mounted on a silicon substrate. On the silicon substrate 120, the first word line 111 (corresponding to the word line 313 in FIG. 4), the first magnetization fixed layer 11, the first transition region 12, the magnetization free layer 13, and the second word line. 117 (corresponding to the word line 312 in FIG. 4), the second transition region 14, the second magnetization fixed layer 15, and the bit line 116 (corresponding to the bit line 311 in FIG. 3) are commonly used in the semiconductor field. It is formed by lithography technology. The bit line 116 is formed parallel to the paper surface, and the first word line 111 and the second word line 117 are formed in a direction perpendicular to the paper surface. Other layers or regions are filled with an interlayer insulating film 118.

  FIG. 5 shows only one memory element, which is formed on the silicon substrate 120 in an XY matrix. In the example shown in the figure, Cu is used for the wiring material of the bit line and the word line, and Co is used for the ferromagnetic material. Since the bit line 116 and the first word line 111 are connected to the first and second magnetization fixed layers 11 and 15, respectively, the magnetization fixed layer may be used as it is. That is, the first and second magnetization fixed layers 11 and 15 do not need to be independent for each memory element. Further, when the first and second magnetization fixed layers 11 and 15 are made of Co, the specific resistance is not so large, so there is no problem in terms of electric circuit. By doing so, the lithography and magnetization fixation processes become easier.

(Example 3)
(Application to other types of solid-state memory devices)
FIG. 6 is a diagram showing a cross-sectional structure of the magnetoresistive element 20 of the present invention. A first transition region is provided by forming an insulator layer 26 having a thickness of 10 nm on a Co thin wire 21 having a thickness of 100 nmφ and a length of 100 nm serving as a magnetization fixed layer. Subsequently, a 10 nm thick magnetization free layer 23 is formed. Next, an insulator layer 27 having a thickness of 10 nm is formed to provide a second transition region. Further, a magnetization fixed layer is formed by Co thin wires 25 having a thickness of 100 nmφ and a length of 100 nm. The function of each part is the same as in FIG. At the time when the insulators 26 and 27 serving as the first and second transition regions are provided, Au nanometer-sized fine particles are placed on the Co thin wires 21 and 23. When forming the insulator layers 26 and 27 having a thickness of 10 nm, the fine particles form pinholes 28 and 29 in the insulator layer and function as transition regions. Here, the insulator layers 26 and 27 are preferably formed of, for example, Al ₂ O ₃ .

  In order to form pinholes, it is not possible to place Au nanometer-size fine particles on Co thin wires 21 and 23 one by one. For example, an appropriate number of Au nanometer-size fine particles can be loaded. It is practical to sprinkle, and as a result, the number of Au nanometer-sized fine particles on the Co thin wires 21 and 23 is a statistically distributed number. In FIG. 6, the number of cross sections is three and two. Of course, it may be more when viewed as a plane, and in some cases, there may be only one. FIG. 7 is a perspective view schematically showing a state where five pinholes 28 are formed in the insulator layer 26 as the first transition region in FIG. 6. A state in which two pinholes 28 are formed in addition to the three pinholes 28 in the cross-sectional position is shown.

Also in the magnetoresistive effect element 20, when an external electrode is installed, a direct current having a pulse width of 1 ns is supplied at a current density of 10 ⁶ A / cm ² and the polarity of the current is reversed at regular time intervals, 2 is obtained. The magnetoresistive effect element 20 of the present invention has a magnetoresistance of 300% according to the same calculation as described in FIG.

Example 4
(Further application to different types of solid-state memory devices)
8 and 9 are diagrams showing a planar structure of the magnetoresistive effect element 40 of the present invention and a corresponding schematic perspective view. In this embodiment, first and second magnetization fixed layers 41 and 45 are formed at both ends of a Co thin layer having a thickness of 10 nm, a magnetization free layer 43 is formed at the center, and a notch is provided between them. First and second transition regions 42 and 44 are provided. Furthermore, a tunnel magnetic junction 46 for reading the magnetization information of the magnetization free layer 43 is disposed at the center of the magnetization free layer 43. As can be seen from FIG. 8, the tunnel magnetic junction 46 includes an insulator tunnel barrier layer 47 and a magnetization fixed layer 48. The function of each part is the same as in FIG. 1, but in order for the tunnel magnetic junction 46 to function, the magnetization direction of the magnetization fixed layer 48 is the same as the magnetization direction of one of the magnetization fixed layers 41 and 45. There is a need to.

When the length of the magnetization free layer 43 in FIG. 8 is 10 nm, when a DC current having a pulse width of 1 ns is supplied at a current density of 10 ⁶ A / cm ² and the polarity of the current is reversed at regular time intervals, A signal output similar to that shown in FIG. 2 is obtained.

  Since the magnetoresistive effect element 40 has a planar structure and can share the magnetization fixed layer of adjacent memory elements, the magnetoresistive effect element 40 is advantageous in increasing the density in application to a solid-state memory.

(Example 5)
(Further application to different types of solid-state memory devices)
FIG. 10 is a diagram showing a cross-sectional structure of the magnetoresistive element 50 of the present invention. First, steps having a height of several atomic layers and a length of 10 nm are formed on the silicon substrate 120. By depositing Co thereon and planarizing the surface, the magnetization free layer 53 having a relatively thin Co thickness can be formed as a result. Steps on the silicon substrate 120 correspond to the magnetization free layer 53, and step edges on the silicon substrate become first and second transition regions 52 and 54. One magnetization of the magnetization fixed layers 51 and 55 is kept opposite to the other magnetization by an external magnetic field. Furthermore, a tunnel magnetic junction 46 (insulator tunnel barrier layer 47 and magnetization fixed layer 48) for reading the magnetization information of the magnetization free layer 53 is disposed. In this configuration, first and second transition regions 42 and 44 formed by cutting the magnetoresistive effect element 40 described with reference to FIGS. 7 and 8 are formed by step edges 52 and 54.

Also in the magnetoresistive effect element 50, when an external electrode is installed, a direct current with a pulse width of 1 ns is supplied at a current density of 10 ⁶ A / cm ² and the polarity of the current is reversed at regular time intervals, 2 is obtained. The magnetoresistive effect element 50 also has a planar structure similar to the magnetoresistive effect element 40, and can share the magnetization fixed layer of the adjacent memory element, so that it is advantageous for increasing the density when applied to a solid-state memory. It is.

(Example 6)
(Further application to different types of solid-state memory devices)
FIG. 11 is a diagram showing a cross-sectional structure of the magnetoresistive element 60 of the present invention. A Cu 62 film having a thickness of 10 nm is deposited on a Co wire 61 having a thickness of 50 nm and a thickness of 100 nm to form a transition region. The Co thin wire 61 is a magnetization fixed layer. Subsequently, a 50 nm-thick magnetization free layer 63 is formed. The magnetization direction of the magnetization free layer 63 is set opposite to the magnetization direction of the magnetization fixed layer 61 by an external magnetic field.

Electrodes are provided outside the magnetization fixed layer 61 and the magnetization free layer 63 in the magnetoresistive element 60. First, a measurement current is passed between the external electrodes in the direction from the magnetization fixed layer 61 to the magnetization free layer 63. The measurement current is a direct current with a current density of 10 ² A / cm ² . Next, a direct current having a pulse width of 1 ns is supplied between the external electrodes at a current density of 10 ⁶ A / cm ² , and the polarity of the current is inverted at intervals of 10 s. Then, an output signal similar to that in FIG. 2 is observed. Also in this example, when the current supplied between the external electrodes in the same measurement is simply a direct current, a current density of 10 ⁹ A / cm ² or more is required to observe the result equivalent to FIG. Need to supply.

  Since the magnetoresistive effect element 60 is a two-terminal element, it is advantageous for high integration and high density when applied to a solid-state memory.

(Example 7)
(Application to other types of solid-state memory)
Next, an example of a solid-state memory using the magnetoresistive effect element 60 shown in FIG. 11 will be described. FIG. 12 is a diagram showing a solid-state memory in the case of two vertical rows and two horizontal rows as an example in which the magnetoresistive effect elements 60 shown in FIG. 11 are arranged in an XY matrix. In FIG. 12, the magnetoresistive effect element 700 shown in FIG. 11 is arranged at the intersection of the bit line 711 _{1, the} bit line 711 ₂ , the word line 712 ₁ , and the word line 712 ₂ . Reference numeral 715 denotes a bit line decoder, and reference numeral 716 denotes a word line decoder. Decoders 715 and 716 select one of a bit line and a word line in response to addressing for writing or reading, and a current is supplied to magnetoresistive element 700. Note that the word line is selectively connected to the data line 713 by opening and closing the gate of the MOS-FET 714.

For example, by supplying a current with a pulse width of 1 ns at 10 ⁶ A / cm ² between the bit line 711 ₁ and the word line 712 ₁ selectively connected to the data line 713, the magnetization free in FIG. The magnetization direction of the layer is reversed or maintained. That is, writing is performed by changing the magnetization direction of the magnetization free layer in FIG. On the other hand, for reading, for example, a voltage is applied between the bit line 711 ₁ and the word line 712 ₁ selectively connected to the data line 713, whereby the magnetization fixed layer 61 and the magnetization free layer 63 in FIG. This is done by reading out the resistance depending on the relative direction of the magnetization of.

In the above-described embodiments, the length of the magnetization free layer of the magnetoresistive effect element 60 of FIG. 11 is 50 nm, except that the length of the magnetization free layer is 10 nm, and the width of the write pulse current is 1 ns. Although an example to ¹⁰ 6 a / cm ² and is, as a 1μm length of the magnetization free layer, even 100ns width of the write pulse current, the magnitude of the write pulse current ¹⁰ 6 a / possible to the cm ^2.

(Industrial applicability)
According to the present invention, it is possible to obtain a solid-state memory element that operates with a current that is three orders of magnitude smaller than that of a simple direct current drive, and also to simplify the lithography and magnetization fixing processes as a solid-state memory.

It is a conceptual diagram for demonstrating the magnetoresistive effect element 10 of this invention. It is a figure explaining the characteristic of the magnetoresistive effect element 10 shown in FIG. FIG. 2 is a diagram showing the relationship between the pulse width of the pulse current of the magnetoresistive effect element 10 shown in FIG. 1 and the length of the magnetization free layer 13. FIG. 2 is a connection diagram illustrating an example in which a solid-state memory in the case of two vertical columns and two horizontal columns is configured as an example in which the magnetoresistive effect element 10 illustrated in FIG. 1 is a memory element and arranged in an XY matrix. FIG. 5 is a cross-sectional view schematically showing an example in which the solid-state memory shown in FIG. 4 is mounted on a silicon substrate for one memory element 110. It is a figure which shows the cross-section of the magnetoresistive effect element 20 of this invention. It is a figure which shows typically a mode that five pinholes 28 are formed in the insulator layer 26 as a 1st transition area | region in FIG. 6 in the form of a perspective view. It is a figure which shows the typical planar structure of the magnetoresistive effect element 40 of this invention. It is a typical perspective view of the magnetoresistive effect element 40 of this invention. It is a figure which shows the cross-section of the magnetoresistive effect element 50 of this invention. It is a figure which shows the cross-section of the magnetoresistive effect element 60 of this invention. It is a figure which shows the solid-state memory in the case of 2 vertical rows and 2 horizontal rows as an example which arranged the magnetoresistive effect element 60 shown in FIG. 11 in XY matrix form.

Explanation of symbols

10, 20, 40, 50, 60 ... magnetoresistive effect element, 11, 21, 41, 51, 61 ... first magnetization fixed layer, 12, 26, 42, 52, 62 ... first transition region, 13, 23, 43, 53, 63 ... magnetization free layer, 14, 27, 44, 54 ... second transition region, 15, 25, 45, 55 ... second magnetization fixed layer, 16 ... DC power source for measurement, 17 ... Meter for measurement, 18 ... Pulse current source, 28, 29 ... Pinhole, 46 ... Tunnel magnetic junction, 47 ... Insulator tunnel barrier layer, 48 ... Magnetization fixed layer, 110, 300, 700 ... Memory element, 116, 311 ₁ , 311 ₂ , 711 _1, 711 _2, ..., Bit line, 117, 312 ₁ , 312 _2, read word line, 111, 313 ₁ , 313 _2, write word line, 314, data line, 3 15 ₁ , 315 ₂ ... power supply line, 316 ₁ , 316 ₂ , 317 ₁₁ , 317 ₁₂ , 317 ₂₁₁ , 317 ₂₂ ... MOS-FET, 318 ... bit line decoder, 319 ₁ ... read word line decoder, 319 ₂ ... Decoder for write word line, 118... Interlayer insulating film, 712 ₁ , 712 ₂ ... Word line, 713... Data line, 714.

Claims (12)

A magnetoresistive effect element having a first magnetization fixed layer / magnetization free layer / second magnetization fixed layer, wherein at least one of the magnetization fixed layer / magnetization free layer or the magnetization free layer / second magnetization fixed layer It has a mechanism for inducing domain wall generation in the transition region between the magnetization fixed layer and the magnetization free layer that becomes the boundary, and the magnetization direction of these magnetization fixed layers is set to be approximately antiparallel, and the transition between the magnetization fixed layer and the magnetization free layer In a structure in which a domain wall exists in one of the regions, by applying a current having a predetermined pulse width, the domain wall moves between the two transition regions with a current not exceeding the DC current density of 10 ⁶ A / cm ^2. Thus, the magnetoresistive effect element is characterized in that the magnetization of the magnetization free layer is reversed and the magnetoresistance associated with the change in the direction of relative magnetization is detected.   2. The magnetism according to claim 1, wherein the transition region has a smaller sectional area than other regions as a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer or the magnetization free layer / magnetization fixed layer. Resistance element.   3. The magnetoresistive element according to claim 2, wherein when the magnetization fixed layer / magnetization free layer is of the order of 100 × 100 × 100 nm, the transition region is of the order of 20 × 20 × 20 nm.   The transition region is configured as a structure of a magnetization fixed layer / magnetization free layer / magnetization fixed layer, and a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer or the magnetization free layer / magnetization fixed layer 2. The magnetoresistive effect element according to claim 1, wherein the magnetoresistive effect element is formed of an insulating material, and a pinhole connected to the magnetization fixed layer-magnetization free layer or the magnetization free layer-magnetization fixed layer is formed in the insulation material.   Tunnel magnetism in which the structure of the magnetization fixed layer / magnetization free layer / magnetization fixed layer is composed of a single flat ferromagnetic material, and an insulating tunnel barrier layer and a magnetization fixed layer are formed on the magnetization free layer. 2. The magnetism according to claim 1, wherein the magnet is provided with a junction and a notch is formed in the single flat ferromagnetic material as a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer. Resistive effect element.   As a mechanism for inducing domain wall generation in the transition region of the magnetization fixed layer / magnetization free layer or the magnetization free layer / magnetization fixed layer, the magnetization free layer is configured as a magnetization fixed layer / magnetization free layer / magnetization fixed layer structure. The magnetoresistive effect according to claim 1, wherein the thickness of the layer is smaller than the thickness of the magnetization fixed layer, and a tunnel magnetic junction comprising an insulator tunnel barrier layer and a magnetization fixed layer is provided on the magnetization free layer. element.   The magnetoresistive element according to claim 1, wherein the current having the predetermined pulse width is a current having a pulse width in a range of 0.3 ns to 1.6 ns. A magnetoresistive effect element having a first magnetization fixed layer / magnetization free layer / second magnetization fixed layer, in which the magnetization directions of these magnetization fixed layers are set substantially antiparallel, is arranged in a matrix as a memory element. A bit line is connected to the first magnetization fixed layer or the second magnetization fixed layer of each memory element, a word line is connected to the second magnetization fixed layer or the first magnetization fixed layer of each memory element, and A data line is selectively connected to the magnetization free layer of each memory element according to a write address or a read address, respectively, and a predetermined pulse width is set between the first magnetization fixed layer and the second magnetization fixed layer. by applying with polarity corresponding to the data to be stored the current, said by reversing the magnetization of the magnetization free layer in a current not exceeding the DC current density 10 6 ^{a /} cm ^2, the first magnetization pinned layer / Data is stored in each memory element by moving a domain wall between two transition regions between the magnetization free layer or the magnetization free layer / second magnetization fixed layer, and a data line of each memory element A magnetic recording apparatus for reading data magnetically stored between the first magnetization fixed layer and the second magnetization fixed layer of each memory element.   9. The magnetic recording apparatus according to claim 8, wherein the current having the predetermined pulse width is a current having a pulse width in a range of 0.3 ns to 1.6 ns.   In order to apply a current with a very short pulse width between the first magnetization fixed layer and the second magnetization fixed layer with a polarity corresponding to data to be stored, the second magnetization fixed layer or the first magnetization of each memory element 9. The magnetic recording apparatus according to claim 8, wherein the word line connected to the magnetization fixed layer is selectively connected to different power supply lines depending on data to be stored. A magnetoresistive effect element having a magnetization fixed layer / insulator layer / magnetization free layer is arranged in a matrix as a memory element, and a bit line is provided in the magnetization free layer of each memory element, and a magnetization fixed layer of each memory element is provided. A word line is connected, and a data line is selectively connected to each word line according to a write address or a read address, and a current having a predetermined pulse width is stored between the magnetization fixed layer and the magnetization free layer. By applying the polarity in accordance with the data to be obtained, the magnetization of the magnetization free layer is reversed with a current not exceeding a DC current density of 10 ⁶ A / cm ² , so that the transition region of the magnetization fixed layer / magnetization free layer A word line connected to a data line of each memory element by magnetically storing data in each memory element by moving a domain wall between them The magnetic recording apparatus, characterized in that for reading magnetic data stored between the bit lines of the magnetization free layer of each memory device.   12. The magnetic recording apparatus according to claim 11, wherein the current having the predetermined pulse width is a current having a pulse width in a range of 0.3 ns to 1.6 ns.

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