JP2018182106A - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic capacitor which can adequately increase the adhesion strength of an interface of an underlying layer of an external electrode and a plating layer, and a method for manufacturing the multilayer ceramic capacitor.SOLUTION: A multilayer ceramic capacitor comprises: a laminate chip having a substantially rectangular parallelepiped shape, arranged by alternately laminating dielectric layers including a ceramic as a primary component and internal electrode layers, and formed so that the internal electrode layers thus laminated are alternately exposed from two end faces; and external electrodes formed on the two end faces. The external electrodes each have a structure in which a plating layer is formed on an underlying layer. At least part of a surface of the underlying layer includes, in a region where a height from a bottom to a peak is 0.4 μm or more, a region where the average spacing between local tops is 0.5 μm or less.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a multilayer ceramic capacitor and a method of manufacturing the same.

  In the chip strength design of a multilayer ceramic capacitor, it is important to improve the strength of the body portion such as the bending strength. The element portion is a laminated chip in which a dielectric layer and an internal electrode layer are laminated. On the other hand, the recent market strongly demands to increase the deflection resistance after mounting on a substrate. In the conventional multilayer ceramic capacitor, when deflection stress is applied after mounting on a substrate, the relationship of (element strength) <(interfacial adhesion strength between the base layer of the external electrode and the plating layer) is obtained. In recent years in which multi-layering has been performed, there is a problem that (element strength)> (interfacial adhesion strength between the underlying layer of the external electrode and the plating layer). Therefore, it is desirable to increase the interface adhesion strength between the base layer of the external electrode and the plating layer. For example, Patent Document 1 discloses a technique for effectively increasing the bonding strength between a thick film conductive layer and a plated conductive layer.

Unexamined-Japanese-Patent No. 2006-128385

  However, in the technique of Patent Document 1, it is difficult to sufficiently increase the interface adhesion strength between the base layer of the external electrode and the plating layer.

  The present invention has been made in view of the above problems, and it is an object of the present invention to provide a laminated ceramic capacitor capable of sufficiently increasing the interfacial adhesion strength between the underlayer of the external electrode and the plating layer, and a method of manufacturing the same. .

  In the multilayer ceramic capacitor according to the present invention, dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, and a plurality of the laminated internal electrode layers are exposed at two oppositely facing end faces And an external electrode formed on the two end faces, wherein the external electrode has a structure in which a plating layer is formed on a base layer, and At least a part of the surface of the formation is characterized in that the average distance between local peaks is 0.5 μm or less in a region where the height from the bottom to the peak is 0.4 μm or more.

  In the multilayer ceramic capacitor, the thickness of the thinnest portion of the underlayer may be 1.0 μm or more.

  In the multilayer ceramic capacitor, the base layer may be mainly composed of Cu, and the plating layer may have a structure in which a Sn plating layer is provided on a Ni plating layer.

  In the above laminated ceramic capacitor, the number of laminated dielectric layers in the laminated chip may be 250 layers / mm or more.

  In the method of manufacturing a multilayer ceramic capacitor according to the present invention, dielectric layers and internal electrode layers are alternately stacked, and a plurality of the stacked internal electrode layers are formed so as to be exposed at two opposing end faces alternately. In a laminate having an undercoat layer mainly composed of metal on the two end faces of the laminated chip having a rectangular parallelepiped shape, the height from the bottom to the peak is 0.4 μm or more in at least part of the surface of the undercoat layer The base layer is subjected to a roughening treatment so that the average distance between local peaks is 0.5 μm or less, and a plating layer is formed on the base layer after the roughening treatment. .

  According to the present invention, the interface adhesion strength between the base layer of the external electrode and the plating layer can be sufficiently increased.

1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor according to an embodiment. It is the sectional view on the AA line of FIG. It is the BB sectional drawing of FIG. (A) is a cross-sectional view of an external electrode, (b) and (c) are partially enlarged views. It is the figure which expanded the cross section of the surface of the base layer. It is a figure for demonstrating the average space | interval S of a local summit. It is a figure which illustrates the flow of the manufacturing method of a multilayer ceramic capacitor. (A) is a roughness curve measured in Example 1, (b) is a roughness curve measured in Comparative Example 1. 6 is a roughness curve measured in Comparative Example 1;

  Hereinafter, embodiments will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a partial cross-sectional perspective view of the multilayer ceramic capacitor 100 according to the embodiment. FIG. 2 is a cross-sectional view taken along line AA of FIG. FIG. 3 is a cross-sectional view taken along line B-B of FIG. As illustrated in FIGS. 1 to 3, the laminated ceramic capacitor 100 includes the laminated chip 10 having a substantially rectangular parallelepiped shape, and the external electrodes 20 a and 20 b provided on any two opposing end faces of the laminated chip 10. . Of the four surfaces other than the two end surfaces of the laminated chip 10, the two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The external electrodes 20 a and 20 b have extension regions extending to the upper surface, the lower surface, and at least one of the two side surfaces in the stacking direction of the layered chip 10. In the present embodiment, as an example, the external electrodes 20 a and 20 b have extension regions on the upper surface, the lower surface, and the two side surfaces of the laminated chip 10. However, the external electrodes 20a and 20b are separated from each other.

  The laminated chip 10 has a configuration in which a dielectric layer 11 containing a ceramic material functioning as a dielectric and an internal electrode layer 12 containing a base metal material are alternately stacked. The edge of each internal electrode layer 12 is alternately exposed to the end face of the laminated chip 10 on which the external electrode 20a is provided and the end face on which the external electrode 20b is provided. Thus, the internal electrode layers 12 are alternately conducted to the external electrode 20a and the external electrode 20b. Further, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is disposed as the outermost layer in the stacking direction, and the upper surface and the lower surface of the laminate are covered by the cover layer 13. The cover layer 13 contains a ceramic material as a main component. For example, the material of the cover layer 13 is the same as the main component of the dielectric layer 11 and the ceramic material.

  The size of the multilayer ceramic capacitor 100 is, for example, 0.2 mm in length, 0.125 mm in width, 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, 0.2 mm in height, or length 0.6 mm, width 0.3 mm, height 0.3 mm, or length 1.0 mm, width 0.5 mm, height 0.5 mm, or length 3.2 mm, width 1.6 mm, height Although it is 1.6 mm, or 4.5 mm in length, 3.2 mm in width, 2.5 mm in height, it is not limited to these sizes.

The internal electrode layer 12 contains a base metal such as Ni (nickel), Cu (copper), Sn (tin) or the like as a main component. As the internal electrode layer 12, a noble metal such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold) or the like, or an alloy containing these may be used. The dielectric layer 11 contains, for example, a ceramic material having a perovskite structure represented by the general formula ABO ₃ as a main component. In addition, the said perovskite structure contains ABO _{3- (alpha)} which remove | deviated from the stoichiometric composition. For example, as the ceramic materials, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), Ba _1-x-y forming a perovskite structure It is possible to use Ca _x Sr _y Ti _1-z Zr _z O ₃ (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1) or the like.

  As exemplified in FIG. 2, the region where the internal electrode layer 12 connected to the external electrode 20 a and the internal electrode layer 12 connected to the external electrode 20 b are opposed is a region that generates electric capacitance in the multilayer ceramic capacitor 100. . Therefore, the region is referred to as a capacitance region 14. That is, the capacitance region 14 is a region where two adjacent internal electrode layers 12 connected to different external electrodes face each other.

  A region in which the internal electrode layers 12 connected to the external electrode 20 a face each other without interposing the internal electrode layer 12 connected to the external electrode 20 b is referred to as an end margin 15. An end margin 15 is also a region where the internal electrode layers 12 connected to the external electrode 20 b face each other without interposing the internal electrode layer 12 connected to the external electrode 20 a. That is, the end margin 15 is an area where the internal electrode layers 12 connected to the same external electrode face each other without interposing the internal electrode layers 12 connected to different external electrodes. The end margin 15 is an area where no capacity is generated.

  As illustrated in FIG. 3, in the laminated chip 10, a region from the two side surfaces of the laminated chip 10 to the internal electrode layer 12 is referred to as a side margin 16. That is, the side margin 16 is a region provided so as to cover the end portion of the plurality of internal electrode layers 12 stacked in the above-described stacked structure extending to the two side surfaces, and the dielectric layer 11 serves as the internal electrode layer 12. It is the area | region laminated | stacked without interposition.

  FIG. 4A is a cross-sectional view of the external electrode 20b, and is a partial cross-sectional view of line A-A of FIG. In FIG. 4A, hatches representing cross sections are omitted. As illustrated in FIG. 4A, the external electrode 20 b has a structure in which the plating layer 22 is formed on the underlayer 21. In the present embodiment, the foundation layer 21 and the plating layer 22 extend from both end surfaces of the laminated chip 10 to the upper surface, the lower surface, and the two side surfaces. Although the external electrode 20b is illustrated in FIG. 4A, the external electrode 20a also has a similar structure.

  The underlayer 21 contains a metal such as Cu or Ni as a main component. The underlayer 21 is provided for bonding the external electrodes 20 a and 20 b to the internal electrode layer 12. The underlayer 21 may contain a glass component for densifying the underlayer 21 and a co-material for controlling the sinterability of the underlayer 21. The underlayer 21 has, for example, a thickness of about 60 μm. The plating layer 22 is mainly composed of a metal such as Ni, Sn, or Cu, and has a structure in which an Sn plating layer with a thickness of about 10 μm is formed on a Ni plating layer with a thickness of about 2 μm, for example. In this case, the Ni plating layer is provided for the purpose of solder wicking prevention. The Sn plating layer is provided for securing solderability. When the plating layer 22 includes the Ni plating layer and the Sn plating layer, the multilayer ceramic capacitor 100 can be used as a surface mounting device.

  FIG.4 (b) is the elements on larger scale of Fig.4 (a). As illustrated in FIG. 4B, the base layer 21 is formed on the cover layer 13 and the plating layer 22 is formed on the base layer 21 on the upper and lower surfaces of the layered chip 10. As illustrated in FIG. 4C, in the side margin 16, the foundation layer 21 is formed on the side margin 16 (dielectric layer 11), and the plating layer 22 is formed on the foundation layer 21. In FIGS. 4 (b) and 4 (c), hatches are omitted as in FIG. 4 (a).

  FIG. 5 is an enlarged view of the cross section of the surface of the base layer 21. As shown in FIG. As illustrated in FIG. 5, the underlayer 21 has irregularities on the surface. As illustrated in FIG. 5, the surface of the base layer 21 also has unevenness between the local bottom and the local peak. Also, in the roughness curve of the surface of the base layer 21, the average spacing S of local crests is not more than 0.5 μm with respect to the region where the height A from the local bottom to the local peak is 0.4 μm or more. The area that has been included is included. In Category 1, the height A is 0.610 μm (≧ 0.4 μm), and the height S is 0.403 μm (≦ 0.5 μm). In Category 2, the height A is 0.551 μm (≧ 0.4 μm), and S is 0.498 μm (≦ 0.5 μm). In Category 3, the height A = 0.761 μm (≧ 0.4 μm), and S = 0.384 μm (≦ 0.5 μm).

  In addition, in order to give roughness to base layer 21, it is preferable that average interval S of local crests is 0.45 μm or less with respect to a region having height A of 0.6 μm or more, and height A is More preferably, the average spacing S between local peaks is 0.4 μm or less for a region of 0.7 μm or more.

  FIG. 6 is a diagram for explaining the average spacing S of local crests. The average spacing S of local peaks is defined by the JIS 1994 standard. Specifically, as illustrated in FIG. 6, the roughness curve is extracted by the reference length L in the direction of its average line, and the length of the corresponding average line between adjacent local crests in the extracted portion is the local crest. The arithmetic mean value of the spacings of the multiple local peaks can be defined as the average spacing S of the local peaks.

  According to the present embodiment, in the roughness curve of the surface of the base layer 21, the unevenness is large and the local crests are close to each other. In this case, the surface of the base layer 21 has sufficient roughness, and the surface area of the base layer 21 is sufficiently large. As a result, the contact area between the underlayer 21 and the plating layer 22 becomes sufficiently large. As a result, the anchor effect is increased, and the interface adhesion strength between the underlayer 21 and the plating layer 22 is sufficiently improved.

  The element strength such as the bending strength of the laminated chip 10 is increased according to the number of laminated layers of the dielectric layer 11 and the internal electrode layer 12, and (element strength) <(underlayer 21 and plated layer 22 The relationship of the interface adhesion strength of (1) is reversed to the relationship of (element strength)> (interface adhesion strength between the base layer 21 and the plating layer 22). In this case, in particular, an improvement in the interface adhesion strength between the underlayer 21 and the plating layer 22 is required. Therefore, the surface shape of the base layer 21 according to the present embodiment exerts an effect particularly when the number of laminated layers 10 is large. For example, it is preferable to apply the present embodiment when the number of stacked dielectric layers 11 is 250 / mm or more in the stacking direction of the stacked chip 10.

  When the plating layer 22 is composed of two or more plating layers (for example, Ni plating layer and Sn plating layer), the magnitude of the interfacial adhesion strength is determined by the interface between the laminated chip 10 and the base layer 21> the interface between the plating layers It becomes the relationship of> the interface of base layer 21 and plating layer 22. From this relationship, the interface between the base layer 21 and the plating layer 22 is considered to be in close contact mainly by the anchor effect. With respect to such a configuration, the surface shape of the base layer 21 according to the present embodiment exerts an effect particularly.

  When the underlayer 21 is thin, there is a possibility that liquid penetration or hydrogen absorption may occur during electrolytic plating of the plating layer 22. Therefore, the underlayer 21 is preferably formed thick. For example, the thinnest portion of the underlayer 21 preferably has a thickness of 1.0 μm or more. The thinnest portion of the base layer 21 tends to be the thinnest at a corner portion having a curvature and a rounded shape at each corner of the substantially rectangular parallelepiped laminated chip 10. Therefore, in the edge portion, the base layer 21 preferably has a thickness of 1 μm or more.

  Subsequently, a method of manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 7 is a diagram illustrating a flow of a method of manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, a powder of a ceramic material which is a main component of the dielectric layer 11 is prepared. A predetermined additive compound is added to the powder of the ceramic material according to the purpose. As the additive compounds, Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Dy (dysprosium), Tm (thulium), Ho (holmium), Tb (Thomium) Terbium), Yb (ytterbium), Sm (samarium), Eu (eurobium), oxides of Gd (gadolinium) and Er (erbium), and Co (cobalt), Ni, Li (lithium), B, Na (B) And sodium oxides, glasses of K (potassium) and Si. For example, first, a powder containing a ceramic material is mixed with a compound containing an additive compound to perform calcination. Subsequently, the particles of the ceramic material obtained are wet mixed with the additive compound, dried and ground to prepare a powder of the ceramic material.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol and toluene, and a plasticizer such as dioctyl phthalate (DOP) are added to the obtained powder of the ceramic material and wet mixed. Using the obtained slurry, for example, a strip-like dielectric green sheet having a thickness of, for example, 0.8 μm or less is coated and dried on a substrate by, for example, a die coater method or a doctor blade method.

  Next, the conductive paste for internal electrode formation is printed on the surface of the dielectric green sheet by screen printing, gravure printing or the like to arrange the pattern of the internal electrode layer 12. The conductive paste for internal electrode layer formation contains a powder of a main component metal of the internal electrode layer 12, a binder, a solvent, and, if necessary, other auxiliary agents. The binder and the solvent are preferably different from the above-mentioned ceramic slurry. In addition, a ceramic material which is a main component of the dielectric layer 11 may be dispersed in the conductive paste for internal electrode formation as a co-material.

  Next, the dielectric green sheet on which the internal electrode layer pattern is printed is punched to a predetermined size, and the punched dielectric green sheet is peeled off from the base material, and the internal electrode layer 12 and the dielectric layer 11 are removed. So that the internal electrode layers 12 are alternately exposed at the opposite end surfaces in the longitudinal direction of the dielectric layer 11 and are alternately drawn out to a pair of external electrodes of different polarities. A number (for example, 200 to 1500 layers) is stacked.

  Next, a cover sheet to be the cover layer 13 is crimped to the upper and lower sides of the obtained laminate, and cut into a predetermined chip size (for example, 3.2 mm × 2.5 mm). Thereby, a substantially rectangular parallelepiped ceramic laminate is obtained.

(Firing process)
Thus, after removing the binder in the N ₂ atmosphere at 250 to 500 ° C., the ceramic laminate is fired at 1100 ° C. to 1300 ° C. for 10 minutes to 24 hours in a reducing atmosphere to obtain a dielectric green. Each compound which comprises a sheet sinters. Thus, the laminated chip 10 in which the cover layer 13 is formed as the outermost layer is obtained by alternately laminating the dielectric layers 11 made of a sintered body and the internal electrode layers 12 inside.

(Annealing process, reoxidation process)
Thereafter, annealing may be performed for 4 to 24 hours in a reducing atmosphere at 1000 ° C. to 1300 ° C. Further, re-oxidation may be performed at 600 ° C. to 1000 ° C. in an N ₂ gas atmosphere.

(Bonding process of base layer 21)
Next, the conductive paste for base layer formation is applied from the two end surfaces to the upper surface, the lower surface, and part of the two side surfaces of the obtained laminated chip 10. The conductive paste for base layer formation contains powder of a main component metal of the base layer 21, a binder, a solvent, a glass fillet, and the like. As the binder and the solvent, those similar to the above-mentioned ceramic paste can be used. In addition, the conductive paste for base layer formation can be thickly applied by applying the conductive paste for base layer formation several times.

Thereafter, the conductive paste for base layer formation is baked, for example, in an N ₂ atmosphere at 800 ° C. A laminated body in which the base layer 21 is formed on the two end faces of the laminated chip 10 is obtained. After that, a roughening process is performed by etching the underlayer 21 by a necessary amount using a soft etching agent (for example, containing potassium persulfate, potassium hydrogen sulfate or the like as a main component). In this case, the surface of the base layer 21 has unevenness even between the local bottom and the local peak, and the height A from the local bottom to the local peak is 0.4 μm or more. A roughening process is performed on the area so that the average spacing S of local crests is equal to or less than 0.5 μm. For example, it is preferable to perform the roughening treatment so that the reduction rate of the thickness of the base layer 21 is 5% or more and 50% or less. For example, the surface roughness of the base layer 21 can be adjusted by adjusting the etching time.

(Plating process)
Thereafter, in order to prevent solder corrosion and enable mounting of the laminated ceramic capacitor 100, the plating layer 22 is formed by plating. By the above steps, the multilayer ceramic capacitor 100 is completed.

  According to the method for manufacturing a laminated ceramic capacitor in accordance with the present embodiment, as the surface roughness of the surface of the base layer 21 is roughened by the roughening treatment, the local crests become closer together as well as the unevenness increases. In this case, the surface of the base layer 21 has sufficient roughness, and the surface area of the base layer 21 is sufficiently large. As a result, the contact area between the underlayer 21 and the plating layer 22 becomes sufficiently large. As a result, the anchor effect is increased, and the interface adhesion strength between the underlayer 21 and the plating layer 22 is sufficiently improved. Note that even if an oxide film is formed on the surface of the base layer 21 in the baking step, the oxide film is removed during the roughening treatment. Therefore, the metal bondability between the underlayer 21 and the plating layer 22 is also improved.

  When the underlayer 21 is thin, there is a possibility that liquid penetration or hydrogen absorption may occur during electrolytic plating of the plating layer 22. Therefore, the thickness of the thinnest portion of the underlayer 21 is preferably 1.0 μm or more. In the edge portion of the laminated chip 10, the base layer 21 tends to be formed thin. Therefore, it is preferable to form the underlayer 21 thick in the edge portion. Specifically, it is preferable to form the base layer 21 so as to have a thickness of 1 μm or more in the edge portion after the roughening treatment.

  In the above embodiment, after the laminated chip 10 is obtained, the base layer forming conductive paste is applied to both end surfaces of the laminated chip 10 and baked. However, the present invention is not limited thereto. For example, after obtaining a ceramic laminate having a substantially rectangular parallelepiped shape in the laminating step, the conductive paste for forming an underlayer is applied to both end faces of the ceramic laminate, and in the firing step, the ceramic laminate and the conductive paste for forming an underlayer are simultaneously applied. You may bake.

  The multilayer ceramic capacitor according to the embodiment was produced and examined for characteristics.

(Examples 1-2)
Necessary additives were added to the barium titanate powder, and sufficiently wet-mixed and ground in a ball mill to obtain a dielectric material. PVB (polyvinyl butyral) as an organic binder was added to the dielectric material, and toluene, ethanol and the like were added as a solvent, and a dielectric green sheet was produced by the doctor blade method. Next, a conductive material for forming an internal electrode, which contains a powder of the main component metal (Ni) of the internal electrode layer 12, a binder (ethyl cellulose), a solvent (toluene, ethanol etc.) and, if necessary, other auxiliary agents. A paste was made. The conductive paste for internal electrode formation was screen-printed on the dielectric sheet. Over 1000 sheets on which the conductive paste for forming an internal electrode was printed were stacked, and a cover sheet of the same main component as the dielectric green sheet was laminated on the top and the bottom, respectively. Thereafter, a ceramic laminate was obtained by thermocompression bonding and cut into a predetermined shape. The obtained ceramic laminate was debindered in an N ₂ atmosphere and then fired to obtain a sintered body. Thereafter, the sintered body was subjected to an annealing treatment and then to a reoxidation treatment. Thereby, a laminated chip 10 was obtained. The thickness of the dielectric layer 11 after the reoxidation treatment was 1.5 μm. The thickness of the internal electrode layer 12 was 1.0 μm.

Next, a conductive paste for forming a base layer containing a glass fillet and containing Cu as a main component metal is applied multiple times from both end faces of the laminated chip 10 to the upper surface, lower surface and part of two side surfaces, N ₂ atmosphere at 800 ° C. The underlying layer 21 was formed by baking. Thereafter, the base layer 21 was roughened using a soft etching agent (main component is potassium persulfate or potassium hydrogen sulfate). The treatment time of Example 1 was 5 minutes, the treatment time of Example 2 was 10 minutes, and after roughening treatment, the base layer 21 was subjected to ultrasonic cleaning. Thereafter, the surface roughness of the base layer 21 was measured using a violet laser VK9710 microscope manufactured by Keyence Corporation. Thereafter, the base layer 21 was covered with the plating layer 22 by performing plating treatment of Ni and Sn. Thereby, a multilayer ceramic capacitor 100 was produced. Ten samples were prepared for each of Examples 1-2.

(Comparative Examples 1 and 2)
In Comparative Examples 1 and 2, the laminated ceramic capacitor 100 was produced under the same conditions as in Examples 1 and 2. However, in Comparative Examples 1 and 2, roughening treatment and ultrasonic cleaning were not performed. Ten samples were prepared for each of Comparative Examples 1 and 2. The surface roughness of the base layer 21 was measured using a violet laser VK9710 microscope manufactured by Keyence Corporation, and then the base layer 21 was covered with the plating layer 22 by performing a plating process of Ni and Sn.

(Analysis 1)
FIG. 8 (a) is a roughness curve measured in Example 1. FIG. FIG. 8 (b) is a roughness curve measured in Comparative Example 1. As shown in FIGS. 8A and 8B, it can be seen that the surface of the base layer 21 is roughened by performing the roughening treatment. In Examples 1 and 2, in the roughness curve of the underlayer 21, the average spacing S of the local crests relative to the region where the height A from the local bottom to the local peak is 0.4 μm or more. An area of 5 μm or less was included. In Comparative Examples 1 and 2, in the roughness curve of the underlayer 21, the average spacing S of the local crests relative to the region where the height A from the local bottom to the local peak is 0.4 μm or more. The region of 5 μm or less was not included. For example, as shown in FIG. 9, with respect to the result of FIG. 8B, in the segment 1, the height A = 1.127 μm (≧ 0.4 μm) whereas the S = 1.081 > 0.5 μm). In Category 2, while the height A is 0.700 μm (0.40.4 μm), S = 1.794 μm (> 0.5 μm). In Category 3, while the height A = 1.027 μm (≧ 0.4 μm), S = 0.683 μm (> 0.5 μm).

A deflection test was performed on Examples 1-2 and Comparative Examples 1-2. Specifically, after each prepared sample is mounted on a dedicated substrate 100 mm in length, 40 mm in width, and 1.6 mm in thickness, the center of the substrate is set to 0 mm as a fulcrum, and ± 45 mm points are set as power points. Bending. In this case, it was examined whether interface peeling occurred between the underlayer 21 and the plating layer 22. Table 1 shows the results. In Table 1, “o” indicates the average spacing S of local crests in a region where the height A from the local bottom to the local peak is 0.4 μm or more in the roughness curve of the underlayer 21. It indicates that a region of 0.5 μm or less is included. In the roughness curve of the underlayer 21, “×” is the average spacing S of local crests S = 0.5 μm or less with respect to a region where the height A from the local bottom to the local peak is 0.4 μm or more Indicates that the area is not included. As shown in Table 1, in Examples 1 and 2, interfacial peeling did not occur between the underlayer 21 and the plating layer 22. On the other hand, in Comparative Examples 1 and 2, interfacial peeling occurred between the underlayer 21 and the plating layer 22. This is considered to be because the surface roughness of the underlayer 21 is not sufficient in Comparative Examples 1 and 2 and the surface roughness of the underlayer 21 is sufficient in Examples 1 and 2.

(Example 3 to Example 7)
Multilayer ceramic capacitors according to Examples 3 to 7 were produced under the same conditions as in Examples 1 and 2. However, the thickness of the thinnest portion of the underlayer 21 was made different by changing the number of times of application of the conductive paste for forming the underlayer. The number of samples was set to 500 for each of Example 3 to Example 7. The thinnest part appeared at the edge. A high temperature and humidity resistance test was conducted on these Examples 3 to 7. Specifically, the initial insulation resistance R0 of each sample was measured. Next, the substrate was held at an ambient temperature of 85 ° C., a relative humidity of 85% RH, and a 10 V / μm application for 100 hours. Thereafter, the insulation resistance Rt of each sample was measured. A sample satisfying Rt ≦ 0.1 × R0 was defined as a defective product. Table 2 shows the failure rate. As shown in Table 2, it was confirmed that when the thickness of the thinnest part was less than 1.0 μm, the reliability was reduced. From this result, it was found that the thickness of the thinnest portion of the underlayer 21 is preferably 1.0 μm or more.

(Reference Examples 1 to 7)
Multilayer ceramic capacitors according to reference examples 1 to 7 were produced under the same conditions as in comparative examples 1 and 2. However, the size specification was 3.2 mm in length, 2.5 mm in height, and 2.5 mm in width, and the actual thickness (height) was 2.8 mm. By changing the number of stacked dielectric layers, the number of layers per 1 mm was made different. The above-described deflection test was performed on each of the reference examples 1 to 7 to find out where the failure occurred. The results are shown in Table 3. In Table 3, "layer thickness" indicates the thickness of each dielectric layer. As shown in Table 3, in the reference examples 1 to 5, failure (interface peeling) occurred between the underlayer 21 and the plating layer 22, while in the reference examples 6 to 7, failure (cracks) in the element body There has occurred. This corresponds to the relation of (element strength) <(interfacial adhesion strength between the base layer and the plating layer) <(element strength)> (interface adhesion strength between the base layer and the plating layer) according to the number of layers. It is considered to be because it was reversed. The reversed number of laminations was 250 layers / mm. From this result, it was found that it is preferable to make the surface shape of the base layer 21 as in the above embodiment, when the number of laminated dielectric layers is 250 layers / mm or more.

  As mentioned above, although the embodiment of the present invention has been described in detail, the present invention is not limited to the specific embodiment, and various modifications may be made within the scope of the present invention described in the claims. Changes are possible.

DESCRIPTION OF SYMBOLS 10 laminated chip 11 dielectric material layer 12 internal electrode layer 13 cover layer 14 capacity area 15 end margin 16 side margin 20a, 20b external electrode 21 base layer 22 plating layer 100 laminated ceramic capacitor

Claims (5)

A dielectric layer mainly composed of ceramic and an internal electrode layer are alternately laminated, and a plurality of laminated internal electrode layers are formed so as to be exposed at two opposing end faces alternately and have a substantially rectangular parallelepiped shape Having a laminated chip,
And an external electrode formed on the two end faces,
The external electrode has a structure in which a plating layer is formed on an underlayer,
At least a part of the surface of the underlayer includes a region in which the average distance between local peaks is 0.5 μm or less in a region where the height from the bottom to the peak is 0.4 μm or more Capacitor.   The thickness of the thinnest part of the said foundation layer is 1.0 micrometer or more, The laminated ceramic capacitor of Claim 1 characterized by the above-mentioned. The underlayer mainly contains Cu,
The multilayer ceramic capacitor according to claim 1, wherein the plating layer has a structure in which a Sn plating layer is provided on a Ni plating layer.   The laminated ceramic capacitor according to any one of claims 1 to 3, wherein the number of laminated dielectric layers in the laminated chip is 250 layers / mm or more. A dielectric layer and an internal electrode layer are alternately laminated, and a plurality of the laminated internal electrode layers are formed so as to be exposed at two opposing end faces alternately, and metal is used at the two end faces of the laminated chip having a substantially rectangular parallelepiped shape And the average distance between local peaks is 0.5 μm in a region where the height from the bottom to the peak is 0.4 μm or more on at least a part of the surface of the underlayer, in a laminate having the underlayer mainly composed of Roughening the underlying layer so that
A method for producing a laminated ceramic capacitor, comprising forming a plating layer on the underlayer after roughening treatment.

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