JP2018182080A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art for forming a low lifetime layer to enable inhibition of positional deviation between the low lifetime layer and a semiconductor region.SOLUTION: A semiconductor device manufacturing method comprises: a first implantation process of implanting an n-type or p-type impurity into a first range of a surface of a semiconductor substrate; a second implantation process of implanting an n-type or p-type impurity into a second range which is part of the first range so as to make an implantation depth of the impurity be shallower than that in the first implantation process, at a higher concentration than that in the first implantation process to form crystal fault in a region at the bottom of the impurity implantation region; a first heating process of irradiating the first range with laser beams after performing the first implantation process and the second implantation process to heat the impurity implantation depth in the first implantation process; and a second heating process of irradiating the second range with laser beams after performing the first heating process to heat the impurity implantation depth in the second implantation process.SELECTED DRAWING: Figure 4

Description

  The technology disclosed herein relates to a method of manufacturing a semiconductor device.

  Patent Document 1 discloses a technique of forming a low lifetime layer inside a semiconductor substrate by irradiating a helium beam. By forming the low lifetime layer, the characteristics of the semiconductor device may be able to be improved.

JP, 2008-192737, A

  In the method of irradiating a helium wire as in Patent Document 1, the control of the irradiation position is difficult, and the accuracy of the formation position of the low lifetime layer is low. Therefore, the position where the low lifetime layer is formed may be shifted with respect to the p-type or n-type semiconductor region. The present specification proposes a technique for forming a low lifetime layer, which is capable of suppressing positional deviation between the low lifetime layer and the semiconductor region.

  The present specification proposes a method of manufacturing a semiconductor device. This manufacturing method has a first injection step, a second injection step, a first heating step, and a second heating step. In the first implantation step, an n-type or p-type impurity is implanted into a first range of the surface of the semiconductor substrate. In the second implantation step, in a second range which is a part of the first range, the concentration of the impurity implanted is higher than that in the first implantation step so that the implantation depth of the impurity becomes shallower than the first implantation step. By implanting a type or p-type impurity, a crystal defect is formed in a region under the impurity implantation region in the first implantation step under the impurity implantation region in the second implantation step. In the first heating step, after the first implantation step and the second implantation step are performed, the first range is irradiated with a laser to heat the implantation depth of the impurity in the first implantation step. In the second heating step, after the execution of the first heating step, a laser is irradiated to the second range to heat the implantation depth of the impurity in the second implantation step.

  Either of the first injection step and the second injection step may be performed first. Further, the impurity implanted in the first implantation step and the impurity implanted in the second implantation step may have the same conductivity type or may have different conductivity types.

  In the first implantation step, the impurity is implanted into the first range. Here, impurities are implanted at relatively deep positions. Hereinafter, the impurity implantation region in the first implantation step is referred to as a first implantation region. In the second implantation step, the impurity is implanted into a second range which is a part of the first range. Hereinafter, the impurity implantation region in the second implantation step is referred to as a second implantation region. In the second implantation step, the impurity is implanted at a position shallower than the first implantation step. In the second implantation step, the impurity is implanted at a higher concentration than in the first implantation step. For this reason, crystal defects are formed in the second implantation region at a higher concentration than in the first implantation region. In addition, since the impurity is implanted at a high concentration into the second implantation region, crystal defects are also formed in the lower (deep side) region of the second implantation region. At this time, the crystal defects are distributed to the region under the first implantation region below the second implantation region.

  Next, in the first heating step, the implantation depth of the impurity in the first implantation step (that is, the depth of the first implantation region) is heated by laser irradiation to the first range. By heating the first implantation region, the impurities in the first implantation region are activated, and the crystal defects in the first implantation region disappear. Thus, a semiconductor region having n-type or p-type characteristics (hereinafter referred to as a first semiconductor region) is formed in the first implantation region. At this time, since the laser is disturbed in the second implantation region in which crystal defects are formed at a high concentration, the first semiconductor region under the second implantation region is not easily heated. As a result, the heating temperature of the first semiconductor region under the second implantation region is lowered. Therefore, many crystal defects remain in the lower part of the first semiconductor region. That is, the number of crystal defects remaining in the lower portion of the first semiconductor region below the second implantation region increases. The region in which many crystal defects remain is a low lifetime layer. Thereafter, the impurity implantation depth in the second implantation step (that is, the depth of the second implantation region) in the second implantation step is heated in the second heating step, thereby activating the impurities in the second implantation region, and Crystal defects in the implantation region disappear. As a result, a semiconductor region having n-type or p-type characteristics (hereinafter referred to as a second semiconductor region) is formed in the second implantation region. Therefore, a structure in which the low lifetime layer is disposed in the lower portion of the second semiconductor region (more specifically, the lower portion of the first semiconductor region in the lower portion of the second semiconductor region) is obtained. According to this manufacturing method, the low lifetime layer can be accurately provided under the second semiconductor region.

FIG. 2 is a cross-sectional view of the semiconductor device 10; 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. 13 is an explanatory view of the manufacturing method of the semiconductor device 10; FIG. Sectional drawing of the semiconductor device of a modification. Sectional drawing of the semiconductor device of a modification.

  In the manufacturing method of the embodiment, the semiconductor device 10 shown in FIG. 1 is manufactured. The semiconductor device 10 is a semiconductor device in which an IGBT (insulated gate bipolar transistor) and a diode are provided on a single semiconductor substrate 12. Hereinafter, in the semiconductor substrate 12, a region in which the IGBT is provided is referred to as an IGBT region 20, and a region in which a diode is provided is referred to as a diode region 40. The semiconductor substrate 12 is a substrate made of silicon. The semiconductor device 10 further includes an upper electrode 14 and a lower electrode 16. The upper electrode 14 is disposed on the upper surface 12 a of the semiconductor substrate 12. The upper electrode 14 doubles as the emitter electrode of the IGBT and the anode electrode of the diode. The upper electrode 14 is an electrode in which Al (or AlSi), Ti, Ni and Au are sequentially stacked on the upper surface 12 a, and has a thickness of about 3 to 30 μm. The lower electrode 16 is disposed on the lower surface 12 b of the semiconductor substrate 12. The lower electrode 16 doubles as the collector electrode of the IGBT and the cathode electrode of the diode. The lower electrode 16 is an electrode in which Al (or AlSi), Ti, Ni, and Au are sequentially stacked on the lower surface 12 b, or an electrode in which Ti, Ni, and Au are sequentially stacked on the lower surface 12 b. The lower electrode 16 has a thickness of about 1 to 30 μm.

  A plurality of trenches are provided on the upper surface 12 a of the semiconductor substrate 12. The depth of each trench is about 4 to 7 μm. The inner surface of each trench is covered by a gate insulating film 38. A gate electrode 34 is disposed inside a trench provided in the IGBT region 20. A control electrode 36 is disposed inside a trench provided in the diode region 40. Each gate electrode 34 and each control electrode 36 are insulated from the semiconductor substrate 12 by the gate insulating film 38. An upper surface of each gate electrode 34 and each control electrode 36 is covered with an interlayer insulating film 18. The potential of the gate electrode 34 can be controlled independently of the potential of the control electrode 36. The control electrode 36 is connected to the upper electrode 14 at a position not shown.

  Emitter region 22, body region 24, drift region 26 and collector region 30 are arranged in semiconductor substrate 12 in IGBT region 20.

Emitter region 22 is an n-type region and is ohmically connected to upper electrode 14. Emitter region 22 is in contact with gate insulating film 38. Emitter region 22 contains arsenic or phosphorus as an impurity. The peak p-type impurity concentration of the emitter region 22 is about 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ . The thickness of the emitter region 22 is about 0.2 to 1.5 μm.

Body region 24 is a p-type region. Body region 24 contains boron as an impurity. Body region 24 has a body contact region 24a and a low concentration body region 24b. Body contact region 24 a is ohmically connected to upper electrode 14. The low concentration body region 24 b has a lower p-type impurity concentration than the body contact region 24 a. The low concentration body region 24b is disposed below the emitter region 22 and the body contact region 24a. The low concentration body region 24 b is in contact with the gate insulating film 38 below the emitter region 22. The peak p-type impurity concentration of the low concentration body region 24 b is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ³ . The thickness of the low concentration body region 24 b is about 0.2 to 5 μm.

  Drift region 26 is an n-type region and is disposed below body region 24. Drift region 26 is in contact with gate insulating film 38 below body region 24. Drift region 26 contains phosphorus as an n-type impurity. The resistivity of the drift region 26 is 40 to 100 Ωcm. The thickness of the drift region 26 is about 80 to 165 μm.

The collector region 30 is a p-type region and is disposed below the drift region 26. The collector region 30 is ohmically connected to the lower electrode 16. Collector region 30 contains boron as a p-type impurity. The peak p-type impurity concentration of the collector region 30 is approximately 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ³ . The thickness of the collector region 30 is about 0.2 to 3 μm.

An n-type buffer layer having an n-type impurity concentration higher than that of drift region 26 may be provided between collector region 30 and drift region 26. The buffer layer can contain phosphorus as an n-type impurity. The peak n-type impurity concentration of the buffer layer can be about 1 × 10 ¹⁵ to 1 × 10 ¹⁸ / cm ³ . The thickness of the buffer layer can be about 0.2 to 5 μm.

  An anode contact region 42, a high concentration n-type region 44, a low concentration p-type region 46, a drift region 48, and a cathode region 50 are disposed in the semiconductor substrate 12 in the diode region 40.

  The anode contact region 42 is a p-type region and is exposed to the upper surface 12 a of the semiconductor substrate 12. The anode contact region 42 has a high p-type impurity concentration. The anode contact region 42 is ohmically connected to the upper electrode 14. The anode contact region 42 contains boron as a p-type impurity.

  The high concentration n-type region 44 is exposed on the upper surface 12 a of the semiconductor substrate 12. The high concentration n-type region 44 has a high n-type impurity concentration. The high concentration n-type region 44 is ohmically connected to the upper electrode 14. The high concentration n-type region 44 contains phosphorus or arsenic as an n-type impurity.

The low concentration p-type region 46 has a p-type impurity concentration lower than that of the anode contact region 42. The low concentration p-type region 46 is disposed below the anode contact region 42 and the high concentration n-type region 44. The low concentration p-type region 46 contains boron as an impurity. The peak p-type impurity concentration of the low concentration p-type region 46 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁹ / cm ³ . The thickness of the low concentration p-type region 46 is about 0.2 to 5 μm.

  The drift region 48 is an n-type region and is disposed below the low concentration p-type region 46. The n-type impurity concentration of drift region 48 is lower than the n-type impurity concentration of high concentration n-type region 44. Drift region 48 is connected to drift region 26 in IGBT region 20. Drift region 48 contains phosphorus as an n-type impurity. The resistivity of the drift region 48 is 40 to 100 Ωcm. The thickness of the drift region 48 is about 80 to 165 μm.

The cathode region 50 is an n-type region and is disposed below the drift region 48. The n-type impurity concentration of cathode region 50 is higher than the n-type impurity concentration of drift region 26. The cathode region 50 is ohmically connected to the lower electrode 16. The cathode region 50 contains phosphorus as an impurity. The peak n-type impurity concentration of the cathode region 50 is about 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ . The thickness of the cathode region 50 is about 0.2 to 3 μm.

In the drift region 48, a low lifetime layer 52 having a high crystal defect density is provided. The low lifetime layer 52 is disposed in a range adjacent to the low concentration p-type region 46 (that is, the upper end of the drift region 48). The low lifetime layer 52 is disposed below the high concentration n-type region 44 and not disposed below the anode contact region 42. In the low lifetime layer 52, crystal defects are distributed at a high density as compared with the outside. Crystal defects function as carrier recombination centers. Therefore, in the low lifetime layer 52, the lifetime of the carrier is shorter than that of the outside. The resistivity of the low lifetime layer 52 is about 40 to 80 Ω / cm ² .

  The pn junction at the interface between the low concentration p-type region 46 and the drift region 48 constitutes a pn diode. When the potential of the upper electrode 14 becomes higher than the potential of the lower electrode 16, a current flows from the upper electrode 14 to the lower electrode 16 through the anode contact region 42, the low concentration p-type region 46, the drift region 48 and the cathode region 50. . If the low lifetime layer 52 is not provided below the anode contact region 42 as shown in FIG. 1, the loss caused when the current flowing through the diode is low will be low. When the current flowing to the diode is high, the low lifetime layer 52 suppresses the inflow of holes from the low concentration p-type region 46 to the drift region 48. Therefore, when the voltage applied to the diode is switched from the forward voltage to the reverse voltage, recovery current does not easily flow in the diode.

  Next, a method of manufacturing the semiconductor device 10 will be described. The manufacturing method of the present embodiment is characterized in the manufacturing process of the diode region 40. Therefore, the description of the manufacturing process of IGBT region 20 is omitted.

  As shown in FIG. 2, a semiconductor substrate (semiconductor substrate 12 before processing) in which the entire inside of the diode region 40 is constituted by the drift region 48 is prepared. First, as shown in FIG. 3, boron, which is a p-type impurity, is ion implanted into the upper surface 12 a of the semiconductor substrate 12 (first implantation step). Thus, the first implantation region 46a in which the p-type impurity concentration is increased is formed. Although not shown, in this case, a mask is formed on the upper surface 12a with an opening in the range where the low concentration p-type region 46 is to be formed and the other range, and the upper surface of the semiconductor substrate 12 is formed through the mask. P-type impurities are implanted into 12a. Here, ion implantation is performed by adjusting the implantation energy so that the implanted p-type impurity stops in the depth range where the low concentration p-type region 46 is to be formed. Thus, the first injection region 46a is formed. In the first implantation step, crystal defects are formed in the semiconductor substrate 12. However, since the concentration of the p-type impurity implanted in the first implantation step is low, crystal defects formed in the semiconductor substrate 12 are small. Therefore, in FIG. 3, illustration of the crystal defect formed in the first implantation step is omitted. The p-type impurity implanted into the first implantation region 46a is not activated at this stage. Therefore, the first implantation region 46a does not exhibit the characteristics of the p-type semiconductor at this stage.

  Next, as shown in FIG. 4, a mask 60 is formed on the upper surface 12 a of the semiconductor substrate 12 by photolithography. The mask 60 has a plurality of openings. Each opening is disposed in the upper surface 12 a in a range where the high concentration n-type region 44 is to be formed. The other area of the top surface 12 a is covered by the mask 60. Next, an n-type impurity is implanted into the upper surface 12 a of the semiconductor substrate 12 through the mask 60 (second implantation step). Thus, the second implantation region 44a in which the n-type impurity concentration is increased is formed. As shown in FIGS. 3 and 4, the range in which the n-type impurity is implanted in the second implantation step is a part of the range in which the p-type impurity is implanted in the first implantation step. In the second implantation step, phosphorus or arsenic is implanted as an n-type impurity. In the second implantation step, the n-type impurity is implanted at a higher concentration than in the first implantation step. In the second implantation step, the n-type impurity is implanted at a depth shallower than the depth at which the p-type impurity is implanted in the first implantation step. Therefore, the second implantation region 44a in which the n-type impurity concentration is increased is formed in part of the region above the first implantation region 46a (on the upper surface 12a side). As shown in FIG. 4, crystal defects 52 a are formed in the semiconductor substrate 12 in the second implantation step. In the second implantation step, since the n-type impurity is implanted at a high concentration, crystal defects 52a are formed at a high density. In particular, in the second implantation step, phosphorus or arsenic having a larger atomic weight than the p-type impurity (i.e., boron) implanted in the first implantation step is implanted as the n-type impurity. Therefore, in the second implantation step, crystal defects are easily formed in the semiconductor substrate 12. Therefore, crystal defects 52a are formed at a high density. The crystal defect 52a is likely to extend along the ion implantation direction from the upper surface 12a. Therefore, crystal defects 52a are distributed in the inside of the second implantation region 44a and in the region under the second implantation region 44a. That is, the crystal defects 52a are distributed over the range from the second implantation region 44a to the upper end of the drift region 48 through the first implantation region 46a. In addition, almost no crystal defects 52a are formed in the semiconductor layer in the range where the n-type impurity is not implanted (the range covered with the mask 60). After the n-type impurity implantation, the mask 60 is removed.

  Next, as shown in FIG. 5, a mask 62 is formed on the upper surface 12a of the semiconductor substrate 12 by photolithography. The mask 62 has a plurality of openings. Each opening is disposed in the upper surface 12 a in the range where the anode contact region 42 is to be formed. Next, p-type impurities (boron) are implanted into the upper surface 12 a of the semiconductor substrate 12 through the mask 62 (third implantation step). Thus, the third implantation region 42a in which the p-type impurity concentration is increased is formed. In the third implantation step, the p-type impurity is implanted at a higher concentration than in the first implantation step. The concentration of the p-type impurity implanted in the third implantation step is lower than the concentration of the n-type impurity implanted in the second implantation step. Also, the atomic weight of the p-type impurity (boron) implanted in the third implantation step is much smaller than the atomic weight of the n-type impurity (phosphorus or arsenic) implanted in the second implantation step. Therefore, the number of crystal defects formed in the third implantation step is small. For this reason, in FIG. 5, the crystal defects formed in the third implantation step are not shown.

  Next, as shown in FIG. 6, the upper surface 12 a of the semiconductor substrate 12 is irradiated with the laser 90. Here, the laser 90 having a relatively long wavelength is irradiated to heat the depth of the first injection region 46a. By heating the first injection region 46a, the p-type impurity in the first injection region 46a is activated. As a result, as shown in FIG. 6, the low concentration p-type region 46 is formed in the region where the first implantation region 46a has been formed. Further, most of the crystal defects 52a in the first implantation region 46a disappear by heating. Therefore, a low concentration p-type region 46 with a low crystal defect density is formed. In the second implantation region 44a, the laser 90 is disturbed by the high density of crystal defects 52a. For this reason, in the first injection region 46a below the second injection region 44a, the temperature hardly rises. Therefore, the crystal defect 52a (that is, the crystal defect 52a in the drift region 48) in the lower portion of the second implantation region 44a (more specifically, in the lower portion of the first implantation region 46a below the second implantation region 44a) disappears Being suppressed. Therefore, high-density crystal defects 52a remain in the drift region 48 below the second implantation region 44a. The crystal defects 52 a remaining in the drift region 48 form the low lifetime layer 52.

  Next, as shown in FIG. 7, the upper surface 12 a of the semiconductor substrate 12 is irradiated with the laser 92. Here, a laser 92 having a wavelength shorter than that of the laser 90 is irradiated to heat the depths of the second injection region 44a and the third injection region 42a. Thus, the n-type impurity in the second implantation region 44a is activated, and the p-type impurity in the third implantation region 42a is activated. As a result, as shown in FIG. 7, the high concentration n-type region 44 is formed in the range in which the second injection region 44a is formed, and the anode contact region 42 is in the range in which the third injection region 42a is formed. Is formed. Further, by heating, most of the crystal defects 52a in the second implantation region 44a disappear, and most of the crystal defects in the third implantation region 42a disappear. Therefore, high concentration n-type region 44 and anode contact region 42 with low crystal defect density are formed.

  Thereafter, as shown in FIG. 8, a trench is formed on the upper surface 12a of the semiconductor substrate 12, and the gate insulating film 38 and the control electrode 36 are formed in the trench. Thereafter, interlayer insulating film 18, upper electrode 14, cathode region 50 and lower electrode 16 are formed to complete diode region 40 shown in FIG.

  According to the manufacturing method described above, the low lifetime layer 52 is formed immediately below the high concentration n-type region 44. Therefore, relative displacement between the position of the high concentration n-type region 44 and the position of the low lifetime layer 52 can be prevented. That is, the low lifetime layer 52 can be accurately positioned and formed with respect to the high concentration n-type region 44. Further, since the high concentration n-type region 44 is formed by photolithography, the positional accuracy when forming the high concentration n-type region 44 is extremely high. Therefore, the low lifetime layer 52 is also formed with extremely high positional accuracy. For this reason, the low lifetime layer 52 is formed with extremely high positional accuracy also to semiconductor regions other than the high concentration n-type region 44. When a low lifetime layer is formed by a method of irradiating a helium wire as in the prior art, helium is applied to the semiconductor substrate through a metal mask (a member having an opening in a metal plate for cutting the helium wire). A line is illuminated. In this method, the accuracy in aligning the metal mask with the semiconductor substrate is low, and the low lifetime layer can not be accurately formed. On the other hand, according to the method of the embodiment, the low lifetime layer 52 can be formed with photolithography accuracy, and the low lifetime layer 52 can be formed with extremely high positional accuracy. Therefore, according to this manufacturing method, the semiconductor device 10 can be manufactured with stable quality. Further, in this manufacturing method, since the crystal defect 52a of the low lifetime layer 52 is formed simultaneously with the formation of the high concentration n-type region 44, the process for forming the crystal defect 52a is not performed. The lifetime layer 52 can be formed. Therefore, according to this method, the semiconductor device 10 can be manufactured at low cost.

  In the embodiment described above, the low concentration p-type region 46 is provided below the high concentration n-type region 44 and the anode contact region 42. However, instead of the low concentration p-type region 46, a low concentration n-type region (an n-type region having a lower n-type impurity concentration than the high concentration n-type region 44) may be disposed. In such a configuration, the pn junction at the interface between the anode contact region 42 and the low concentration n-type region constitutes a pn diode. Also in this configuration, the low lifetime layer 52 can be formed under the high concentration n-type region 44.

  Further, as shown in FIG. 9, an n-type region 54 may be provided in the middle of the low concentration p-type region 46 in the depth direction to divide the low concentration p-type region 46 up and down.

  Further, as shown in FIG. 10, a low lifetime layer 56 may be provided in the IGBT region 20. The crystal defects of the low lifetime layer 56 in the IGBT region 20 can be formed by the same principle as the above-described embodiment by increasing the implantation concentration of the n-type impurity to the emitter region 22.

  Further, in the above-described embodiment, although the diode and the IGBT are provided on a single semiconductor substrate, the technology described in the present specification is a semiconductor device in which only the diode or only the IGBT is provided on the semiconductor substrate. May apply.

  As mentioned above, although embodiment was described in detail, these are only examples and do not limit the range of a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the techniques illustrated in the present specification or the drawings simultaneously achieve a plurality of purposes, and achieving one of the purposes itself has technical utility.

10: semiconductor device 12: semiconductor substrate 14: upper electrode 16: lower electrode 18: interlayer insulating film 20: IGBT region 22: emitter region 24: body region 24a: body contact region 24b: low concentration body region 26: drift region 30: Collector region 34: gate electrode 36: control electrode 38: gate insulating film 40: diode region 42: anode contact region 44: high concentration n-type region 46: low concentration p-type region 48: drift region 50: cathode region 52: low life Time layer 52a: crystal defects

Claims (1)

A method of manufacturing a semiconductor device;
A first implantation step of implanting an n-type or p-type impurity into a first region of the surface of the semiconductor substrate;
In the second range, which is a part of the first range, the n-type or p-type impurity is doped at a higher concentration than the first implantation step so that the implantation depth of the impurities becomes shallower than the first implantation step. A second implantation step of implanting, and forming a crystal defect in a region under the impurity implantation region in the first implantation step under the impurity implantation region in the second implantation step;
A first heating step of irradiating the first region with a laser after the execution of the first implantation step and the second implantation step to heat the implantation depth of the impurity in the first implantation step;
A second heating step of irradiating the second range with a laser after the execution of the first heating step to heat the implantation depth of the impurity in the second implantation step;
Manufacturing method.

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