JP2018173838A - Semiconductor device, battery monitoring system, and reference voltage creating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a battery monitoring system, and a reference voltage creating method capable of improving a PSRR characteristic.SOLUTION: According to a semiconductor device 10, a power supply voltage VDD is input from a terminal 30 via an LPF 12. An LPF 42 includes: a capacitor element 46 connectable via a terminal 38 and provided to the exterior; and a resistor element 44 provided in the interior, and executes filtering on the power supply voltage VDD input via the terminal 30 with the resistor element 44 and the capacitor element 46 being connected via the terminal 38. A reference voltage creating circuit 32 creates a reference voltage VREF on the basis of a signal having undergone the filtering by the LPF 42, and outputs the created reference voltage VREF to the exterior via a terminal 40.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, a battery monitoring system, and a reference voltage generation method.

  Conventionally, a reference voltage generation circuit has been used as a semiconductor device that generates an electrical signal corresponding to a reference voltage (hereinafter referred to as “reference voltage VREF”) from an electrical signal corresponding to the power supply voltage VDD (hereinafter referred to as “power supply voltage VDD”). Are known. A technique for improving PSRR (Power Supply Rejection Ratio) is known in order to reduce the influence of fluctuations in the power supply voltage VDD and noise superimposed on the power supply voltage VDD.

  As this technique, for example, in Patent Documents 1 and 2, the power supply voltage VDD is input to the reference voltage generation circuit via the LPF, so that the noise of the high frequency component superimposed on the power supply voltage VDD is removed by the LPF. Is described.

  As such a reference voltage generation circuit, a reference voltage generation circuit 132 including a BGR (Bandgap reference) 134 and an AMP (Amplifier) 136 is known as shown in FIG. In the reference voltage generation circuit 132 included in the semiconductor device 100 illustrated in FIG. 8, the power supply voltage VDD is input to the terminal 130 through the LPF 112 including the resistor element 120 and the capacitor element 122. Then, the power supply voltage VDD is input from the terminal 130 to the BGR 134 of the reference voltage generation circuit 132. The reference voltage VREF generated based on the power supply voltage VDD by the BGR 134 is output to the outside via the terminal 40.

JP 2012-118808 A JP 2009-301551A

  By the way, in the conventional reference voltage generation circuit 132 shown in FIG. 8, the band of the BGR 134 is narrower than that of the AMP 136. For this reason, a capacitor for expanding the band of the BGR 134 is connected between the BGR 134 and the AMP 136. In the reference voltage generation circuit 132 shown in FIG. 8, a capacitive element 147 provided outside the semiconductor device 100 is connected via the terminal 141 between the output of the BGR 134 and the input of the AMP 136.

  FIG. 9 shows an example of the frequency characteristics of PSRR (hereinafter referred to as “PSRR characteristics”) in the reference voltage generation circuit 132 of the conventional semiconductor device 100 shown in FIG. In FIG. 9, for comparison of the PSRR characteristics, the PSRR characteristics when the capacitor 147 and the BGR 134 are not connected in the conventional semiconductor device 100 shown in FIG.

  FIG. 9 shows that the lower the gain, the better the PSRR characteristic. The PSRR characteristic improves as the capacitance value of the capacitive element 147 increases. For example, in the PSRR characteristic shown in FIG. 9, the gain in the intermediate frequency region decreases as the capacitance value of the capacitive element 147 increases (see arrow A). .

  However, when the capacitance value of the capacitor 147 is increased in this way, the cost may increase or the overall circuit scale may increase. Therefore, when the capacitance value of the capacitor 147 is limited, as described above, the PSRR characteristics may not be sufficiently improved.

  In order to suppress an increase in the overall circuit scale or an increase in cost due to the increase in the capacitance of the capacitive element in this way, the PSRR characteristics of the semiconductor device (reference voltage generation circuit) are improved. It is hoped that.

  An object of the present invention is to provide a semiconductor device, a battery monitoring system, and a reference voltage generation method capable of improving PSRR characteristics.

  In order to achieve the above object, a semiconductor device of the present invention is subjected to a filtering process by a second filter for filtering a signal corresponding to a power supply voltage input from an input terminal via the first filter, and the second filter. A reference voltage generating circuit that generates a reference voltage based on the generated signal and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal.

  In order to achieve the above object, a semiconductor device of the present invention includes an external capacitive element that can be connected via a connection terminal, and a resistive element provided inside, the resistive element and the A second filter for filtering a signal corresponding to a power supply voltage input from the input terminal via the first filter in a state where the capacitive element is connected via the connection terminal, and a filtering process by the second filter A reference voltage generating circuit that generates a reference voltage based on the generated signal and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal.

  Furthermore, in order to achieve the above object, a battery monitoring system of the present invention includes a semiconductor device of the present invention and a plurality of battery cells connected in series by driving a reference voltage output from the semiconductor device as a driving voltage. A control unit that outputs a control signal for controlling measurement of a battery voltage of a battery cell to be measured from a battery equipped with a voltage at one end and a voltage at the other end of each of the plurality of battery cells. A cell selection unit that selects a voltage according to the battery cell to be measured according to the control signal from the measured voltage and outputs a signal according to the selected voltage; and a reference voltage output from the semiconductor device is a drive voltage. And an analog-to-digital converter that converts a signal corresponding to the voltage output from the cell selection unit into a digital signal and outputs the digital signal to the control unit.

  Furthermore, in order to achieve the above object, the reference voltage generation method of the present invention filters the signal according to the power supply voltage input from the input terminal via the first filter by the second filter, and the second filter Includes a process of generating a reference voltage based on the signal subjected to the filtering process and outputting a signal corresponding to the generated reference voltage to the outside through the output terminal.

  In order to achieve the above object, the reference voltage generation method of the present invention includes an external capacitive element connectable via a connection terminal and a resistive element provided inside, the resistive element And the capacitor element are connected via the connection terminal, the signal corresponding to the power supply voltage input from the input terminal via the first filter is filtered by the second filter, and the second filter It includes processing for generating a reference voltage based on the filtered signal and outputting a signal corresponding to the generated reference voltage to the outside via an output terminal.

  According to the present invention, there is an effect that PSRR characteristics can be improved.

It is a block diagram showing the outline of an example of the semiconductor device in 1st Embodiment. It is a figure which shows an example of the frequency characteristic of PSRR of the semiconductor device (reference voltage generation circuit) of 1st Embodiment. It is a block diagram showing the outline of an example of the semiconductor device in 2nd Embodiment. It is a block diagram showing the outline of an example of the semiconductor device in 3rd Embodiment. It is a block diagram showing the outline of the other example of the semiconductor device in 3rd Embodiment. It is a block diagram showing the outline of the example of a position of the battery monitoring system in 4th Embodiment. It is a block diagram showing the outline of the other example of the semiconductor device in 1st Embodiment. It is a block diagram showing the outline of an example of the semiconductor device which is a comparative example. It is a figure which shows an example of the PSRR characteristic of the semiconductor device (reference voltage generation circuit) which is a comparative example.

  Hereinafter, each embodiment will be described in detail with reference to the drawings.

[First Embodiment]
First, the configuration of the semiconductor device of this embodiment will be described. FIG. 1 is a configuration diagram illustrating an outline of an example of the semiconductor device 10 of the present embodiment.

  As shown in FIG. 1, the semiconductor device 10 of this embodiment includes a terminal 30, a reference voltage generation circuit 32, a terminal 38, a terminal 40, and an LPF (Low Pass Filter) 42.

  An electric signal corresponding to the power supply voltage VDD (hereinafter referred to as “power supply voltage VDD”) is input to the terminal 30 from the outside via the LPF 12 provided outside the semiconductor device 10. The LPF 12 includes a resistance element 20 and a capacitance element 22 and performs a filtering process for removing power supply noise of a high frequency component superimposed on the power supply voltage VDD. The terminal 30 of the present embodiment is an example of the input terminal of the present disclosure, and the LPF 12 of the present embodiment is an example of the first filter of the present disclosure.

  The power supply voltage VDD input to the terminal 30 is input to the reference voltage generation circuit 32 via the LPF 42. The LPF 42 of this embodiment includes a resistance element 44 and a capacitive element 46. The LPF 42 according to the present embodiment has a function of assisting the LPF 12 and further cuts off power supply noise (filtering processing) for the power supply voltage VDD from which power supply noise is cut off (filtering processing) by the LPF 12. Therefore, the time constant (frequency to cut off) of the LPF 42 of the present embodiment is different from that of the LPF 12.

  The capacitive element 46 of the LPF 42 of the present embodiment is provided outside the semiconductor device 10 and is connected to the capacitive element 46 via the terminal 38. That is, in the semiconductor device 10 of the present embodiment, the LPF 42 functions as a low-pass filter by connecting the resistor element 44 and the capacitor element 46 via the terminal 38. The resistance element 44 has one end connected to the terminal 30 and the other end connected to the reference voltage generation circuit 32 and the terminal 38. The LPF 42 of the present embodiment is an example of the second filter of the present disclosure, and the terminal 38 of the present embodiment is an example of the connection terminal of the present disclosure.

  The reference voltage generation circuit 32 includes a BGR (Bandgap reference) circuit (hereinafter referred to as “BGR”) 34 and an amplifier circuit (hereinafter referred to as “AMP”) 36. The BGR 34 is connected to the terminal 30 via the LPF 42 and generates the reference voltage VREF from the input power supply voltage VDD. The terminal 30 and the BGR 34 are connected to the AMP 36, and the reference voltage VREF generated by the BGR 34 is amplified by the AMP 36. The reference voltage VREF amplified by the AMP 36 is output to the outside of the semiconductor device 10 through the terminal 40. The terminal 40 of the present embodiment is an example of the output terminal of the present disclosure.

  Next, the frequency characteristics of PSRR (hereinafter referred to as “PSRR characteristics”) in the reference voltage generation circuit 32 of the semiconductor device 10 of the present embodiment will be described. FIG. 2 shows an example of the PSRR characteristic in the reference voltage generation circuit 32 of the semiconductor device 10 of the present embodiment. In addition to the PSRR characteristics of the semiconductor device 10 of the present embodiment, FIG. 2 shows a comparison with the semiconductor device 10 shown in FIG. 1 for comparison, and the power supply voltage VDD is input without passing through the LPF 12. The comparative example A shows the PSRR characteristics of a semiconductor device that does not include For comparison, FIG. 2 shows, as Comparative Example B, the PSRR characteristics of a semiconductor device that does not include the LPF 42, unlike the semiconductor device 10 shown in FIG.

  FIG. 2 shows that the lower the gain, the better the PSRR characteristic. As shown in FIG. 2, in Comparative Example B, the high-frequency component is removed by the LPF 12, and therefore Comparative Example B has better PSRR characteristics in the high-frequency region than Comparative Example A. Note that the time constant in the LPF 12, that is, the resistance value of the resistance element 20 and the capacitance value of the capacitance element 22 depend on the state of noise superimposed on the power supply voltage VDD, the PSSR characteristic when the LPF 12 is not provided (see Comparative Example A), and the like. The values obtained on the basis can be used, and these values can be obtained experimentally.

  On the other hand, as shown in FIG. 2, when this embodiment is compared with Comparative Example B, it can be seen that the PSRR characteristics are improved in the semiconductor device 10 of this embodiment in the intermediate frequency region. Note that the time constant in the LPF 42, that is, the resistance value of the resistor element 44 and the capacitance value of the capacitor element 46 are the state of superimposed noise, PSSR characteristics when the LPF 42 is not provided (see Comparative Example A and Comparative Example B), and characteristics. It is possible to use values obtained based on an intermediate frequency region or the like where it is desired to improve, and these values can be obtained experimentally.

  Thus, in the semiconductor device 10 of this embodiment, the power supply voltage VDD is input from the terminal 30 via the LPF 12. The LPF 42 includes an externally provided capacitive element 46 that can be connected via the terminal 38 and an internal resistive element 44, and the resistive element 44 and the capacitive element 46 are connected via the terminal 38. In this state, the power supply voltage VDD input through the terminal 30 is filtered. The reference voltage generation circuit 32 generates a reference voltage VREF based on the signal filtered by the LPF 42 and outputs the generated reference voltage VREF to the outside via the terminal 40. Further, the LPF 12 and the LPF 42 have different time constants.

  According to the semiconductor device 10 of the present embodiment, the power supply voltage VDD is input to the reference voltage generation circuit 32 via the two LPFs LPF12 and LPF42, so that PSRR characteristics can be improved.

[Second Embodiment]
In the first embodiment, the configuration in which the semiconductor device 10 includes one reference voltage generation circuit (reference voltage generation circuit 32) has been described. In contrast, in the present embodiment, a mode in which the semiconductor device 10 includes a plurality of reference voltage generation circuits will be described. In addition, since the semiconductor device 10 of this embodiment includes the same configuration as the semiconductor device 10 of the first embodiment, detailed description of the same configuration is omitted.

  FIG. 3 is a configuration diagram illustrating an outline of an example of the semiconductor device 10 of the present embodiment. As shown in FIG. 3, the semiconductor device 10 of the present embodiment includes a reference voltage generation circuit 32A and a reference voltage generation circuit 32B instead of the reference voltage generation circuit 32 in the semiconductor device 10 of the first embodiment.

  The power supply voltage VDD input to the terminal 30 is input to the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B via the LPF 42. The resistance element 44 of the LPF 42 is connected to the BGR 34A and the BGR 34B.

  The first reference voltage generation circuit 32A includes a BGR 34A and an AMP 36A. The BGR 34A is connected to the terminal 30 via the LPF 42, and generates the reference voltage VREF1 from the input power supply voltage VDD. The AMP 36A is connected to the terminal 30 and the BGR 34A, and the reference voltage VREF1 generated by the BGR 34A is amplified by the AMP 36A. The reference voltage VREF1 amplified by the AMP 36A is output to the outside of the semiconductor device 10 through the terminal 40A. The terminal 40A in this case is an example of the first output terminal of the present disclosure.

  On the other hand, the second reference voltage generation circuit 32B includes a BGR 34B and an AMP 36B. The BGR 34B is connected to the terminal 30 via the LPF 42, and generates the reference voltage VREF2 from the input power supply voltage VDD. The AMP 36B is connected to the terminal 30 and the BGR 34B, and the reference voltage VREF2 generated by the BGR 34B is amplified by the AMP 36B. The reference voltage VREF2 amplified by the AMP 36B is output to the outside of the semiconductor device 10 through the terminal 40B. The terminal 40B in this case is an example of the second output terminal of the present disclosure.

  In the semiconductor device 10 of the present embodiment, the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B have the same configuration, and BGR34A and BGR34B, and AMP36A and AMP36B have the same configuration. . In addition, the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B have the same connection relationship with the terminal 30 and the LPF 42. Further, the reference voltage VREF1 and the reference voltage VREF2 are the same values when the error is ignored.

  Thus, each of the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B in the semiconductor device 10 of the present embodiment is the same as the reference voltage generation circuit 32 in the semiconductor device 10 of the first embodiment.

  Therefore, similarly to the semiconductor device 10 of the first embodiment, according to the semiconductor device 10 of the present embodiment, the power supply voltage VDD is supplied to the first reference voltage generation circuit 32A and the second reference voltage through the two LPFs LPF12 and LPF42. Since the voltage is input to each of the reference voltage generation circuits 32B, PSRR characteristics can be improved in each of the reference voltage VREF1 and the reference voltage VREF2.

  Unlike the present embodiment, the voltage value of the reference voltage VREF1 generated by the first reference voltage generation circuit 32A may be different from the voltage value of the reference voltage VREF2 generated by the second reference voltage generation circuit 32B. Needless to say. In this case, each of the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B includes BGR34A and AMP36A, or BGR34B and AMP36B corresponding to the voltage value of the reference voltage VREF1 or reference voltage VREF2 to be generated. Good.

  However, it may be necessary to provide a plurality of reference voltage generation circuits that generate the same reference voltage VREF, for example, in conformity with the specification of ISO 26262, which is a functional safety standard in the automotive field. In such a case, like the semiconductor device 10 of the present embodiment, the first reference voltage generation circuit 32A that generates the reference voltage VREF1, and the second reference that generates the reference voltage VREF2 having the same voltage value as the reference voltage VREF1. It is preferable to include a voltage generation circuit 32B.

  Further, in the semiconductor device 10 of the present embodiment, the case where the two reference voltage generation circuits, ie, the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B are provided has been described. However, the semiconductor device 10 includes three or more reference voltages. It goes without saying that a voltage generation circuit may be provided. In this case, the number of LPFs 42 may be one regardless of the number of reference voltage generation circuits included in the semiconductor device 10.

[Third Embodiment]
In the above embodiments, the semiconductor device 10 that generates the reference voltage (VREF, or the reference voltage VREF1 and the reference voltage VREF2) based on the power supply voltage VDD input from the outside has been described. In contrast, in the semiconductor device 10 of the present embodiment, a case where the power supply voltage VDD is generated internally will be described. In addition, since the semiconductor device 10 of this embodiment includes the same configuration as the semiconductor device 10 of the first embodiment, detailed description of the same configuration is omitted.

  FIG. 4 is a configuration diagram illustrating an outline of an example of the semiconductor device 10 of the present embodiment. As shown in FIG. 4, in the semiconductor device 10 of the present embodiment, the power supply voltage VCC that is higher than the power supply voltage VDD is input to the terminal 30 via the LPF 12.

  In addition, the semiconductor device 10 of the present embodiment includes a high voltage regulator circuit (hereinafter referred to as “REG”) 50 between the terminal 30 and the LPF 42. The REG 50 converts (generates) the power supply voltage VCC input from the terminal 30 into the power supply voltage VDD and outputs it. The power supply voltage VDD generated by the REG 50 is supplied to the LPF 42 and is output to the outside of the semiconductor device 10 via the terminal 52. The REG 50 of this embodiment is an example of the conversion circuit of the present disclosure.

  As described above, in the semiconductor device 10 of the present embodiment, the LPF 42 is connected to the REG 50, and the power supply voltage VDD is input from the REG 50 instead of the terminal 30, as in the semiconductor device 10 of the first embodiment. It is.

  Therefore, similarly to the semiconductor device 10 of the first embodiment, according to the semiconductor device 10 of the present embodiment, the power supply voltage VDD is input to the reference voltage generation circuit 32 via the two LPFs LPF 12 and LPF 42. The PSRR characteristics can be improved at the reference voltage VREF.

  In the semiconductor device 10 shown in FIG. 4, the case where one reference voltage generation circuit (reference voltage generation circuit 32) is provided has been described. However, similarly to the second embodiment, a plurality of reference voltage generation circuits are provided. Needless to say. As an example of this case, FIG. 5 is a configuration diagram illustrating an outline of an example of the semiconductor device 10 of the present embodiment in the case where the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B are provided. The semiconductor device 10 shown in FIG. 5 is a combination of the semiconductor device 10 of the present embodiment shown in FIG. 4 and the semiconductor device 10 shown in FIG. 3 of the second embodiment.

  Also in the semiconductor device 10 shown in FIG. 5, similarly to the semiconductor device 10 shown in FIG. 4, the power supply voltage VDD is supplied to the first reference voltage generation circuit 32 </ b> A and the second reference voltage via the two LPFs LPF 12 and LPF 42. Since the voltage is input to each of the voltage generation circuits 32B, PSRR characteristics can be improved in each of the reference voltage VREF1 and the reference voltage VREF2.

[Fourth Embodiment]
The semiconductor device 10 of each of the above embodiments is preferably applied to a battery voltage monitoring system that monitors the battery voltage by measuring the battery voltage of the battery cell. In particular, as described above, since it is preferable to apply the semiconductor device 10 shown in FIG. 5 in the third embodiment to a system for monitoring the battery voltage of a battery cell used in an automobile or the like, in this embodiment, A battery monitoring system to which the semiconductor device 10 of FIG. 5 is applied will be described with reference to FIG.

  The battery monitoring system 60 to which the semiconductor device 10 shown in FIG. 6 is applied has a function of measuring the battery voltage of each battery cell V of a battery 61 including a plurality of battery cells V connected in series. In the battery monitoring system 60 illustrated in FIG. 6 as an example, the battery 61 includes n (n = 2) battery cells V (Vn, Vn−1). The number of battery cells V provided is not particularly limited.

  The high potential side of the battery cell Vn is connected to the terminal 70n, and the voltage on the high potential side of the battery cell Vn is input to the terminal 70n. Further, the low potential side of the battery cell Vn and the low potential side of the battery cell Vn-1 are connected to the terminal 70n-1, and the terminal 70n-1 has a voltage on the low potential side of the battery cell Vn (battery cell Vn− 1 on the high potential side). Furthermore, the low potential side of the battery cell Vn-1 is connected to the terminal 70n-2, and the voltage on the low potential side of the battery cell Vn-1 is input to the terminal 70n-2.

  As shown in FIG. 6, the voltage on the high potential side of the battery cell Vn is input as the power supply voltage VCC to the terminal 30 of the battery monitoring system 60 of the present embodiment via the LPF 12. The power supply voltage VCC input to the terminal 30 is converted into the power supply voltage VDD by the REG 50. The power supply voltage VDD is output from the terminal 52 and also input to the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B via the LPF 42.

  As shown in FIG. 6, the battery monitoring system 60 of this embodiment includes a cell voltage measurement circuit 62A including a first reference voltage generation circuit 32A and a cell voltage measurement circuit 62B including a second reference voltage generation circuit 32B. I have.

  The cell voltage measurement circuit 62A measures the battery voltage of each of the battery cells Vn-1 and Vn and outputs a measurement result. The cell voltage measurement circuit 62B measures the battery voltage of each of the battery cells Vn-1 and Vn and outputs the measurement result. As described above, the battery monitoring system 60 of this embodiment includes two measurement paths for measuring the battery voltage of each battery cell.

  In the battery monitoring system 60 of the present embodiment, the battery voltage is monitored by measuring the battery voltage of the battery cell V to be measured under the control of an MCU (Microcontroller) 80 provided outside.

  The cell voltage measurement circuit 62A further includes a cell selection switch (hereinafter referred to as “cell selection SW”) 64A, an analog level shifter 66A, an analog-digital converter (hereinafter referred to as “A / D”) 68A, and a control unit 69A. Yes. The cell voltage measurement circuit 62B further includes a cell selection SW 64B, an analog level shifter 66B, an A / D 68B, and a control unit 69B. The cell selection SW 64A and the cell selection SW 64B of the present embodiment are examples of the cell selection unit of the present disclosure.

  Thus, the cell voltage measurement circuit 62A and the cell voltage measurement circuit 62B differ only in whether the reference voltage generation circuit provided is the first reference voltage generation circuit 32A or the second reference voltage generation circuit 32B. Since the rest is the same, hereinafter, the configuration and operation of the cell voltage measurement circuit 62A will be described in detail, and the detailed description of the configuration and operation of the cell voltage measurement circuit 62B will be omitted.

  The control unit 69A of the present embodiment is driven by the power supply voltage VDD supplied from the cell voltage measurement circuit 62A, and generates a control signal for measuring the battery voltage to be measured according to the control of the MCU 80 of the battery monitoring system 60. Generate and output to the cell selection SW 64A. In FIG. 6, in order to avoid complication, the signal lines connecting the control unit 69A and the cell selection SW 64A are omitted. Further, the control unit 69A of the present embodiment transmits the measurement result input from the A / D 68A to the MCU 80 via a communication unit (not shown).

  The cell selection SW 64A is connected to the terminals 70n-2 to 70n, and voltages corresponding to the battery cells Vn and Vn-1 are input from the terminals 70n-2 to 70n, respectively. The cell selection SW 64A selects a voltage corresponding to the battery cell V to be measured by the cell selection SW 64A in accordance with a control signal input from the control unit 69A, and outputs the selected voltage to the analog level shifter 66B. For example, when the battery cell to be measured is the battery cell Vn, the cell selection SW 64A selects a voltage input from the terminal 70n and a voltage input from the terminal 70n-1, and uses these selected voltages as an analog level shifter. To 66A.

  The analog level shifter 66A outputs a differential voltage, which is a voltage difference according to the battery cell V input from the cell selection SW 64A, at a level with reference to the ground potential. For example, when the battery cell to be measured is the battery cell Vn as described above, the differential voltage that is the difference between the voltage input from the terminal 70n and the voltage input from the terminal 70n-1 is used as a reference for the ground potential. Output by level.

  The A / D 68A generates and outputs a digital signal corresponding to the differential voltage input from the analog level shifter 66A by driving the reference voltage VREF1 supplied from the first reference voltage generation circuit 32A as a drive voltage. This digital signal is output as a measurement result of the battery voltage of the battery cell V to be measured by the control unit 69B to the MCU 80 via a communication unit (not shown).

  Thus, by applying the semiconductor device 10 of each of the above embodiments to the battery monitoring system 60, it is possible to improve PSRR characteristics while suppressing an increase in cost and an increase in the circuit scale of the entire battery monitoring system 60. . In particular, when a reference voltage generation circuit 32 that generates a similar reference voltage VREF is provided, such as when complying with the above-mentioned provisions of ISO 26262, it is only necessary to provide one LPF 42 regardless of the number of reference voltage generation circuits 32. The PSRR characteristics can be improved while further suppressing the increase in the circuit scale of the battery monitoring system 60 and the increase in the circuit scale of the battery monitoring system 60 as a whole.

  As described above, in the semiconductor device 10 of each of the above embodiments, the power supply voltage VDD or the power supply voltage VDD converted from the power supply voltage VCC is input to the reference voltage generation circuit 32 through the two LPFs LPF12 and LPF42. The Therefore, according to the semiconductor device 10 of each of the above embodiments, noise superimposed on the power supply voltage VDD can be cut off in two stages, so that the PSRR characteristics, particularly the PSRR characteristics in the intermediate frequency region can be improved.

  In the semiconductor device 100 of the prior art shown in FIG. 8 described above, in order to improve the PSRR characteristic in the intermediate frequency region, the capacitance value of the capacitive element 147 provided outside must be increased. On the other hand, in the semiconductor device 10 of each of the above embodiments, the PSRR characteristics are improved according to the time constant of the LPF 42. Here, the capacitance value of the capacitance element 46 of the LPF 42 may be relatively smaller than the capacitance value of the capacitance element 147 connected to the conventional semiconductor device 100. Therefore, according to the semiconductor device 10 of each of the above embodiments, the cost can be suppressed and the increase in the scale of the entire circuit can be suppressed as compared with the semiconductor device 100 of the prior art.

  In addition, when the conventional semiconductor device 100 is provided with a plurality of reference voltage generation circuits, a capacitance element 147 is required for each reference voltage generation circuit. Therefore, both the cost and the scale of the entire circuit increase according to the number of reference voltage generation circuits included in the semiconductor device 100. On the other hand, the semiconductor device 10 shown in FIG. 3 of the second embodiment and the semiconductor device 10 shown in FIG. 5 of the third embodiment have a plurality of reference voltage generation circuits (FIG. 3 and FIG. 5, the PSRR characteristics can be improved for each of the first reference voltage generation circuit 32A and the second reference voltage generation circuit 32B. Therefore, according to the semiconductor device 10 of each of the above embodiments, it is possible to drastically reduce costs and suppress an increase in the scale of the entire circuit as compared with the semiconductor device 100 of the prior art.

  In the semiconductor device 10 of each of the embodiments described above, in order to improve the PSRR characteristics, when the time constant of the LPF 42 is increased, at least one of the resistance value of the resistance element 44 and the capacitance value of the capacitance element 46 may be increased. . Therefore, in the semiconductor device 10 of each of the above embodiments, which of the resistance value of the resistance element 44 and the capacitance value of the capacitance element 46 is to be increased or what value is to be determined is determined by the power supply voltage VDD of the resistance element 44. The voltage can be appropriately selected according to the voltage drop, the cost of the capacitor 46, the circuit scale, and the like.

  In general, unlike the semiconductor device 10 of each of the embodiments described above, when trying to improve the PSRR characteristics using only the LPF 12, the time constant of the LPF 12 is increased. In this case, at least one of the resistance value of the resistance element 20 and the capacitance value of the capacitance element 22 is increased. When the resistance value of the resistance element 20 is increased, the voltage drop of the power supply voltage VDD is increased. On the other hand, when the capacitance value of the capacitive element 22 is increased, the cost generally increases relatively. Therefore, it is often not preferable to improve the PSRR characteristics of the semiconductor device 10 using only the LPF 12.

  On the other hand, according to the semiconductor device 10 of each of the above embodiments, the LPF 42 functions as an auxiliary to the LPF 12 to improve the PSRR characteristic. An increase or the like can be suppressed.

  In each of the above embodiments, the case where the capacitive element 46 of the LPF 42 is provided outside the semiconductor device 10 and is connected to the resistance element 44 provided inside through the terminal 38 has been described with reference to FIG. As shown, the capacitor element 46 may be provided in the semiconductor device 10. In this case, unlike the semiconductor device 10 of each of the above embodiments, the semiconductor device 10 shown in FIG. 7 does not include the terminal 38, and the resistor element 44 and the capacitor element 46 are connected without the terminal 38 interposed therebetween. .

  Further, the configurations and operations of the semiconductor device 10 and the battery monitoring system 60 described in the other embodiments described above are merely examples, and can be changed according to the situation without departing from the gist of the present invention. Not too long.

10 Semiconductor device 12, 42 LPF
20, 44 Resistance elements 22, 46 Capacitance elements 30, 38, 40, 52 Terminal 32 Reference voltage generation circuit, 32A First reference voltage generation circuit, 32B Second reference voltage generation circuit 60 Battery monitoring system 61 Battery 62A, 62B Cell voltage Measurement circuit 64A, 64B Cell selection SW
68A, 68B A / D (analog / digital converter)
69A, 69B Control unit Vn, Vn-1 (V) Battery cell

Claims (9)

A second filter for filtering a signal corresponding to the power supply voltage input from the input terminal via the first filter;
A reference voltage generation circuit that generates a reference voltage based on the signal filtered by the second filter and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal;
A semiconductor device comprising: The second filter is a low-pass filter including a resistance element and a capacitance element.
The semiconductor device according to claim 1. A capacitance element provided outside that can be connected via a connection terminal, and a resistance element provided inside; in a state where the resistance element and the capacitance element are connected via the connection terminal; A second filter for filtering a signal corresponding to the power supply voltage input from the input terminal via the one filter;
A reference voltage generation circuit that generates a reference voltage based on the signal filtered by the second filter and outputs a signal corresponding to the generated reference voltage to the outside via an output terminal;
A semiconductor device comprising: The output terminal includes a first output terminal and a second output terminal,
The reference voltage generation circuit generates a first reference voltage based on the signal filtered by the second filter, generates the first reference voltage, and outputs the first reference voltage via a first output terminal. And a second reference voltage generation circuit that generates a second reference voltage based on the signal filtered by the second filter and outputs the generated second reference voltage via a second output terminal. ,
The semiconductor device according to claim 1. A first power supply voltage is input to the input terminal, and the second filter is converted by a conversion circuit that converts the first power supply voltage input from the input terminal via the first filter into a second power supply voltage. Filtering the signal according to the second power supply voltage,
The semiconductor device according to claim 1. The first filter and the second filter have different time constants.
The semiconductor device according to claim 1. A semiconductor device according to any one of claims 1 to 6,
Control for driving a reference voltage output from the semiconductor device as a drive voltage and outputting a control signal for controlling measurement of a battery voltage of a battery cell to be measured from a battery having a plurality of battery cells connected in series And
A voltage at one end and a voltage at the other end of each of the plurality of battery cells are input, a voltage corresponding to the battery cell to be measured is selected from the input voltage according to the control signal, and according to the selected voltage A cell selection unit for outputting the selected signal;
An analog-to-digital converter that drives a reference voltage output from the semiconductor device as a drive voltage, converts a signal corresponding to the voltage output from the cell selection unit into a digital signal, and outputs the signal to the control unit;
Battery monitoring system with A signal corresponding to the power supply voltage input from the input terminal through the first filter is filtered by the second filter,
Generating a reference voltage based on the signal filtered by the second filter;
Output a signal according to the generated reference voltage to the outside via the output terminal.
Reference voltage generation method. A capacitance element provided outside that can be connected via a connection terminal, and a resistance element provided inside; in a state where the resistance element and the capacitance element are connected via the connection terminal; Filtering the signal according to the power supply voltage input from the input terminal through the first filter by the second filter,
Generating a reference voltage based on the signal filtered by the second filter;
Output a signal according to the generated reference voltage to the outside via the output terminal.
Reference voltage generation method.