JP2018170324A - Display device - Google Patents

Display device Download PDF

Info

Publication number
JP2018170324A
JP2018170324A JP2017064916A JP2017064916A JP2018170324A JP 2018170324 A JP2018170324 A JP 2018170324A JP 2017064916 A JP2017064916 A JP 2017064916A JP 2017064916 A JP2017064916 A JP 2017064916A JP 2018170324 A JP2018170324 A JP 2018170324A
Authority
JP
Japan
Prior art keywords
oxide semiconductor
film
display device
insulating film
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017064916A
Other languages
Japanese (ja)
Inventor
陽平 山口
Yohei Yamaguchi
陽平 山口
功 鈴村
Isao Suzumura
功 鈴村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Display Inc
Original Assignee
Japan Display Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Display Inc filed Critical Japan Display Inc
Priority to JP2017064916A priority Critical patent/JP2018170324A/en
Priority to US15/892,513 priority patent/US10453965B2/en
Priority to CN202211306654.8A priority patent/CN115498028A/en
Priority to CN201810159539.XA priority patent/CN108695362B/en
Publication of JP2018170324A publication Critical patent/JP2018170324A/en
Priority to US16/565,760 priority patent/US11177363B2/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Nonlinear Science (AREA)
  • Nanotechnology (AREA)
  • Electromagnetism (AREA)
  • Composite Materials (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve reliability of a TFT using an oxide semiconductor.SOLUTION: Provided is a display device that includes a substrate having a display area formed with a plurality of pixels. Each pixel includes a first TFT using a first oxide semiconductor 12. A first gate insulating film 13 is formed on the first oxide semiconductor 12. The first gate insulating film 13 is formed by a lamination structure of a first silicon oxide film 131 and a first aluminum oxide film 132. A first gate electrode 14 is formed on the first aluminum oxide film 131.SELECTED DRAWING: Figure 4

Description

本発明は表示装置に係り、特に酸化物半導体を用いたＴＦＴを有する表示装置に関する。   The present invention relates to a display device, and more particularly to a display device having a TFT using an oxide semiconductor.

液晶表示装置や有機ＥＬ表示装置では各画素のスイッチング素子や駆動回路に薄膜トランジスタ（ＴＦＴ：Ｔｈｉｎ Ｆｉｌｍ Ｔｒａｎｓｉｓｔｏｒ）を用いている。ＴＦＴには、ａ-Ｓｉ（非晶質シリコン）、Ｐｏｌｙ−Ｓｉ（Ｐｏｌｙ Ｓｌｉｃｉｏｎ）、あるいは酸化物半導体等が用いられている。   In a liquid crystal display device and an organic EL display device, a thin film transistor (TFT) is used for a switching element and a drive circuit of each pixel. For the TFT, a-Si (amorphous silicon), Poly-Si (Poly Slicion), an oxide semiconductor, or the like is used.

ａ-Ｓｉは移動度が小さいので、これを用いたＴＦＴを周辺駆動回路に使用することには問題がある。Ｐｏｌｙ−Ｓｉは移動度が大きく、これを用いたＴＦＴを周辺駆動回路に使用することが出来るが、画素のスイッチング素子として用いる場合は、リーク電流が大きいという問題がある。酸化物半導体は移動度がａ-Ｓｉよりも大きく、また、リーク電流も小さいが、膜欠陥の制御に関連する信頼性に課題がある。   Since a-Si has low mobility, there is a problem in using a TFT using the same for a peripheral driver circuit. Poly-Si has a high mobility, and a TFT using this can be used for a peripheral driver circuit. However, when it is used as a switching element of a pixel, there is a problem that a leak current is large. An oxide semiconductor has a mobility higher than that of a-Si and a small leakage current, but has a problem in reliability related to film defect control.

特許文献１には、ゲート電極を含み酸化物半導体で形成されたＴＦＴ全体を無機絶縁膜、例えば酸化アルミニウム膜、酸化チタン膜、または酸化インジウム膜で覆う構成が記載されている。   Patent Document 1 describes a configuration in which an entire TFT including an oxide semiconductor including a gate electrode is covered with an inorganic insulating film such as an aluminum oxide film, a titanium oxide film, or an indium oxide film.

特許文献２には、酸化物半導体を用いたＴＦＴの性能を向上させるためにゲート絶縁膜を薄くする場合のトンネル効果によるゲートリークを抑える構成が記載されている。ゲート絶縁膜として、誘電率の高い酸化ハフニウム、酸化タンタル等の高誘電率材料を用いるが、これと積層して、酸化シリコン、窒化シリコン、酸化アルミニウムなどを含む膜を積層することが記載されている。   Patent Document 2 describes a configuration that suppresses gate leakage due to a tunnel effect when the gate insulating film is thinned in order to improve the performance of a TFT using an oxide semiconductor. As the gate insulating film, a high dielectric constant material such as hafnium oxide or tantalum oxide having a high dielectric constant is used. However, it is described that a film containing silicon oxide, silicon nitride, aluminum oxide, or the like is stacked therewith. Yes.

特許文献３には、酸化物半導体を用いたＴＦＴの特性を安定化するために、酸化物半導体をチャネル部において、無機絶縁膜でサンドイッチする構成が記載されている。この場合の無機絶縁膜として、酸化アルミニウム、酸化チタン、酸化インジウム等が例示されている。   Patent Document 3 describes a structure in which an oxide semiconductor is sandwiched with an inorganic insulating film in a channel portion in order to stabilize characteristics of a TFT using an oxide semiconductor. Examples of the inorganic insulating film in this case include aluminum oxide, titanium oxide, and indium oxide.

特開２０１２−１５４３６号公報JP 2012-15436 A 特開２０１５−９２６３８号公報Japanese Patent Laying-Open No. 2015-92638 ＷＯ２０１０/０４１６８６号公報WO2010 / 041686

酸化物半導体としては、ＩＧＺＯ（Ｉｎｄｉｕｍ Ｇａｌｌｉｕｍ Ｚｉｎｃ Ｏｘｉｄｅ）、ＩＴＺＯ（Ｉｎｄｉｕｍ Ｔｉｎ Ｚｉｎｃ Ｏｘｉｄｅ）、ＺｎＯＮ（Ｚｉｎｃ Ｏｘｉｄｅ Ｎｉｔｒｉｄｅ）、ＩＧＯ（Ｉｎｄｉｕｍ Ｇａｌｌｉｕｍ Ｏｘｉｄｅ）等がある。これらの酸化物半導体は透明であることから、ＴＡＯＳ（Ｔｒａｎｓｐａｒｅｎｔ Ａｍｏｒｐｈｏｕｓ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）と呼ばれることもある。なお、例えばＩＧＺＯ等はＩｎ：Ｇａ：Ｚｎ＝１：１：１の場合が多いが、本明細書ではこの割合からずれた場合も含まれるものとする。   Examples of the oxide semiconductor include IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnON (Zinc Oxide Nitride), and IGO (Indium Gallium Oxide). Since these oxide semiconductors are transparent, they are sometimes referred to as TAOS (Transparent Amorphous Oxide Semiconductor). Note that, for example, IGZO or the like often has In: Ga: Zn = 1: 1: 1, but in this specification, a case of deviation from this ratio is included.

酸化物半導体を用いたＴＦＴは酸化物半導体中の酸素量、あるいは、酸化物半導体と接触する絶縁膜中の酸素量で初期特性を調整することができるが、信頼性の制御が難しい。特に、絶縁膜の酸素量を増やすと絶縁膜中の欠陥が増加する。したがって、初期特性と信頼性がトレードオフの関係になっていた。   A TFT using an oxide semiconductor can adjust the initial characteristics by the amount of oxygen in the oxide semiconductor or the amount of oxygen in the insulating film in contact with the oxide semiconductor, but it is difficult to control reliability. In particular, increasing the amount of oxygen in the insulating film increases the number of defects in the insulating film. Therefore, the initial characteristics and reliability are in a trade-off relationship.

また、初期において酸化物半導体中の酸素の量を制御しても、この酸素が動作寿命中に徐々に抜けていき、ＴＦＴの特性の変動をきたすという問題が生じていた。   In addition, even when the amount of oxygen in the oxide semiconductor is controlled at an early stage, this oxygen gradually escapes during the operation life, causing a problem of variation in TFT characteristics.

本発明の課題は、酸化物半導体を用いたＴＦＴの初期特性と動作寿命中の信頼性の両方を確保し、初期特性と、信頼性の優れた表示装置を実現することである。   An object of the present invention is to secure both initial characteristics and reliability during operation life of a TFT using an oxide semiconductor, and to realize a display device having excellent initial characteristics and reliability.

本発明は上記問題を克服するものであり、具体的な手段は次のとおりである。   The present invention overcomes the above problems, and specific means are as follows.

（１）複数の画素が形成された表示領域を有する基板を含む表示装置であって、前記画素は第１の酸化物半導体を用いた第１のＴＦＴを含み、前記第１の酸化物半導体の上には第１のゲート絶縁膜が形成され、前記第１のゲート絶縁膜は第１のシリコン酸化膜と第１のアルミニウム酸化膜の積層構造で形成され、前記第１のアルミニウム酸化膜の上に第１のゲート電極が形成されていることを特徴とする表示装置。   (1) A display device including a substrate having a display region in which a plurality of pixels are formed, wherein the pixels include a first TFT using a first oxide semiconductor, A first gate insulating film is formed on the first aluminum oxide film. The first gate insulating film is formed of a stacked structure of a first silicon oxide film and a first aluminum oxide film, and is formed on the first aluminum oxide film. A display device, wherein a first gate electrode is formed.

（２）前記第１のゲート電極は第２の酸化物半導体とその上に形成された金属の積層構造で構成されていることを特徴とする（１）に記載の表示装置。   (2) The display device according to (1), wherein the first gate electrode includes a stacked structure of a second oxide semiconductor and a metal formed thereon.

（３）前記第１のシリコン酸化膜の欠陥密度は、ＥＳＲ分析で、１×１０１８（ｓｐｉｎｓ/ｃｍ３）以下であることを特徴とする（１）に記載の表示装置。 (3) The display device according to (1), wherein the defect density of the first silicon oxide film is 1 × 10 18 (spins / cm 3 ) or less by ESR analysis.

（４）前記第１のシリコン酸化膜は、ＴＤＳ分析で、Ｍ/ｚ＝３２において、酸素（Ｏ２）放出量が１００℃乃至２５０℃で１×１０１５（ｍｏｌｅｃ．/ｃｍ２）以上であることを特徴とする（３）に記載の表示装置。 (4) The first silicon oxide film has an oxygen (O 2 ) release amount of 1 × 10 15 (molec./cm 2 ) or more at 100 ° C. to 250 ° C. at M / z = 32 by TDS analysis. (3) The display device according to (3).

液晶表示装置の平面図である。It is a top view of a liquid crystal display device. 図１のＡ−Ａ断面図である。It is AA sectional drawing of FIG. 液晶表示装置の表示領域の断面図である。It is sectional drawing of the display area of a liquid crystal display device. 実施例１を示す断面図である。1 is a cross-sectional view showing Example 1. FIG. 実施例１の第２の態様を示す断面図である。FIG. 3 is a cross-sectional view showing a second mode of Example 1. 実施例１の第３の態様を示す断面図である。FIG. 6 is a cross-sectional view showing a third aspect of Example 1. 実施例２を示す断面図である。6 is a cross-sectional view showing Example 2. FIG. 実施例３を示す断面図である。6 is a cross-sectional view showing Example 3. FIG. 実施例４を示す断面図である。6 is a cross-sectional view showing Example 4. FIG. 実施例４の第２の態様を示す断面図である。10 is a cross-sectional view showing a second aspect of Example 4. FIG. 実施例４の第３の態様を示す断面図である。10 is a cross-sectional view showing a third aspect of Example 4. FIG. 実施例４の第４の態様を示す断面図である。10 is a cross-sectional view showing a fourth aspect of Example 4. FIG. 実施例５を示す断面図である。10 is a cross-sectional view showing Example 5. FIG. 実施例５の第２の態様を示す断面図である。FIG. 10 is a cross-sectional view showing a second aspect of Example 5. 有機ＥＬ表示装置の断面図である。It is sectional drawing of an organic electroluminescence display.

以下、実施例によって本発明の内容を詳細に説明する。   Hereinafter, the contents of the present invention will be described in detail by way of examples.

図１は、本発明が適用される一例としての携帯電話等に使用される液晶表示装置の平面図である。図１において、複数の画素９３が形成されたＴＦＴ基板１０と対向基板４０とがシール材８０によって接着している。ＴＦＴ基板１０と対向基板４０の間に液晶が挟持されている。シール材８０の内側が表示領域９０となっている。表示領域９０において、走査線９１が横方向に延在し、縦方向に配列している。また、映像信号線９２が縦方向に延在し、横方向に配列している。   FIG. 1 is a plan view of a liquid crystal display device used in a mobile phone or the like as an example to which the present invention is applied. In FIG. 1, the TFT substrate 10 on which a plurality of pixels 93 are formed and the counter substrate 40 are bonded together by a sealing material 80. Liquid crystal is sandwiched between the TFT substrate 10 and the counter substrate 40. The inside of the sealing material 80 is a display area 90. In the display area 90, the scanning lines 91 extend in the horizontal direction and are arranged in the vertical direction. The video signal lines 92 extend in the vertical direction and are arranged in the horizontal direction.

走査線９１と映像信号線９２とに囲まれた領域に画素９３が形成されている。各画素９３には画素電極や、画素電極に供給される信号を制御するＴＦＴが形成されている。ＴＦＴ基板１０は対向基板４０よりも大きく形成され、ＴＦＴ基板１０が対向基板４０と重なっていない部分が端子領域となっている。端子領域には、信号を制御するドライバＩＣ９５が搭載されている。また、端子領域には、液晶表示装置に信号や電源を供給するためのフレキシブル配線基板９６が接続している。   Pixels 93 are formed in a region surrounded by the scanning lines 91 and the video signal lines 92. Each pixel 93 is formed with a pixel electrode and a TFT for controlling a signal supplied to the pixel electrode. The TFT substrate 10 is formed larger than the counter substrate 40, and a portion where the TFT substrate 10 does not overlap the counter substrate 40 is a terminal region. A driver IC 95 for controlling signals is mounted in the terminal area. In addition, a flexible wiring board 96 for supplying signals and power to the liquid crystal display device is connected to the terminal area.

図２は図１のＡ−Ａ断面図である。図２において、ＴＦＴ基板１０と対向基板４０が積層されている。液晶層はＴＦＴ基板１０や対向基板４０の厚さに比べてはるかに小さいので、図２では省略されている。ＴＦＴ基板１０が対向基板４０と重なっていない部分が端子領域となっており、この部分にドライバＩＣ９５が搭載され、フレキシブル配線基板９６が接続している。   2 is a cross-sectional view taken along the line AA in FIG. In FIG. 2, the TFT substrate 10 and the counter substrate 40 are laminated. The liquid crystal layer is omitted in FIG. 2 because it is much smaller than the thickness of the TFT substrate 10 and the counter substrate 40. A portion where the TFT substrate 10 does not overlap with the counter substrate 40 is a terminal region, a driver IC 95 is mounted on this portion, and a flexible wiring substrate 96 is connected.

液晶は、自らは発光しないので、ＴＦＴ基板１０の背面にバックライト１０００が配置している。バックライト１０００からの光を画素毎に制御することによって画像を形成している。液晶は偏光光のみを制御できるので、ＴＦＴ基板１０の下側に下偏光板５１０、対向基板４０の上側に上偏光板５２０が貼り付けられている。   Since the liquid crystal itself does not emit light, the backlight 1000 is disposed on the back surface of the TFT substrate 10. An image is formed by controlling light from the backlight 1000 for each pixel. Since the liquid crystal can control only polarized light, the lower polarizing plate 510 is attached to the lower side of the TFT substrate 10, and the upper polarizing plate 520 is attached to the upper side of the counter substrate 40.

図３は、液晶表示装置の表示領域の断面図である。図３において、ＴＦＴ基板１０はガラスあるいは樹脂で形成されている。ＴＦＴ基板１０の上には、ガラスあるいは樹脂からの不純物が半導体層を汚染することを防止するために下地膜１１が形成されている。下地膜１１はシリコン酸化膜（以後ＳｉＯともいう）、シリコン窒化膜（以後ＳｉＮともいう）の積層膜で形成されるが、アルミニウム酸化膜（以後ＡｌＯともいう）等が積層される場合もある。   FIG. 3 is a cross-sectional view of the display area of the liquid crystal display device. In FIG. 3, the TFT substrate 10 is made of glass or resin. A base film 11 is formed on the TFT substrate 10 in order to prevent impurities from glass or resin from contaminating the semiconductor layer. The base film 11 is formed of a stacked film of a silicon oxide film (hereinafter also referred to as SiO) and a silicon nitride film (hereinafter also referred to as SiN), but an aluminum oxide film (hereinafter also referred to as AlO) may be stacked.

下地膜１１の上に例えばＩＧＺＯによる酸化物半導体１２が形成される。酸化物半導体１２を覆ってゲート絶縁膜１３が形成される。本発明では、後で説明するように、ゲート絶縁膜１３の構成が、シリコン酸化膜の上にアルミニウム酸化膜が積層された構成となっている。ゲート絶縁膜１３の上にゲート電極１４が形成される。本発明の実施態様では、後で説明するように、ゲート電極１４が第２の酸化物半導体と金属膜の積層構造となっている。金属膜は、Ｍｏ、Ｗあるいはこれらの合金が好適である。   An oxide semiconductor 12 made of, for example, IGZO is formed on the base film 11. A gate insulating film 13 is formed so as to cover the oxide semiconductor 12. In the present invention, as will be described later, the gate insulating film 13 has a structure in which an aluminum oxide film is stacked on a silicon oxide film. A gate electrode 14 is formed on the gate insulating film 13. In the embodiment of the present invention, the gate electrode 14 has a stacked structure of a second oxide semiconductor and a metal film, as will be described later. The metal film is preferably Mo, W or an alloy thereof.

図３において、ゲート電極１４を形成後、ゲート電極１４をマスクにしてイオンを打ち込むことによって、酸化物半導体１２に欠陥を形成して導電性を付与し、酸化物半導体１２にドレイン領域１２１、ソース領域１２２を形成する。ゲート電極１４及びゲート絶縁膜１３を覆って層間絶縁膜１５が形成されている。層間絶縁膜１５は、シリコン酸化膜により形成されるが、シリコン窒化膜、あるいはシリコン酸化膜とシリコン窒化膜の積層膜でもよい。層間絶縁膜１５およびゲート絶縁膜１３にスルーホールを形成し、ドレイン電極１６あるいはソース電極１７を形成する。ドレイン電極１６は映像信号線と接続し、ソース電極１７はスルーホール２３を介して画素電極２１と接続する。   In FIG. 3, after forming the gate electrode 14, ions are implanted using the gate electrode 14 as a mask, thereby forming defects in the oxide semiconductor 12 and imparting conductivity to the oxide semiconductor 12. Region 122 is formed. An interlayer insulating film 15 is formed so as to cover the gate electrode 14 and the gate insulating film 13. The interlayer insulating film 15 is formed of a silicon oxide film, but may be a silicon nitride film or a laminated film of a silicon oxide film and a silicon nitride film. Through holes are formed in the interlayer insulating film 15 and the gate insulating film 13, and the drain electrode 16 or the source electrode 17 is formed. The drain electrode 16 is connected to the video signal line, and the source electrode 17 is connected to the pixel electrode 21 through the through hole 23.

層間絶縁膜１５、ドレイン電極１６、ソース電極１７等を覆って有機パッシベーション膜１８が形成されている。有機パッシベーション膜１８は平坦化膜を兼ねているので、２乃至４μｍというように厚く形成される。画素電極２１とＴＦＴのソース電極１７を接続するために、有機パッシベーション膜１８にスルーホール２３を形成する。   An organic passivation film 18 is formed so as to cover the interlayer insulating film 15, the drain electrode 16, the source electrode 17, and the like. Since the organic passivation film 18 also serves as a planarizing film, it is formed as thick as 2 to 4 μm. In order to connect the pixel electrode 21 and the TFT source electrode 17, a through hole 23 is formed in the organic passivation film 18.

有機パッシベーション膜１８の上に、平面状にコモン電極１９を形成する。コモン電極１９を覆ってＳｉＮによって容量絶縁膜２０が形成され、容量絶縁膜２０の上に画素電極２１が形成される。コモン電極１９を覆う絶縁膜は画素電極との間に画素容量を形成するので容量絶縁膜２０と呼ばれる。画素電極２１を覆って、液晶を初期配向させるための配向膜２２が形成されている。画素電極２１は平面で視てストライプ状あるいは櫛歯状に形成され、画素電極２１に電圧が印加されると、図３の矢印で示すような電気力線が発生し、これによって液晶分子３０１が回転し、画素におけるバックライトからの光の透過率が制御される。   On the organic passivation film 18, a common electrode 19 is formed in a planar shape. A capacitive insulating film 20 is formed of SiN so as to cover the common electrode 19, and a pixel electrode 21 is formed on the capacitive insulating film 20. The insulating film covering the common electrode 19 forms a pixel capacitance between the pixel electrode and is called a capacitive insulating film 20. An alignment film 22 for initial alignment of the liquid crystal is formed so as to cover the pixel electrode 21. The pixel electrode 21 is formed in a stripe shape or a comb-like shape when seen in a plan view. When a voltage is applied to the pixel electrode 21, electric lines of force as indicated by arrows in FIG. Rotating, the transmittance of light from the backlight in the pixel is controlled.

図３において、液晶層３００を挟んで対向基板４０が配置されている。対向基板４０において、画素電極に対応してカラーフィルタ４１が形成され、カラー画像を形成可能としている。また、カラーフィルタ４１とカラーフィルタ４１の間にブラックマトリクス４２が形成され、画像のコントラストを向上させる。カラーフィルタ４１およびブラックマトリクス４２を覆ってオーバーコート膜４３が形成されている。オーバーコート膜４３は、カラーフィルタ４１を構成する色素が液晶層３００中に溶け出すのを防止する。オーバーコート膜４３を覆って配向膜４４が形成されている。   In FIG. 3, the counter substrate 40 is disposed with the liquid crystal layer 300 interposed therebetween. In the counter substrate 40, a color filter 41 is formed corresponding to the pixel electrode, so that a color image can be formed. In addition, a black matrix 42 is formed between the color filter 41 and the color filter 41 to improve the contrast of the image. An overcoat film 43 is formed to cover the color filter 41 and the black matrix 42. The overcoat film 43 prevents the dye constituting the color filter 41 from dissolving into the liquid crystal layer 300. An alignment film 44 is formed so as to cover the overcoat film 43.

図４は、本発明の実施例１を示す断面図である。図４において、下地膜１１を構成するＳｉＯとＳｉＮの積層膜の上に例えばＩＧＺＯで形成された第１の酸化物半導体１２が形成されている。第１の酸化物半導体１２の厚さは１０ｎｍ乃至７０ｎｍである。第１の酸化物半導体１２を覆ってゲート絶縁膜１３が形成されている。ゲート絶縁膜１３はシリコン酸化膜１３１と第１のアルミニウム酸化膜１３２の２層構成となっている。ゲート絶縁膜１３を構成するシリコン酸化膜１３１の厚さは例えば５０ｎｍ乃至２００ｎｍであり、これを覆うアルミニウム酸化膜１３２の厚さは例えば１ｎｍ乃至２０ｎｍである。   FIG. 4 is a cross-sectional view showing Example 1 of the present invention. In FIG. 4, a first oxide semiconductor 12 made of, for example, IGZO is formed on a laminated film of SiO and SiN constituting the base film 11. The thickness of the first oxide semiconductor 12 is 10 nm to 70 nm. A gate insulating film 13 is formed so as to cover the first oxide semiconductor 12. The gate insulating film 13 has a two-layer structure of a silicon oxide film 131 and a first aluminum oxide film 132. The thickness of the silicon oxide film 131 constituting the gate insulating film 13 is, for example, 50 nm to 200 nm, and the thickness of the aluminum oxide film 132 covering the silicon oxide film 131 is, for example, 1 nm to 20 nm.

図４において、第１のアルミニウム酸化膜１３２の上にゲート電極１４が形成されているが、図４におけるゲート電極１４は、第２の酸化物半導体１４１と金属層１４２の２層構造となっている。金属層１４２は例えば、Ｍｏ、Ｗあるいはこれらの合金である。第２の酸化物半導体１４１は例えばＩＧＺＯで形成されている。第２の酸化物半導体１４１と第１の酸化物半導体１２は、同じ材料でなくともよいが、同じ材料であればプロセスが簡単になる。第２の酸化物半導体１４１の厚さは１乃至３０ｎｍである。   In FIG. 4, the gate electrode 14 is formed on the first aluminum oxide film 132, but the gate electrode 14 in FIG. 4 has a two-layer structure of the second oxide semiconductor 141 and the metal layer 142. Yes. The metal layer 142 is, for example, Mo, W, or an alloy thereof. The second oxide semiconductor 141 is made of, for example, IGZO. The second oxide semiconductor 141 and the first oxide semiconductor 12 do not have to be the same material, but the process is simplified if they are the same material. The thickness of the second oxide semiconductor 141 is 1 to 30 nm.

酸化物半導体１２を用いたＴＦＴは、ゲート絶縁膜１３から酸素を酸化物半導体１２に供給することによって特性が維持されている。ゲート絶縁膜１３から酸素を酸化物半導体１２に供給するためには、ゲート絶縁膜１３に欠陥を多くしておく必要がある。しかし、欠陥の多いゲート絶縁膜１３には、プロセスで用いたガス等が吸収されやすく、酸化物半導体１２の信頼性を損ねる。   The characteristics of the TFT using the oxide semiconductor 12 are maintained by supplying oxygen from the gate insulating film 13 to the oxide semiconductor 12. In order to supply oxygen from the gate insulating film 13 to the oxide semiconductor 12, the gate insulating film 13 needs to have many defects. However, the gate insulating film 13 with many defects easily absorbs gas used in the process, which impairs the reliability of the oxide semiconductor 12.

本発明の特徴は、ゲート絶縁膜１３として欠陥の少ないシリコン酸化膜１３１を用い、シリコン酸化膜１３１の上にアルミニウム酸化膜１３２を形成していることである。このような構成とすることによって、アルミニウム酸化膜１３２からシリコン酸化膜１３１を通して酸化物半導体１２に酸素が供給されるので、酸化物半導体１２の特性を安定して維持することが出来る。   A feature of the present invention is that a silicon oxide film 131 with few defects is used as the gate insulating film 13 and an aluminum oxide film 132 is formed on the silicon oxide film 131. With such a structure, oxygen is supplied from the aluminum oxide film 132 to the oxide semiconductor 12 through the silicon oxide film 131, so that the characteristics of the oxide semiconductor 12 can be stably maintained.

本実施例では、さらに、ゲート電極１４を構成する下層に第２の酸化物半導体１４１を用いることによって、第２の酸化物半導体１４１からＴＦＴを構成する第１の酸化物半導体１２に酸素が供給される。また、第２の酸化物半導体１４１を形成する時に基板のアニールを行うが、この時にアルミニウム酸化膜１３２から放出される酸素がＴＦＴを構成する第１の酸化物半導体１２に供給されることになる。したがって、本発明によれば、ゲート絶縁膜１３として欠陥の少ないシリコン酸化膜１３１を用いても、酸化物半導体１２の特性を維持することが出来るので、酸化物半導体１２を用いたＴＦＴの信頼性を向上させることが出来る。   In this example, oxygen is supplied from the second oxide semiconductor 141 to the first oxide semiconductor 12 constituting the TFT by using the second oxide semiconductor 141 in the lower layer constituting the gate electrode 14. Is done. The substrate is annealed when the second oxide semiconductor 141 is formed. At this time, oxygen released from the aluminum oxide film 132 is supplied to the first oxide semiconductor 12 constituting the TFT. . Therefore, according to the present invention, the characteristics of the oxide semiconductor 12 can be maintained even when the silicon oxide film 131 with few defects is used as the gate insulating film 13. Therefore, the reliability of the TFT using the oxide semiconductor 12 can be maintained. Can be improved.

本発明におけるゲート絶縁膜１３を構成するシリコン酸化膜１３１の特性は次のとおりである。第１に欠陥密度が小さいことであり、具体的にはＥＳＲ（Ｅｌｅｃｔｒｏｎ Ｓｐｉｎ Ｒｅｓｏｎａｎｃｅ）分析で、１×１０１８（ｓｐｉｎｓ/ｃｍ３）以下である。ＥＳＲの測定条件は、測定温度：85K.、μ波パワー：10[mW]、磁場の向き：膜面と平行、磁場範囲：317±25[mT]、変調幅：0.5[mT]、変調周波数：100[kHz]、時定数：0.03[s]で行った。第２に、酸素の供給量は酸化物半導体の特性を維持するのに十分な量でなければならない。具体的には、ＴＤＳ（Ｔｈｅｒｍａｌ Ｄｅｓｏｒｐｔｉｏｎ Ｓｐｅｃｔｒｏｍｅｔｒｙ）分析で、Ｍ/ｚ＝３２において、酸素（Ｏ２）放出量が１００℃乃至２５０℃で１×１０１５（ｍｏｌｅｃ．/ｃｍ２）以上である。第１の特性と第２の特性を同時に満足する構成は従来では実現することができなかった。 The characteristics of the silicon oxide film 131 constituting the gate insulating film 13 in the present invention are as follows. First, the defect density is small. Specifically, the defect density is 1 × 10 18 (spins / cm 3 ) or less in ESR (Electron Spin Resonance) analysis. The measurement conditions of ESR are: measurement temperature: 85 K., μ wave power: 10 [mW], magnetic field direction: parallel to the film surface, magnetic field range: 317 ± 25 [mT], modulation width: 0.5 [mT], modulation frequency : 100 [kHz], time constant: 0.03 [s]. Second, the amount of oxygen supply must be sufficient to maintain the properties of the oxide semiconductor. Specifically, in TDS (Thermal Desorption Spectrometry) analysis, at M / z = 32, the oxygen (O 2 ) release amount is 1 × 10 15 (molec./cm 2 ) or more at 100 to 250 ° C. A configuration that satisfies the first characteristic and the second characteristic at the same time cannot be realized in the past.

第３に、酸素以外のガスの放出が小さいことである。ＴＦＴ基板は色々なプロセスを通過するが、膜欠陥が多いと、この欠陥にプロセスガスが含まれてしまい、このガスが酸化物半導体の特性に悪影響を及ぼし、信頼性を低下させる。したがって、膜欠陥の小さいシリコン酸化膜１３１を用いることによって、酸化物半導体１２を用いたＴＦＴの信頼性を向上させることが出来る。   Third, the release of gases other than oxygen is small. The TFT substrate passes through various processes. However, if there are many film defects, a process gas is contained in the defects, and this gas adversely affects the characteristics of the oxide semiconductor and decreases the reliability. Therefore, by using the silicon oxide film 131 having a small film defect, the reliability of the TFT using the oxide semiconductor 12 can be improved.

具体的には、プロセスにおいて晒されるガスのうち、Ｎ２Ｏを例にとって評価すると、次のとおりである。ＴＤＳでＭ/ｚ＝４４において、Ｎ２Ｏの放出量が１００℃乃至４００℃で８×１０１３（ｍｏｌｅｃ．/ｃｍ２）以下である。 Specifically, of the gases exposed in the process, N 2 O is evaluated as an example as follows. When T / M is M / z = 44, the amount of N 2 O released is 8 × 10 13 (molec./cm 2 ) or less at 100 to 400 ° C.

以上の特性は、表示装置が完成した状態におけるシリコン酸化膜１３１の特性である。完成品におけるシリコン酸化膜１３１の特性を測定するには、図４において、ゲート絶縁膜１３を構成するシリコン酸化膜１３１よりも上側の層を除去してＥＳＲ分析やＴＤＳ分析を行えばよい。   The above characteristics are the characteristics of the silicon oxide film 131 when the display device is completed. In order to measure the characteristics of the silicon oxide film 131 in the finished product, ESR analysis and TDS analysis may be performed by removing the layer above the silicon oxide film 131 constituting the gate insulating film 13 in FIG.

図４において、下地膜１１はＳｉＮ、ＳｉＯの２層となっている。最下層はＳｉＮ、上層はＳｉＯである。ＳｉＮは特に水分に対するブロック性に優れているので、必須の層であるが、酸化物半導体１２を還元する水素の供給源になる。このために、ＳｉＮの上にＳｉＯを積層している。ＳｉＯ、ＳｉＮの積層膜は、ＣＶＤを用いて連続して行うことが出来る。   In FIG. 4, the base film 11 has two layers of SiN and SiO. The lowermost layer is SiN and the upper layer is SiO. Since SiN is particularly excellent in blocking property against moisture, it is an essential layer, but serves as a hydrogen supply source for reducing the oxide semiconductor 12. For this purpose, SiO is laminated on SiN. A laminated film of SiO and SiN can be continuously formed using CVD.

この上層のシリコン酸化膜（ＳｉＯ）は酸化物半導体１２と直接接触するので、特性を制御する必要がある。具体的な特性は、ゲート絶縁膜１３におけるＳｉＯと同じである。第１に欠陥密度が小さいことであり、具体的にはＥＳＲ（Ｅｌｅｃｔｒｏｎ Ｓｐｉｎ Ｒｅｓｏｎａｎｃｅ）分析で、１×１０１８（ｓｐｉｎｓ/ｃｍ３）以下である。なお、層間絶縁膜１５の欠陥密度はＥＳＲ（Ｅｌｅｃｔｒｏｎ Ｓｐｉｎ Ｒｅｓｏｎａｎｃｅ）分析で、１×１０１８（ｓｐｉｎｓ/ｃｍ３）以上であった。第２に、酸素の供給量は酸化物半導体の特性を維持するのに十分な量でなければならない。具体的には、ＴＤＳ（Ｔｈｅｒｍａｌ Ｄｅｓｏｒｐｔｉｏｎ Ｓｐｅｃｔｒｏｍｅｔｒｙ）分析で、Ｍ/ｚ＝３２において、酸素（Ｏ２）放出量が１００℃乃至２５０℃で１×１０１５（ｍｏｌｅｃ．/ｃｍ２）以上である。第３に酸素以外のガスの放出が小さいことであり、Ｎ２Ｏを例にとった場合、ＴＤＳ分析で、Ｍ/ｚ＝４４において、Ｎ２Ｏの放出量が１００℃乃至４００℃で８×１０１３（ｍｏｌｅｃ．/ｃｍ２）以下である。 Since the upper silicon oxide film (SiO) is in direct contact with the oxide semiconductor 12, it is necessary to control the characteristics. Specific characteristics are the same as those of SiO in the gate insulating film 13. First, the defect density is small. Specifically, the defect density is 1 × 10 18 (spins / cm 3 ) or less in ESR (Electron Spin Resonance) analysis. Note that the defect density of the interlayer insulating film 15 was 1 × 10 18 (spins / cm 3 ) or more by ESR (Electron Spin Resonance) analysis. Second, the amount of oxygen supply must be sufficient to maintain the properties of the oxide semiconductor. Specifically, in TDS (Thermal Desorption Spectrometry) analysis, at M / z = 32, the oxygen (O 2 ) release amount is 1 × 10 15 (molec./cm 2 ) or more at 100 to 250 ° C. Third, the release of gases other than oxygen is small. When N 2 O is taken as an example, the TDS analysis shows that the release amount of N 2 O is 8 at 100 ° C. to 400 ° C. at M / z = 44. × 10 13 (molec./cm 2 ) or less.

下地膜１１におけるシリコン酸化膜（ＳｉＯ）に対する測定方法も、ゲート絶縁膜１３におけるシリコン酸化膜（ＳｉＯ）に対する測定方法と同じであって、測定するシリコン酸化膜（ＳｉＯ）より上の層を除去し、露出したシリコン酸化膜（ＳｉＯ）に対してＥＲＳ分析やＴＤＳ分析を行えばよい。   The measurement method for the silicon oxide film (SiO) in the base film 11 is the same as the measurement method for the silicon oxide film (SiO) in the gate insulating film 13, and the layer above the silicon oxide film (SiO) to be measured is removed. Then, ERS analysis or TDS analysis may be performed on the exposed silicon oxide film (SiO).

図５は本実施例における第２の態様を示す断面図である。図５が図４と異なる点は、下地膜１１に第２のアルミニウム酸化膜１１２が追加されていることである。第２のアルミニウム酸化膜１１２の膜厚も１ｎｍ乃至２０ｎｍでよい。図５において、下地膜はＳｉＯ、ＳｉＮの積層膜１１１の上に第２のアルミニウム酸化膜１１２が形成されている。ＳｉＯとＳｉＮの積層膜がＳｉＯ/ＳｉＮ/ＳｉＯの３層構造の場合、最上層のＳｉＯの上にアルミニウム酸化膜１１２を積層してもよいし、最上層のＳｉＯに替えてアルミニウム酸化膜１１２を形成してもよい。   FIG. 5 is a cross-sectional view showing a second mode in the present embodiment. FIG. 5 differs from FIG. 4 in that a second aluminum oxide film 112 is added to the base film 11. The film thickness of the second aluminum oxide film 112 may also be 1 nm to 20 nm. In FIG. 5, a second aluminum oxide film 112 is formed on a laminated film 111 of SiO and SiN as a base film. When the laminated film of SiO and SiN has a three-layer structure of SiO / SiN / SiO, an aluminum oxide film 112 may be laminated on the uppermost SiO, or an aluminum oxide film 112 may be used instead of the uppermost SiO. It may be formed.

アルミニウム酸化膜は水分やガスに対するブロック性能がすぐれている上に、酸化物半導体１２に対する酸素の供給源となる。したがって、酸化物半導体１２に対する下地膜としては好適である。一方、アルミニウム酸化膜はシリコン酸化膜等に比べて膜欠陥が多い。したがって、この欠陥部分に吸収されたガス等が酸化物半導体１２に対して悪影響を及ぼす危険がある。しかし、ＴＦＴの動作は、酸化物半導体１２における第１ゲート絶縁膜１３側の特性が支配的になるので、ＴＦＴとして大きな問題になることはない。   The aluminum oxide film has excellent blocking performance against moisture and gas, and also serves as a supply source of oxygen to the oxide semiconductor 12. Therefore, it is suitable as a base film for the oxide semiconductor 12. On the other hand, the aluminum oxide film has more film defects than the silicon oxide film or the like. Therefore, there is a risk that the gas or the like absorbed in the defective portion may adversely affect the oxide semiconductor 12. However, the operation of the TFT does not pose a major problem as the TFT because the characteristics of the oxide semiconductor 12 on the first gate insulating film 13 side are dominant.

図６は、本実施例の第３の形態を示す断面図である。図６が図４と異なる点は、酸化物半導体１２がドレイン電極１６およびソース電極１７と接続する部分において、金属で形成された保護層５０が形成されていることである。ドレイン電極１６およびソース電極１７は層間絶縁膜１５およびゲート絶縁膜１３に形成されたスルーホールに形成されている。スルーホールの形成はドライエッチング等で行われる。酸化物半導体１２の厚さは１０ｎｍ乃至７０ｎｍというように、非常に薄いので、層間絶縁膜１５やゲート絶縁膜１３をエッチングしたときに、同時に除去されてしまう危険がある。   FIG. 6 is a cross-sectional view showing a third mode of this embodiment. 6 differs from FIG. 4 in that a protective layer 50 made of metal is formed in a portion where the oxide semiconductor 12 is connected to the drain electrode 16 and the source electrode 17. The drain electrode 16 and the source electrode 17 are formed in through holes formed in the interlayer insulating film 15 and the gate insulating film 13. Through holes are formed by dry etching or the like. Since the thickness of the oxide semiconductor 12 is very thin, such as 10 nm to 70 nm, when the interlayer insulating film 15 and the gate insulating film 13 are etched, there is a risk that they are removed at the same time.

図６では、酸化物半導体１２がドレイン電極１６あるいはソース電極１７と導通する部分に金属で形成された保護層５０を形成し、酸化物半導体１２がエッチングによって除去されることを防止している。保護層５０を構成する金属は、映像信号線９２を形成する金属と同じ構成でよい。例えば、Ａｌ合金をＴｉ等でサンドイッチした構成である。図６のような構成とすることによって、信頼性の高い、酸化物半導体を用いたＴＦＴを製造することが出来る。   In FIG. 6, a protective layer 50 made of metal is formed in a portion where the oxide semiconductor 12 is electrically connected to the drain electrode 16 or the source electrode 17 to prevent the oxide semiconductor 12 from being removed by etching. The metal constituting the protective layer 50 may be the same as the metal forming the video signal line 92. For example, an Al alloy is sandwiched with Ti or the like. With the structure shown in FIG. 6, a highly reliable TFT using an oxide semiconductor can be manufactured.

図７は本発明の実施例２を示す断面図である。図７が図４と異なる点は、ゲート絶縁膜１３がゲート電極１４の下にのみ形成されていることである。図７において、酸化物半導体１２の上にゲート絶縁膜１３を構成するシリコン酸化膜１３１が形成され、その上にアルミニウム酸化膜１３２が形成されている。シリコン酸化膜１３１およびアルミニウム酸化膜１３２の膜厚は実施例１と同様である。   FIG. 7 is a sectional view showing Embodiment 2 of the present invention. 7 differs from FIG. 4 in that the gate insulating film 13 is formed only under the gate electrode 14. In FIG. 7, a silicon oxide film 131 constituting the gate insulating film 13 is formed on the oxide semiconductor 12, and an aluminum oxide film 132 is formed thereon. The film thicknesses of the silicon oxide film 131 and the aluminum oxide film 132 are the same as those in the first embodiment.

図７において、シリコン酸化膜１３１およびアルミニウム酸化膜１３２はゲート電極１３の下以外の部分では除去されている。図７のメリットは次のとおりである。酸化物半導体１２は、チャネル部以外の領域は導電性を持つ必要がある。このために、図４の構成では、ゲート電極１４をマスクとしてイオンインプランテーションを行って結晶欠陥を形成して導電性を付与する必要がある。   In FIG. 7, the silicon oxide film 131 and the aluminum oxide film 132 are removed at portions other than under the gate electrode 13. The advantages of FIG. 7 are as follows. The oxide semiconductor 12 needs to have conductivity in a region other than the channel portion. Therefore, in the configuration shown in FIG. 4, it is necessary to provide conductivity by forming crystal defects by ion implantation using the gate electrode 14 as a mask.

図７の構成によれば、ゲート絶縁膜１３がゲート電極１４の下以外において除去された後は、酸化物半導体１２が露出した状態になる。この状態において、例えばシラン（ＳｉＨ４）を通すことによって、酸化物半導体１２を還元し、導電性を付与することが出来る。あるいは、酸化物半導体１２が露出した状態において、ＡｒプラズマあるいはＮ２プラズマにさらすことによって、酸化物半導体１２に欠陥を与え、導電性を付与することが出来る。したがって、本実施例の構成によればイオンインプランテーションを用いなくとも、酸化物半導体１２に必要な特性を与えることが出来る。 According to the configuration of FIG. 7, the oxide semiconductor 12 is exposed after the gate insulating film 13 is removed except under the gate electrode 14. In this state, for example, by passing silane (SiH 4 ), the oxide semiconductor 12 can be reduced and conductivity can be imparted. Alternatively, when the oxide semiconductor 12 is exposed, exposure to Ar plasma or N 2 plasma can impart defects to the oxide semiconductor 12 and impart conductivity. Therefore, according to the structure of this embodiment, necessary characteristics can be given to the oxide semiconductor 12 without using ion implantation.

図７において、酸化物半導体１２の必要な部分に導電性を付与した後、従来と同様に層間絶縁膜間１５をＳｉＯまたはＳｉＮ、あるいはＳｉＯおよびＳｉＮの積層膜によって形成する。下地膜１１に第２のアルミニウム酸化膜を用いてもよいこと、酸化物半導体１２のドレイン領域、ソース領域に金属による保護層を用いてもよいことは実施例１と同様である。酸化物半導体を用いたＴＦＴの性能は実施例１と同様である。   In FIG. 7, after providing conductivity to a necessary portion of the oxide semiconductor 12, the interlayer insulating film 15 is formed by SiO or SiN or a laminated film of SiO and SiN as in the conventional case. As in the first embodiment, a second aluminum oxide film may be used for the base film 11 and a protective layer made of metal may be used for the drain region and the source region of the oxide semiconductor 12. The performance of a TFT using an oxide semiconductor is the same as that of Example 1.

図８は実施例３を示す断面図である。図８が実施例１の図４と異なる点は、ゲート電極１４が金属のみで形成されており、第２の酸化物半導体は存在していないことである。この場合は、第２のアルミニウム酸化膜１３２が酸化物半導体１２に対する酸素の供給源となる。したがって、ゲート絶縁膜１３を構成するシリコン酸化膜１３１も欠陥の少ない膜とすることが出来る。   FIG. 8 is a cross-sectional view showing the third embodiment. FIG. 8 is different from FIG. 4 of the first embodiment in that the gate electrode 14 is formed of only metal and the second oxide semiconductor does not exist. In this case, the second aluminum oxide film 132 serves as a supply source of oxygen to the oxide semiconductor 12. Therefore, the silicon oxide film 131 constituting the gate insulating film 13 can also be a film having few defects.

すなわち、アルミニウム酸化膜１３２は酸化物半導体１２に対する酸素の供給源になると同時に酸化物半導体１２側に酸素を閉じ込める作用もあるので、多くの場合、酸化物半導体１２の特性と信頼性を維持することが出来る。   That is, the aluminum oxide film 132 serves as a supply source of oxygen to the oxide semiconductor 12 and also has an effect of confining oxygen on the oxide semiconductor 12 side. Therefore, in many cases, the characteristics and reliability of the oxide semiconductor 12 are maintained. I can do it.

本実施例においても、下地膜１１に第２のアルミニウム酸化膜を用いてもよいこと、酸化物半導体１２のドレイン領域、ソース領域に金属による保護層を用いてもよいことは実施例１と同様である。また、実施例２の構成も併用することが出来る。   Also in this embodiment, the second aluminum oxide film may be used for the base film 11 and a metal protective layer may be used for the drain region and the source region of the oxide semiconductor 12 as in the first embodiment. It is. Moreover, the structure of Example 2 can also be used together.

図９は実施例４を示す断面図である。酸化物半導体１２を用いたＴＦＴのＯＮ電流は、ａ−Ｓｉを用いたＴＦＴのＯＮ電流の１０倍程度とすることが出来る。しかし、Ｐｏｌｙ−Ｓｉを用いたＴＦＴのＯＮ電流には及ばない。酸化物半導体１２を用いたＴＦＴのＯＮ電流を増やす方法としてデュアルゲート方式を用いることが出来る。   FIG. 9 is a cross-sectional view showing the fourth embodiment. The ON current of the TFT using the oxide semiconductor 12 can be about 10 times the ON current of the TFT using a-Si. However, it does not reach the ON current of TFTs using Poly-Si. As a method for increasing the ON current of the TFT using the oxide semiconductor 12, a dual gate method can be used.

図９はその構成を示す断面図である。図９において、ＴＦＴ基板１０の上に第２ゲート電極６０が形成され、第２ゲート電極６０を覆って第２ゲート絶縁膜６１が形成されている。第２ゲート絶縁膜６１の上にＴＦＴを構成する第１の酸化物半導体１２が形成されている。第１の酸化物半導体１２よりも上の層は実施例１における図４と同様である。   FIG. 9 is a cross-sectional view showing the configuration. In FIG. 9, a second gate electrode 60 is formed on the TFT substrate 10, and a second gate insulating film 61 is formed to cover the second gate electrode 60. A first oxide semiconductor 12 constituting a TFT is formed on the second gate insulating film 61. The layers above the first oxide semiconductor 12 are the same as those in FIG.

図９の構成によれば、酸化物半導体１２の上側と下側において電流を流すことが出来るので、ＯＮ電流を増大することが出来る。図９において、第２ゲート絶縁膜６１はシリコン酸化膜であり、第２ゲート電極６０は金属であり、例えばＭｏまたはＷ、あるいは、これらの合金である。第２ゲート絶縁膜６１はシリコン窒化膜とシリコン酸化膜との積層でもよい。その場合はシリコン窒化膜が下層、シリコン酸化膜が上層となる。   According to the configuration of FIG. 9, since the current can flow on the upper side and the lower side of the oxide semiconductor 12, the ON current can be increased. In FIG. 9, the second gate insulating film 61 is a silicon oxide film, and the second gate electrode 60 is a metal, for example, Mo or W, or an alloy thereof. The second gate insulating film 61 may be a stacked layer of a silicon nitride film and a silicon oxide film. In that case, the silicon nitride film is the lower layer and the silicon oxide film is the upper layer.

図１０は、図９の構造に対して、酸化物半導体１２のドレイン領域およびソース領域に保護層５０を形成したものである。層間絶縁膜１５およびゲート絶縁膜１３にスルーホールを形成する時に酸化物半導体１２が消失することを防止するという効果は実施例１の図６で説明したのと同様である。   FIG. 10 shows a structure in which a protective layer 50 is formed in the drain region and the source region of the oxide semiconductor 12 in the structure of FIG. The effect of preventing the oxide semiconductor 12 from disappearing when forming a through hole in the interlayer insulating film 15 and the gate insulating film 13 is the same as that described in FIG.

図１１は、本実施例における他の態様を示す断面図である。図１１は、酸化物半導体１２の第２ゲート電極６０側においても、信頼性を向上したＴＦＴとするめに、第２ゲート絶縁膜６１をシリコン酸化膜６１２と第３アルミニウム酸化膜６１１の２層構成とし、第２ゲート電極６０を金属６０１と第３酸化物半導体６０２の２層構成としたものである。   FIG. 11 is a cross-sectional view showing another aspect of the present embodiment. FIG. 11 shows that the second gate insulating film 61 includes a silicon oxide film 612 and a third aluminum oxide film 611 on the second gate electrode 60 side of the oxide semiconductor 12 in order to obtain a TFT with improved reliability. The second gate electrode 60 has a two-layer structure of a metal 601 and a third oxide semiconductor 602.

すなわち、図１１において、第２ゲート電極６０を覆って第３アルミニウム酸化膜６１１が形成され、その上にシリコン酸化膜６１２が形成されている。また、第２ゲート電極は、ＭｏＷ等の金属６０１の上に酸化物半導体６０３が形成されている構成である。各層の膜厚等は第１ゲート電極側と同様である。   That is, in FIG. 11, a third aluminum oxide film 611 is formed to cover the second gate electrode 60, and a silicon oxide film 612 is formed thereon. The second gate electrode has a structure in which an oxide semiconductor 603 is formed over a metal 601 such as MoW. The thickness of each layer is the same as that on the first gate electrode side.

図１２は、図１１の構成において、第２ゲート電極６０から酸化物半導体６０２を省略した構成である。この構成の作用効果は実施例３で説明したのと同様である。図１１および図１２の構成によれば、さらに信頼性を向上させたデュアルゲート方式の酸化物半導体ＴＦＴを実現することが出来る。なお、図１１および図１２においても、図１０で示したように、酸化物半導体１２のドレイン領域、ソース領域に保護層５０を設け、酸化物半導体の消失を防止する構成とすることが出来る。   12 is a configuration in which the oxide semiconductor 602 is omitted from the second gate electrode 60 in the configuration of FIG. The operational effect of this configuration is the same as that described in the third embodiment. 11 and 12, it is possible to realize a dual gate type oxide semiconductor TFT with further improved reliability. 11 and 12, as illustrated in FIG. 10, the protective layer 50 can be provided in the drain region and the source region of the oxide semiconductor 12 to prevent the oxide semiconductor from disappearing.

Ｐｏｌｙ−Ｓｉはキャリアの移動度が高いので、ＴＦＴを高速動作させることが出来る。一方、酸化物半導体はリーク電流が小さいので、これを用いたＴＦＴはスイッチング素子として好適である。したがって、Ｐｏｌｙ−ＳｉＴＦＴと酸化物半導体ＴＦＴを併用することによって、性能の高い表示装置を実現することが出来る。例えば、Ｐｏｌｙ−ＳｉＴＦＴを駆動回路に用い、酸化物半導体ＴＦＴを画素におけるスイッチングＴＦＴとして用いることが出来る。   Since Poly-Si has high carrier mobility, the TFT can be operated at high speed. On the other hand, since an oxide semiconductor has a small leakage current, a TFT using the oxide semiconductor is suitable as a switching element. Therefore, a display device with high performance can be realized by using a Poly-Si TFT and an oxide semiconductor TFT in combination. For example, a Poly-Si TFT can be used as a driving circuit, and an oxide semiconductor TFT can be used as a switching TFT in a pixel.

図１３は、Ｐｏｌｙ−ＳｉによるＴＦＴと酸化物半導体によるＴＦＴが併存している、本発明の実施例５を示す断面図である。このような構成をハイブリッド構成と呼ぶ。図１３に示す酸化物半導体ＴＦＴはデュアルゲート方式である。図１３において、ＴＦＴ基板１０の上に下地膜１１が形成されている。下地膜１１の構成は実施例１で説明したと同じ構成を用いることが出来る。   FIG. 13 is a cross-sectional view showing a fifth embodiment of the present invention in which a TFT made of Poly-Si and a TFT made of an oxide semiconductor coexist. Such a configuration is called a hybrid configuration. The oxide semiconductor TFT illustrated in FIG. 13 is a dual gate method. In FIG. 13, a base film 11 is formed on the TFT substrate 10. The configuration of the base film 11 can be the same as that described in the first embodiment.

下地膜１１の上にまず、Ｐｏｌｙ−Ｓｉ７０が形成される。Ｐｏｌｙ−Ｓｉ７０は、まず、ａ−Ｓｉ膜を形成し、これにエキシマレーザを照射してＰｏｌｙ−Ｓｉに変換し、パターニングしたものである。Ｐｏｌｙ−Ｓｉ７０を覆って第３ゲート絶縁膜７１が形成される。第３ゲート絶縁膜７１は、例えば、ＴＥＯＳ（Ｔｅｔｒａｅｔｈｙｌ ｏｒｔｈｏｓｉｌｉｃａｔｅ）を材料としたＣＶＤで形成することが出来る。   First, Poly-Si 70 is formed on the base film 11. Poly-Si 70 is formed by first forming an a-Si film, irradiating it with excimer laser, converting it into Poly-Si, and patterning. A third gate insulating film 71 is formed to cover the Poly-Si 70. The third gate insulating film 71 can be formed by, for example, CVD using TEOS (Tetraethyl orthosilicate) as a material.

第３ゲート絶縁膜７１の上に酸化物半導体ＴＦＴの第２ゲート電極６０を形成する。同時にＰｏｌｙ−Ｓｉを用いたＴＦＴのゲート電極（第３ゲート電極）７２も形成する。その後、第２ゲート電極６０および第３ゲート電極７２を覆って、酸化物半導体１２の第２ゲート絶縁膜となるシリコン酸化膜６１を形成する。その上に酸化物半導体１２を形成する。   A second gate electrode 60 of the oxide semiconductor TFT is formed on the third gate insulating film 71. At the same time, a TFT gate electrode (third gate electrode) 72 using Poly-Si is also formed. Thereafter, a silicon oxide film 61 serving as a second gate insulating film of the oxide semiconductor 12 is formed so as to cover the second gate electrode 60 and the third gate electrode 72. An oxide semiconductor 12 is formed thereon.

酸化物半導体１２を覆ってシリコン酸化膜１３１とアルミニウム酸化膜１３２で構成されるゲート絶縁膜１３を形成し、その上に第２酸化物半導体１４１と金属１４２で構成されるゲート電極１４を形成することは実施例１で説明したとおりである。なお、実施例１で説明したように、第１ゲート絶縁膜１３を第１ゲート電極１４の下にのみ形成することが出来る。また、第１ゲート電極１４から第２酸化物半導体１４１を省略することが出来る点も実施例１で説明したとおりである。   A gate insulating film 13 composed of a silicon oxide film 131 and an aluminum oxide film 132 is formed to cover the oxide semiconductor 12, and a gate electrode 14 composed of a second oxide semiconductor 141 and a metal 142 is formed thereon. This is as described in the first embodiment. As described in Embodiment 1, the first gate insulating film 13 can be formed only under the first gate electrode 14. In addition, as described in the first embodiment, the second oxide semiconductor 141 can be omitted from the first gate electrode 14.

図１３において、ドレイン電極１６とソース電極１７は酸化物半導体ＴＦＴとＰｏｌｙ−ＳｉＴＦＴで同時に形成される。つまり、ドレイン電極１６、ソース電極１７が形成されるスルーホールは酸化物半導体ＴＦＴ側とＰｏｌｙ−ＳｉＴＦＴ側とで同時に形成される。   In FIG. 13, the drain electrode 16 and the source electrode 17 are simultaneously formed of an oxide semiconductor TFT and a Poly-Si TFT. That is, the through hole in which the drain electrode 16 and the source electrode 17 are formed is simultaneously formed on the oxide semiconductor TFT side and the Poly-Si TFT side.

図１３に示すように、Ｐｏｌｙ−Ｓｉ７０側ではスルーホールは５層の絶縁膜に対して形成されるのに対して、酸化物半導体１２側ではスルーホールは３層の絶縁膜に対して形成される。したがって、酸化物半導体ＴＦＴ側においては、酸化物半導体１２がエッチング液にさらされる時間が長くなるので、酸化物半導体１２が消失しやすい。   As shown in FIG. 13, the through-hole is formed for the five-layer insulating film on the Poly-Si 70 side, whereas the through-hole is formed for the three-layer insulating film on the oxide semiconductor 12 side. The Therefore, on the oxide semiconductor TFT side, the time during which the oxide semiconductor 12 is exposed to the etching solution becomes long, and thus the oxide semiconductor 12 tends to disappear.

加えて、Ｐｏｌｙ−Ｓｉ７０側においては、スルーホールを形成した後、弗酸ＨＦで洗浄する必要がある。この時、酸化物半導体１２も弗酸ＨＦにさらされる。酸化物半導体１２は弗酸ＨＦにさらされると容易に消失する。   In addition, on the Poly-Si 70 side, it is necessary to clean with hydrofluoric acid HF after forming a through hole. At this time, the oxide semiconductor 12 is also exposed to hydrofluoric acid HF. The oxide semiconductor 12 easily disappears when exposed to hydrofluoric acid HF.

図１４は、この問題を対策したハイブリッド方式のＴＦＴである。図１４が図１３と異なる点は、酸化物半導体１２のドレイン領域とソース領域に金属による保護層５０が形成されていることである。酸化物半導体１２側のＴＦＴのこの構成は、実施例４における図１２と同じ構成である。   FIG. 14 shows a hybrid TFT in which this problem is countered. FIG. 14 is different from FIG. 13 in that a protective layer 50 made of metal is formed in the drain region and the source region of the oxide semiconductor 12. This configuration of the TFT on the oxide semiconductor 12 side is the same as that in FIG.

図１３および図１４の構成は、酸化物半導体を用いたＴＦＴはデュアルゲート方式であるが、これに限らず、酸化物半導体を用いたＴＦＴが図４乃至図８に示すようなシングルゲートの場合であっても、本発明を適用することが出来る。このように、本実施例によれば、特性がすぐれ、かつ、信頼性の高いハイブリッドタイプのＴＦＴを実現することが出来る。   13 and 14, the TFT using an oxide semiconductor is a dual gate method, but the present invention is not limited to this, and the TFT using an oxide semiconductor is a single gate as shown in FIGS. Even so, the present invention can be applied. Thus, according to the present embodiment, a hybrid type TFT having excellent characteristics and high reliability can be realized.

実施例１乃至５では図１乃至３に示すような液晶表示装置について説明した。しかし、本発明は、液晶表示装置に限らず、有機ＥＬ表示装置についても同様に適用することが出来る。図１５は、有機ＥＬ表示装置の表示領域の断面図である。図１５において、ＴＦＴ基板１０の上にＴＦＴが形成され、その上に有機パッシベーション膜１８が形成され、有機パッシベーション膜１８にスルーホールが形成されるまでは液晶表示装置における図３と同様である。   In Examples 1 to 5, the liquid crystal display device as shown in FIGS. 1 to 3 was described. However, the present invention is not limited to the liquid crystal display device and can be similarly applied to an organic EL display device. FIG. 15 is a cross-sectional view of the display area of the organic EL display device. In FIG. 15, the TFT is formed on the TFT substrate 10, the organic passivation film 18 is formed thereon, and the process is the same as that of FIG. 3 in the liquid crystal display device until the through hole is formed in the organic passivation film 18.

したがって、実施例１乃至５において説明した酸化物半導体ＴＦＴの構成はそのまま有機ＥＬ表示装置について適用することが出来る。   Therefore, the structure of the oxide semiconductor TFT described in Examples 1 to 5 can be applied to an organic EL display device as it is.

図１５において、有機パッシベーション膜１８の上に反射電極３０が形成され、その上にアノード３１となるＩＴＯ（Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ）等による酸化物導電膜が形成されている。アノード３１や有機パッシベーション膜１８を覆ってアクリル等の有機材料によるバンク３２が形成されている。バンク３２のホール部分において、アノード３１の上に発光層としての有機ＥＬ層３３が形成されている、有機ＥＬ層３３は複数の層から形成されているが、全部合わせても数百ｎｍであり、非常に薄い。バンク３２は有機ＥＬ層３３がアノード３１や反射電極３０によって段切れを生ずることを防止する。   In FIG. 15, a reflective electrode 30 is formed on the organic passivation film 18, and an oxide conductive film made of ITO (Indium Tin Oxide) or the like to be the anode 31 is formed thereon. A bank 32 made of an organic material such as acrylic is formed so as to cover the anode 31 and the organic passivation film 18. In the hole portion of the bank 32, an organic EL layer 33 as a light emitting layer is formed on the anode 31, and the organic EL layer 33 is formed of a plurality of layers, but the total is several hundred nm. Very thin. The bank 32 prevents the organic EL layer 33 from being disconnected due to the anode 31 and the reflective electrode 30.

図１５において、有機ＥＬ層３３を覆ってカソード３４となる上部電極がＩＴＯやＩＺＯ（Ｉｎｄｉｕｍ Ｚｉｎｃ Ｏｘｉｄｅ）等の酸化物導電膜あるいは薄い金属膜によって形成される。有機ＥＬ層３３は水分によって分解するので、主に、水分の侵入を防止するために、ＳｉＮ等によって保護膜３５が形成される。   In FIG. 15, the upper electrode which covers the organic EL layer 33 and becomes the cathode 34 is formed of an oxide conductive film such as ITO or IZO (Indium Zinc Oxide) or a thin metal film. Since the organic EL layer 33 is decomposed by moisture, the protective film 35 is mainly formed of SiN or the like in order to prevent moisture from entering.

有機ＥＬ表示装置は反射電極３０を用いているので、外光が反射電極３０によって反射する。そうすると、画面が見づらくなる。これを防止するために、円偏光板３７を表示面に接着材３６等によって貼り付けている。   Since the organic EL display device uses the reflective electrode 30, external light is reflected by the reflective electrode 30. This makes it difficult to see the screen. In order to prevent this, the circularly polarizing plate 37 is attached to the display surface with an adhesive 36 or the like.

このように、有機ＥＬ表示装置であっても、酸化物半導体１２のドレイン電極１６およびソース電極１７を形成するまでは液晶表示装置の場合と同じ構成とすることが出来るので、実施例１乃至５で説明した構成をそのまま適用することが出来る。   Thus, even in the organic EL display device, the same configuration as that of the liquid crystal display device can be used until the drain electrode 16 and the source electrode 17 of the oxide semiconductor 12 are formed. The configuration described in (1) can be applied as it is.

１０…ＴＦＴ基板、 １１…下地膜、 １２…第１酸化物半導体、 １３…第１ゲート絶縁膜、 １４…第１ゲート電極、 １５…層間絶縁膜、 １６…ドレイン電極、 １７…ソース電極、 １８…有機パッシベーション膜、 １９…コモン電極、 ２０…容量絶縁膜、 ２１…画素電極、 ２２…配向膜、 ２３…スルーホール、 ３０…反射電極、 ３１…アノード、 ３２…バンク、 ３３…有機ＥＬ層、 ３４…カソード、 ３５…保護膜、 ３６…接着材、 ３７…円偏光板、 ４０…対向基板、 ４１…カラーフィルタ、 ４２…ブラックマトリクス、 ４３…オーバーコート膜、 ４４…配向膜、 ５０…保護層、 ６０…第２ゲート電極、 ６１…第２ゲート絶縁膜、 ７０…Ｐｏｌｙ−Ｓｉ、 ７１…第３ゲート絶縁膜、 ７２…第３ゲート電極、 ８０…シール材、 ９０…表示領域、 ９１…走査線 、９２…映像信号線、 ９３…画素、 ９５…ドライバＩＣ、 ９６…フレキシブル配線基板、 １１１…ＳｉＯ/ＳｉＮの積層膜、 １１２…第２アルミニウム酸化膜、 １２１…ドレイン領域、 １２２…ソース領域、 １３１…シリコン酸化膜、 １３２…アルミニウム酸化膜、 １４１…第２酸化物半導体、 １４２…金属、 ３００…液晶層、 ３０１…液晶、 ５１０…下偏光板、 ５２０…上偏光板、 ６０１…第３酸化物半導体、 ６０２…金属、 ６１１…第３アルミニウム酸化膜、 ６１２…第２シリコン酸化膜、 １０００…バックライト   DESCRIPTION OF SYMBOLS 10 ... TFT substrate, 11 ... Base film, 12 ... 1st oxide semiconductor, 13 ... 1st gate insulating film, 14 ... 1st gate electrode, 15 ... Interlayer insulating film, 16 ... Drain electrode, 17 ... Source electrode, 18 DESCRIPTION OF SYMBOLS ... Organic passivation film, 19 ... Common electrode, 20 ... Capacitance insulating film, 21 ... Pixel electrode, 22 ... Orientation film, 23 ... Through-hole, 30 ... Reflective electrode, 31 ... Anode, 32 ... Bank, 33 ... Organic EL layer, 34 ... cathode, 35 ... protective film, 36 ... adhesive, 37 ... circularly polarizing plate, 40 ... counter substrate, 41 ... color filter, 42 ... black matrix, 43 ... overcoat film, 44 ... alignment film, 50 ... protective layer 60 ... second gate electrode 61 ... second gate insulating film 70 ... Poly-Si 71 ... third gate insulating film 72 ... third gate electrode Electrode, 80 ... Sealing material, 90 ... Display area, 91 ... Scanning line, 92 ... Video signal line, 93 ... Pixel, 95 ... Driver IC, 96 ... Flexible wiring board, 111 ... Laminated film of SiO / SiN, 112 ... First 2 Aluminum oxide film 121 ... Drain region 122 122 Source region 131 Silicon oxide film 132 Aluminum oxide film 141 Second oxide semiconductor 142 Metal Metal 300 Liquid crystal 301 Liquid crystal 510 Lower polarizing plate, 520 ... Upper polarizing plate, 601 ... Third oxide semiconductor, 602 ... Metal, 611 ... Third aluminum oxide film, 612 ... Second silicon oxide film, 1000 ... Backlight

Claims (20)

複数の画素が形成された表示領域を有する基板を含む表示装置であって、
前記画素は第１の酸化物半導体を用いた第１のＴＦＴを含み、
前記第１の酸化物半導体の上には第１のゲート絶縁膜が形成され、
前記第１のゲート絶縁膜は第１のシリコン酸化膜と第１のアルミニウム酸化膜の積層構造で形成され、
前記第１のアルミニウム酸化膜の上に第１のゲート電極が形成されていることを特徴とする表示装置。 A display device including a substrate having a display region in which a plurality of pixels are formed,
The pixel includes a first TFT using a first oxide semiconductor,
A first gate insulating film is formed on the first oxide semiconductor,
The first gate insulating film is formed of a stacked structure of a first silicon oxide film and a first aluminum oxide film,
A display device, wherein a first gate electrode is formed on the first aluminum oxide film. 前記第１のゲート電極は第２の酸化物半導体とその上に形成された金属の積層構造で構成されていることを特徴とする請求項１に記載の表示装置。   2. The display device according to claim 1, wherein the first gate electrode includes a stacked structure of a second oxide semiconductor and a metal formed thereon. 前記第１のゲート絶縁膜と前記第１のゲート電極を覆って層間絶縁膜が形成され、前記第１のシリコン酸化膜の欠陥密度は前記層間絶縁膜の欠陥密度より低く、ＥＳＲ分析で、１×１０１８（ｓｐｉｎｓ/ｃｍ３）以下であることを特徴とする請求項１に記載の表示装置。 An interlayer insulating film is formed to cover the first gate insulating film and the first gate electrode, and the defect density of the first silicon oxide film is lower than the defect density of the interlayer insulating film. The display device according to claim 1, wherein the display device is not more than × 10 18 (spins / cm 3 ). 前記第１のシリコン酸化膜は、ＴＤＳ分析で、Ｍ/ｚ＝３２において、酸素（Ｏ２）放出量が１００℃乃至２５０℃で１×１０１５（ｍｏｌｅｃ．/ｃｍ２）以上であることを特徴とする請求項３に記載の表示装置。 According to TDS analysis, the first silicon oxide film has an oxygen (O 2 ) release amount of 1 × 10 15 (molec./cm 2 ) or more at 100 ° C. to 250 ° C. when M / z = 32. The display device according to claim 3, wherein 前記第１のシリコン酸化膜は、ＴＤＳ分析で、Ｍ/ｚ＝４４において、Ｎ２Ｏの放出量が１００℃乃至４００℃で８×１０１３（ｍｏｌｅｃ．/ｃｍ２）以下であることを特徴とする請求項３に記載の表示装置。 The first silicon oxide film has an N 2 O release amount of 8 × 10 13 (molec./cm 2 ) or less at 100 ° C. to 400 ° C. when M / z = 44 according to TDS analysis. The display device according to claim 3. 前記第１の酸化物半導体は、第２のシリコン酸化膜の上に形成され、前記第２のシリコン酸化膜の欠陥密度は、ＥＳＲ分析で、１×１０１８（ｓｐｉｎｓ/ｃｍ３）以下であることを特徴とする請求項１に記載の表示装置。 The first oxide semiconductor is formed on a second silicon oxide film, and a defect density of the second silicon oxide film is 1 × 10 18 (spins / cm 3 ) or less by ESR analysis. The display device according to claim 1. 前記第１の酸化物半導体は、第２のアルミニウム酸化膜の上に形成されていることを特徴とする請求項１に記載の表示装置。   The display device according to claim 1, wherein the first oxide semiconductor is formed on a second aluminum oxide film. 前記第１のアルミニウム酸化膜の厚さは１乃至２０ｎｍであることを特徴とする請求項１に記載の表示装置。   2. The display device according to claim 1, wherein the thickness of the first aluminum oxide film is 1 to 20 nm. 前記第２の酸化物半導体の厚さは前記第１の酸化物半導体厚さよりも小さいことを特徴とする請求項２に記載の表示装置。   The display device according to claim 2, wherein a thickness of the second oxide semiconductor is smaller than a thickness of the first oxide semiconductor. 前記第１のゲート絶縁膜は、前記第１のゲート電極の下にのみ形成されていることを特徴とする請求項１に記載の表示装置。   The display device according to claim 1, wherein the first gate insulating film is formed only under the first gate electrode. 前記第１の酸化物半導体は、ドレイン電極と接続するドレイン領域と、ソース電極と接続するソース領域を有し、前記ドレイン電極と前記ドレイン領域の間、及び、前記ソース電極と前記ソース領域の間には金属または合金よる保護層が形成されていることを特徴とする請求項１に記載の表示装置。   The first oxide semiconductor includes a drain region connected to a drain electrode, and a source region connected to a source electrode, between the drain electrode and the drain region, and between the source electrode and the source region. The display device according to claim 1, wherein a protective layer made of a metal or an alloy is formed on the display device. 前記保護層は、映像信号線と同じ材料で形成されていることを特徴とする請求項１１に記載の表示装置。   The display device according to claim 11, wherein the protective layer is formed of the same material as the video signal line. 前記基板は、Ｐｏｌｙ−Ｓｉを用いた第２のＴＦＴを有し、前記Ｐｏｌｙ−Ｓｉと前記基板の距離は、前記第１の酸化物半導体と前記基板の距離よりも小さいことを特徴とする請求項１に記載の表示装置。   The substrate includes a second TFT using Poly-Si, and a distance between the Poly-Si and the substrate is smaller than a distance between the first oxide semiconductor and the substrate. Item 4. The display device according to Item 1. 前記基板は、Ｐｏｌｙ−Ｓｉを用いた第２のＴＦＴを有し、前記Ｐｏｌｙ−Ｓｉと前記基板の距離は、前記第１の酸化物半導体と前記基板の距離よりも小さいことを特徴とする請求項１１に記載の表示装置。   The substrate includes a second TFT using Poly-Si, and a distance between the Poly-Si and the substrate is smaller than a distance between the first oxide semiconductor and the substrate. Item 12. The display device according to Item 11. 前記第１の酸化物半導体の下には、第３のシリコン酸化膜を含む第２のゲート絶縁膜が形成され、前記第２のゲート絶縁膜の下には第２のゲート電極が形成され、
前記第１の酸化物半導体は前記第３のシリコン酸化膜の上に形成されていることを特徴とする請求項１に記載の表示装置。 A second gate insulating film including a third silicon oxide film is formed under the first oxide semiconductor, and a second gate electrode is formed under the second gate insulating film,
The display device according to claim 1, wherein the first oxide semiconductor is formed on the third silicon oxide film. 前記第２のゲート絶縁膜は第３のシリコン酸化膜と第３のアルミニウム酸化膜の積層膜で形成され、前記第２のゲート電極は前記第３のアルミニウム酸化膜と接していることを特徴とする請求項１５に記載の表示装置。   The second gate insulating film is formed of a laminated film of a third silicon oxide film and a third aluminum oxide film, and the second gate electrode is in contact with the third aluminum oxide film. The display device according to claim 15. 前記第２のゲート電極は金属と第３の酸化物半導体の積層膜で形成され、前記第３の酸化物半導体は前記第２のゲート絶縁膜と接していることを特徴とする請求項１５に記載の表示装置。   16. The method according to claim 15, wherein the second gate electrode is formed of a stacked film of a metal and a third oxide semiconductor, and the third oxide semiconductor is in contact with the second gate insulating film. The display device described. 前記第１の酸化物半導体は、ドレイン電極と接続するドレイン領域と、ソース電極と接続するソース領域を有し、前記ドレイン電極と前記ドレイン領域の間、及び、前記ソース電極と前記ソース領域の間には金属または合金よる保護層が形成されていることを特徴とする請求項１５に記載の表示装置。   The first oxide semiconductor includes a drain region connected to a drain electrode, and a source region connected to a source electrode, between the drain electrode and the drain region, and between the source electrode and the source region. The display device according to claim 15, wherein a protective layer made of a metal or an alloy is formed on the display device. 前記基板は、Ｐｏｌｙ−Ｓｉを用いた第２のＴＦＴを有し、前記Ｐｏｌｙ−Ｓｉと前記基板の距離は、前記第２のゲート電極と前記基板の距離よりも小さいことを特徴とする請求項１５に記載の表示装置。   The substrate includes a second TFT using Poly-Si, and a distance between the Poly-Si and the substrate is smaller than a distance between the second gate electrode and the substrate. 15. The display device according to 15. 前記基板は、Ｐｏｌｙ−Ｓｉを用いた第２のＴＦＴを有し、前記Ｐｏｌｙ−Ｓｉと前記基板の距離は、前記第２のゲート電極と前記基板の距離よりも小さいことを特徴とする請求項１８に記載の表示装置。   The substrate includes a second TFT using Poly-Si, and a distance between the Poly-Si and the substrate is smaller than a distance between the second gate electrode and the substrate. 18. The display device according to 18.
JP2017064916A 2017-03-29 2017-03-29 Display device Pending JP2018170324A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2017064916A JP2018170324A (en) 2017-03-29 2017-03-29 Display device
US15/892,513 US10453965B2 (en) 2017-03-29 2018-02-09 Display device
CN202211306654.8A CN115498028A (en) 2017-03-29 2018-02-26 Display device
CN201810159539.XA CN108695362B (en) 2017-03-29 2018-02-26 Display device
US16/565,760 US11177363B2 (en) 2017-03-29 2019-09-10 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017064916A JP2018170324A (en) 2017-03-29 2017-03-29 Display device

Publications (1)

Publication Number Publication Date
JP2018170324A true JP2018170324A (en) 2018-11-01

Family

ID=63669926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017064916A Pending JP2018170324A (en) 2017-03-29 2017-03-29 Display device

Country Status (3)

Country Link
US (2) US10453965B2 (en)
JP (1) JP2018170324A (en)
CN (2) CN115498028A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11532687B2 (en) 2019-07-30 2022-12-20 Samsung Display Co., Ltd. Thin film transistor, display panel having the same, and method of manufacturing the display panel
WO2023105569A1 (en) * 2021-12-06 2023-06-15 シャープディスプレイテクノロジー株式会社 Display device
WO2023157110A1 (en) * 2022-02-16 2023-08-24 シャープディスプレイテクノロジー株式会社 Display device
WO2023238746A1 (en) * 2022-06-07 2023-12-14 株式会社ジャパンディスプレイ Semiconductor device and method for manufacturing semiconductor device

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018170324A (en) * 2017-03-29 2018-11-01 株式会社ジャパンディスプレイ Display device
CN107393934B (en) 2017-08-14 2020-02-21 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
JP2019040026A (en) * 2017-08-24 2019-03-14 株式会社ジャパンディスプレイ Display
CN107507841B (en) * 2017-09-22 2021-01-22 京东方科技集团股份有限公司 Array substrate, manufacturing method thereof and display device
JP7109902B2 (en) * 2017-10-26 2022-08-01 株式会社ジャパンディスプレイ Display device and manufacturing method thereof
JP2019091794A (en) * 2017-11-14 2019-06-13 シャープ株式会社 Semiconductor device
JP2019129281A (en) * 2018-01-26 2019-08-01 株式会社ジャパンディスプレイ Display device and method of manufacturing the same
CN110426906B (en) * 2018-08-10 2022-03-04 友达光电股份有限公司 Pixel array substrate
KR102625448B1 (en) * 2018-10-10 2024-01-17 삼성디스플레이 주식회사 Organic light emitting display device and a method of manufacturing organic light emitting display device
KR20200060629A (en) * 2018-11-22 2020-06-01 삼성디스플레이 주식회사 Display device and method of manufacturing the same
CN109728003B (en) * 2019-01-03 2020-12-01 合肥鑫晟光电科技有限公司 Display substrate, display device and manufacturing method of display substrate
US11009757B2 (en) * 2019-03-14 2021-05-18 Sharp Kabushiki Kaisha Liquid crystal display
CN110190067B (en) * 2019-05-17 2021-07-06 武汉华星光电技术有限公司 Array substrate and manufacturing method thereof
US11121263B2 (en) * 2019-08-27 2021-09-14 Apple Inc. Hydrogen trap layer for display device and the same
KR20220019880A (en) * 2020-08-10 2022-02-18 삼성디스플레이 주식회사 Display device and method for manufacturing threrof
CN112530978B (en) * 2020-12-01 2024-02-13 京东方科技集团股份有限公司 Switching device structure, preparation method thereof, thin film transistor film layer and display panel
KR20220077305A (en) * 2020-12-01 2022-06-09 삼성디스플레이 주식회사 Display device and manufacturing method thereof
KR20220088596A (en) * 2020-12-18 2022-06-28 삼성디스플레이 주식회사 Display apparatus
JP2022178141A (en) * 2021-05-19 2022-12-02 株式会社ジャパンディスプレイ Semiconductor device and manufacturing method for the same
CN113571587B (en) * 2021-07-14 2023-12-01 深圳市华星光电半导体显示技术有限公司 Array substrate, display panel and manufacturing method of array substrate

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US38100A (en) * 1863-04-07 Improved hopple for horses and other animals
US6673126B2 (en) * 1998-05-14 2004-01-06 Seiko Epson Corporation Multiple chamber fabrication equipment for thin film transistors in a display or electronic device
CN100592523C (en) * 1999-06-02 2010-02-24 株式会社半导体能源研究所 Semiconductor device and a method of manufacturing the same
JP5552753B2 (en) 2008-10-08 2014-07-16 ソニー株式会社 Thin film transistor and display device
KR101065407B1 (en) * 2009-08-25 2011-09-16 삼성모바일디스플레이주식회사 Organic light emitting diode display and method for manufacturing the same
KR20170142998A (en) 2009-12-25 2017-12-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Method for manufacturing semiconductor device
US8791463B2 (en) * 2010-04-21 2014-07-29 Sharp Kabushiki Kaisha Thin-film transistor substrate
JP2012015436A (en) 2010-07-05 2012-01-19 Sony Corp Thin film transistor and display device
US9040981B2 (en) * 2012-01-20 2015-05-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9653614B2 (en) * 2012-01-23 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
KR102196949B1 (en) * 2013-03-29 2020-12-30 엘지디스플레이 주식회사 Thin film transistor, method for manufacturing the same and display device comprising the same
JP6345023B2 (en) * 2013-08-07 2018-06-20 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
KR102080484B1 (en) * 2013-10-31 2020-02-24 엘지디스플레이 주식회사 Array substrate for Liquid crystal display device and Method for manufacturing the same
CN103745955B (en) * 2014-01-03 2017-01-25 京东方科技集团股份有限公司 Display device, array substrate and manufacturing method of array substrate
CN104900654B (en) * 2015-04-14 2017-09-26 深圳市华星光电技术有限公司 The preparation method and its structure of dual gate oxide semiconductor TFT substrate
CN105097550A (en) * 2015-08-04 2015-11-25 深圳市华星光电技术有限公司 Low-temperature polycrystalline silicon thin film transistor (TFT) and manufacture method thereof
JP6970511B2 (en) * 2016-02-12 2021-11-24 株式会社半導体エネルギー研究所 Transistor
JP2018170324A (en) * 2017-03-29 2018-11-01 株式会社ジャパンディスプレイ Display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11532687B2 (en) 2019-07-30 2022-12-20 Samsung Display Co., Ltd. Thin film transistor, display panel having the same, and method of manufacturing the display panel
WO2023105569A1 (en) * 2021-12-06 2023-06-15 シャープディスプレイテクノロジー株式会社 Display device
WO2023157110A1 (en) * 2022-02-16 2023-08-24 シャープディスプレイテクノロジー株式会社 Display device
WO2023238746A1 (en) * 2022-06-07 2023-12-14 株式会社ジャパンディスプレイ Semiconductor device and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
US20180286888A1 (en) 2018-10-04
US10453965B2 (en) 2019-10-22
CN108695362A (en) 2018-10-23
CN115498028A (en) 2022-12-20
US20200006568A1 (en) 2020-01-02
CN108695362B (en) 2022-11-11
US11177363B2 (en) 2021-11-16

Similar Documents

Publication Publication Date Title
JP2018170324A (en) Display device
US11521990B2 (en) Display device
US11348948B2 (en) Manufacturing method of a display device
JP5468657B2 (en) Display device
US20170256569A1 (en) Semiconductor device and display device and manufacturing method thereof
TWI525705B (en) Semiconductor device and manufacturing method thereof
JP2019049718A (en) Display device
JP2018170325A (en) Display device
JP2019036746A (en) Semiconductor device
JP2018170326A (en) Display device
JP2018074076A (en) Display device
US10411039B2 (en) Semiconductor device, display device, and method for manufacturing the same
JP2018046140A (en) Display device and method of manufacturing the same
JP2020017558A (en) Display device
CN109427874B (en) Display device and method for manufacturing the same
US10804406B2 (en) Thin-film transistor substrate, liquid crystal display device including the same, and method for producing thin-film transistor substrate
JP6482256B2 (en) Thin film transistor substrate and liquid crystal display device
WO2019082465A1 (en) Display device and method for manufacturing same
JP2008218626A (en) Tft array substrate and manufacturing method therefor
US20200044090A1 (en) Thin film transistor substrate and method for manufacturing same
JP2020181985A (en) Display device