JP2018160625A - Flat surface coil substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a flat surface coil substrate which allows for easy handling of both ends of a coil.SOLUTION: A flat surface coil substrate includes a conductive layer of n layers (n is 2 or more), where the wiring patterns of multiple conductive layers are close or overlap in the plan view, and are segmented into m (m is 2 or more) fan-shaped regions, a pair of terminals electrically connected with one side end of the outermost wiring in a specific fan-shaped region in the first conductive layer, and the other side end of the outermost wiring of a fan-shaped region adjacent to one side of the fan-shaped region, and multiple interstitial via holes connected electrically with the one side end of the p-th (p is 1-m) fan-shaped region counting to the one side in the k-th (k is 1-n) conductive layer, and the other side end of the (p+1)th fan-shaped region in a conductive layer other than the k-th layer, moving to the center from one side of the pair of terminals in the plan view, and disposed to constitute a spiral closed loop moving from the center to the other side terminal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a planar coil substrate.

  An RFID (Radio Frequency IDentification) system using a near field communication (NFC) technology, a contactless IC card, and the like are widely used. In addition, wireless (non-contact type) power supply devices using an electromagnetic induction phenomenon are becoming widespread. In these non-contact communication and power supply, two adjacent coils transmit and receive information and energy via radio waves or electromagnetic fields.

  Such portable devices and cards used for non-contact communication and power supply have a small size, and the coils provided therein are also small and efficient. It is requested. For example, Patent Document 1 discloses that a single closed loop coil is formed by forming a spiral circuit pattern in a plan view on each of a plurality of conductive layers of a multilayer substrate and connecting these circuit patterns with a plurality of through holes. The printed circuit board which comprises is disclosed.

JP 2016-19338 A

  In the printed circuit board disclosed in Patent Document 1, a first connection terminal serving as one end of a coil is connected to an end of the outermost multi-row circuit of the circuit pattern, and an end of the innermost multi-row circuit of the circuit pattern An intermediate terminal which is the other end of the coil is connected to the terminal. With such a configuration, it is necessary to separately provide a layer having a jumper wire in order to make an electrical connection from the outside of the circuit pattern to the innermost intermediate terminal, and it is necessary to devise handling of both ends of the coil.

  This invention is made | formed based on the above situations, and it aims at providing the planar coil board | substrate which can handle the both ends of a coil easily.

  A planar coil substrate according to an aspect of the present invention, which has been made to solve the above problems, includes one or a plurality of insulating layers mainly composed of a synthetic resin and n layers (n is 2 or more) including multiple wiring patterns. A plurality of conductive layer wiring patterns, the wiring patterns of the plurality of conductive layers approximating or overlapping in plan view, and divided into m (m is 2 or more) fan-shaped regions passing through the center. And electrically connected to one end of the outermost wiring of the specific fan-shaped region in the first conductive layer and the other end of the outermost wiring of the fan-shaped region adjacent to the fan-shaped region on one side. A pair of terminals, and one end of the p-th (p is 1 to m) fan-shaped region counted on the one side in the k-th (k is 1 to n) conductive layer and the conductivity other than the k-th layer. Electrically connected to the other end of the (p + 1) th fan-shaped region in the layer and The one moves from the side to the center of the terminal, and includes a plurality of interstitial via holes are arranged to constitute a spiral loop to move the other side of the terminal from the center.

  The planar coil substrate according to one embodiment of the present invention can easily handle both ends of the coil.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the planar coil board | substrate which concerns on one Embodiment of this invention from multiple viewpoints, and is a typical top view from the top, a typical fragmentary sectional view in the AA line, and a typical bottom view. FIG. 2 is a schematic plan view of the planar coil substrate of FIG. 1, schematically showing an electrical connection mode of wiring. It is the figure which reversed the typical bottom view of the planar coil board | substrate of FIG. 1 to the up-down direction, and is a figure which shows typically the electrical connection aspect of wiring. FIG. 2 is a schematic plan view of a planar coil substrate according to an embodiment different from the planar coil substrate of FIG. 1. It is a figure which shows the planar coil board | substrate of FIG. 3A, and is the typical top view which removed the insulating layer under the 1st conductive layer and the 1st conductive layer. It is the figure which reversed the typical bottom view which shows the planar coil board | substrate of FIG. 3A to the up-down direction. It is a typical fragmentary sectional view in the AA line of FIG. 3A. It is a typical top view which shows the planar coil board | substrate which concerns on embodiment different from the planar coil board | substrate of FIG. 1A and 3A. It is a figure which shows the planar coil board | substrate of FIG. 5A, and is a schematic top view which removed the insulating layer under the 1st conductive layer and the 1st conductive layer. It is a figure which shows the planar coil board | substrate of FIG. 5A, and is a schematic top view which removed further the conductive layer of the 2nd layer, and the insulating layer under the 2nd conductive layer from FIG. 5B. It is the figure which reversed the typical bottom view which shows the planar coil board | substrate of FIG. 5A to the up-down direction. It is a typical fragmentary sectional view in the AA line of FIG. 5A. It is a typical fragmentary sectional view which shows the planar coil board | substrate which concerns on embodiment different from the planar coil board | substrate of FIG. 1A, FIG. 3A and FIG. 5A. FIG. 8 is a schematic plan view showing a planar coil substrate according to an embodiment different from the planar coil substrates of FIGS. 1A, 3A, 5A and 7. FIG. FIG. 9 is a schematic plan view showing a planar coil substrate according to an embodiment different from the planar coil substrates of FIGS. 1A, 3A, 5A, 7 and 8. FIG. It is the figure which reversed the typical bottom view which shows the planar coil board | substrate of FIG. 9A to the up-down direction.

[Description of Embodiment of the Present Invention]
First, embodiments of the present invention will be listed and described.

  A planar coil substrate according to one embodiment of the present invention is a plane including alternately one or a plurality of insulating layers mainly composed of a synthetic resin and n layers (n is 2 or more) including multiple wiring patterns. A coil substrate, wherein the wiring patterns of the plurality of conductive layers are divided or divided into m (m is 2 or more) fan-shaped regions that approximate or overlap in plan view and pass through the center. A pair of terminals electrically connected to one end of the outermost wiring of the specific fan-shaped region in the layer and the other end of the outermost wiring of the fan-shaped region adjacent to the fan-shaped region; and the kth layer One end of the p-th (p is 1 to m) fan-shaped region counted on one side of the conductive layer (k is 1 to n) and the other of the p + 1-th fan-shaped regions in the conductive layers other than the k-th layer. It is electrically connected to the side end and moved from one side of the pair of terminals to the center in plan view. And and a plurality of interstitial via holes are arranged to constitute a spiral loop that moves from the center to the other side of the terminal.

  The planar coil substrate has a spiral closed loop in which a plurality of fan-shaped regions of a plurality of conductive layers are electrically connected by interstitial via holes and move from one side of a pair of terminals to the other terminal via the center. Therefore, the end of the coil is not provided in the innermost part of the coil. For this reason, it is not necessary to separately provide a layer having a jumper wire in order to perform electrical connection from the outside of the coil. The planar coil substrate includes a pair of terminals that are electrically connected to the outermost wirings of two adjacent fan-shaped regions in the first conductive layer. That is, since the pair of terminals are connected to the outermost wirings of two adjacent fan-shaped regions with the same conductive layer, the planar coil substrate can easily handle both ends of the coil.

  Of the n conductive layers, the wiring pattern of one conductive layer may have an innermost wiring that is partly divided and the other part is not divided. When the planar coil substrate has such an innermost wiring, it is easy to form a closed loop that spirals so as to approach the center from the outside, makes a U-turn at the innermost wiring, and then spirals away from the center to the outside.

  It is preferable that one insulating layer and two conductive layers stacked on both sides of the insulating layer are provided, and the wiring pattern of these conductive layers is divided into two fan-shaped regions. When the planar coil substrate is configured in this way, a wiring pattern can be formed using a double-sided substrate and the number of interstitial via holes can be reduced, so that the planar coil substrate can be easily manufactured.

  In the present invention, the term “spiral closed loop” means that when electricity flows through the multiple wiring pattern from one terminal to the other terminal, the current approaches the center as the current swirls, or the current flows. It means a closed loop that moves away from the center as it turns. The “fan-shaped region passing through the center” indicates a fan-shaped region having the center of the coil as the center of the fan, and includes a shape in which two sides serving as a radius are a straight line, a curved line, or a broken line. “The wiring pattern is divided into fan-shaped areas” means that the wiring pattern is divided into a plurality of fan-shaped areas and the wiring pattern is electrically disconnected from other fan-shaped areas at or near the boundary line of the fan-shaped areas. Indicates that

[Details of the embodiment of the present invention]
Hereinafter, a planar coil substrate according to an embodiment of the present invention will be described with reference to the drawings as appropriate.

[First embodiment]
<Planar coil substrate>
The planar coil substrates of FIGS. 1, 2A and 2B are alternately provided with one insulating layer 1 mainly composed of synthetic resin and two conductive layers including multiple wiring patterns 2. The planar coil substrate includes two conductive layers stacked on both sides of the insulating layer 1. That is, the planar coil substrate has a structure in which the insulating layer 1 is sandwiched between two conductive layers, and includes the insulating layers 1 and the conductive layers alternately. The planar coil substrate has a first conductive layer on the front side of the insulating layer 1 and a second conductive layer on the back side of the insulating layer 1. The first conductive layer includes the multiple wiring pattern 2 and the innermost wiring 6, and the second conductive layer includes the multiple wiring pattern 2. In addition, as shown in FIGS. 2A and 2B, the planar coil substrate is a pair of terminals electrically connected to the end of the outermost wiring 2a and the end of the outermost wiring 2p in the first conductive layer. 4 and a plurality of interstitial via holes 5 that electrically connect the end portions of the multiple wiring pattern 2 of the first conductive layer and the multiple wiring pattern 2 of the second conductive layer. (Not shown in FIG. 1).

(Insulating layer)
The insulating layer 1 is a layer mainly composed of a synthetic resin having electrical insulation. The insulating layer 1 is also a base film for forming a conductive layer. The insulating layer 1 may have a configuration that does not have flexibility, but a configuration having flexibility is preferable because the planar coil substrate can be configured as a flexible planar coil substrate. As the main component of the insulating layer 1, for example, a synthetic resin such as polyimide, polyethylene terephthalate, polyethylene naphthalate, liquid crystal polymer, or fluororesin is selected. The “main component” means a component having the largest content, for example, a component having a content of 50% by mass or more.

  The lower limit of the average thickness of the insulating layer 1 is preferably 2.5 μm and more preferably 5 μm. On the other hand, the upper limit of the average thickness of the insulating layer 1 is preferably 100 μm, and more preferably 80 μm. If the average thickness of the insulating layer 1 is less than the lower limit, the strength and insulating properties of the insulating layer may be insufficient. Conversely, if the average thickness of the insulating layer 1 exceeds the above upper limit, the planar coil substrate may not be thinned.

(Conductive layer)
The conductive layer of the first layer and the conductive layer of the second layer include a substantially circular multiple wiring pattern 2 in plan view. The multiple wiring pattern 2 in the first conductive layer and the multiple wiring pattern 2 in the second conductive layer have a plurality of substantially ring-shaped wirings. The plurality of wirings are formed in a substantially annular shape having different radii, and are arranged so as to be substantially concentric circles. The first conductive layer has an annular innermost wiring 6 as a wiring pattern different from the multiple wiring pattern 2 inside the multiple wiring pattern 2.

  Each wiring and innermost wiring 6 of the multiplex wiring pattern 2 are formed in a strip-like shape with a substantially equal width and a metal foil, for example, a copper foil. The multiplex wiring pattern 2 and the innermost wiring 6 are not particularly limited, but are formed, for example, by etching metal layers laminated on both surfaces of the insulating layer 1.

  Each wiring of the multiple wiring pattern 2 and the innermost wiring 6 are formed to have a substantially uniform thickness. The lower limit of the average thickness of the wiring is preferably 0.1 μm, and more preferably 1 μm. On the other hand, the upper limit of the average wiring thickness is preferably 230 μm, and more preferably 210 μm. If the average thickness is less than the lower limit, conductor loss may increase due to conductor resistance, or the strength may be insufficient. Conversely, if the average thickness exceeds the upper limit, the planar coil substrate may not be thinned.

  The multiple wiring pattern 2 in the first conductive layer and the multiple wiring pattern 2 in the second conductive layer are formed so as to make a pair on the front and back of the insulating layer 1, as shown in FIG. It has a shape that approximates or overlaps in plan view. That is, the wiring patterns of the plurality of conductive layers are approximated or overlapped in plan view. Note that “the wiring patterns of the plurality of conductive layers approximate in plan view” means that the wiring patterns in the plurality of conductive layers are formed so as to include a common shape or a symmetric shape in plan view. For example, most of the shapes are the same, those having a similar shape whose similarity ratio is close to 1, or those having a mirror relationship. “The wiring patterns of a plurality of conductive layers overlap in a plan view” means that the wiring patterns in the plurality of conductive layers are formed so as to include portions that overlap each other in a plan view. Includes shapes that do not overlap. In the planar coil substrate, the wiring patterns of the plurality of conductive layers are approximated and overlapped in plan view.

  It is preferable that the multiple wiring pattern 2 in the first conductive layer and the multiple wiring pattern 2 in the second conductive layer have a high degree of overlap in plan view. The multiple wiring pattern 2 in the first conductive layer and the multiple wiring pattern 2 in the second conductive layer preferably overlap in plan view in 30% or more of the whole, and overlap in 70% or more. It is more preferable that it is overlapped at 90% or more. If the overlapping degree of the multiple wiring pattern 2 in the first conductive layer and the multiple wiring pattern 2 in the second conductive layer is less than the lower limit, the design of the multiple wiring pattern 2 may be complicated. .

  The multiple wiring pattern 2 of the first conductive layer and the multiple wiring pattern 2 of the second conductive layer are divided into two fan-shaped regions passing through the center. Specifically, as shown in FIG. 1, the ring-shaped multiple wiring pattern 2 of each conductive layer is divided into two regions to form a fan-shaped region 3a and a fan-shaped region 3b passing through the center. More specifically, the fan-shaped region 3a of the first conductive layer has four semicircular wirings 2a, 2c, 2e, and 2g, and the fan-shaped region 3b of the first conductive layer. Has four semicircular wirings 2j, 2l, 2n, and 2p, and the fan-shaped region 3a of the second conductive layer has four semicircular wirings 2i, 2k, and wirings. 2m, wiring 2o, and the fan-shaped region 3b of the second conductive layer includes four semicircular wirings 2b, wiring 2d, wiring 2f, and wiring 2h. The wiring pattern is divided into fan-shaped regions. On the other hand, the innermost wiring 6 of the first conductive layer is divided only at one portion and is not divided at the other portion. That is, the wiring pattern of the conductive layer of the first layer has the innermost wiring 6 that is partly divided and the other parts are not divided.

  The lower limit of the central angle of the fan-shaped region is preferably 15 degrees, more preferably 30 degrees, and still more preferably 90 degrees. On the other hand, the upper limit of the central angle of the fan-shaped region is preferably 345 degrees, more preferably 330 degrees, and even more preferably 270 degrees. If the central angle of the fan-shaped region is less than the lower limit, the length of the wiring in the fan-shaped region is shortened, and the contribution of the wiring in the fan-shaped region in the coil may be reduced. Conversely, if the central angle of the fan-shaped region exceeds the above upper limit, the length of the wiring in the other fan-shaped region is shortened, and the contribution of the wiring in the other fan-shaped region in the coil may be reduced. The central angle of the fan-shaped region indicates an angle formed by the two dividing positions and the center of the innermost wiring of the multiple wiring pattern.

  As shown in FIG. 1, the multiple wiring pattern 2 divided into fan-shaped regions is continuous from one region boundary to the other region boundary, and as shown in FIG. 2A and FIG. It is formed so as to be located in the vicinity of the region boundary. That is, the multiple wiring pattern 2 of the first conductive layer and the multiple wiring pattern 2 of the second conductive layer are electrically cut in the vicinity of the boundary of the fan-shaped regions, so that they are divided into a plurality of fan-shaped regions. Has been.

  As shown in FIGS. 2A and 2B, each of the divided fan-shaped regions and the innermost wiring 6 has a shape in which an end is bent in the vicinity of the region boundary line. That is, each wiring in the fan-shaped region and the innermost wiring 6 have an arc-shaped main body portion and a bent connection end portion. Since each wiring in the fan-shaped region and the innermost wiring 6 have a bent connection end, the ends of the wirings in different conductive layers are electrically connected via the interstitial via hole 5 as will be described later. Connected.

  On the left side adjacent to one end (lower left end) of the outermost wiring 2p of the right fan-shaped region (specific fan-shaped region) in the first conductive layer and one side (lower left side) of the right fan-shaped region A pair of terminals 4 are electrically connected to the other end (lower right end) of the outermost wiring 2a in the fan-shaped region. The pair of terminals 4 are connection terminals for performing electrical connection, and are not particularly limited. For example, the pair of terminals 4 are formed of a copper foil continuous from the wiring, and soldering, intermetal pressure welding, ultrasonic metal bonding, or a connector is used. Used to be electrically connected to other wiring.

  One end portion of the multiple wiring pattern 2 in the fan-shaped region of one conductive layer is a fan-shaped region adjacent to one side of the fan-shaped region, and is a multiple of fan-shaped regions in a conductive layer different from the one conductive layer. The wiring pattern 2 is formed so as to overlap with the other end of the wiring pattern 2 in plan view, and the two ends are electrically connected via the interstitial via hole 5 at the overlapping position. In other words, the planar coil substrate is other than the one side end of the p-th (p is 1 to 2) fan-shaped region and the k-th layer counted on the one side in the k-th (k is 1 to 2) conductive layer. A plurality of interstitial via holes 5 electrically connected to the other end of the (p + 1) th sector region in the conductive layer. For example, one side end (upper right side end) of the left-side fan-shaped multiple wiring pattern 2 in the first conductive layer is the right-side fan-shaped multiple wiring pattern 2 in the second conductive layer. Is electrically connected to the other side end portion (upper left end portion) via the interstitial via hole 5. When p is 2, p + 1 indicates the third, but since there are two fan-shaped regions in the conductive layer of the planar coil substrate, p + 1 returns and indicates the first.

  The interstitial via hole 5 starts from one side of the pair of terminals 4 and moves to the center while turning in one direction in plan view, and the innermost wiring 6 of one conductive layer (first conductive layer) is connected. The ends of a plurality of wiring patterns 2 in a plurality of fan-shaped regions are connected to each other so as to form a spiral closed loop that goes around in one direction and turns in one direction and moves from the center to the other terminal. Yes. That is, the plurality of interstitial via holes 5 move from one side of the pair of terminals to the center in a plan view by electrically connecting the ends of the plurality of multiple wiring patterns 2 in the plurality of fan-shaped regions. And a spiral closed loop that moves from the center to the other terminal.

  The electrical connection of the wiring in the planar coil board | substrate of 1st embodiment is demonstrated concretely with reference to FIG. 2A and FIG. 2B. 2A and 2B, the wiring that moves from one side of the pair of terminals to the center is represented by a thick line, and the wiring that moves from the center to the other terminal is represented by a thin line. ing. First, the terminal 4 on one side is connected to the other end of the outermost wiring 2a of the first conductive layer. Next, one end of the outermost wiring 2 a of the first conductive layer is electrically connected to the other end of the outermost wiring 2 b of the second conductive layer through the interstitial via hole 5. The Next, one end of the outermost wiring 2b of the second conductive layer is electrically connected to the other end of the outermost wiring 2c of the first conductive layer through the interstitial via hole 5. The Similarly for the other wirings, one end of the wiring 2c is connected to the other end of the wiring 2d, one end of the wiring 2d is connected to the other end of the wiring 2e, and one of the wirings 2e is connected. The side end is connected to the other end of the wiring 2f, the one end of the wiring 2f is connected to the other end of the wiring 2g, and the one end of the wiring 2g is connected to the other end of the wiring 2h. Connected. One end of the second conductive layer wiring 2h is connected to the other end of the innermost wiring 6 of the first conductive layer, and the one end of the innermost wiring 6 is connected to the second end. It is connected to the other end of the wiring 2i of the conductive layer. Similarly, one end of the wiring 2i is connected to the other end of the wiring 2j, one end of the wiring 2j is connected to the other end of the wiring 2k, and one end of the wiring 2k is connected to the other end. Connected to the other end of the wiring 2l, one end of the wiring 2l connected to the other end of the wiring 2m, one end of the wiring 2m connected to the other end of the wiring 2n, One end of 2n is connected to the other end of wiring 2o, and one end of wiring 2o is connected to the other end of wiring 2p. Finally, one end of the outermost wiring 2p of the first conductive layer is connected to the terminal 4 on the other side.

  Here, the order of passage of the wiring in the planar coil substrate of the first embodiment is shown in Table 1. In Table 1, “layer” indicates a conductive layer, and for example, the first layer indicates a first layer of the conductive layer. In Table 1, “side” indicates a fan-shaped area, and for example, the left side indicates a left-side fan-shaped area in FIG. The “wiring number” in Table 1 indicates the wiring number in the conductive layer, and the larger the number, the outer wiring. The number of “passing order” indicates the passing order of the wiring starting from the left side of the pair of terminals 4 and reaching the right side of the pair of terminals 4 in ascending order, and the wiring is interstitial via holes according to this passing order. 5 indicates connection. -In the “passing order” indicates that there is no wiring to pass.

  As shown in Table 1, the wiring of the planar coil substrate is connected so as to move alternately between the first layer of the conductive layer and the second layer of the conductive layer. Further, the wiring of the planar coil substrate is connected so that the divided wirings of the two conductive layers are interchanged in series between the two conductive layers. Further, in the area of the wiring numbers (2) to (5), all the divided wirings are connected.

[advantage]
In the planar coil substrate, two outermost wirings adjacent to each other in the first conductive layer become wirings at both ends of the coil. Therefore, by connecting a pair of terminals 4 to these outermost wirings, It can be handled easily. In addition, since the planar coil substrate does not have wiring that becomes one end of the coil inside the coil, it is not necessary to separately provide a layer having a jumper wire. Further, the planar coil substrate has an annular innermost wiring 6 that is partly divided and the other parts are not divided. Therefore, the innermost wiring 6 functions as a U-turn wiring, and all the parts are divided. It is easy to form a closed loop in which a plurality of multiple wiring patterns 2 are connected through interstitial via holes 5. The planar coil substrate has a structure in which two conductive layers are laminated on both sides of an insulating layer, and the wiring pattern of these conductive layers is divided into two fan-shaped regions. Can be formed, and the number of interstitial via holes 5 can be reduced, which facilitates the manufacture of the planar coil substrate. Further, since the wiring of the planar coil substrate is connected so as to move alternately between the first conductive layer and the second conductive layer, it is formed of the first conductive layer and the second conductive layer. The capacitance of the capacitor to be reduced can be reduced, and the deterioration of the frequency characteristics of the coil due to this can be suppressed.

[Second Embodiment]
The planar coil substrate of the first embodiment has a configuration in which the multiple wiring pattern of the two conductive layers is divided into two fan-shaped regions, but the planar coil substrate of the second embodiment has three conductive layers. The multiple wiring pattern is different from the planar coil substrate of the first embodiment in that the multiple wiring pattern is divided into two fan-shaped regions. Hereinafter, the description overlapping with the description of the planar coil substrate of the first embodiment will be omitted, and differences from the planar coil substrate of the first embodiment will be described.

<Planar coil substrate>
The planar coil substrates of FIGS. 3A, 3B, 3C, and 4 are alternately provided with two insulating layers 11 mainly composed of synthetic resin and three conductive layers including multiple wiring patterns 12. Yes. As shown in FIG. 4, the planar coil substrate has a multilayer substrate structure in which an insulating layer 11 is sandwiched between two layers between three conductive layers. Although the said planar coil board | substrate is not specifically limited, For example, it manufactures by laminating | stacking one layer at a time by the sequential lamination method. The conductive layer including the multiple wiring pattern 12 shown in FIG. 3A is a first conductive layer, and the conductive layer including the multiple wiring pattern 12 shown in FIG. 3B is a second conductive layer. The conductive layer including the multiple wiring pattern 12 and the innermost wiring 13 shown in FIG. 3C is the third conductive layer.

(Conductive layer)
As shown in FIGS. 3A, 3B, and 3C, each conductive layer of the planar coil substrate includes a multiple wiring pattern 12 having a substantially rectangular shape (rounded square shape) in plan view. The multiple wiring patterns 12 of these conductive layers are formed so as to approximate or overlap in plan view. The conductive layer of the first layer has an innermost wiring 6 having a rounded rectangular shape as a wiring pattern different from the multiple wiring pattern 12, which is partly divided and the other parts are not divided. Note that the multiple wiring pattern 12 of each conductive layer is divided into two fan-shaped regions passing through the center in the same manner as the planar coil substrate of the first embodiment. The wiring patterns of the layers are approximate and overlap in plan view.

  One end of the multiple wiring pattern 12 in the fan-shaped region of one conductive layer is a fan-shaped region adjacent to one side of the fan-shaped region, and is a multiple of fan-shaped regions in a conductive layer different from the one conductive layer. The wiring pattern 12 is formed so as to overlap with the other end of the wiring pattern 12 in plan view, and the two ends are electrically connected via the interstitial via hole 5 at the overlapping position. In other words, the planar coil substrate is other than the one end of the p-th (p is 1 to 2) fan-shaped region and the k-th layer counted on the one side in the k-th (k is 1 to 3) conductive layer. A plurality of interstitial via holes 5 electrically connected to the other end of the (p + 1) th sector region in the conductive layer.

  Here, Table 2 shows the order of passage of wiring in the planar coil substrate of the second embodiment. The meaning of terms in the table is the same as in Table 1.

  As shown in Table 2, the wiring of the planar coil substrate is connected so as to cyclically move from the first layer to the third layer of the conductive layer. Further, the wiring of the planar coil substrate is connected so that the divided wirings of the two conductive layers are interchanged in series between the two conductive layers. Further, in the area of the wiring numbers (2) to (4), all divided wirings are connected.

[advantage]
Similar to the planar coil substrate of the first embodiment, the planar coil substrate can easily handle both ends of the coil, and there is no need to separately provide a layer having jumper wires. In addition, since the multiple wiring pattern 12 and the innermost wiring 6 of the planar coil substrate have a substantially rectangular shape in plan view, the wiring pattern can be efficiently arranged along the periphery of the rectangular substrate. The central area of the substrate is also easy to use for other purposes.

[Third embodiment]
The planar coil substrate of the third embodiment is different from the planar coil substrate of the first embodiment in that the wiring pattern of the four conductive layers is divided into three fan-shaped regions. Hereinafter, the description overlapping with the description of the planar coil substrate of the first embodiment will be omitted, and differences from the planar coil substrate of the first embodiment will be described.

<Planar coil substrate>
5A, FIG. 5B, FIG. 5C, FIG. 5D, and FIG. 6 are alternately composed of three insulating layers 21 mainly composed of synthetic resin and four conductive layers including multiple wiring patterns 22. In preparation. As shown in FIG. 6, the planar coil substrate has a multilayer substrate structure in which one insulating layer 21 is sandwiched between three gaps between four conductive layers. Although the said planar coil board | substrate is not specifically limited, For example, it manufactures by laminating | stacking one layer at a time by the sequential lamination method. The conductive layer including the multiple wiring pattern 22 and the innermost wiring 6 shown in FIG. 5A is the first conductive layer, and the conductive layer including the multiple wiring pattern 22 shown in FIG. 5B is the second layer. The conductive layer including the multiple wiring pattern 22 shown in FIG. 5C is the third conductive layer, and the conductive layer including the multiple wiring pattern 22 shown in FIG. 5D is the fourth conductive layer. It is.

(Conductive layer)
As shown in FIGS. 5A, 5B, 5C, and 5D, each conductive layer of the planar coil substrate includes an annular wiring pattern 22 in a plan view. The multiple wiring patterns 22 are formed so as to approximate or overlap in plan view. Also in the planar coil substrate, the wiring patterns of the plurality of conductive layers are approximated and overlapped in plan view.

  The multiple wiring pattern 22 of each conductive layer is divided into three fan-shaped regions passing through the center. Specifically, as shown in FIG. 5A, FIG. 5B, FIG. 5C, and FIG. 5D, the ring-shaped multiple wiring pattern 22 of each conductive layer has a fan-shaped region 23a having a central angle of about 120 degrees, and a fan-shaped region. 23b and a fan-shaped region 23c. On the other hand, the annular innermost wiring 6 of the first conductive layer is divided only at the boundary between the fan-shaped region 23a and the fan-shaped region 23c, and is not divided at other portions. That is, the wiring pattern of the conductive layer of the first layer has the innermost wiring 6 in which only a part is divided and the other part is not divided.

  The multiple wiring pattern 22 divided into fan-shaped regions is continuous from the vicinity of one region boundary to the vicinity of the other region boundary, and is formed so that both ends thereof are positioned in the vicinity of the region boundary. That is, the multiple wiring pattern 22 of the first conductive layer, the multiple wiring pattern 22 of the second conductive layer, the multiple wiring pattern 22 of the third conductive layer, and the multiple conductive pattern of the fourth conductive layer. The wiring pattern 22 is divided into a plurality of fan-shaped regions by being electrically cut in the vicinity of the boundary of the fan-shaped regions.

  One end of the multiple wiring pattern 22 in the fan-shaped region of one conductive layer is a fan-shaped region adjacent to one side of the fan-shaped region, and the multiple of the fan-shaped regions in a conductive layer different from the one conductive layer. The wiring pattern 22 is formed so as to overlap with the other end portion of the wiring pattern 22 in plan view, and the two end portions are electrically connected through the interstitial via hole 5 at the overlapping position. In other words, the planar coil substrate is other than the one side end of the p-th (p is 1 to 3) fan-shaped region and the k-th layer counted on the one side in the k-th (k is 1 to 4) conductive layer. A plurality of interstitial via holes 5 electrically connected to the other end of the (p + 1) th sector region in the conductive layer.

  Table 3 shows the order of passage of wiring in the planar coil substrate of the third embodiment. The meaning of terms in the table is the same as in Table 1.

  As shown in Table 3, the wiring of the planar coil substrate is connected so as to cyclically move from the first layer of the conductive layer to the fourth layer of the conductive layer. Further, in the area of the wiring numbers (2) to (3), all divided wirings are connected.

[advantage]
Similar to the planar coil substrate of the first embodiment, the planar coil substrate can easily handle both ends of the coil, and there is no need to separately provide a layer having jumper wires. Moreover, since the said planar coil board | substrate has the innermost wiring 6 which is partly divided | segmented and the other part is not parted, it is easy to form a closed loop.

[Other Embodiments]
The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is not limited to the configuration of the embodiment described above, but is defined by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims. The

  In the first embodiment, the number of insulating layers of the planar coil substrate is 1, the number of conductive layers is 2, and the number of divided fan-shaped regions is 2, and in the second embodiment, the planar coil is described. The number of insulating layers of the substrate is 2, the number of conductive layers is 3, and the number of divided fan-shaped regions is 2, and in the third embodiment, the number of insulating layers of the planar coil substrate is 3, The number of conductive layers is 4 and the number of divided fan-shaped regions is 3. However, if two outermost wirings in the same conductive layer are the wirings at both ends of the coil, these numbers are It is possible to set arbitrarily. Therefore, the planar coil substrate may be configured to alternately include one or a plurality of insulating layers mainly composed of a synthetic resin and n layers (n is 2 or more) of conductive layers including a multiple wiring pattern. The wiring patterns of the plurality of conductive layers may be divided into m (m is 2 or more) fan-shaped regions that approximate or overlap in plan view and pass through the center.

  In the first embodiment, the case where the number of wirings in the multiple wiring pattern is four will be described. In the second embodiment, the case where the number of wirings in the multiple wiring pattern is three will be described. In the third embodiment, the case where the number of wirings of the multiple wiring pattern is two has been described, but the number of wirings of the multiple wiring pattern is not particularly limited, and can be increased or decreased as necessary. .

  In each of the above embodiments, the wiring patterns of the plurality of conductive layers have been described as being approximate and overlapping in plan view, and further described that it is preferable that the degree of overlap is high in plan view. Not. For example, like the planar coil substrate of FIG. 7 shown as a modification of the first embodiment, the multiple wiring pattern 32 of the second conductive layer is smaller than the multiple wiring pattern 32 of the first conductive layer. By using a shape and a similar shape, the multiple wiring patterns 32 of a plurality of conductive layers may be configured not to overlap in plan view. That is, a configuration in which multiple wiring patterns of a plurality of conductive layers are approximated in plan view and do not overlap may be employed. However, considering that the multiple wiring pattern 2 can be easily designed, it is preferable that the wiring patterns of the plurality of conductive layers overlap in plan view.

  In each of the above embodiments, the spiral closed loop has been described in which a circular or rounded quadrangular multiple wiring pattern is divided into a plurality of fan-shaped regions in plan view, and ends of these fan-shaped regions are connected to each other. The multiple wiring patterns constituting the spiral closed loop are not limited to those in the above embodiments. For example, an elliptical or polygonal multiple wiring pattern in plan view may be divided into a plurality of fan-shaped regions. Further, the wiring of the multiple wiring pattern constituting the spiral closed loop is not limited to one having a main body portion and a bent connection end portion. That is, the wiring of the multiple wiring pattern constituting the spiral closed loop may be a curved line shape or a polygonal line shape that approaches (or moves away from) the center as the current flows so as to flow when electricity flows through the wiring.

  In each of the above embodiments, the conductive layer multiple wiring pattern is divided into fan-shaped regions at predetermined positions. However, the interstitial via hole may be configured to connect the ends of the wiring of each conductive layer. For example, the position at which the multiple wiring pattern is divided can be arbitrarily set for each wiring. However, it is preferable that the position where the multiple wiring pattern is divided is set to a position that is rotationally symmetric. For example, when a multiple wiring pattern is divided into two parts, it is divided every time it is wound about 180 degrees, and when divided into three parts, it is divided every time it is wound about 120 degrees and divided into four parts. When divided, it is good to divide every time it is wound about 90 degrees. When the multiple wiring pattern is divided in this way, the symmetry of the wiring pattern is increased, so that a reduction in the frequency characteristics of the coil can be suppressed.

  In a configuration in which the position where the multiple wiring pattern is divided is set to a rotationally symmetric position, it is preferable that the radial direction of the position changes as the distance from the center changes. For example, like the planar coil substrate of FIG. 8 shown as a modified example of the first embodiment, the position where the multiple wiring pattern is divided may be set to move clockwise as the distance from the center increases. The position where the multiple wiring pattern is divided may be set so as to move counterclockwise as the distance from the position increases. When the width of the arrangement area of the interstitial via hole is larger than the width of the wiring, there is a possibility that these interfering via holes interfere with each other when the interstitial via holes are arranged close to each other. For this reason, if the radial direction of the position where the multiple wiring pattern is divided changes with distance from the center, these interferences can be prevented.

  In each of the above embodiments, the configuration in which the wiring pattern of one conductive layer has an innermost wiring that is partly divided and the other parts are not divided has been described. However, the planar coil substrate has such innermost wiring. It is not limited to what it has. For example, a configuration in which the wiring pattern of one conductive layer has a fragmentary innermost wiring 53 may be employed, as in the planar coil substrate of FIGS. 9A and 9B shown as a modification of the first embodiment. However, it is preferable that the planar coil substrate has an innermost wiring in which only a part is divided and the other parts are not divided in that a closed loop is easily formed.

  The planar coil substrate may include a cover lay having flexibility and insulation, and the cover lay may cover the outer surface side of the conductive layer. If comprised in this way, a conductive layer can be protected from the outside.

  The planar coil substrate of the present invention can easily handle both ends of the coil. Therefore, it can be suitably used as a planar coil substrate for articles that require small coils such as small electronic articles.

1, 11, 21, 31, 41, 51 Insulating layer 2, 12, 22, 32, 42, 52 Multiple wiring patterns 2a to 2p Wiring 3a, 3b, 23a, 23b, 23c, 43a, 43b Fan-shaped area 4 Terminal 5 Interstitial via hole 6,53 Inner wiring

Claims (3)

One or more insulating layers mainly composed of synthetic resin;
A planar coil substrate comprising alternately n layers (n is 2 or more) of conductive layers including a multiple wiring pattern,
The wiring patterns of the plurality of conductive layers are divided into m (m is 2 or more) fan-shaped regions that approximate or overlap in plan view and pass through the center,
A pair of terminals electrically connected to one end of the outermost wiring of the specific fan-shaped region in the first conductive layer and the other end of the outermost wiring of the fan-shaped region adjacent to one side of the fan-shaped region When,
One side end of the p-th (p is 1 to m) fan-like region counted on the one side in the conductive layer of the k-th layer (k is 1 to n) and the (p + 1) -th sector in the conductive layers other than the k-th layer. It is electrically connected to the other end of the region, and is disposed so as to form a spiral closed loop that moves from one side of the pair of terminals to the center and moves from the center to the other terminal in a plan view. A planar coil substrate comprising a plurality of interstitial via holes.   2. The planar coil substrate according to claim 1, wherein the wiring pattern of one conductive layer among the n conductive layers has an innermost wiring in which only a part is divided and the other part is not divided. One insulating layer;
And two conductive layers laminated on both sides of the insulating layer,
The planar coil substrate according to claim 2, wherein the wiring pattern of these conductive layers is divided into two fan-shaped regions.

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