JP2002050740A - Spiral inductor - Google Patents

Spiral inductor

Info

Publication number
JP2002050740A
JP2002050740A JP2000235428A JP2000235428A JP2002050740A JP 2002050740 A JP2002050740 A JP 2002050740A JP 2000235428 A JP2000235428 A JP 2000235428A JP 2000235428 A JP2000235428 A JP 2000235428A JP 2002050740 A JP2002050740 A JP 2002050740A
Authority
JP
Japan
Prior art keywords
spiral
inductor
conductive wiring
center line
spirals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000235428A
Other languages
Japanese (ja)
Inventor
Akihiro Sawada
昭弘 澤田
Joji Hayashi
錠二 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000235428A priority Critical patent/JP2002050740A/en
Publication of JP2002050740A publication Critical patent/JP2002050740A/en
Pending legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)
  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a spiral inductor, having a small area which has the same high Q-value, as viewed from both ends of the inductor. SOLUTION: First and second spirals are formed spirally inwards from a first and a second connection end 10, 11 which are disposed symmetrically about a center line 14 passing the center of the spiral. Within the same turn, the spirals on the same side with the connection ends are formed using the one and the same conductive interconnection layer, while the spirals on the opposite side from the connection end side are formed using other conductive interconnection layer, which is electrically separated by an insulating layer from the conductive interconnection layer. The different conductive interconnection layers are cross-connected through via holes 15 on the center line, with the first and second spirals being formed symmetrically with respect to the center line.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、高周波を取り扱う
装置に用いられる受動部品の一つであるインダクタの両
端から見て同じかつ高い特性をもつ低面積のスパイラル
インダクタに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-area spiral inductor having the same and high characteristics as viewed from both ends of an inductor, which is one of passive components used in a device handling high frequency.

【0002】[0002]

【従来の技術】図2は従来のスパイラルインダクタの構
造を示すもので、図2(a)は従来のスパイラルインダ
クタの斜視図、図2(b)は平面図、図2(c)はA−
A'線における断面図である。
2. Description of the Related Art FIG. 2 shows the structure of a conventional spiral inductor. FIG. 2 (a) is a perspective view of the conventional spiral inductor, FIG. 2 (b) is a plan view, and FIG.
It is sectional drawing in the A 'line.

【0003】図2に示すように、従来のスパイラルイン
ダクタは基板21上に形成された第一の導電体配線層2
2を用いて形成され、第一の接続端23から中心に向か
ってスパイラル状に回りながら入る構造を持ち、インダ
クタの中心部に形成されたビアホール24を介して、絶
縁層25上、絶縁層26下の第二の導電体配線層27を
用いてインダクタ外の第二の接続端28へと導かれる構
成になっている。
As shown in FIG. 2, a conventional spiral inductor includes a first conductor wiring layer 2 formed on a substrate 21.
2 and has a structure that spirally enters from the first connection end 23 toward the center and enters through a via hole 24 formed in the center of the inductor. It is configured to be guided to a second connection end 28 outside the inductor by using the lower second conductor wiring layer 27.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の構成では、前記第一と第二の接続端に使用さ
れる導電体配線層が異なることにより、対基板間容量の
差が生じ、さらに前記引き出し配線とインダクタ配線の
容量結合により、インダクタの重要な特性であるQ値
は、第一の接続端23から見たからみた場合と第二の接
続端28から見た場合で異なってくる。
However, in such a conventional structure, a difference in capacitance between the substrates occurs due to the difference in the conductor wiring layers used for the first and second connection ends. Furthermore, due to the capacitive coupling between the lead wiring and the inductor wiring, the Q value, which is an important characteristic of the inductor, differs between when viewed from the first connection end 23 and when viewed from the second connection end 28.

【0005】したがって、従来のインダクタを図3に示
すような差動型発振器のインダクタに用いる場合は、イ
ンダクタの対称性を保つために図4に示すような二つの
スパイラルインダクタを対称に配置し、インダクタの両
接続端から見た特性を同じにする必要があった。
Therefore, when a conventional inductor is used as an inductor of a differential oscillator as shown in FIG. 3, two spiral inductors as shown in FIG. 4 are symmetrically arranged to maintain the symmetry of the inductor. It was necessary to make the characteristics seen from both connection ends of the inductor the same.

【0006】しかしながら図4のような構成では、スパ
イラルインダクタは見かけ上二つ必要になり、インダク
タの面積増加に伴う製造コスト増やスパイラルを形成す
る導電体配線層と基板間の容量の増加に伴うQ値の劣化
を招いてしまうことになる。
However, in the configuration shown in FIG. 4, two apparently required spiral inductors are required, and the manufacturing cost is increased due to the increase in the inductor area, and the capacitance between the conductive wiring layer forming the spiral and the substrate is increased. This results in deterioration of the Q value.

【0007】本発明はかかる点に鑑み、インダクタの両
端からみて同じかつ高いQ値を持つ低面積のスパイラル
インダクタを提供することを目的とする。
SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide a low-area spiral inductor having the same and high Q value as viewed from both ends of the inductor.

【0008】[0008]

【課題を解決するための手段】本発明のスパイラルイン
ダクタは、外部に接続するための第一,第二の接続端の
位置をスパイラルの中心を通る中心線に対して対称に配
置し、前記第一,第二の接続端から内側へらせん状に形
成される第一,第二のスパイラルを有し、前記第一,第
二のスパイラルは、同一ターン内では、前記中心線に対
し、各々の接続端と同じ側のスパイラルは同一の導電性
配線層を用いて形成し、各々の接続端と反対側のスパイ
ラルは前記導電性配線層とは絶縁層で電気的に分離され
た他の導電性配線層を用いて形成し、異なる導電性配線
層間は、前記中心線上のビアホールで接続されることを
特徴とする。
In a spiral inductor according to the present invention, the positions of first and second connection ends for external connection are arranged symmetrically with respect to a center line passing through the center of the spiral. The first and second spirals are formed spirally inward from the first and second connection ends, and the first and second spirals are each disposed within the same turn with respect to the center line. The spiral on the same side as the connection end is formed using the same conductive wiring layer, and the spiral on the opposite side to each connection end is formed of another conductive material electrically separated from the conductive wiring layer by an insulating layer. It is formed using a wiring layer, and different conductive wiring layers are connected by a via hole on the center line.

【0009】これにより、単一のスパイラルインダクタ
で、両接続端から見た対基板間の容量やスパイラル配線
間の容量を同一にすることができ、両端から見た特性を
同一にすることができ、両接続端から見たQ値を同じに
できる。
[0009] This makes it possible to make the capacitance between the substrates and the capacitance between the spiral wires as viewed from both connection ends the same with a single spiral inductor, and to make the characteristics as viewed from both ends the same. , The Q value viewed from both connection ends can be the same.

【0010】さらに、同一ターン内において、異なる導
電性配線層で形成される前記第一及び第二のスパイラル
は、各々、前記中心線に対し対称に形成されることによ
り、異なる導電性配線層を基板に対し垂直に形成するこ
とができ、スパイラル配線と基板間の容量を削減するこ
とができ、高いQ値を実現できる。
Further, in the same turn, the first and second spirals formed of different conductive wiring layers are formed symmetrically with respect to the center line so that different conductive wiring layers are formed. It can be formed perpendicular to the substrate, the capacitance between the spiral wiring and the substrate can be reduced, and a high Q value can be realized.

【0011】このように、両端からみた同一でかつ高い
Q値をもつスパイラルインダクタが低面積で実現可能と
なる。
As described above, a spiral inductor having the same high Q value as viewed from both ends can be realized with a small area.

【0012】[0012]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。
Embodiments of the present invention will be described below with reference to the drawings.

【0013】本発明の一実施形態におけるスパイラルイ
ンダクタの斜視図を図1(a)に、平面図を図1(b)
に、A−A'線における断面図を図1(c)に、B−B'
線における断面図を図1(d)に示す。
FIG. 1A is a perspective view of a spiral inductor according to an embodiment of the present invention, and FIG.
FIG. 1C is a cross-sectional view taken along line AA ′, and FIG.
A cross-sectional view taken along the line is shown in FIG.

【0014】図中10は第一の接続端、11は第二の接
続端、12は第一の導電性配線層、13は第二の導電性
配線層、14はインダクタの中心線、15はビアホー
ル、16は半導体基板、17は第一の絶縁層、18は第
二の絶縁層である。
In the figure, 10 is a first connection end, 11 is a second connection end, 12 is a first conductive wiring layer, 13 is a second conductive wiring layer, 14 is a center line of an inductor, and 15 is a center line of an inductor. A via hole, 16 is a semiconductor substrate, 17 is a first insulating layer, and 18 is a second insulating layer.

【0015】図に示すように、本実施形態のスパイラル
インダクタは、半導体基板16上に形成された第一の絶
縁層17と、第一の絶縁層17上に形成された第二の導
電性配線層13と、第二の導電性配線層13上に形成さ
れた第二の絶縁層18と、第二の絶縁層18上に形成さ
れた第一の導電体配線層12と、第一の導電性配線層1
2と第二の導電性配線層13とを電気的に接続するため
のビアホール15を有している。
As shown in FIG. 1, a spiral inductor according to the present embodiment includes a first insulating layer 17 formed on a semiconductor substrate 16 and a second conductive wiring formed on the first insulating layer 17. A layer 13, a second insulating layer 18 formed on the second conductive wiring layer 13, a first conductor wiring layer 12 formed on the second insulating layer 18, Wiring layer 1
2 has a via hole 15 for electrically connecting the second conductive wiring layer 13 to the second conductive wiring layer 13.

【0016】ここで、スパイラルインダクタを外部へ接
続するための2つの接続端10及び11は、スパイラル
の中心を通る中心線14より、対称な位置に配置する。
Here, the two connection ends 10 and 11 for connecting the spiral inductor to the outside are arranged symmetrically with respect to a center line 14 passing through the center of the spiral.

【0017】この2つの接続端よりスパイラルの中心の
周りをらせん状にまわるスパイラルの内、中心線より各
々の接続端と同じ側のスパイラルを第一の導電性配線層
12で形成し、中心線より各々の接続端と異なる側のス
パイラルを第二の導電性配線層13で形成し、第一の導
電性配線層12及び第二の導電性配線層13は中心線1
4上でビアホール15により交差的に接続する。つま
り、スパイラルが中心線14を横切る毎に、スパイラル
を形成する導電性配線層を変え、各々の導電性配線をビ
アホール15で接続する。
Of the spirals spiraling around the center of the spiral from the two connection ends, a spiral on the same side as each connection end from the center line is formed in the first conductive wiring layer 12, and the center line is formed. The spiral on the side different from each connection end is formed by the second conductive wiring layer 13, and the first conductive wiring layer 12 and the second conductive wiring layer 13
4 are cross-connected by via holes 15. That is, every time the spiral crosses the center line 14, the conductive wiring layer forming the spiral is changed, and each conductive wiring is connected by the via hole 15.

【0018】さらに、各々の接続端から始まる同一のタ
ーン数目を形成する同一層の導電性配線層を用いたスパ
イラルは、中心線14を軸に左右の形状は幾何学的に対
称に形成する。
Further, in the spiral using the same conductive wiring layer forming the same number of turns starting from each connection end, the left and right shapes are formed geometrically symmetric with respect to the center line 14 as an axis.

【0019】最後に、各々の接続端から始まるスパイラ
ルは、各々の接続端から同一の配線長及び同一のターン
数で、中心線14上で接続する。
Finally, the spirals starting from each connection end are connected on the center line 14 with the same wiring length and the same number of turns from each connection end.

【0020】したがって、本実施形態によると、見かけ
上一つのインダクタ面積において、二つの接続端から見
た対基板間容量、及び二つの接続端から見たスパイラル
を形成する導電性配線層への配線間容量は同一になり、
2つの接続端から見たQ値は同一なインダクタを実現で
き、さらに、異なる導電性配線層が基板に対し垂直に重
なることにより、スパイラルを形成する導電性配線と基
板間容量を削減することができる。
Therefore, according to the present embodiment, in an apparently one inductor area, the wiring between the conductive wiring layer forming the spiral as viewed from the two connection ends and the capacitance between the substrate as viewed from the two connection ends. The capacity between them will be the same,
The Q value seen from the two connection ends can realize the same inductor, and furthermore, since the different conductive wiring layers are vertically overlapped with the substrate, the conductive wiring forming the spiral and the capacitance between the substrates can be reduced. it can.

【0021】尚、本実施形態では、正方形のスパイラル
形状の図面を用いて説明したが、その他の多角形及び円
形形状のスパイラルでも、スパイラルの中心線に対し、
対称にスパイラルが形成できればよいことは言うまでも
ない。
Although the present embodiment has been described with reference to a square spiral shape drawing, other polygonal and circular spirals may be arranged with respect to the center line of the spiral.
It goes without saying that a spiral can be formed symmetrically.

【0022】また、本実施形態では、スパイラルを二つ
の導電性配線層を用いて形成した例を説明したが、中心
線に対し、スパイラルの左右が別の配線層である限り、
三つ以上の導電性配線層で形成してもよい。
In this embodiment, the example in which the spiral is formed using two conductive wiring layers has been described. However, as long as the left and right sides of the spiral are different wiring layers with respect to the center line,
It may be formed of three or more conductive wiring layers.

【0023】[0023]

【発明の効果】以上のように、本発明は、複数の配線層
を用いて対称な二つのインダクタを作成、接続すること
により、各々の接続端から見て同じQ値を持つインダク
タを低面積で実現でき、さらにスパイラルを形成する導
電性配線層と基板間容量の減少により、高いQ値を得る
スパイラルインダクタを実現することができる。
As described above, according to the present invention, by forming and connecting two symmetrical inductors using a plurality of wiring layers, an inductor having the same Q value as viewed from each connection end can be reduced in area. And a reduction in the capacitance between the conductive wiring layer forming the spiral and the inter-substrate can realize a spiral inductor having a high Q value.

【0024】これは半導体装置を実現する際のコスト削
減及び高性能化につながり、その効果は極めて大きい。
This leads to cost reduction and higher performance in realizing a semiconductor device, and the effect is extremely large.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(a)本発明の一実施形態におけるスパイラル
インダクタの斜視図 (b)同平面図 (c)(b)のA−A'線断面図 (d)(b)のB−B'線断面図
1A is a perspective view of a spiral inductor according to an embodiment of the present invention, FIG. 1B is a plan view thereof, FIG. 1C is a cross-sectional view taken along line AA ′ of FIG. Line cross section

【図2】(a)従来のスパイラルインダクタの斜視図 (b)同平面図 (c)(b)のA−A'線断面図2A is a perspective view of a conventional spiral inductor, FIG. 2B is a plan view thereof, and FIG.

【図3】従来の1インダクタを用いた差動型発振器の回
路図
FIG. 3 is a circuit diagram of a conventional differential oscillator using one inductor.

【図4】従来のスパイラルインダクタを用いて構成した
対称型インダクタの平面図
FIG. 4 is a plan view of a symmetrical inductor formed using a conventional spiral inductor.

【符号の説明】[Explanation of symbols]

10 第一の接続端 11 第二の接続端 12 第一の導電性配線層 13 第二の導電性配線層 14 インダクタの中心線 15 ビアホール 16 半導体基板 17 第一の絶縁層 18 第二の絶縁層 DESCRIPTION OF SYMBOLS 10 First connection end 11 Second connection end 12 First conductive wiring layer 13 Second conductive wiring layer 14 Center line of inductor 15 Via hole 16 Semiconductor substrate 17 First insulating layer 18 Second insulating layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に導電体配線をらせん状に形成し
て作られるスパイラルインダクタであって、 外部に接続するための第一及び第二の接続端の位置をス
パイラルの中心を通る中心線に対して対称に配置し、 前記第一及び第二の接続端から内側へらせん状に形成さ
れる第一及び第二のスパイラルを有し、 前記第一及び第二のスパイラルは、同一ターン内では、
前記中心線に対し、各々の接続端と同じ側のスパイラル
は同一の導電性配線層を用いて形成し、 各々の接続端と反対側のスパイラルは前記導電性配線層
とは絶縁層で電気的に分離された他の導電性配線層を用
いて形成し、 異なる導電性配線層間は、前記中心線上のビアホールで
接続されることを特徴とするスパイラルインダクタ。
1. A spiral inductor formed by spirally forming a conductor wiring on a substrate, wherein a center line passing through the center of the spiral is provided at first and second connection ends for connection to the outside. The first and second spirals are symmetrically disposed with respect to each other, and have first and second spirals formed spirally inward from the first and second connection ends, wherein the first and second spirals are in the same turn. Then
The spiral on the same side as each connection end with respect to the center line is formed by using the same conductive wiring layer, and the spiral on the opposite side to each connection end is an insulating layer with the conductive wiring layer and electrically. A spiral inductor formed by using another conductive wiring layer separated into a plurality of conductive wiring layers, wherein the different conductive wiring layers are connected by a via hole on the center line.
【請求項2】 同一ターン内において、異なる導電性配
線層で形成される前記第一及び第二のスパイラルは、各
々、前記中心線に対し対称に形成されることを特徴とす
る請求項1記載のスパイラルインダクタ。
2. The device according to claim 1, wherein the first and second spirals formed of different conductive wiring layers in the same turn are each formed symmetrically with respect to the center line. Spiral inductor.
JP2000235428A 2000-08-03 2000-08-03 Spiral inductor Pending JP2002050740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000235428A JP2002050740A (en) 2000-08-03 2000-08-03 Spiral inductor

Publications (1)

Publication Number Publication Date
JP2002050740A true JP2002050740A (en) 2002-02-15

Family

ID=18727639

Family Applications (1)

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Country Status (1)

Country Link
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005045272A (en) * 2003-07-26 2005-02-17 Samsung Electronics Co Ltd Inductor having coupling member and inductor portion in order to offer coupled magnetic field
JP2007165761A (en) * 2005-12-16 2007-06-28 Casio Comput Co Ltd Semiconductor device
EP2345152A2 (en) * 2008-10-09 2011-07-20 Altera Corporation Techniques for providing option conductors to connect components in an oscillator circuit
CN102800645A (en) * 2011-05-23 2012-11-28 矽品精密工业股份有限公司 Symmetrical Differential Inductance Structure
JP2013539924A (en) * 2010-10-15 2013-10-28 ザイリンクス インコーポレイテッド Multi-loop symmetrical inductor
JP2018160625A (en) * 2017-03-23 2018-10-11 住友電工プリントサーキット株式会社 Flat surface coil substrate

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005045272A (en) * 2003-07-26 2005-02-17 Samsung Electronics Co Ltd Inductor having coupling member and inductor portion in order to offer coupled magnetic field
JP2007165761A (en) * 2005-12-16 2007-06-28 Casio Comput Co Ltd Semiconductor device
EP2345152A2 (en) * 2008-10-09 2011-07-20 Altera Corporation Techniques for providing option conductors to connect components in an oscillator circuit
JP2012505599A (en) * 2008-10-09 2012-03-01 アルテラ コーポレイション Technology that provides an optional conductor to connect components in an oscillation circuit
EP2345152A4 (en) * 2008-10-09 2013-02-27 Altera Corp Techniques for providing option conductors to connect components in an oscillator circuit
JP2013102456A (en) * 2008-10-09 2013-05-23 Altera Corp Techniques for providing option conductors to connect components in oscillator circuit
JP2013539924A (en) * 2010-10-15 2013-10-28 ザイリンクス インコーポレイテッド Multi-loop symmetrical inductor
KR101441837B1 (en) 2010-10-15 2014-09-18 자일링크스 인코포레이티드 A multiple-loop symmetrical inductor
CN102800645A (en) * 2011-05-23 2012-11-28 矽品精密工业股份有限公司 Symmetrical Differential Inductance Structure
JP2018160625A (en) * 2017-03-23 2018-10-11 住友電工プリントサーキット株式会社 Flat surface coil substrate

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