JP2018158486A - Ink jet head control device and ink jet printer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ink jet head control device efficiently performing data transfer, and an ink jet printer.SOLUTION: An ink jet head control device according to one embodiment controls an ink jet head forming an image on a printing medium on the basis of image data and fine data. The ink jet head control device comprises: an acquisition part acquiring a plurality of pieces of byte data having the image data and the fine data; a data decompression part packetizing the plurality of pieces of byte data acquired and decompressing them on a memory; and data output part transferring the plurality of pieces of byte data decompressed on the memory to the ink jet head for each packet.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to an inkjet head control device and an inkjet printer.

  Inkjet printers that print images according to print data have been put into practical use. The inkjet printer includes, for example, an inkjet head and an inkjet head control device (inkjet head control circuit) that controls the inkjet head. The inkjet head control device develops print data input from the host PC in a page memory and transfers it to the inkjet head. The ink jet head drives an actuator for ejecting ink based on the print data input from the ink jet head control device, and forms an image on the print medium.

  In addition, there is an ink jet head having a fine adjustment function for adjusting an ink discharge amount, an ink discharge position, an ink discharge speed, and the like. The inkjet head control device receives print data including image data indicating an image to be printed and fine adjustment data for adjusting an ink ejection amount, an ink ejection position, an ink ejection speed, and the like from the host PC. get. The inkjet head control device develops image data and fine adjustment data in the page memory, and individually transfers the image data and fine adjustment data to the inkjet head. The inkjet head forms an image on the print medium based on the image data while adjusting the ink discharge amount, the ink discharge position, the ink discharge speed, and the like based on the fine adjustment data. However, in the conventional system in which image data and fine adjustment data are transferred by independent data paths, the inkjet head control device needs to transfer the image data and fine adjustment data to the inkjet head in parallel at the same timing. There is. For this reason, there is a problem that a circuit for performing Direct Memory Access (DMA) control is required by the number of data paths.

JP 2013-059961 A

  The problem to be solved by the present invention is to provide an inkjet head control device and an inkjet printer that efficiently transfer data.

  An inkjet head control device according to an embodiment is an inkjet head control device that controls an inkjet head that forms an image on a print medium based on image data and fine adjustment data, the byte having the image data and the fine adjustment data An acquisition unit that acquires a plurality of data, a data expansion unit that packetizes the acquired plurality of byte data and expands it on a memory, and a plurality of the byte data that is expanded on the memory for each packet to the inkjet head A data output unit for transfer.

FIG. 1 is a diagram for explaining a configuration example of an inkjet printer according to an embodiment. FIG. 2 is a diagram for explaining an example of byte data for each pixel used in the ink jet printer according to the embodiment. FIG. 3 is a diagram for explaining an example of packet data used in the inkjet printer according to the embodiment. FIG. 4 is a diagram for explaining a configuration example of the data output unit according to the embodiment. FIG. 5 is a diagram for describing an example of a lookup table according to an embodiment. FIG. 6 is a diagram for explaining an example of a packet counter according to an embodiment. FIG. 7 is a diagram for explaining an example of development of byte data into a page memory according to an embodiment.

Hereinafter, an inkjet head control device and an inkjet printer according to an embodiment will be described with reference to the drawings.
First, an inkjet printer 1 according to an embodiment will be described. FIG. 1 is an explanatory diagram illustrating a configuration example of an inkjet printer 1 according to an embodiment. The ink jet printer 1 is an example of an ink jet recording apparatus.

  The inkjet printer 1 receives print data from a host PC (personal computer) 2.

  The host PC 2 is an electronic device on which a program (printer driver) having a printing function is mounted, for example. The host PC 2 inputs print data, a command for changing the setting of the inkjet printer 1, and the like to the inkjet printer 1 by executing the printer driver.

  The inkjet printer 1 forms an image corresponding to print data on a print medium while conveying the print medium such as paper. The ink jet printer 1 is a printer that forms an image on a print medium by an ink jet method, for example. The ink jet printer performs print processing for forming an image on a print medium based on print data input from the host PC 2.

  The ink jet printer 1 includes a first system controller 11, a second system controller 12, an ink jet head 13, a first semiconductor memory 14, and a second semiconductor memory 15.

  The first system controller 11 performs control of data transfer to the inkjet head 13, control of communication with the host PC 2, and the like. The first system controller 11 functions as an inkjet head control device that controls the inkjet head 13.

  The second system controller 12 controls the supply of power to the inkjet head 13 and manages the status of the inkjet head 13.

  The inkjet head 13 is an image forming unit for forming an image on a print medium. The ink jet head 13 ejects ink by driving the actuator 41 based on the image data and fine adjustment data input from the first system controller 11. The inkjet head 13 forms an image on the printing medium by ejecting ink onto the printing medium conveyed by a conveyance member (not shown). The ink jet printer 1 may include a plurality of ink jet heads 13 respectively corresponding to colors such as cyan, magenta, yellow, and black, for example.

  The first semiconductor memory 14 is a storage device that stores a program executed in the first system controller 11 and data for control. The first semiconductor memory 14 is configured as, for example, a dynamic random access memory (DRAM). More specifically, the first semiconductor memory 14 is configured as a Double-Data-Rate 3 Synchronous Dynamic Random Access Memory (DDR3 SDRAM).

  The second semiconductor memory 15 is a storage device that stores a program executed in the first system controller 11 and data for control. The second semiconductor memory 15 is configured as a dynamic random access memory (DRAM), for example. More specifically, the second semiconductor memory 15 is configured as a Double-Data-Rate 3 Synchronous Dynamic Random Access Memory (DDR3 SDRAM).

  Further, the inkjet printer 1 includes a paper feed cassette, a paper discharge tray, a display unit, an operation unit, a transport motor, a motor drive circuit, a pump, a pump drive circuit, and a power supply circuit, which are not shown.

  The paper feed cassette is a cassette that stores a plurality of print media. The paper discharge tray accommodates a print medium that has been image-formed by the inkjet printer 1 and discharged.

  The display unit is a display device that displays a screen in accordance with a video signal input from the first system controller 11 or a display control unit such as a graphic controller (not shown). For example, a screen for setting the inkjet printer 1 is displayed on the display unit.

  The operation unit generates an operation signal based on the operation of the operation member. The operation member is, for example, a touch sensor, a numeric keypad, a power key, a paper feed key, various function keys, or a keyboard. The touch sensor is, for example, a resistive touch sensor or a capacitive touch sensor. The touch sensor acquires information indicating a specified position in a certain area. The touch sensor is configured as a touch panel integrally with the display unit, and inputs a signal indicating the touched position on the screen displayed on the display unit to the first system controller 11.

  The conveyance motor operates a conveyance member in a conveyance path (not shown) for conveying the print medium by rotating. The conveying member is a belt, a roller, a guide, or the like that conveys the print medium. The conveyance motor conveys the print medium along the guide by driving a roller that operates in conjunction with a belt that holds the print medium.

  The motor drive circuit is a circuit that drives the transport motor. The motor drive circuit drives the carry motor in accordance with the carry control signal input from the first system controller 11 to carry the print medium in the paper feed cassette to the paper discharge tray via the inkjet head 13.

  The pump includes, for example, a tube that communicates an ink tank (not shown) that holds ink and a common liquid chamber of the inkjet head 13.

  The pump driving circuit drives the pump in accordance with the control signal input from the first system controller 11 to supply ink in the ink tank to the common liquid chamber of the inkjet head 13.

  As shown in FIG. 1, the first system controller 11 includes a first communication unit 21, a second communication unit 22, an external I / F control circuit 23, and a first CPU (Central Processing Unit) 24. , A first memory controller 25, a second memory controller 26, a data output unit 27, a reference signal output unit 28, and the like.

  The first communication unit 21 is an interface for communicating with the host PC 2. The first communication unit 21 communicates with the host PC 2 according to a standard such as Universal Serial Bus (USB), LAN, Bluetooth (registered trademark), or Wi-Fi (registered trademark).

  The second communication unit 22 is an interface for communicating with the second system controller 12. The second communication unit 22 is configured as, for example, a Universal Asynchronous Receiver Transmitter (UART). Note that the second communication unit 22 may be configured to communicate with the second system controller 12 by other methods.

  The external I / F control circuit 23 performs data communication with, for example, a device compatible with the USB interface.

  The first CPU 24 includes an arithmetic element (for example, a processor) that executes arithmetic processing. The first CPU 24 performs various processes by executing programs stored in the first semiconductor memory 14, the second semiconductor memory 15, or a ROM (Read Only Memory) (not shown). For example, the first CPU 24 acquires print data from the host PC 2 via the first communication unit 21. The first CPU 24 generates image data indicating an image to be printed based on the print data, and fine adjustment data for adjusting the ink discharge amount, the ink discharge position, the ink discharge speed, and the like in the inkjet head 13. Generate.

  The first memory controller 25 controls data reading and data writing to the first semiconductor memory 14. The first memory controller 25 configures a page memory area in which image data and fine adjustment data are expanded on a storage area of the first semiconductor memory 14. The second memory controller 26 controls data reading and data writing to the second semiconductor memory 15. The second memory controller 26 configures a page memory area in which image data and fine adjustment data are expanded on a storage area of the second semiconductor memory 15. Note that the page memory area may be configured in either the first semiconductor memory 14 or the second semiconductor memory.

  The data output unit 27 controls data transfer to the inkjet head 13. The data output unit 27 converts the image data and fine adjustment data expanded in the page memory area into data transfer packets, and outputs the packetized image data and fine adjustment data to the inkjet head 13. The detailed configuration of the data output unit 27 will be described later.

  The reference signal output unit 28 outputs a reference signal (reference signal) of a drive signal used in the inkjet head 13 to the inkjet head 13.

  As shown in FIG. 1, the second system controller 12 includes a third communication unit 31, a second CPU 32, a status register 33, and a power supply control circuit 34.

  The third communication unit 31 is an interface for communicating with the first system controller 11. The third communication unit 31 is configured as a UART, for example. The third communication unit 31 performs handling by transmitting and receiving commands to and from the first CPU 24 of the first system controller 11. In addition, the 3rd communication part 31 may be provided with the structure which communicates with the 1st system controller 11 by another system.

  The second CPU 32 includes an arithmetic element (for example, a processor) that executes arithmetic processing. The second CPU 32 performs various processes by executing a program stored in a ROM (not shown) that stores the program. For example, the second CPU 32 controls the power supply of the inkjet head 13 and manages the status of the inkjet head 13. The second CPU 32 acquires the status of the inkjet head 13 and writes it in the status register 33.

  The status register 33 stores various statuses relating to the inkjet head 13 and the inkjet printer 1. The status includes, for example, the temperature and voltage of the inkjet head 13 and a print control status. The status stored by the status register 33 is read by the second CPU 32.

  The power control circuit 34 converts AC power supplied from a commercial power source (not shown) into DC power, and supplies the DC power to each component in the inkjet printer 1.

  As shown in FIG. 1, the inkjet head 13 includes an actuator 41 for ejecting ink, a driver IC 42 for driving the actuator 41, and the like.

  The actuator 41 is a piezoelectric element that changes the pressure in the pressure chamber of the ink liquid chamber filled with ink by being deformed according to the applied voltage. The actuator 41 is driven by the voltage input from the driver IC 42. When the actuator 41 is driven to lower the pressure in the pressure chamber, ink is drawn from the common liquid chamber of the ink liquid chamber to the pressure chamber of the ink liquid chamber. In addition, when the actuator 41 is driven to increase the pressure in the pressure chamber of the ink liquid chamber, the ink in the pressure chamber of the ink liquid chamber is discharged from the discharge nozzle provided in the ink liquid chamber.

  The driver IC 42 drives the actuator 41 by applying a potential to the electrode of the actuator 41 based on the control of the first system controller 11. For example, the driver IC 42 generates a drive signal for driving the actuator 41 according to the data transmitted from the first system controller 11, and inputs the generated drive signal to the actuator 41.

  Specifically, the driver IC 42 includes a first shift register 43, a second shift register 44, and a plurality of drive signal generation units 45.

  The first shift register 43 and the second shift register 44 are registers that temporarily store data input from the first system controller 11. The first shift register 43 temporarily stores image data. The second shift register 44 temporarily stores fine adjustment data.

  The drive signal generation unit 45 generates a drive signal for driving the actuator 41. The drive signal generation unit 45 includes image data stored in the first shift register 43, fine adjustment data stored in the second shift register 44, and a reference signal supplied from the first system controller 11. A drive signal is generated based on the above.

(About data expansion to the page memory area)
The first CPU 24 of the first system controller 11 acquires print data from the host PC 2. The first CPU 24 generates image data and fine adjustment data based on the print data, and expands the image data and fine adjustment data in the page memory area on the first semiconductor memory 14 or the second semiconductor memory 15. That is, the first CPU 24 manages the addresses of image data and fine adjustment data on the page memory area. When transferring image data and fine adjustment data, the first CPU 24 transfers the image data and fine adjustment data to the inkjet head 13 by using Direct Memory Access (DMA), which will be described later.

  For example, when the print data is an 8-bit grayscale Tiff, the first CPU 24 converts the 8-bit grayscale Tiff into 4-bit image data and 4-bit fine adjustment data for each pixel. The first CPU 24 acquires 8-bit (1 byte) data (byte data) composed of 4-bit image data and 4-bit fine adjustment data for each pixel. That is, the first CPU 24 functions as an acquisition unit that acquires byte data including image data and fine adjustment data for each pixel.

  The fine adjustment data is composed of data of 2 bits or more and 4 bits or less. The fine adjustment data includes types such as fine adjustment data A for adjusting the ink discharge amount, fine adjustment data B for adjusting the ink discharge position, and fine adjustment data C for adjusting the ink discharge speed.

  The byte data includes one or two of a plurality of types of fine adjustment data. That is, the byte data may be configured to include two of the fine adjustment data A, the fine adjustment data B, and the fine adjustment data C, or may include any one of the fine adjustment data A, the fine adjustment data B, and the fine adjustment data C. It may be a configuration. FIG. 2 shows an example of a data structure for each pixel. In the example of FIG. 2, the byte data 51 includes 4-bit image data and 4-bit fine adjustment data A. The byte data 52 includes 4-bit image data and 4-bit fine adjustment data B. The byte data 53 includes 4-bit image data and 4-bit fine adjustment data C. The byte data 54 includes 4-bit image data, 2-bit fine adjustment data A, and 2-bit fine adjustment data B. The byte data 55 includes 4-bit image data, 2-bit fine adjustment data A, and 2-bit fine adjustment data C.

  The first CPU 24 develops byte data composed of 4-bit image data and 4-bit fine adjustment data in the page memory area. That is, byte data for each pixel including 4-bit image data and 4-bit fine adjustment data is developed on the page memory area.

  The first CPU 24 packetizes byte data of a plurality of pixels and transfers it to the inkjet head 13 using DMA or the like. For this purpose, for example, the first CPU 24 uses the byte data for N nozzles (N pixels) to packetize and develop on the page memory area. More specifically, the first CPU 24 pads the byte data of a plurality of pixels so as to become data of a transfer alignment unit (packet unit) in DMA. As shown in FIG. 3, the first CPU 24 handles the data of the transfer alignment unit in the DMA as one packet. That is, the first CPU 24 generates a packet (for example, 128 bytes) composed of byte data for N nozzles and padding data. Note that the transfer alignment unit may be any number of bytes. As described above, the first CPU 24 functions as a data expansion unit that packetizes a plurality of acquired byte data and expands it on the page memory area.

(Configuration of data output unit)
Next, the configuration of the data output unit 27 will be described in detail. The data output unit 27 converts the image data and fine adjustment data developed on the page memory area as described above into data transfer packets and outputs them to the inkjet head 13. That is, the data output unit 27 transfers the byte data packetized on the page memory and expanded to the inkjet head 13 for each data transfer packet.

  FIG. 4 is an explanatory diagram illustrating a configuration example of the data output unit 27.

  The data output unit 27 includes a direct memory access (DMA) circuit 61, a first DP-RAM 62, a second DP-RAM 63, a first lookup table 64, a second lookup table 65, and a third lookup. Table 66, fourth lookup table 67, first first in first out (FIFO) circuit 68, second FIFO circuit 69, third FIFO circuit 70, fourth FIFO circuit 71, first divided transfer A control circuit 72, a second divided transfer control circuit 73, a third divided transfer control circuit 74, a fourth divided transfer control circuit 75, and a selector 76 are provided.

  The DMA circuit 61 is a circuit that reads data on the page memory area for each packet by DMA and writes the read data to the DP-RAM. The DMA circuit 61 reads data for one packet (hereinafter referred to as packet data) on the page memory area, writes the image data of the packet data into the first DP-RAM 62, and transfers the fine adjustment data of the packet data to the second DP. Write to RAM 63 Note that the clock for reading data from the page memory area (DDR clock) in the DMA circuit 61 is required to have a sufficient margin with respect to the clock for transferring packet data to the inkjet head 13 (transfer clock). .

  The first DP-RAM 62 is a buffer memory that inputs and outputs data based on a clock. The first DP-RAM 62 temporarily stores image data included in the packet data read from the page memory. The first DP-RAM 62 is, for example, a line buffer. The first DP-RAM 62 supplies the image data written by the DMA circuit 61 to the first FIFO circuit 68 via the first lookup table 64. As a result, the first DP-RAM 62 absorbs the asynchronism between the reading of data from the page memory area and the writing of data to the first FIFO circuit 68.

  The first lookup table 64 is a register in which 4 gradations (values) out of 15 gradations represented by 4 bits are associated with a logical value represented by 2 bits. When a 2-bit logical value is input, the first lookup table 64 supplies a 4-bit value associated with the input logical value to a subsequent circuit. In the first lookup table 64, a value associated with a 2-bit logical value is arbitrarily set. Note that the first lookup table 64 is an image supplied from the first DP-RAM 62 without performing the above conversion when the image data supplied from the first DP-RAM 62 is 4-bit data. The data value is supplied as it is to the subsequent circuit.

  The first FIFO circuit 68 is a circuit that stores the supplied data in order and outputs the stored data in order from the oldest stored order. The first FIFO circuit 68 stores the supplied image data in order. Also, the first FIFO circuit 68 supplies the oldest image data among the stored image data to the first division transfer control circuit 72.

  The first division transfer control circuit 72 transfers the image data supplied from the first FIFO circuit 68 to the inkjet head 13. The first division transfer control circuit 72 transfers data to the inkjet head 13 at a transfer rate corresponding to the printing frequency in the inkjet head 13.

  The second DP-RAM 63 is a buffer memory that inputs and outputs data based on a clock. The second DP-RAM 63 temporarily stores fine adjustment data included in the packet data read from the page memory. The second DP-RAM 63 is, for example, a line buffer. The second DP-RAM 63 supplies the fine adjustment data written by the DMA circuit 61 to the subsequent circuit. For example, the second DP-RAM 63 supplies the fine adjustment data A written by the DMA circuit 61 to the second FIFO circuit 69 via the second lookup table 65. Also, for example, the second DP-RAM 63 supplies the fine adjustment data B written by the DMA circuit 61 to the third FIFO circuit 70 via the third lookup table 66. For example, the second DP-RAM 63 supplies the fine adjustment data C written by the DMA circuit 61 to the fourth FIFO circuit 71 via the fourth lookup table 67. As a result, the second DP-RAM 63 absorbs the asynchronism between the reading of data from the page memory area and the writing of data to the FIFO circuit at the subsequent stage.

  The second look-up table 65, the third look-up table 66, and the fourth look-up table 67 each have 4 gradations (values) out of 15 gradations expressed by 4 bits and 2 bits. This is a register in which a logical value to be expressed is associated. The second look-up table 65, the third look-up table 66, and the fourth look-up table 67 are, when a 2-bit logical value is input, a 4-bit associated with the input logical value. The value is supplied to the subsequent circuit. In the second look-up table 65, the third look-up table 66, and the fourth look-up table 67, a value associated with a 2-bit logical value is arbitrarily set. The second look-up table 65, the third look-up table 66, and the fourth look-up table 67 are described above when the fine adjustment data supplied from the second DP-RAM 63 is 4-bit data. Without performing this conversion, the value of the fine adjustment data supplied from the second DP-RAM 63 is supplied to the subsequent circuit as it is.

  FIG. 5 is an explanatory diagram for explaining examples of the first lookup table 64, the second lookup table 65, the third lookup table 66, and the fourth lookup table 67. As shown in FIG. 5, four of the 15 gradations and 2 bits of the input value are associated with each lookup table.

  “REG_A” in FIG. 5 corresponds to the second lookup table 65 that converts the value of the fine adjustment data A. For example, when fine adjustment data A having a logical value “00” with 2 bits is input to the second lookup table 65, the second lookup table 65 stores fine adjustment data A having a value of “9” with 4 bits. Output.

  “REG_B” in FIG. 5 corresponds to the third lookup table 66 that converts the value of the fine adjustment data B. For example, when fine data B having a logical value of “00” is input by 2 bits to the third lookup table 66, the third lookup table 66 stores the fine data B having a value of “1” by 4 bits. Output.

  “REG_C” in FIG. 5 corresponds to the fourth lookup table 67 that converts the value of the fine adjustment data C. For example, if fine data C having a logical value of “00” with 2 bits is input to the fourth lookup table 67, the fourth lookup table 67 stores fine data C having a value of “8” with 4 bits. Output.

  “RESET” in FIG. 5 corresponds to the first lookup table 64 that converts the value of the image data. Since 4-bit image data is input to the first lookup table 64, the first lookup table 64 outputs the input image data as it is. Note that the first look-up table 64 may be configured to output more multi-gradation data based on the input 4-bit image data.

  The second FIFO circuit 69, the third FIFO circuit 70, and the fourth FIFO circuit 71 are circuits that store the supplied data in order and output the stored data in the oldest order. is there.

  The second FIFO circuit 69 stores the fine adjustment data A supplied from the second lookup table 65 in order. The second FIFO circuit 69 supplies the oldest fine adjustment data A among the stored fine adjustment data A to the second division transfer control circuit 73.

  The third FIFO circuit 70 stores the fine adjustment data B supplied from the third lookup table 66 in order. The third FIFO circuit 70 supplies the oldest fine adjustment data B among the stored fine adjustment data B to the third division transfer control circuit 74.

  The fourth FIFO circuit 71 stores the fine adjustment data C supplied from the fourth lookup table 67 in order. Further, the fourth FIFO circuit 71 supplies the oldest fine adjustment data C among the stored fine adjustment data C to the fourth division transfer control circuit 75.

  The second division transfer control circuit 73, the third division transfer control circuit 74, and the fourth division transfer control circuit 75 supply fine adjustment data supplied from the preceding FIFO circuit to the subsequent selector 76. The second divided transfer control circuit 73, the third divided transfer control circuit 74, and the fourth divided transfer control circuit 75 transfer data to the selector 76 at a transfer rate corresponding to the print frequency in the inkjet head 13.

  The selector 76 is a circuit that selects and outputs one of a plurality of inputs. The selector 76 selects any one of the second divided transfer control circuit 73, the third divided transfer control circuit 74, and the fourth divided transfer control circuit 75, and supplies the fine adjustment data supplied from the selected circuit to the inkjet head. 13 for transfer. That is, the selector 76 transfers data to the inkjet head 13 at a transfer rate corresponding to the printing frequency in the inkjet head 13.

(About data transfer processing)
Next, data transfer processing executed by the first system controller 11 will be described.
The first CPU 24 starts preparation for data transfer to the inkjet head 13 having a fine adjustment function. First, the first CPU 24 sets parameters necessary for data transfer in the register of the DMA circuit 61 and activates the DMA circuit 61. The parameter sets an address (transfer start address) indicating the head of data to be transferred to the inkjet head 13 and a capacity (transfer byte) of data to be transferred to the inkjet head 13. The transfer start address is an address on the page memory. Further, the first CPU 24 activates a circuit necessary for data transfer among the first divided transfer control circuit 72 to the fourth divided transfer control circuit 75.

  The DMA circuit 61 performs burst transfer of data on the page memory to the inkjet head 13 based on the transfer start address set by the first CPU 24 and the transfer byte. Specifically, the DMA circuit 61 reads the data on the page memory from the transfer start address set by the first CPU 24 by the number of bytes specified by the transfer byte, and transfers the image data to the first DP-RAM 62. Write and fine adjustment data are written in the second DP-RAM 63.

  When the first CPU 24 develops byte data for each pixel in the page memory area, the first CPU 24 packetizes and develops the data so that the data amount to be packetized corresponds to the DMA burst transfer. Thereby, the first CPU 24 can cause the DMA circuit 61 to perform burst transfer by designating the transfer start address and the number of transfer bytes.

  The first DP-RAM 62 and the second DP-RAM 63 manage the written data with pointers. The first DP-RAM 62 and the second DP-RAM 63 each include a packet counter shown in FIG. The first DP-RAM 62 and the second DP-RAM 63 update the packet counter every time packetized data is read from the page memory area. For example, when data is written by the DMA circuit 61, the first DP-RAM 62 and the second DP-RAM 63 increment the pointer on the packet counter. Further, the first DP-RAM 62 and the second DP-RAM 63 are when data is read from the first DP-RAM 62 and the second DP-RAM 63, that is, when data is output to the subsequent circuit. Decrement the pointer on the packet counter. Since one packet includes image data and fine adjustment data, the pointer given to the image data written in the first DP-RAM 62 and the second DP-RAM 63 are written. The pointer assigned to the fine adjustment data matches. That is, the first DP-RAM 62 and the second DP-RAM 63 add the same pointer to the image data and fine data of the same packet. Thus, the first DP-RAM 62 and the second DP-RAM 63 can stock a certain amount of data by distinguishing the data on the storage area with the pointer.

  By writing data in the first DP-RAM 62 and the second DP-RAM 63 in this way, fine data having the same amount as the image data amount is transferred to the first DP-RAM 62 and the second stage before the transfer control to the inkjet head 13 is performed. The second DP-RAM 63 is aligned. According to such a configuration, the subsequent circuits of the first DP-RAM 62 and the second DP-RAM 63 perform pipeline processing, so that adjustment of the output timing of image data and fine adjustment data is facilitated. That is, the first DP-RAM 62 and the second DP-RAM 63 can easily output the image data and fine adjustment data of the same packet in a synchronized state.

  Further, the FIFO circuit and the division transfer control circuit in the subsequent stage transfer the data output from the first DP-RAM 62 and the second DP-RAM 63 to the inkjet head 13 at a transfer rate corresponding to the printing frequency.

  As described above, the first CPU 24 develops packet data packetized for each pixel in the page memory area. The data output unit 27 reads the developed packet data in units of data transfer packets, distributes and stores the image data and the fine adjustment data in different line buffers, and uses the same pointer for the image data and the fine adjustment data of the same data transfer packet. It is given on the line buffer. Further, the data output unit 27 reads out the image data and the fine adjustment data to which the same pointer is assigned from each line buffer, and transfers them to the inkjet head 13.

  According to such a configuration, the data output unit 27 can asynchronously read data from the page memory area and transfer data to the inkjet head 13. That is, the data output unit 27 is not affected by the printing frequency when data is transferred to the inkjet head 13. This eliminates the need for the data output unit 27 to adjust the reading of data from the page memory area by the DMA according to the state of the subsequent FIFO. As a result, it is possible to provide an inkjet head control device that can output image data and fine adjustment data in a synchronized state by a single DMA circuit.

  Further, according to the conventional configuration, the inkjet head control device needs to control the read clock in the DMA according to the state of the FIFO. However, the data output circuit configured as described above can asynchronously read data from the page memory area and transfer data to the inkjet head 13. For this reason, the control in the data output unit 27 can be simplified.

  Further, the data output unit 27 can convert the 2-bit fine adjustment data into the 4-bit fine adjustment data via the lookup table.

  Further, when the inkjet head 13 is a shared wall type inkjet head in which one actuator is shared by two ink chambers, the packet data is transferred from the packet data according to a preset rule to form an image for one line. Need to be transferred to. This rule is, for example, a rule in which byte data for one line is divided into groups such as X, Y, and Z and transferred to the inkjet head. In such a case, the first system controller 11 needs to transfer byte data to the inkjet head for each group.

  Therefore, the first CPU 24 controls the address of the byte data on the page memory according to the order of transferring the byte data to the inkjet head 13. More specifically, the first CPU 24 develops byte data on the page memory in accordance with the order of transferring the byte data to the inkjet head 13.

  The data output unit 27 transfers the byte data to the inkjet head 13 according to the order in which the first CPU 24 develops the byte data on the page memory area. For this reason, when the first CPU 24 expands the byte data on the page memory area, the first system controller 11 controls the transfer procedure of the byte data by expanding the byte data according to a preset rule. Can do. Specifically, as shown in FIG. 7, the first CPU 24 of the first system controller 11 divides byte data for one line into groups and develops them on the page memory area. Accordingly, the first system controller 11 can easily transfer byte data to the inkjet head for each group. It should be noted that the functions described in the above embodiments are not limited to being configured using hardware, but can be realized by causing a computer to read a program describing each function using software. Each function may be configured by appropriately selecting either software or hardware.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Inkjet printer, 11 ... 1st system controller, 12 ... 2nd system controller, 13 ... Inkjet head, 14 ... 1st semiconductor memory, 15 ... 2nd semiconductor memory, 21 ... 1st communication part, DESCRIPTION OF SYMBOLS 22 ... 2nd communication part, 23 ... External I / F control circuit, 24 ... 1st CPU, 25 ... 1st memory controller, 26 ... 2nd memory controller, 27 ... Data output part, 28 ... Reference signal Output unit 31 ... third communication unit 32 ... second CPU 33 ... status register 34 ... power supply control circuit 41 ... actuator 42 ... driver IC 43 ... first shift register 44 ... second Shift register 45... Drive signal generator 61 61 DMA circuit 62 first DP-RAM 63 second DP-RAM 64 first look-up 65, second look-up table, 66 ... fourth look-up table, 67 ... fifth look-up table, 68 ... first FIFO circuit, 69 ... second FIFO circuit, 70 ... third FIFO circuit 71... Fourth FIFO circuit 72... First divided transfer control circuit 73. Second divided transfer control circuit 74. Fourth divided transfer control circuit 75. Fifth divided transfer control circuit 76 ... Selector.

Claims (5)

An inkjet head control device that controls an inkjet head that forms an image on a print medium based on image data and fine adjustment data,
An acquisition unit for acquiring a plurality of byte data having the image data and the fine adjustment data;
A data expansion unit that packetizes a plurality of the obtained byte data and expands the data on a memory;
A data output unit for transferring the plurality of byte data expanded on the memory to the inkjet head for each packet;
An inkjet head control device comprising:   2. The inkjet head control device according to claim 1, wherein the data expansion unit controls an address at which the byte data on the memory is expanded according to an order in which the byte data is transferred to the inkjet head.   3. The inkjet head control device according to claim 1, wherein the data output unit reads the byte data from the memory by a specified capacity from a specified address on the memory and transfers the byte data to the inkjet head. The data output unit includes:
A first buffer for temporarily storing the image data included in the packet read from the memory;
A second buffer for temporarily storing the fine adjustment data included in the packet read from the memory;
A division transfer control unit that reads out the image data and the fine adjustment data of the same packet from the first buffer and the second buffer, and transfers them to the inkjet head;
An inkjet head control device according to claim 1, comprising: An inkjet head that forms an image on a print medium based on the image data and the fine adjustment data;
An acquisition unit for acquiring a plurality of byte data having the image data and the fine adjustment data;
A data expansion unit that packetizes a plurality of the obtained byte data and expands the data on a memory;
A data output unit for transferring the plurality of byte data expanded on the memory to the inkjet head for each packet;
An inkjet printer comprising: