JP2018157008A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing capacity between a gate and a drain and improving switching speed.SOLUTION: A semiconductor device comprises: a first insulating layer 17 arranged between a control electrode 16 and a first main electrode 15, on a semiconductor region; a plurality of first plates 60 arranged on the first insulating layer 17 so as to be separated from each other; a second insulating layer 18 arranged on the first plate 60; a plurality of second plates 61 arranged on the second insulating layer 18 so as to be separated from each other; and a third plate 62 arranged at the control electrode 16 side from the second plate 61, on the second insulating layer, and electrically connected with a second main electrode 14. The third plate 62 and at least a part of the first plate 60 at the control electrode 16 side are overlapped with each other.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device including a lateral device.

  As a semiconductor device that operates using a two-dimensional electron gas (2DEG) as a channel, for example, a HEMT (High Electron Mobility Transistor) is known. In the HEMT, as shown by the semiconductor device 100 in FIG. 3, a two-dimensional electron gas layer (2DEG) 13 on the electron transit layer 11 side at the interface between the electron transit layer (eg GaN) 11 and the electron supply layer (eg AlGaN) 12. Is formed. A channel between the source electrode 14 and the drain electrode 15 includes the two-dimensional electron gas layer 13, and the semiconductor device performs an on / off switching operation by controlling a depletion layer generated under the gate electrode 16.

  Especially in HEMTs composed of nitride semiconductors, the forbidden band width of nitride semiconductors is wide, and the electron saturation rate of the two-dimensional electron gas layer is high, so switching operation with high power is possible with low on-resistance. It is. A semiconductor device is required to have a low on-resistance, and a high voltage of 500 V or higher may be applied to the drain electrode. Therefore, a high breakdown voltage is required between the gate electrode and the drain electrode. The withstand voltage is greatly affected by the location where the electric field is locally increased between the gate and the drain in the off state. That is, if there is a location where this electric field concentration occurs, avalanche breakdown is likely to occur at this location, and the breakdown voltage of the semiconductor device is lowered. For this reason, a structure in which a field plate electrically connected to a drain electrode or a gate electrode is provided on a nitride-based semiconductor via an insulating film, as in Patent Document 1. Further, as in the semiconductor device 100 of FIG. 3, field plates 21 and 24 are provided on the nitride semiconductor 12 via the insulating film 17 on the drain electrode 15 and the gate electrode 16, respectively. A structure in which a plurality of plates 60 that are floating potentials and are spaced apart from each other is provided between the gate electrode 16 and the gate electrode 16. As a result, the potential applied between the drain and the gate is divided by the capacitively coupled plate 60, and the potential applied to the nitride-based semiconductor 12 or the two-dimensional electron gas layer 13 under the plate 60 is the voltage of the plate 60. It is possible to make the potential corresponding to. Thereby, the location where the electric field is locally increased can be suppressed, and the breakdown voltage of the semiconductor device 100 can be increased.

JP 2007-537594 A

  The gate-drain capacitance CGD greatly contributes to the switching speed of the semiconductor device. In the HEMT, since there is a two-dimensional electron gas layer on the electron transit layer side at the interface between the electron transit layer (eg, GaN) and the electron supply layer (eg, AlGaN), the gate-drain capacitance CGD is generated over a wide range. A drain-to-drain capacitance CGD becomes a problem. In the semiconductor device 1 shown in FIG. 3, not only the capacitance between the field plate connected to the gate electrode and the 2DEG but also the capacitance via the plate 60 on the gate electrode side is added to the gate-drain capacitance CGD. .

  Accordingly, the present invention has been made in view of such problems, and an object thereof is to provide a semiconductor device that can solve the above problems.

In order to solve the above problems, the present invention has the following configurations.
The semiconductor device of the present invention includes a semiconductor region, a first main electrode provided on the semiconductor region, a second main electrode provided on the semiconductor region, and a first main electrode provided on the semiconductor region. A control electrode provided between the electrode and the second main electrode; a first insulating layer disposed between the control electrode and the first main electrode on the semiconductor region; and a first insulating layer A plurality of first plates spaced apart above, a second insulating layer disposed on the first plate, and a plurality of second plates spaced apart on the second insulating layer A plate, and a third plate disposed on the control electrode side of the second insulating layer on the second insulating layer and electrically connected to the second main electrode. At least a part of the first plate on the electrode side overlaps.

  Since the present invention is configured as described above, a semiconductor device with improved switching speed can be provided.

1 is a cross-sectional view of a semiconductor device 10. 1 is a schematic diagram showing a mechanism of a semiconductor device 10. FIG. It is a schematic diagram which shows the mechanism of the conventional semiconductor device.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described. However, it should be noted that the drawings are schematic, and the ratio of the thickness of each layer is different from the actual one. Further, the embodiment described below exemplifies an apparatus for embodying the technical idea of the present invention, and the embodiment of the present invention describes the material, shape, structure, arrangement, etc. of the components as follows. It is not limited to things.

  A cross-sectional view of a semiconductor device 10 of one embodiment is shown in FIG. The semiconductor device 10 is a HEMT (High Electron Mobility Transistor) in which a two-dimensional electron gas (2DEG) formed between two main electrodes is used as a channel. In this semiconductor device 10, an electron supply layer 12 that is a second semiconductor layer is formed on an electron transit layer 11 that is a first semiconductor layer. The electron transit layer 11 is a non-doped single crystal GaN layer, and is formed by epitaxial growth on a substrate 1 such as a silicon substrate. The thickness is, for example, about 0.5 to 10 μm. Instead of directly growing the electron transit layer 11 on the substrate 2, the electron transit layer 11 may be grown on the buffer layer 2 via the buffer layer 2 such as AlGaN. The electron transit layer 11 can be formed on the substrate 1 by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). The electron supply layer 12 is, for example, mixed crystal AlxGa1-xN (x = 0.1 to 0.4), and the thickness thereof is about 5 to 50 nm. The lattice constant of AlGaN is smaller than that of GaN. As is well known, in this structure, since a discontinuity of the band structure occurs, a two-dimensional electron gas (2DEG) layer 13 is formed on the electron transit layer 11 side at the interface between the electron transit layer 11 and the electron supply layer 12. It is formed. The electron supply layer 12 can also be formed on the electron transit layer 11 by, for example, the MOCVD method.

  A source electrode 14 that is a first main electrode (one of two main electrodes) formed on the electron transit layer 11 and a second main electrode (two main electrodes) formed on the electron transit layer 11 The drain electrode 15, which is the other of them, is electrically connected to 2DEG, and a main current flows from the drain electrode 15 to the source electrode 14 through the 2DEG when the semiconductor device is turned on. The source electrode 14 and the drain electrode 15 are made of, for example, Ti / Au as a metal capable of ohmic junction with 2DEG. A gate electrode (control electrode) 16 is provided on the electron transit layer 11 between the source electrode 14 and the drain electrode 15. The gate electrode 16 is made of, for example, a material that can be a Schottky junction with 2DEG, and can apply a voltage higher than a threshold value to the gate electrode 16 to block the 2DEG immediately below the gate electrode 16 by a depletion layer. Used. Further, a p-type metal oxide semiconductor (for example, NiOx) or the like can be used in order to perform a normally-off operation with the gate threshold of the semiconductor device 10 (HEMT) as a positive voltage. In this case, a stacked structure of a p-type metal oxide semiconductor and a metal can be used.

  A first insulating layer 17 is formed on the electron supply layer 12. The first insulating layer 17 is composed of, for example, a SiO 2 film on the TEOS film, and covers the space between the source electrode 14 and the gate electrode 16 and the space between the drain electrode 15 and the gate electrode 16, for example, 0.2 μm to 2 μm. The thickness can be as low as possible. A first field plate 21 electrically connected to the drain electrode 15 is formed on the first insulating layer 17 between the drain electrode 15 and the gate electrode 16 so as to extend to the gate electrode 16 side. . Further, a second field plate 24 electrically connected to the gate electrode 16 is formed on the first insulating layer 17 between the drain electrode 15 and the gate electrode 16 so as to extend to the drain electrode 15 side. ing. A plurality of first plates 60 are formed on the first insulating layer 17 between the first field plate 21 and the second field plate 24 so as to be separated from each other.

  The second insulating layer 18 is formed on the first field plate 21, the second field plate 24, and the plurality of first plates 60. The second insulating layer 18 is made of, for example, a TEOS film, and covers the upper part between the source electrode 14 and the gate electrode 16 and the upper part between the drain electrode 15 and the gate electrode 16, for example, 0.1 μm to 1 μm. The thickness can be as low as possible. On the second insulating layer 18 between the drain electrode 15 and the gate electrode 16, a third field plate 23 electrically connected to the drain electrode 15 through the via wiring 22 extends to the gate electrode 16 side. It is formed as follows. Further, on the second insulating layer 18 between the drain electrode 15 and the gate electrode 16, a fourth field plate 26 electrically connected to the gate electrode 16 through the via wiring 25 is formed on the drain electrode 15 side. It is formed to stretch. A plurality of second plates 61 are formed on the second insulating layer 18 between the third field plate 23 and the fourth field plate 26 so as to be separated from each other.

  The first field plate 21, the via wiring 22, the third field plate 23, the second field plate 24, the via wiring 25, and the fourth field plate 26 are made of the same metal as the source electrode 14 and the drain electrode 15. be able to. The first plate 60, the second plate 61, and the third plate 62 can be made of conductive polysilicon doped with impurities or the same metal as the source electrode 14 and the drain electrode 15.

  As shown in FIG. 1, a fifth field plate 27 electrically connected to the source electrode 14 extends toward the gate electrode 16 on the first insulating layer 17 between the source electrode 14 and the gate electrode 16. It may be formed so as to. Further, a second insulating layer 18 is also formed on the fifth field plate 27, and on the second insulating layer 18 between the source electrode 14 and the gate electrode 16, via wires 28 are provided. A sixth field plate 29 electrically connected to the source electrode 14 may be formed to extend to the gate electrode 16 side.

Of the plurality of second plates 61, the second plate 61 closest to the gate electrode 16 (hereinafter referred to as the third plate 62) is electrically connected to the source electrode 14. Therefore, the connection between the third plate 62 and the source electrode 14 is connected beyond the gate electrode 16, the second field plate 24, and the fourth field plate 26, or they are bypassed. Has been. The remaining second plate 61 and first plate 60 are at a floating potential.
In the configuration of the semiconductor device 10, the first plate 60 and the third plate 62 on the second field plate 24 side, that is, the gate electrode 16 side overlap each other by Y 1 when the semiconductor device 10 is viewed from above. As a result, the capacitance between the third plate 62 and the first plate 60 on the second field plate 24 side is reduced between the second field plate 24 and the first plate 60 on the second field plate 24 side. It can be made smaller than the capacity between. Therefore, as shown in FIG. 2, the capacity between the first plate 60 on the second field plate 24 side is dominated by the capacity between the third plate 62 and the capacity between the second plate and the first plate 60. Thus, the influence of the first plate 60 on the second field plate 24 side on the gate-drain capacitance CGD can be greatly reduced. In addition, the first plate 60 on the second field plate 24 side has the potential of the source electrode 14 + α, and can suppress a decrease in breakdown voltage.

  In the configuration of the semiconductor device 10, the fourth field plate 26 does not extend closer to the drain electrode 15 than the second field plate 24, and is on the same second insulating film 18 as the fourth field plate 26. The third plate 63 is electrically connected to the source electrode 14. Accordingly, the gate electrode is secured while ensuring the distance between the third plate 63 having the same potential as the source electrode 14 and the third field plate 23 having the same potential as the drain electrode 15 and suppressing the decrease in breakdown voltage. Electric field concentration in the vicinity of 16 can be suppressed.

  In the configuration of the semiconductor device 10, it is desirable that the first plates 60 be arranged at equal intervals in order to alleviate electric field concentration in the channel between the drain and the gate. As a result, as shown in FIG. 2, the adjacent first plates 60 are capacitively coupled to each other, and the 2DEG immediately below the first plate 60 becomes a potential corresponding to the potential of the first plate 60. The voltage between the gates can be divided at equal intervals.

  In addition, since the second plate 61 functions as a shield against foreign ions entering from the outside of the semiconductor device 10, the interval between the adjacent second plates 61 is between the third plate 62 and the third field plate. It is desirable to arrange them at equal intervals. Thereby, it is possible to suppress foreign ions entering from the upper side of FIG. 1 from entering the lower side of the second plate 61. In order to achieve the above object, the first plate 60 and the third plate 62 are overlapped by Y1 when the semiconductor device 10 is viewed from above, but the first plate 60 and the second plate 61 are not overlapped. Is desirable.

  Further, it is desirable that the thickness H1 between the first plate 60 and the third plate 62 is smaller than the thickness H2 of the first insulating layer. As a result, the capacity between the first plate 60 on the second field plate 24 side and the capacity between the third plate 62 becomes dominant compared with the capacity between the second plate and the second plate. The influence of the first plate 60 on the field plate 24 side on the gate-drain capacitance CGD can be greatly reduced.

  Further, the distance Y3 between the second field plate 24 and the first plate 60 on the second field plate 24 side is larger than the thickness H1 between the first plate 60 and the third plate. desirable. As a result, the capacity between the first plate 60 on the second field plate 24 side and the capacity between the third plate 62 becomes dominant compared with the capacity between the second plate and the second plate. The influence of the first plate 60 on the field plate 24 side on the gate-drain capacitance CGD can be greatly reduced.

  Further, it is desirable that the width Y2 of the third plate 62 is larger than the width Y4 of the first plate 60. As a result, the capacity between the first plate 60 on the second field plate 24 side and the capacity between the third plate 62 becomes dominant compared with the capacity between the second plate and the second plate. The first plate 60 on the field plate 24 side can easily realize significant reduction of the influence on the gate-drain capacitance CGD.

  In the above example, the first nitride semiconductor made of GaN is used as the electron transit layer, and the second nitride semiconductor made of AlGaN is used as the electron supply layer. In the case of a first nitride semiconductor made of InGaN, a second nitride semiconductor made of GaN as an electron supply layer, a first nitride semiconductor made of GaAs as an electron transit layer, and AlGaAs as an electron supply layer It is obvious that the same effect can be obtained if the semiconductor device uses a two-dimensional electron gas, such as the second nitride semiconductor. In addition, it is clear that the same effect can be obtained in the MESFET in which the two-dimensional electron gas layer is not formed. That is, it is obvious that the present invention can be applied to the configuration of the semiconductor layer other than the above materials.

Further, different materials can be used for the first insulating layer 17 and the second insulating layer 18 for the insulating layer.
Thus, it is needless to say that the present invention includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 10 Semiconductor device 11 Electron traveling layer 12 Electron supply layer 13 Two-dimensional electron gas (2DEG) layer 14 Source electrode 15 Drain electrode 16 Gate electrode 17 First insulating layer 18 Second insulating layer 21 First Field plates 22 and 25 Via wiring 23 Third field plate 24 Second field plate 26 Fourth field plate 60 First plate 61 Second plate 62 Third plate

Claims (4)

A semiconductor region;
A first main electrode provided on the semiconductor region;
A second main electrode provided on the semiconductor region;
A control electrode provided on the semiconductor region and provided between the first main electrode and the second main electrode;
A first insulating layer disposed between the control electrode and the first main electrode on the semiconductor region;
A plurality of first plates spaced apart on the first insulating layer;
A second insulating layer disposed on the first plate;
A plurality of second plates spaced apart on the second insulating layer;
A third plate disposed on the control electrode side of the second insulating layer on the second insulating layer and electrically connected to the second main electrode;
A semiconductor device, wherein at least a part of the third plate and the first plate on the control electrode side overlap. The semiconductor device according to claim 1, wherein a thickness between the first plate and the third plate is smaller than a thickness of the first insulating layer. The control electrode has a field plate;
3. The semiconductor device according to claim 1, wherein a distance between the field plate and the first plate is larger than a thickness between the first plate and the third plate. The semiconductor device according to claim 1, wherein a width of the third plate is wider than a width of the first plate.

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