JP2018153304A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine comprising a structure in which always a large sized accessory can be controlled stably.SOLUTION: A game machine comprises: a driver group formed of two drivers DVH, VDLi which are arranged so as to acquire pieces of same drive data Φ1-Φ4 in common; and a performance motor EMOk which operates by receiving pieces of drive data Φ1-Φ4 in four bit length from the drivers DVH, VDLi belonging to the driver group, all or some of movable performances of the game machine are achieved. In plural driver groups, a representative driver of each group except for a lowermost stream group transfers drive data which is received in synchronization with a clock signal SLCK to a downstream side driver group via an internal circuitry.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a gaming machine that performs a lottery process resulting from a game operation and executes an effect operation corresponding to the lottery result, and in particular, a game that can be stably driven and controlled even for a large accessory. Related to the machine.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

Japanese Patent Laid-Open No. 2006-7258

  In this type of gaming machine, it is desirable to excite the player by a flashy directing action. As the production operation, not only a flashy image production but also a movable production using an accessory driven by a production motor is desired to be powerful (for example, Patent Document 1).

  However, in order to achieve a powerful effect production based on such a request, the movable features increase in size and the number and the movable range tend to increase, and the power consumption increases accordingly. Therefore, with the normal device configuration, the operation limit of the drive element (driver) that drives the effect motor may be exceeded.

  Here, it is conceivable to use an expensive driver instead of a general-purpose driver. However, in that case, not only the price of the equipment of the model will rise, but also the equipment that is used in common by multiple models. It lacks general versatility.

  The present invention has been made in view of the above-described problems, and has a versatility that can be used in a plurality of models with only a minimum circuit change, and has a configuration that can stably control a large-sized object. The purpose is to provide a machine.

  In order to achieve the above object, the present invention is a gaming machine that executes an effect operation corresponding to a lottery process based on a predetermined switch signal, and the effect operation includes a movable body based on the rotation of an effect motor. The control data that serially outputs the drive data that defines the operation mode of the effect motor, one bit at a time in synchronization with the clock signal, can be acquired in common at the same timing. A plurality of M driver groups composed of a plurality of N drivers, and a presentation motor that operates by receiving drive data of a plurality of K bits as a whole from different drivers belonging to a predetermined driver group. Thus, all or part of the movable effect is realized, and the drive data is sequentially applied from the most upstream group that receives the drive data from the control circuit. In the plurality of M driver groups that have received the transfer, the representative driver of each group excluding the most downstream group sends the drive data received in synchronization with the clock signal to the downstream side via the internal circuit. It is configured to forward to a driver group.

  The N drivers preferably drive the effect motor by outputting drive data at different bit positions among the same drive data of a plurality of K bits acquired in each internal circuit. Each of the N drivers includes K shift registers connected in series, K output circuits that receive the output of each shift register and output one bit of drive data in synchronization, and the most downstream And an output shift register that serially outputs the drive data received from the shift register.

  In this case, the clock signal output from the control circuit is a pulse signal having a first edge and a second edge, and the K shift registers receive the drive data received at the input terminals of each shift register as the first clock signal. The output shift register is preferably configured to output the drive data received at the input terminal of the output shift register in synchronization with the second edge of the clock signal, while outputting in synchronization with one edge. Preferably, the K output circuits each include an output register that outputs one bit of drive data in synchronization with a latch signal received from the control circuit.

  Further, each of the K output circuits includes a gate element that receives the output of the output register at the first terminal, and a drive element that performs ON / OFF operation based on the output of the gate element. Is preferred. Here, preferably, the second terminal of the gate element is internally configured to receive a control signal from the control terminal of the driver, while the control terminal of the driver is configured in an open state, whereby the second terminal of the gate element is configured. The two terminals always receive a control signal of a passage permission level. In addition, the K drive elements incorporated in each driver include drive elements that are always in a rest state and do not flow current.

  Preferably, each driver is configured to have a clear terminal that receives a clear signal from the control circuit, and when the control circuit outputs a clear signal, a shift register built in all drivers belonging to a plurality of M driver groups. The output shift register and the output of the output register are configured to be in a clear state. A plurality of second drivers not belonging to the driver group are connected in series and receive serial data output from the control circuit in synchronization with a clock signal. The second driver is synchronized with the clock signal. The serial data received in this way is preferably transferred to the second driver on the downstream side via an internal circuit. Here, preferably, the second driver is driving a small effect motor and / or a light emitter whose power consumption is suppressed by the effect motor.

  According to the above-described present invention, it is possible to realize a gaming machine that has versatility that can be used by a plurality of models with only a minimum circuit change, and that can stably control a large-sized accessory.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is drawing explaining the internal structure of the one-chip microcomputer of an effect control part, the principal part of a motor control board, and operation | movement content. It is drawing explaining the internal structure and operation | movement of a motor driver mounted in a motor drive board | substrate. It is drawing explaining the circuit structure which drives one production | presentation motor with a pair of motor driver. It is a flowchart explaining the control operation of the effect control unit. FIG. 8 is a circuit diagram illustrating a modified circuit example of FIG. 7. It is a circuit diagram which shows the example of a circuit which drives a solenoid. It is a circuit diagram which shows the example of a circuit which drives a light emitting diode. FIG. 10 is a circuit diagram illustrating a modified circuit example of FIG. 9.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, a speaker is disposed below the glass door 6. The front plate 7 is provided with an upper plate 8 for storing game balls for launch, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 at the lower part of the front frame 3; A firing handle 10 is provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A production button 11 is provided on the outer peripheral surface of the upper plate 8. The effect button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the effect button 11 without releasing the right hand from the firing handle 10. The effect button 11 does not function normally, but, for example, when the game state becomes a button chance state, the operation of the effect button can be accepted, and the player is notified that the operation is possible by turning on the built-in lamp. The

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided in an annular shape on the surface of the game board 5, and a central opening HO extending toward the back side is provided in the approximate center. It has been. A display device DS composed of a liquid crystal color display is disposed at the bottom of the central opening HO. In addition, a symbol starting port 15, a big winning port 16, a normal winning port 17, and a gate 18 are arranged at appropriate positions in the game area.

  Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball. When it is detected that a game ball has won at the symbol start opening 15, a big hit lottery process is executed unless the holding upper limit value is exceeded, and it is determined whether or not the game state is advantageous to the player. Is done.

  In a space formed on the front surface of the display device DS, a movable effect body AMU that executes a movable effect is arranged to be movable up and down. The movable effector AMU is configured to be held by the left and right elevating mechanisms ALVa and ALVb, and moves up and down at high speed along the guide shaft PL in accordance with the rotation of the effecting motors MO1 and MO2 that drive the elevating mechanisms ALVa and ALVb.

  The movable effect body AMU may move to a target position such as the lowermost part of the display device DS at the time of the movable effect, and execute a movable effect corresponding to the rotation of the other effect motor MOi. In the standby state (origin region) located at the top, it is hidden from the player. In addition, a plurality of movable objects (not shown) are also arranged around the game board 5, and a complicated movable effect is produced by the small effect motors M1 to Mn, the large effect motors EMO1 to EMO2, and the effect solenoid. Is realized.

  The production motors of the present embodiment are the first group of production motors MOi arranged in the game frame holding the game board 5 and the second group of production motors Mx (M1 to Mn + EMO1 to EMO2) arranged on the game board 5. And, it is divided into. The first group of production motors MOi is a frame-side member GM1 (see FIG. 3) that is separable from the game board 5, and performs a somewhat routine movable production.

  On the other hand, the production motor Mx of the second group is a board-side member GM2 (see FIG. 3) integrated with the game board 5, and has a unique movable production corresponding to the game characteristics of the game machine. Run. For example, in this embodiment, the production motor EMOk (EMO1 to EMO2) suddenly drives a pair of movable objects (large-sized objects) suddenly from the left and right of the game board at the time of a predetermined notice production. The motor Mj (M1 to Mn) appropriately drives a plurality of small accessories associated with this large accessory.

  Although not particularly limited, all the stage motors MOi, Mj, EMOk of the first group and the second group are configured by stepping motors, and each stepping motor is driven by a two-phase excitation method or a 1-2 phase excitation method. (See FIGS. 7C and 7D). In this embodiment, the effect motors MO1 to MO2 that reciprocate the movable effector AMU in the vertical direction are unipolar with a constant current direction, but are preferably bipolar to increase the rotational torque. .

  By the way, an LED display portion LP for specifying the number of lottery processes in the standby state is arranged on the upper portion of the display device DS. The LED display portion LP is composed of four LED lamps corresponding to the holding upper limit value of the embodiment.

  The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has a special symbol display part Da to Dc in the center, a normal symbol display part 19 in the upper right part, and a reserved number display part NUM in the lower center part. The number-of-holds display unit NUM displays the same number of effects on hold in synchronization with the LED display unit LP.

  In the special symbol display portions Da to Dc, a reach effect is executed to expect that a big hit state will be brought about by the big win lottery, and the special symbol display portions Da to Dc and the surroundings indefinitely notify the success / failure result of the big win lottery. A notice effect is performed. The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted at the time when the game ball passes through the gate 18. The stop symbol determined by the random number for lottery is displayed and stopped.

  For example, the symbol start opening 15 is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws, and when the stop symbol after the fluctuation of the normal symbol display unit 19 hits and the symbol is displayed, the opening and closing claws are displayed. It is opened only for a predetermined time or until a predetermined number of game balls are detected.

  When a game ball wins the symbol start opening 15, an image effect in which the display symbols of the special symbol display portions Da to Dc change for a predetermined time is started on the condition that the timing is not being executed. The game stops at a stop symbol determined based on the jackpot lottery result corresponding to the winning timing of the game ball to 15. On the other hand, if a game ball wins in the symbol start opening 15 during the image production, the big hit lottery process is put on hold unless the holding upper limit value (4 pieces) is reached, and the increased number of production holdings is held on the LED display LP. It is displayed in synchronization with the number display part NUM. When the game ball is won at the symbol start opening 15 exceeding the holding upper limit value, the game ball is simply paid out as the winning ball operation, and the big hit lottery process is not executed.

  On the front surface of the display device DS and / or around it, during the series of image effects, the effect motors Mj, EMOk and / or the effect motor MOi operate to perform various movable effects as a notice effect. The For example, the movable effector AMU may drop to the position of the central opening HO. In this case, the movable effector AMU that has lowered to the target position performs an appropriate movable notice effect and then returns to the original origin area. Ascend towards.

  The big winning opening 16 is controlled to open and close by, for example, an opening / closing plate 16a that can be opened forward, but when the stop symbol after the symbol change of the special symbol display portions Da to Dc is a big hit symbol such as “777”, the “big hit game” Is started, and the opening / closing plate 16a is opened.

  After the opening / closing plate 16a of the big prize opening 16 is opened, the opening / closing plate 16a is closed when a predetermined time elapses or when a predetermined number (for example, 10) of game balls wins. In such an operation, the special game is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol of the special symbols, a privilege that the game after the end of the special game is in a high probability state is given.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations. As shown in the figure, this pachinko machine GM mainly receives the AC 24V and outputs various DC voltages, power abnormality signals ABN1, ABN2, system reset signal (power reset signal) SYS, and the like, and game control operations. Based on the main control board 21 that performs overall control, the effect control board 22 that executes the lamp effect and the sound effect based on the control command CMD received from the main control board 21, and the control command CMD ′ received from the effect control board 22 The image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls. It is mainly composed of a launch control board 25 that responds and launches a game ball.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the dispensing control board 24 via the main board relay board 32.

  The control commands CMD, CMD ′, and CMD ”are all 16 bits long, but the control commands related to the main control board 21 and the payout control board 24 are transmitted in parallel every two 8 bits. On the other hand, the control command CMD ′ transmitted from the effect control board 22 to the image control board 23 is transmitted in parallel with a 16-bit length. Even when such control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  The main control board 21, the effect control board 22, the image control board 23, and the payout control board 24 are each equipped with a computer circuit including a one-chip microcomputer. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24.

  That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. As described above, the frame-side member GM1 includes the first group of production motors MOi.

  On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member GM2 is the board side member GM2, and the board side member GM2 includes the second group of production motors Mx (= Mj, EMOk). As described above, in the present embodiment, a large accessory (movable object) is driven by the pair of effect motors EMO1 and EMO2.

  3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, a frame relay board 35, a lamp drive board 36, and a motor drive board 37. , And these circuit boards are respectively fixed at appropriate positions of the front frame 3. Here, the lamp driving board 36 is configured by connecting in series a plurality of lamp drivers having the same configuration that receives the serial signal output from the effect control unit 22 '.

  Further, the motor drive board 37 drives the first group of effect motors MOi, and the origin switch signal from the origin detection sensor arranged at the origin position of each effect motor MOi, and the button signal indicating the operation of the effect button 11 Is configured to receive. Specifically, the motor drive board 37 is configured by cascading a plurality of motor drivers DV having the same configuration that receive the serial signal output from the effect control unit 22 ′.

  Further, the motor drive board 37 collects the button signal received from the effect button 11 and the origin switch signal having a plurality of bit lengths received from the sensor board SENS, and outputs them to the effect control unit 22 ′ in the form of a serial signal. Yes.

  On the back surface of the game board 5, a main control board 21, an effect control board 22, and an image control board 23 are fixed together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  The system reset signal of the present embodiment is generated by a DC power source based on an AC power source. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset.

  The production control unit 22 ′ and the image control unit 23 ′ execute production operations dependently on the basis of a control command from the main control unit 21, and therefore, in order to avoid complication of the circuit configuration, A system reset signal SYS output from the substrate 20 is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 directly or via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4). The effect control unit 22 ′ receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26.

  Then, the effect control unit 22 ′ transmits necessary drive data to the motor driver DV mounted on the motor drive board 30 and the lamp driver mounted on the lamp drive board 29 via the effect interface board 27. Are supplied as serial signals. Further, the effect control unit 22 ′ grasps the rotation state of each effect motor Mx based on the serial signal received from the motor drive board 30. That is, an origin detection sensor is disposed at each origin motor Mj, EMOk origin position, and an n-bit origin switch signal (parallel signal SN) is transmitted to the motor drive board 30 via the sensor board SENS. And the effect control unit 22 ′ is transmitted as a serial signal SDATA1 together with other data (see FIGS. 3 and 4).

  As shown in FIG. 3, the effect control unit 22 ′ transmits and receives serial signals to and from the motor drive board 37 and the lamp drive board 36 via the effect interface board 27, the frame relay board 34, and the frame relay board 35. Is running. The production control unit 22 ′ grasps the rotation state of each production motor Mj, EMOk based on the serial signal received from the motor drive board 37 and grasps the operation of the production button 11 when necessary. The circuit configuration of the motor drive board 37 is substantially the same as that of the motor drive board 30, and the description of the motor drive board 30 described later is basically applicable to the motor drive board 37.

  As shown in FIGS. 3 and 4, the effect control unit 22 ′ has two types of control commands CMD ′ and strobe signal STB ′, and a system reset signal SYS received from the power supply board 20, with respect to the image control unit 23 ′. DC voltage (12V, 5V).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. The display device DS emits light by an LED backlight, and is driven by receiving five pairs of LVDS (Low voltage differential signaling) signals and a backlight power supply voltage (12 V) from the image interface board 28. (See FIG. 4).

  Next, the configurations of the effect control unit 22 'and the image control unit 23' will be described in more detail. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 32V is stepped down to DC15V by the DC / DC converter and used as the power supply voltage of the effect motors Mj and EMOk.

  Further, the DC voltage 5V is distributed to the production interface board 27, the lamp driving board 29, the motor driving board 30, the image interface board 28, and the image control board 23 as a power supply voltage of the digital logic circuit, and each digital circuit is supplied. It is operating.

  As shown in the drawing, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V is stepped down from 12V by the DC / DC converter, and the direct current voltage is further stepped down from 3.3V by the DC / DC converter. Only the direct current voltage of 1.8 V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  However, the DC voltage 12V received from the power supply board 20 is used as it is as the power supply voltage of the digital amplifier 46 and is distributed to the lamp drive board 29 and the motor drive board 30 to be supplied to the lamp driver and the motor driver DV. Become. Note that the DC 15V power supply voltage is supplied to the production motors Mj and EMOk as described above.

  As shown in FIG. 4, the effect control unit 22 ′ nonvolatilely stores a one-chip microcomputer 40 that executes processing such as a sound effect, a lamp effect, a notice effect by a moving object, and data transfer, and a control program for the one-chip microcomputer 40. A control memory (flash memory) 41 to be stored in memory, a voice synthesis circuit 42 to reproduce and output a voice signal based on an instruction from the one-chip microcomputer 40, and compressed voice data which is the original data of the reproduced voice signal And an audio memory 43 for storing the information.

  Here, the one-chip microcomputer 40, the control memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. It operates and significant power saving is realized. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO (Pi + Po + Po ′) and a plurality of serial input / output ports Si. Here, the serial input / output port Si functions as an input port or an output port based on values set in various control registers RG (see FIG. 5). Therefore, in this embodiment, the serial port S0 of CH0 is set as a serial output port, and the serial port S1 of CH1 is set as a serial input port. The serial port S0 will be further described in detail with reference to FIG.

  The control command CMD and the strobe signal STB from the main control unit 21 are input to the input port Pi of the parallel input / output port PIO, and the control command CMD ′ and the strobe signal STB ′ are output from the command output port Po. It is configured. Specifically, a control command CMD and a strobe signal (interrupt signal) STB output from the main control board 21 correspond to the power supply voltage 3.3 V in the buffer 44 of the effect interface board 27 at the input port Pi. Converted to a logic level to be supplied in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ specifies (2) an outline of various effect operations resulting from winning at the symbol start opening, in addition to (1) abnormality notification and other notification control commands. A control command (variation pattern command) and a control command (designation command) for designating a design type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a motor effect by the effect motors MOi, Mj, EMOk, a lamp effect by blinking the LED group, and a sound effect preparation operation by the speaker, and an image control unit 23 ′ On the other hand, the control command CMD ′ relating to the image effect synchronized with the effect operation by the lamp or the speaker is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′, along with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′, is sent to the image control unit 23 ′ through the command output port Po. CMD ′ is output toward the production interface board 27. When the production control unit 22 ′ receives a design designation command, a notification control command related to the display device DS, and other control commands, the control command is summarized in a 16-bit length. It is output toward the production interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. In this embodiment, the sound synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. The transfer clock signal, the channel control signal LRCLK, and the 2-bit length serial signals SD1 and SD2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, the serial signal SD1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and the serial signal SD2 is a heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for PCM data specifying a monaural signal. The voice synthesis circuit 42 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted.

  As shown in FIG. 4, the production interface board 27 includes parallel output ports Po ′ of the one-chip microcomputer 40 and output buffer circuits 48, 49, 50 for transmitting various signals output from the serial ports S 0, S 1. Is provided. Here, the output buffer 50 corresponds to a lamp drive signal output from a serial output port (not shown), and the output buffer 48 corresponds to a clock signal CK1 output from the serial input port S1 (FIG. 5). ing.

  The clock signal CK1 is supplied to a PS conversion circuit (not shown) of the motor drive board 30 and controls the reception operation of the serial signal SDATA1 including the origin switch signal. In the PS conversion circuit, the origin switch signal and others which are parallel signals are converted into the serial signal SDATA1, and this is serially transmitted to the serial port S1 in synchronization with the clock signal CK1.

  On the other hand, the output buffer 49 corresponds to the clock signal CK0 output from the serial output port S0, the serial signal SDATA0, and various control signals RESET and LATCH output from the parallel port P0. Then, the reset signal RESET, the latch signal LATCH, and the clock signal CK0 are supplied to a plurality of motor drivers DV mounted on the motor drive board 30 to realize a serial transmission operation of motor drive data.

  Note that all the signals RESET, LATCH, CK0, and SDATA0 output from the effect control unit 22 ′ are digital data generated by the one-chip microcomputer 40 having a power supply voltage of 3.3 V, but are leveled by the effect interface board 27. By being converted, digital data corresponding to the power supply voltage 5V is obtained. Therefore, a sufficient noise margin is ensured even when the transmission distance from the production interface board 27 to the motor driver DV is long.

  On the other hand, the serial signal SDATA1 input from the motor drive board 30 to the effect control unit 22 ′ is the reverse of the above, and is output from the motor drive board 30 as digital data corresponding to the power supply voltage 5V, which is the effect interface board. The level is converted at 27 and supplied to the one-chip microcomputer 40 (serial input port S1) having a power supply voltage of 3.3V.

  Next, the relationship between the one-chip microcomputer 40 of the effect control unit 22 ′ and the motor drive board 30 will be described in more detail with reference to FIGS. 5 to 7. 5-7, FIG. 5A shows the overall connection configuration of the one-chip microcomputer 40 and the motor drive board 30, FIG. 6A shows the internal configuration of the motor driver DV1 at the most upstream position, and FIG. (A) has shown the internal structure of a pair of motor driver VDH1 and DVL1 which function in cooperation.

  First, as shown in FIG. 5A, the one-chip microcomputer 40 sends a reset signal to the motor drivers DV (DV1 to DVn, DVHk, DVLk) of the motor drive board 30 via the parallel output port Po ′. RESET and a latch signal LATCH are output to control each motor driver DV. Specifically, the one-chip microcomputer 40 outputs the reset signal RESET, clears the output (drive data) of each motor driver DV to zero, outputs the latch signal LATCH, and updates the output of each motor driver DV. ing.

  Further, the one-chip microcomputer 40 sends the serial signal SDATA0 including the drive data Φi of the effect motors Mj and EMOk to the large number of motor drivers DV mounted on the motor drive board 30 via the serial output port S0. The signal is output in synchronization with the clock signal CK0. That is, the serial output port S0 transmits the serial signal SDATA0 to the motor drive board 30 based on the clock synchronization method.

  Here, the serial signal SDATA0 has an n × 4 bit length obtained by connecting drive data Φ1 to Φ4 for controlling the stepping motions of the n effect motors Mj (M1 to Mn), and two effect motors EMOk (EMO1). To EMO2) is serial data having a total length of (n + 2) × 4 bits obtained by concatenating 2 × 4 bit lengths obtained by concatenating drive data Φ1 to Φ4 for controlling the stepping operation. When an effect solenoid for reciprocating the accessory is provided, the serial signal SDATA0 is a total of (n + 2) × 4 + m bit length including drive data of m bits corresponding to the number m of effect solenoids.

  As shown in the circuit block diagram of FIG. 5A, the motor drive board 30 includes n motor drivers DV1 to DVn for driving n effect motors Mj (M1 to Mn) and two effect motors EMOk. Four motor drivers DVHk and DVLk for driving (EMO1 to EMO2) are arranged in cascade (k = 1 to 2). The n motor drivers DV1 to DVn on the upstream side have a normal cascade connection, but the four motor drivers DVHk and DVLk on the downstream side have a special cascade connection shown in FIG. Yes.

  As shown in FIG. 5A, the first to n-th motor drivers DV1 to DVn directly drive the effect motors M1 to Mn, respectively. On the other hand, the four motor drivers DVH1, DVL1, DVH2, and DVL2 located on the most downstream side respectively drive a large effect motor EMOk one by one in cooperation with a pair of motor drivers DVHk and DVLk. Yes. In this embodiment, two large effect motors are used, but the significance of the motor drivers DVHk and DVLk will be described later, including that this number is arbitrary.

  In any case, each of the motor drivers DV1 to DVn, DVHk, DVLk has the same internal configuration as the motor driver DV1 shown in FIG. That is, all the motor drivers DV include five shift registers SR1 to SR5 connected in series, four D latches LT1 to LT4 that receive Q outputs of the four shift registers SR1 to SR4 except the final stage, The output circuits OUT1 to OUT4 are configured to amplify the Q outputs of the D latches LT1 to LT4 and output them to the effect motors Mj and EMOk.

  Here, the output units OUT1 to OUT4 are configured by AND gates G1 to G4, switching transistors Q1 to Q4, and diodes D1 to D4 that block reverse current. In this embodiment, the ENBL terminal is open so that the four AND gates G1 to G4 connecting the D latches RT1 to RT4 and the output units OUT1 to OUT4 are always in the ON state.

  As shown in FIG. 6A, the CLR terminals of the shift registers SR1 to SR5 and the D latches LT1 to LT4 are internally configured so that the reset signal RESET is supplied all at once. Therefore, when the one-chip microcomputer 40 outputs the reset signal RESET, the Q outputs of the shift registers SR1 to SR5 and the D latches LT1 to LT4 simultaneously become L level.

  The D latches LT1 to LT4 are internally configured so that the latch signal LATCH is supplied to the write clock terminals. Therefore, when the one-chip microcomputer 40 outputs the latch signal LATCH, the Q outputs of the shift registers SR1 to SR5 are acquired by the D latches LT1 to LT4. Since the AND gates G1 to G4 are always in the ON state as described above, when the latch signal LATCH is received at the LATCH terminal of the motor driver DV, the D latches LT1 to LT4 output the Q outputs of the shift registers SR1 to SR4. Immediately after the acquisition, the switching transistors Q1 to Q4 are turned ON / OFF.

  Since the motor driver DV of the present embodiment is configured as described above, the one-chip microcomputer 40 can output the reset signal RESET and clear the output (drive data) of each motor driver DV to zero. Further, the output (drive data) of each motor driver DV can be updated by outputting the latch signal LATCH. Here, the drive data Φ1 to Φ4 are drive data for two-phase excitation or 1-2 phase excitation, and are updated by the operation procedure shown in FIGS. 7C and 7D, and a part of the serial signal SDATA0. Is output from the serial port S0.

  Then, based on the updated drive data, the motor drive current of the exciting coil Φi flows as an ON sink current into the switching transistor Qi that has been turned on in synchronization with the latch signal LATCH. On the other hand, the motor drive current of the excitation coil Φj corresponding to the switching transistor Qj that has been turned OFF in synchronization with the latch signal LATCH flows to the excitation coil Φj while being attenuated as a regenerative current passing through the diode Dj. In the present specification, the excitation coils Φ1 to Φ4 and the drive data Φ1 to Φ4 for controlling the motor drive currents of the excitation coils Φ1 to Φ4 are expressed by the same symbol Φi without being distinguished.

  Incidentally, as shown in FIG. 6A and FIG. 7A, each of the motor drivers DV1 to DVn, DVHk, DVLk includes a motor power terminal VCLAMP and an element power terminal VM. The DC power supply voltage 12V is commonly supplied to the element power supply terminal VM. Further, the motor power supply voltage VVAMP is directly supplied to the motor power supply terminals VCLAMP of the motor drivers DV1 to DVn. The motor power supply terminals VCLAMP of the motor drivers DVHk and DVLk are supplied to the motor power supply via the Zener diode ZD. A voltage of 15V is supplied.

  As shown in FIG. 7A, during the regenerative operation of the large effect motors EMO1 and EMO2, a closed circuit of diode Dj → zener diode ZD → excitation coil Φj is formed. When the switching transistor Qj is turned off, the motor drive current (ON sink current) that has flown up to that time is at a high level, so that a considerably high induced voltage is generated in the excitation coil Φj. However, in this embodiment, since the Zener diodes ZD are respectively arranged corresponding to the drivers DVHk and DVLk of the large effect motor EMOk, the excessive voltage is absorbed by the Zener diode ZD. There is no possibility of a discharge operation or a high current flowing through the exciting coil Φj.

  Returning to FIG. 6A, the description will be continued. As shown in the figure, the four shift registers SR1 to SR4 built in the motor driver DV include a clock terminal commonly connected to the SCLK terminal of the motor driver DV, and A CLR terminal commonly connected to the RESET terminal of the motor driver DV is provided.

  The SIN terminal of the motor driver DV is supplied to the D terminal of the most upstream shift register SR1, and the Q output of the shift register SR1 is supplied to the D terminal of the next stage shift register SR2. The same applies to the following, and the Q output of the i-th shift register SRi is supplied to the D terminal of the i + 1-th shift register SRi + 1.

  The Q output of the preceding shift register SR4 is supplied to the D terminal of the last shift register SR5, and the inverted signal of the SCLK terminal of the motor driver DV is supplied to the clock terminal of the shift register SR5. The Q output of the shift register SR5 is transmitted to the SOUT terminal of the motor driver DV via the output buffer.

  Here, all the shift registers SR1 to SR5 are configured to acquire data of the D terminal at the rising edge of each clock terminal. Therefore, the shift registers SR1 to SR4 acquire input data to each D terminal at the rising edge of the clock signal supplied to the SCLK terminal of the motor driver DV. On the other hand, the shift register SR5 acquires input data (Q output of the shift register SR4) to the D terminal at the falling edge of the clock signal supplied to the SCLK terminal.

  As shown in FIGS. 5 and 6, the clock signal CK0 is supplied from the effect control unit 22 ′ to the SCLK terminal of the motor driver DV, and the reset signal RESET is supplied from the effect control unit 22 ′ to the RESET terminal. It is configured. For this reason, the Q outputs of the shift registers SR1 to SR5 simultaneously become L level when receiving the reset signal RESET from the effect control unit 22 ′, and thereafter, the shift registers SR1 to SR4 It is acquired in synchronization with the rising edge of the signal CK0 (see FIG. 6B).

  On the other hand, the shift register SR5 acquires the data received at its D terminal (Q output of the shift register SR4) in synchronization with the falling edge of the clock signal CK0. Corresponding to such a configuration, for example, the effect control unit 22 ′ outputs the reset signal RESET and then outputs the 4-bit data D3 to D0 in the MSB first format in synchronization with the clock signal CK0. Assuming that at every rising edge of the clock signal CK0, the data D3, which is the MSB bit, is transferred from the shift register SR1-> SR2-> SR3-> SR4 and stored in the shift register SR4 at the rising edge of the fourth clock signal CK0. Will be. The same data D3 is stored in the shift register SR5 and output from the SOUT terminal at the falling edge of the fourth clock signal CK0. FIG. 6B is a time chart illustrating this relationship.

  In this embodiment, n motor drivers DV on the upstream side that perform the above operation are cascade-connected. Then, the n motor drivers DV1 at the most upstream position receive the serial signal SDATA0 from the one-chip microcomputer 40 at their SIN terminals, and the n−1 motor drivers DV2 to DVn located downstream thereof receive the SIN terminals. The terminal receives serial signal SDATA0 from the SOUT terminal of one upstream motor driver DV1 to DVn-1.

  On the other hand, the four downstream motor drivers DVH1, DVL1, DVH2, and DVL2 are different from the normal cascade connection, and as shown in FIG. 5A and FIG. DVHk and DVLk commonly receive the serial signal SDATA0 from the SOUT terminal of the upstream motor driver at each SIN terminal.

  Therefore, the built-in shift registers SR1 to SR4 of the pair of adjacent motor drivers DVHk and DVLk always acquire the same drive data Φ1 to Φ4 and synchronize with the clock signal CK0 received at the SCLK terminal, as shown in FIG. The shift operation shown in FIG. Therefore, four clock signals CK0 are sufficient to cause the motor drivers DVHk and DVLk to acquire new drive data Φ1 to Φ4.

  In general cascade connection, in order to acquire new drive data Φ1 to Φ4 by the motor drivers DVHk and DVLk, the same drive data is sent twice (a total of 8 bits) in synchronization with the eight clock signals CK0. Although it is necessary, according to the configuration of the embodiment, it is possible to cause two motor drivers to acquire the same drive data of DVHk and DVLk only by sending four clock signals CK0.

  With respect to the pair of motor drivers DVH1 and DVL1, as specifically shown in FIG. 7A, among the adjacent pair of motor drivers DVHk and DVLk, the upstream motor driver DVHk has the output portions OUT3 to OUT4. The upper bits Φ3 to Φ4 of the drive data are output via the switching transistors Q3 and Q4, and the motor driver DVLk on the downstream side passes through the switching transistors Q1 and Q2 of the output units OUT1 to OUT2 and outputs the drive data. It is wired to output the lower bits Φ1 to Φ2.

  That is, in this embodiment, the switching transistors Q1 and Q2 of the motor driver DVH1 and the switching transistors Q3 and Q4 of the motor driver DVL1 are not turned on. Therefore, even if the average value I of the motor drive currents flowing through the respective excitation coils Φ1 to Φ4 increases when the effect motor EMO1 rotates, it flows into the switching transistors Q3, Q4 / Q1, Q2 that function in the motor drivers DVH1, DVL1. Since the average value of the sink current is 2 × I for each motor driver and the average value of the sink current is 4 × I for each motor driver, the average value of the sink current is suppressed to half of the normal driving. There is no fear that the drivers DVH1 and DVL1 will run out of heat.

  Next, the serial port S0 will be described. As shown in FIG. 5A, the serial output port S0 receives the 1-byte data from the CPU core and the 1-byte data transferred from the transmission data register DR, and receives the setting data SDATA. As a serial output, the transmission shift register SR, a number of control registers RG for managing the internal operation state of the serial port, and the clock signal CK0 of the division ratio specified by the control register RG in response to the output pulse Φ of the counter circuit CT And a baud rate generator BG for output.

  In the case of the serial output port S0, the control register RG includes a control register capable of being read including the empty bit EMP, and indicates whether or not the transmission data register DR can accept new data. That is, when transmission of 1-byte data in transmission shift register SR is completed, empty bit EMP changes to H level (empty level), indicating that new data can be written into transmission data register DR. Therefore, the CPU core (hereinafter referred to as CPU) writes new data into the transmission data register DR after confirming that the empty bit EMP is at the H level.

  Further, the control register RG of the serial port S0 includes a WRITE control register including the transmission permission bit TXE. When the CPU sets the transmission permission bit TXE to the ON (H) level, the transmission operation of the serial output port S0 is permitted, and when it is set to the OFF level, the transmission operation is prohibited. Therefore, in this embodiment, the CPU sets the transmission permission bit TXE to the ON state at the start of the transmission process, and resets the transmission permission bit TXE to the OFF level at the end of the transmission process.

  FIG. 5B is a time chart showing the operation at the start of transmission for the serial output port S0. As shown in the figure, when the serial output port S0 is in the transmission prohibited state (TXE = L), or after the data of the transmission data register DR is serially output, the clock signal CK is at the fixed H level. The transmission data register DR is empty, and the empty bit EMP is also at the H level (empty level).

  Then, after the CPU sets the transmission permission bit TXE to the ON state (transmission permission state) and then writes the first byte of transmission data to the transmission data register DR, the empty bit EMP transitions to the L level, and then After a predetermined time (τ) elapses, the first byte of transmission data is transferred to the transmission shift register SR, and the serial transmission operation is started.

  Further, since the transmission data is transferred to the transmission shift register SR, the empty bit EMP transitions to the H level (empty level) thereafter in response to the start of serial transmission of the first bit. Therefore, after confirming the H level empty bit EMP, the CPU writes the second byte of transmission data into the transmission data register DR.

  Then, in response to the data write operation to the transmission data register DR, the empty bit EMP transitions to the L level (full level). After that, when all the transmission data of the first byte is transmitted, the second byte of data is transferred from the transmission data register DR to the transmission shift register SR, and the data transmission of the second byte is started, and the empty bit EMP Transitions to the H level.

  The empty bit EMP changes to the L level in response to the data write operation of the third byte to the transmission data register DR. However, as shown in the figure, the empty bit EMP maintains the H level when no new data is written. . Further, after all the data is transmitted, the clock signal CK maintains the H level and does not change.

  Although not particularly limited, in this embodiment, in correspondence with the internal operation of the motor driver DV, transmission is performed in synchronization with the clock signal CK0 from the MSB (Lost Significant Bit) of 1-byte data to the LSB (Least Significant Bit). The operation is set to be executed (MSB first), and an appropriate setting value is set in the corresponding control register RG. Further, as shown in the figure, the transmission operation proceeds in synchronization with the falling edge of the clock signal CK0. Here, the flag sense system has been described in which the CPU determines the empty level of the empty bit EMP and then writes the next 1-byte data into the transmission data register DR. However, the empty bit EMP has changed to the H level. Corresponding to the above, it is also preferable to adopt an interrupt method for starting interrupt processing.

  FIG. 8 is a flowchart for explaining the operation content of the effect control unit 22 ′, which is executed by the CPU of the one-chip microcomputer 40. The operation of the effect control unit 22 ′ includes a main process (FIG. 8A) executed in an infinite loop after the CPU reset, a timer interrupt process started every 1 mS (FIG. 8B), and a main control. And a reception interrupt process (not shown) for receiving a control command transmitted by the unit 21.

  In the timer interrupt process (FIG. 8B), first, a motor update process for updating the drive data of the effect motors MOi, Mj, EMOk is executed (ST20). However, since the drive data of the effect motors MOi, Mj, and EMOk is updated every time the necessary timing is reached, the process of step ST20 may be skipped in practice. Further, when the effect motor does not function, for example, when the notice effect is not being executed, the process of step ST20 is naturally skipped.

  Next, regardless of whether or not the drive data has been updated, the serial signal SDATA0 including the drive data at that time is serially transmitted from the serial output port S0 to the motor driver DV corresponding to the effect motors Mj and EMOk (ST21). . In the process of step ST21, composite data including drive data is transmitted to the motor driver DV of the effect motor MOi using another serial output port.

  The motor output process for the effect motors Mj and EMOk is as shown in FIG. 8C. First, the CPU outputs a reset signal RESET from the parallel output port Po '(ST30). As a result, the Q outputs of a total of 4 × (n + 4) shift registers SR built in n + 4 motor drivers DV all become L level. However, since the latch circuits LT1 to LT4 built in the motor driver DV do not operate at this timing, the output data to the effect motors Mj and EMOk does not change and the previous data value is maintained.

  Next, the CPU controls the serial output port S0 to output the serial signal SDATA0 in synchronization with the clock signal CK0 (ST31). As described above, in this embodiment, since the motor drivers DVHk and DVLk acquire common drive data, the serial signal SDATA0 corresponds to n + 4 motor drivers DV, not 4 × (n + 4) bits. , A total of 4 × (n + 2) bits of serial data.

  The serial signal SDATA0 is output in synchronization with the (n + 2) × 4 clock signals CK0 (ST31), so that the n motor drivers DV and the four motor drivers DVHk and DVLk have a total of 4 ×. (N + 1) -bit drive data is acquired. The acquired data of the motor drivers DVHk and DVLk are the same.

  Therefore, next, the CPU outputs the latch signal LATCH from the parallel output port Po '(ST32). As a result, the Q output data of the built-in registers (SR1 to SR4) of all the motor drivers DV are output to the motor drivers DVj, DVHk, DVLk of the rendering motors Mj, EMOk, and thus the steps of the rendering motors Mj, EMOk. The decimal operation is realized. Motor drivers DVHk and DVLk have acquired common drive data, and, as shown in FIG. 7, cooperate with each other to drive one effect motor EMOk.

  After the motor output process (ST21) is completed as described above, the command output process (ST22) for outputting the control command CMD ′ to the image control unit 23 ′ is executed when necessary, and then the origin switch signal SN is serialized. The serial signal acquisition process (ST23) acquired as a signal is executed, and finally, the CPU executes an interrupt counter increment process (ST24) to finish the 1 mS timer interrupt process.

  Next, the main process (FIG. 8A) will be described. In the main process, corresponding to the configuration of the 1 mS timer interrupt (FIG. 8B), first, the CPU repeatedly checks the interrupt counter and waits until the interrupt counter value becomes 16 (ST10). As described above, since the interrupt counter is updated every 1 mS (ST24), in step ST10, an elapsed time until 16 mS elapses from the previous processing in step ST11 is waited for. Therefore, in this embodiment, the main processing of steps ST11 to ST17 is repeated every 16 ms.

  Next, when the standby time of 16 mS has elapsed, the interrupt counter is cleared to zero (ST11), and the control command CMD transmitted from the main control unit 21 is analyzed (ST12). The control command CMD includes a change pattern command, a notice effect command, a notification control command, a hold number command, and the like.

  Therefore, in the command analysis process, as shown in FIG. 8C, first, it is determined whether or not a variation pattern command is newly received (ST70). An effect lottery that specifically specifies is executed (ST71). Then, the initial setting process is executed for the production scenario to be executed (ST73). In addition, when a notice effect command is received, an initial setting is made for the effect scenario of the notice effect (ST72, ST73). The notice effect includes effects for rotating the effect motors MO1 and MO2 corresponding to the movable effect body AMU, the other first group effect motors MOi, and the second group effect motors Mj and EMOk. The effect scenario initially set in this way is managed and progressed at intervals of 16 mS (ST14).

  Next, after determining the level of the switch signal such as the effect button 11 (ST13), the effect scenario that is set to start is updated (ST14). Then, the audio reproduction operation is advanced in response to the production scenario (ST15). The switch signal from the effect button 11 is acquired by the serial signal acquisition process (ST23).

  Subsequently, with respect to the LED groups connected to the lamp driving substrates 36 and 29, the brightness data defining the brightness of each lamp is updated based on the updated production scenario, and the LED output buffer (not shown) is updated. Luminance data is stored (ST16). Next, the setting data including the luminance data updated in the process of step ST16 is transmitted to each of the lamp driving boards 36 and 29 via a serial output port (not shown) (ST17).

  As mentioned above, although the Example of this invention was described in detail, specific description content does not limit this invention at all. For example, in the embodiment, the case where the number of large effect motors EMOk is two has been described, but there is no limitation, and the number can be increased as appropriate.

  FIG. 9 shows a case where the number of effect motors EMOk is M and driven by 2 × M motor drivers. That is, in the circuit configuration of FIG. 9, each of the plurality of M driver groups, which sequentially receives drive data from the most upstream group that receives drive data from the one-chip microcomputer 40 and reaches the most downstream group, excludes the most downstream group. One driver representing the group transfers drive data received in synchronization with the clock signal to the downstream driver group via the internal circuit.

  In the case of the circuit configuration shown in FIG. 9, each driver group is composed of two drivers, and one driver representing each group is the most downstream driver in each group. However, the number of drivers included in each driver group may be two or more. Regardless of the number of drivers, the drivers included in each driver group receive common drive data, and therefore, one representative driver may be a driver at any position.

  In the embodiment, for convenience, the configuration in which each driver DV drives the effect motor EMOk has been described, but the present invention is not limited thereto. In other words, the circuit configuration shown in FIG. 9 may be used in the case of driving a solenoid for driving an accessory, a high-luminance illumination light, a light-emitting diode, or the like, instead of or in addition to the effect motor EMOk. it can.

  FIG. 10 shows a case where a production solenoid is used, and FIG. 11 shows a case where a light emitting diode is used. For convenience of drawing, in FIG. 11, a single light emitting diode is connected to the output terminal OUTi of the driver DV, but in reality, a large number of light emitting diodes and current limiting resistors are connected in parallel. Thus, a considerable level of sink current flows through each driver DV.

  Further, in the embodiment, the model using the large effect motor EMOk has been described. However, when the large effect motor is not used, the circuit configuration of FIG. 8 or 5 can be diverted with the minimum circuit deformation. it can. FIG. 12 shows an example of a general cascade connection circuit. The SIN terminal of each driver DV is connected to the SOUT terminal of the driver DV on one upstream side and receives serial signal transfer. In the case of this circuit configuration, the Zener diode ZD can be omitted.

  In each of the above embodiments, the ball ball game machine has been described. However, it is needless to say that the application of the present invention is not limited to a ball ball game machine or a revolving game machine. In the spinning machine, the present invention can be applied to a drive motor that rotates a rotating reel. In this case, the rotating reel is a movable body, and the drive motor is positioned in the effect motor of the present invention. Note that all or part of the operation of the spinning machine is positioned as a movable effect.

EMOk Production motor Φ1 to Φ4 Drive data SLCK Clock signal 40 Control circuit DVH, VDLi Driver

Claims (11)

A gaming machine that performs an effect operation corresponding to a lottery process based on a predetermined switch signal, and the effect operation includes a movable effect in which a movable body moves based on rotation of an effect motor,
A control circuit for serially outputting drive data defining the operation mode of the effect motor one bit at a time in synchronization with the clock signal;
A plurality of M driver groups composed of a plurality of N drivers arranged so that the same drive data can be commonly acquired at the same timing;
An effect motor that operates by receiving drive data of a plurality of K-bit lengths as a whole from different drivers belonging to a predetermined driver group, and is configured to realize all or part of the movable effect,
In a plurality of M driver groups that sequentially receive drive data from the most upstream group that receives drive data from the control circuit to the most downstream group,
A representative driver of each group excluding the most downstream group is configured to transfer drive data received in synchronization with a clock signal to a downstream driver group via an internal circuit. .   2. The game according to claim 1, wherein the N drivers output the drive data at different bit positions among the same drive data of a plurality of K bits acquired in each internal circuit to drive the effect motor. Machine.   Each of the N drivers includes K shift registers connected in series, K output circuits that receive the output of each shift register and output one bit of drive data in synchronization, and the most downstream shift The gaming machine according to claim 1, further comprising: an output shift register that receives drive data from the register and serially outputs the data. The clock signal output from the control circuit is a pulse signal having a first edge and a second edge,
The K shift registers output the drive data received at the input terminal of each shift register in synchronization with the first edge of the clock signal,
The gaming machine according to claim 3, wherein the output shift register is configured to output drive data received at an input terminal of the output shift register in synchronization with the second edge of the clock signal.   5. The gaming machine according to claim 3, wherein each of the K output circuits includes an output register that outputs one bit of drive data in synchronization with a latch signal received from the control circuit. .   6. The K output circuits each include a gate element that receives an output of an output register at a first terminal, and a drive element that performs an ON / OFF operation based on the output of the gate element. The gaming machine described in 1.   While the second terminal of the gate element is internally configured to receive a control signal from the control terminal of the driver, the second terminal of the gate element is always passed by being configured in a circuit in which the control terminal of the driver is open. The gaming machine according to claim 6, which receives a control signal of a permission level.   The gaming machine according to claim 6 or 7, wherein the K drive elements incorporated in each driver include a drive element that is always in a rest state and does not flow current. Each driver is configured to have a clear terminal that receives a clear signal from the control circuit,
The shift register, the output shift register, and the output of the output register built in all drivers belonging to a plurality of M driver groups are configured to be in a clear state when the control circuit outputs a clear signal. The gaming machine described in 1. A plurality of second drivers not belonging to the driver group are connected in series and receive serial data output by the control circuit in synchronization with a clock signal;
The gaming machine according to claim 1, wherein the second driver is configured to transfer serial data received in synchronization with the clock signal to the second driver on the downstream side via an internal circuit. .   The gaming machine according to claim 10, wherein the second driver is driving a small effect motor and / or a light emitter whose power consumption is suppressed by the effect motor.

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