JP2018152731A - Receiving circuit and eye monitor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption of a receiving circuit having eye monitor function.SOLUTION: A comparison circuit 13 outputs comparison results obtained by comparing a data signal Di with a threshold TH adjusted based on an offset value THoff at a timing synchronized with a clock signal CKe having a phase adjusted based on a phase difference between the data signal Di and clock signals CKd1, CKd2, and an offset value PSoff. An eye monitor circuit 15 decimates the comparison results between the data signal Di and the threshold in a CDR circuit 12 to be obtained for each of symbols of the data signal Di, selects a comparison result in a symbol where the comparison results by the comparison circuit 13 can be obtained, and compares the selected comparison result with the comparison results of the comparison circuit 13, to determine the presence of an error due to the offset value THoff or the offset value PSoff, and outputs the number of errors generated.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a receiving circuit and an eye monitor system.

  In a receiving circuit used for an information processing device, an LSI (Large Scale Integrated circuit), or the like, CDR (Clock Data Recovery) is performed to recover a value (data) and a clock signal from a transmitted data signal. In the CDR, in order to perform data determination (sampling) at an appropriate timing, a phase difference between the data determination clock signal and the data signal is detected and the phase of the clock signal is adjusted.

  Conventionally, there is a CDR circuit that performs sampling twice (hereinafter referred to as 2 × sampling) per symbol (sometimes referred to as 1 UI (Unit Interval)) of a data signal. In this CDR circuit, a clock signal different from the clock signal for data determination is used to detect the edge portion (zero cross point) of the data signal. Then, based on the amplitude level of the data signal at the timing synchronized with the other clock signal, the timing is adjusted to be locked to the zero cross point. The clock signal for data determination is adjusted so that the phase is shifted by 0.5 UI with respect to the other clock signal.

  However, in the CDR circuit of 2x sampling, the power consumption increases because the sampling operation is performed twice per symbol. As a CDR circuit capable of reducing power consumption due to a clock signal, there is a CDR circuit that performs sampling once per symbol (hereinafter referred to as 1 × sampling). In a 1x sampling CDR circuit, a data determination circuit (including an equalization circuit, for example) determines the value of the data signal of each symbol at a timing synchronized with the clock signal. Further, the phase difference is detected and the phase of the clock signal is adjusted based on the amplitude level of the data signal at the timing of performing data determination for two symbols.

  By the way, the receiving circuit may include an eye monitor function in order to evaluate the reception characteristics inside the circuit. The eye monitor function is a function for detecting how the BER (Bit Error Rate) changes when the phase of the clock signal and the threshold value for data determination are changed. When the eye monitor function is applied to the 2x sampling CDR circuit, an offset value is added to the phase of the clock signal for data determination.

  In the latest communication standards, the multi-value transmission technology such as PAM4 (Pulse Amplitude Modulation 4) is used as a technology to improve the data rate without increasing the operating speed because the operating speed of circuits and elements is approaching the limit. It has been proposed to adopt

JP-A-2015-192200

  In a receiving circuit including a 1x sampling CDR circuit, when an offset value is added to the phase of a clock signal used for both data determination and phase difference detection, the offset value is canceled by the phase adjustment function. For this reason, the eye monitor function cannot be realized. In order to realize the eye monitor function, a clock signal whose phase can be adjusted by an offset value and a data determination circuit are added, and the data determination result is output to the data determination circuit at a timing synchronized with the clock signal. . However, in that case, there is a problem that power consumption increases. Note that this problem becomes more prominent when the multi-level transmission technique is used because the scale of the data determination circuit increases.

  In one aspect, an object of the present invention is to reduce power consumption of a receiving circuit having an eye monitor function.

  In one embodiment, a first comparison result of comparing the data signal with a first threshold at a first timing that receives the data signal and is synchronized with the first clock signal, and at the first timing, A phase difference between the data signal and the first clock signal is detected based on a second comparison result obtained by comparing the data signal with a plurality of second threshold values, and the first clock signal is detected based on the phase difference. A CDR circuit that adjusts the phase of the signal, a third threshold value that is adjusted based on the first offset value, the data signal, and a third threshold value that is adjusted based on the phase difference and the second offset value. A comparison circuit for outputting a third comparison result compared at a second timing synchronized with the second clock signal to be adjusted; and the first comparison result obtained for each symbol of the data signal or the First The first value obtained based on the comparison result is thinned out to select the fourth comparison result or the second value in the first symbol from which the third comparison result is obtained, and the third comparison result And the fourth comparison result or the second value to determine whether there is an error due to the first offset value or the second offset value, and to output the number of occurrences of the error And a monitor circuit.

  In one embodiment, an eye monitor system is provided.

  In one aspect, the present invention can suppress power consumption of a receiving circuit having an eye monitor function.

It is a figure which shows an example of the receiving circuit of 1st Embodiment. It is a figure which shows an example of a data determination circuit (DFE). It is a figure which shows the other example of a data determination circuit. It is a figure which shows an example of the eye monitor system which performs an eye monitor. It is a flowchart which shows the flow of an example of the eye monitor operation | movement of the receiving circuit controlled by a control apparatus. It is a figure which shows the example of correction | amendment of an eye waveform. It is a figure which shows the receiving circuit of a comparative example. It is a figure which shows an example of the receiving circuit of 2nd Embodiment. It is a figure which shows an example of the receiving circuit of 3rd Embodiment. It is a figure which shows the example of allocation of the 2-bit value in the data signal of PAM4. It is a figure which shows the example of adjustment of a threshold value (the 1). It is a figure which shows the example of adjustment of a threshold value (the 2). It is a figure which shows an example of the threshold value used with the data determination circuit which is 1 tap DFE. It is a figure which shows an example of the circuit which detects the characteristic of a comparison circuit. It is a figure which shows an example of a reference voltage generation circuit. It is a figure which shows an example of the receiving circuit of 4th Embodiment. It is a figure which shows an example of the receiving circuit of 5th Embodiment.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram illustrating an example of a receiving circuit according to the first embodiment.

FIG. 1 shows an example of a receiving circuit 10 that performs a half-rate operation.
The reception circuit 10 includes an equalization circuit 11, a CDR circuit 12, a comparison circuit 13, a demultiplexer (denoted as DMX in FIG. 1) 14, and an eye monitor circuit 15.

  The equalization circuit 11 receives a data signal Dr having a binary value of 0 or 1 per symbol, performs equalization processing on the data signal Dr, and outputs a data signal Di. As the equalizing circuit 11, for example, CTLE (Continuous-Time Linear Equalizer) can be used. An amplifier may be used instead of the equalization circuit 11. In that case, the amplifier outputs the data signal Di by amplifying the data signal Dr.

  The CDR circuit 12 includes a data determination circuit 12a, a plurality of comparison circuits 12b1, 12b2, 12c1, and 12c2, a demultiplexer 12d, a phase detection circuit 12e, a filter 12f, phase adjustment circuits 12g1 and 12g2, and a clock generation circuit 12h.

  The data determination circuit 12a is, for example, a DFE (Decision Feedback Equalizer) and includes a plurality of comparison circuits (see FIGS. 2 and 3). The DFE performs an equalization process for suppressing inter-symbol interference (ISI) and performs data determination. In order to perform the half-rate operation, the data determination circuit 12a outputs a comparison result (data determination result) comparing the data signal Di and the threshold at a timing synchronized with the two-phase clock signals CKd1 and CKd2. The clock signals CKd1 and CKd2 are 180 ° out of phase. Note that the rising timing of one clock signal may be used as the clock signal CKd1, and the falling timing may be used as the clock signal CKd2.

  The comparison circuit 12b1 outputs a comparison result obtained by comparing the data signal Di and the threshold value VH at a timing synchronized with the clock signal CKd1, and the comparison circuit 12b2 outputs the data signal Di and the threshold value VH at a timing synchronized with the clock signal CKd2. Output the comparison result.

  The comparison circuit 12c1 outputs a comparison result obtained by comparing the data signal Di and the threshold value VL at a timing synchronized with the clock signal CKd1, and the comparison circuit 12c2 outputs the data signal Di and the threshold value VL at a timing synchronized with the clock signal CKd2. Output the comparison result.

  When the voltage of the data signal Di changes from −1 to +1, the center of change of the amplitude of the data signal Di is 0V. For example, the threshold VH is +2/3, the threshold VL is −2/3, and the like. To do.

  The demultiplexer 12d demultiplexes the 2-bit comparison result output from the data determination circuit 12a into n bits and outputs the result as an output data signal Do. In addition, the demultiplexer 12d demultiplexes a total of 2 bits of comparison results output by the comparison circuits 12b1 and 12b2 into 1 bit, respectively, and outputs the result as a comparison result PH. In addition, the demultiplexer 12d demultiplexes the total 2 bits of the comparison results output by the comparison circuits 12c1 and 12c2 into 1 bit each, and outputs the result as the comparison result PL. For example, n is set according to the processing capability of the phase detection circuit 12e realized by a digital circuit (determined by the frequency of an operation clock signal not shown).

  The phase detection circuit 12e receives the n-bit output data signal Do output from the demultiplexer 12d and the comparison results PH and PL. The phase detection circuit 12e detects the phase difference between the data signal Di and the clock signals CKd1 and CKd2 based on the output data signal Do and the comparison results PH and PL. Then, the phase detection circuit 12e outputs a phase difference signal UD as a result of phase difference detection.

  The phase detection circuit 12e is, for example, an MM (Mueller-Muller) type phase detection circuit. The MM type phase detection circuit outputs the phase difference signal UD based on the comparison results PH and PL for two consecutive symbols and the value of the output data signal Do.

  For example, an output example of the phase difference signal UD in the case where the data signal Di changes to 1, 0 in two consecutive symbols will be described. When the amplitude level of the data signal Di is smaller than the threshold value VH in the first symbol and smaller than the threshold value VL in the next symbol, the phase of the clock signals CKd1 and CKd2 is the phase of the center of the eye of the eye pattern of the data signal Di. It is detected that it is late. In this case, a phase difference signal UD indicating that the phases of the clock signals CKd1 and CKd2 are delayed is output.

  On the other hand, when the amplitude level of the data signal Di is larger than the threshold value VH in the first symbol and larger than the threshold value VL in the next symbol, the phases of the clock signals CKd1 and CKd2 are the center of the eye of the eye pattern of the data signal Di. It is detected that the phase is advanced with respect to the phase. In this case, a phase difference signal UD indicating that the phases of the clock signals CKd1 and CKd2 are advanced is output.

  The filter 12f filters the phase difference signal UD to generate an adjustment signal. The filter 12f is not limited to a digital filter, and has a charge pump that adjusts the current value according to the phase difference signal UD, converts the adjusted current value into a voltage value, and outputs the voltage value as an adjustment signal. Such a circuit may be used.

  The phase adjustment circuit 12g1 receives two of the four (or three) clock signals output from the clock generation circuit 12h, and the clock signals CKd1 and CKd2 whose phases are adjusted based on the adjustment signals output from the filter 12f Is output.

  The phase adjustment circuit 12g2 receives two (or one) clock signal output from the clock generation circuit 12h, and one clock whose phase is adjusted based on the adjustment signal output from the filter 12f and the offset value PSoff. The signal CKe is output.

The clock generation circuit 12h generates and outputs four (or three) clock signals having the same frequency, for example.
The comparison circuit 13 outputs a comparison result obtained by comparing the data signal Di and the threshold value TH whose size is adjusted based on the offset value THoff at a timing synchronized with the clock signal CKE.

The demultiplexer 14 demultiplexes the 1-bit comparison result output from the comparison circuit 13 into n / 2 bits and outputs the result as a data signal Eo.
The eye monitor circuit 15 thins out the comparison result by the data determination circuit 12a obtained for each symbol of the data signal Di, and selects the comparison result in the symbol from which the comparison result by the comparison circuit 13 is obtained. Then, the eye monitor circuit 15 compares the selected comparison result with the comparison result by the comparison circuit 13 to determine the presence / absence of an error based on the offset values PSoff and THoff, and the error count ERRcnt [1: 0] is output. The eye monitor circuit 15 shown in FIG. 1 outputs 1 as a signal ECfin indicating that a predetermined number of times of error determination has been completed.

The eye monitor circuit 15 includes a 2: 1 selector 15a, an error detection circuit 15b, a selector 15c, an error check number counter 15d, and an error number counter 15e.
The 2: 1 selector 15a receives the output data signal Do and the selection signal SEL, and selects either the odd bit or the even bit out of the n-bit output data signal Do based on the selection signal SEL. Output as 2-bit data signal. That is, the 2: 1 selector 15a has a function of thinning out the comparison result by the data determination circuit 12a. The frequency with which the data determination circuit 12a outputs the comparison result is symbol by symbol. On the other hand, since the comparison circuit 13 outputs the comparison result once every two symbols, the 2: 1 selector 15a having such a thinning function is used so that comparison with the same symbol is possible. .

  The error detection circuit 15b receives the n / 2-bit data signal Eo output from the demultiplexer 14 and the n / 2-bit data signal output from the 2: 1 selector 15a. Then, the error detection circuit 15b compares the comparison result by the data determination circuit 12a and the comparison result by the comparison circuit 13 in the same symbol of the data signal Di and determines whether or not they match. That is, the error detection circuit 15b uses the offset values PSoff and THoff to determine whether or not a mismatch between the data signal Eo and the output data signal Do occurs (whether an error occurs). The error detection circuit 15b outputs a signal indicating that error determination has been performed every time error determination is performed, and outputs a signal indicating that an error has occurred when an error has occurred.

  The error detection circuit 15b receives the start signal ST, and when the start signal ST changes from 0 to 1, the error detection circuit 15b detects phase synchronization (lock) between the data signal output from the 2: 1 selector 15a and the data signal Eo. After the lock is detected, error determination is started.

  The selector 15c receives a signal indicating that an error output from the error detection circuit 15b has occurred, and compares the signal indicating that an error has occurred in a certain symbol with the data determination circuit 12a in the symbol preceding that symbol. Separate each value and output separately. The reason for this will be described later. FIG. 1 shows an example of the selector 15c corresponding to the case where the data determination circuit 12a is DFE and the number of taps of the DFE is 1. In this case, the selector 15c is a 1: 2 selector that separately outputs a signal indicating that an error has occurred depending on whether the value of the output data signal Do one bit (one symbol) before is 0 or 1.

When the number of DFE taps is n (n ≧ 2) (when the influence of ISI due to two or more symbols before is considered), the selector 15c is a 1: 2 ⁿ selector.
The error check number counter 15d receives the signal indicating that the error determination output from the error detection circuit 15b has been performed, and counts the number of error determinations (error check number). Further, the error check number counter 15d outputs 1 as the signal ECfin when the count value reaches a predetermined value.

  The error number counter 15e receives a signal indicating that an error output from the selector 15c has occurred, and counts the number of error occurrences separately depending on whether the value of the output data signal Do one bit before is 0 or 1. Then, the error number counter 15e outputs the counted result as the error number ERRcnt [1: 0].

When the data determination circuit 12a is a DFE with n (n ≧ 2) taps, the error number counter 15e outputs n ² types of errors.
Note that the offset values PSoff and THoff, the selection signal SEL, and the start signal ST are supplied from, for example, a control device (not shown) outside or inside the receiving circuit 10. The offset values PSoff and THoff are, for example, digital codes.

  FIG. 1 shows an adjustment example of two consecutive symbols m and m + 1 of the data signal Di and offset values PSoff and THoff. The horizontal axis represents time, and the vertical axis represents voltage. Waveform 16 is a superposition of all transitions of data signal Di. Timings t1, t4, and t6 indicate timings synchronized with the clock signal CKe, timings t2 and t5 indicate timings synchronized with the clock signal CKd1, and timings t3 and t7 indicate timings synchronized with the clock signal CKd2.

For example, when the offset value THoff is increased by ΔTHoff at the timing t1, the threshold value TH in the comparison circuit 13 is increased from the threshold value TH1 by the threshold value TH2.
Further, when the offset value THoff reaches the maximum value at timing t4 (in the example of FIG. 1, the offset value THoff at which the threshold value TH reaches the threshold value VH), the offset value PSoff is increased by ΔPSoff. Then, the offset value THoff is set to the minimum value (in the example of FIG. 1, the value of the offset value THoff at which the threshold value TH becomes the threshold value VL).

  Note that the method of adjusting the offset values THoff and PSoff is not limited to the above method. For example, when the BER obtained based on the error number ERRcnt is greater than a predetermined value, a control device (not shown) may stop increasing the offset values THoff and PSoff and return them to the minimum value.

(Example of data determination circuit (DFE) 12a)
FIG. 2 is a diagram illustrating an example of a data determination circuit (DFE). In FIG. 2, a direct feedback type 1-tap DFE corresponding to the half-rate operation is shown as an example of the data determination circuit 12a.

The data determination circuit 12a includes addition circuits 12a1 and 12a2, comparison circuits 12a3 and 12a4, registers 12a5 and 12a6, and amplifiers 12a7 and 12a8.
The adder circuit 12a1 subtracts the correction value (plus or minus value) output from the amplifier 12a8 from the data signal Di. The adder circuit 12a2 subtracts the correction value (plus or minus value) output from the amplifier 12a7 from the data signal Di.

  The comparison circuit 12a3 outputs a comparison result (0 or 1) obtained by comparing the output signal of the addition circuit 12a1 with a threshold VM (for example, 0V) at a timing synchronized with the clock signal CKd1. The comparison circuit 12a4 outputs a comparison result (0 or 1) comparing the output signal of the addition circuit 12a2 and the threshold value VM at a timing synchronized with the clock signal CKd2.

  The register 12a5 takes in the value output from the comparison circuit 12a3 at a timing synchronized with the clock signal CKd2, and outputs it as the output signal OUT [0]. The register 12a6 takes in the value output from the comparison circuit 12a4 at the timing synchronized with the clock signal CKd1, and outputs it as the output signal OUT [1].

  The amplifier 12a7 outputs a correction value obtained by multiplying the output signal OUT [0] by a predetermined equalization coefficient (corresponding to the gain of the amplifier 12a7). The amplifier 12a8 outputs a correction value obtained by multiplying the output signal OUT [1] by the equalization coefficient (corresponding to the gain of the amplifier 12a8). The equalization coefficient is a value corresponding to the influence of ISI (Inter-Symbol Interference) due to the value one bit before. When the output signals OUT [0] and OUT [1] are 0, the correction value is a negative value. When the output signals OUT [0] and OUT [1] are 1, the correction value is a positive value. It becomes the value of.

  In such a data determination circuit 12a, the output signal OUT [0] and the output signal OUT [1] are alternately output. In addition, the data determination circuit 12a subtracts the deterioration of the signal generated according to the previous value (output signal OUT [0] or output signal OUT [1]) from the data signal Di as the correction value. Correct signal degradation.

However, the feedback loop of the direct feedback type DFE includes a circuit having a large delay time such as the addition circuits 12a1 and 12a2.
Therefore, a data determination circuit as shown below may be used instead of the data determination circuit 12a as shown in FIG.

FIG. 3 is a diagram illustrating another example of the data determination circuit.
The data determination circuit 12i is a 1-tap speculative DFE that supports half-rate operation.

The data determination circuit 12i includes comparison circuits 12i1, 12i2, 12i3, 12i4, selectors 12i5, 12i6, and registers 12i7, 12i8.
The comparison circuit 12i1 outputs a comparison result (0 or 1) comparing the data signal Di and a threshold value VM + (for example, a value obtained by adding the correction value to 0V) at a timing synchronized with the clock signal CKd1. The comparison circuit 12i2 outputs a comparison result (0 or 1) comparing the data signal Di and a threshold value VM− (for example, a value obtained by subtracting the correction value from 0V) at a timing synchronized with the clock signal CKd1.

  The comparison circuit 12i3 outputs a comparison result (0 or 1) comparing the data signal Di and the threshold value VM + at a timing synchronized with the clock signal CKd2. The comparison circuit 12i4 outputs a comparison result (0 or 1) comparing the data signal Di and the threshold value VM− at a timing synchronized with the clock signal CKd2.

  The selector 12i5 selects and outputs the comparison result in the comparison circuit 12i1 when the output signal OUT [1] of the register 12i8 is 1, and the output of the comparison circuit 12i2 when the output signal OUT [1] is 0. Select the comparison result and output it.

  The selector 12i6 selects and outputs the comparison result in the comparison circuit 12i3 when the output signal OUT [0] of the register 12i7 is 1, and the output of the comparison circuit 12i4 when the output signal OUT [0] is 0. Select the comparison result and output it.

  The register 12i7 takes in the value output from the selector 12i5 at the timing synchronized with the clock signal CKd2, and outputs it as the output signal OUT [0]. The register 12i8 takes in the value output from the selector 12i6 at the timing synchronized with the clock signal CKd1, and outputs it as the output signal OUT [1].

  In such a data determination circuit 12i, any one of the comparison results in the comparison circuits 12i1 to 12i4 for comparing the threshold values VM + and VM− to which the correction value considering the influence of ISI is given in advance and the data signal Di is used. 1 bit is selected and output according to the previous value. This compensates for signal degradation. Since the data determination circuit 12i uses a circuit having a relatively short delay time such as the selectors 12i5 and 12i6, the delay time of the feedback loop is shorter than that of the direct feedback type DFE.

(Example of an eye monitor using the receiving circuit 10)
Hereinafter, an example of an eye monitor using the receiving circuit 10 illustrated in FIG. 1 will be described.
FIG. 4 is a diagram illustrating an example of an eye monitor system that executes an eye monitor.

The eye monitor system includes a receiving circuit 10, a control device 20, and a display device 20a.
The control device 20 supplies the offset values PSoff and THoff, the selection signal SEL, and the start signal ST to the reception circuit 10 and receives the data signal Eo, the signal ECfin, and the error number ERRcnt [1: 0] from the reception circuit 10. Then, the control device 20 executes software stored in a memory (not shown), and based on the signal ECfin and the error number ERRcnt [1: 0] when the offset values PSoff and THoff are changed, the display device An eye waveform is displayed at 20a.

The control device 20 may be, for example, a computer (such as a personal computer) or a processor provided on the same substrate as the receiving circuit 10.
FIG. 5 is a flowchart showing a flow of an example of the eye monitor operation of the receiving circuit controlled by the control device.

  The eye monitor operation is performed, for example, at the time of operation verification when a prototype of the reception circuit 10 is manufactured, at the time of a shipping test of the reception circuit 10, or at the time of operation verification in a transmission / reception system including the reception circuit 10.

  First, the offset value THoff is set in the comparison circuit 13 under the control of the control device 20. Further, the offset value PSoff is set in the phase adjustment circuit 12g2 (step S1). Further, the selection signal SEL of the 2: 1 selector 15a is set (step S2), and the start signal ST for the error detection circuit 15b is set to 1 (step S3).

  When the start signal ST is set to 1, the error detection circuit 15b detects the phase synchronization (lock) between the data signal output from the 2: 1 selector 15a and the data signal Eo (step S4), and locks the lock signal. After the detection, error determination is started (step S5). In the process of step S5, the error check number counter 15d receives the signal indicating that the error determination output from the error detection circuit 15b has been performed, and starts counting the number of error determinations (number of error checks). To do. The error number counter 15e receives a signal indicating that an error output from the selector 15c has occurred, and counts the number of occurrences of the error separately depending on whether the value of the output data signal Do one bit before is 0 or 1. .

  The error check number counter 15d determines whether or not the error check number (count value) has reached a predetermined value Nth (step S6). If the error check number has not reached the value Nth, step S6 Repeat the process. The error check number counter 15d outputs 1 as the signal ECfin when the error check number reaches the value Nth (step S7).

  When the signal ECfin becomes 1, the start signal ST is set to 0 under the control of the control device 20 (step S8). Thereby, the error detection circuit 15b stops the error determination.

  Thereafter, if the offset values THoff and PSoff are not the maximum values (step S9: NO), the offset value THoff or the offset value PSoff is incremented (step S10), and the processing from step S1 is repeated.

When the offset values THoff and PSoff are both maximum values (step S9: YES), the eye monitoring operation of the receiving circuit 10 is finished.
For example, in each combination of the offset values THoff and PSoff, the control device 20 causes the display device 20a to display an eye waveform based on the number of errors ERRcnt [1: 0] when the signal ECfin becomes 1.

  For example, in a certain symbol of the data signal Di, when the determination result output by the data determination circuit 12a is 1, when the offset value THoff increases, the threshold value TH increases and may exceed the amplitude level of the data signal Di. In that case, the determination result output from the comparison circuit 13 is inverted to zero. As a result, an error is detected in the error detection circuit 15b.

  When the offset value THoff increases, many such errors are detected. Further, when the offset value THoff decreases, the threshold value TH is often lower than the amplitude level when the value of the data signal Di is 0, and many errors are detected. Therefore, the control device 20 can estimate the amplitude level of the data signal Di, that is, the eye height of the eye waveform from the increase in the number of errors ERRcnt [1: 0].

  Even if the offset value PSoff increases (or increases in the negative direction), the error number ERRcnt [1: 0] increases in the same manner. For example, when the offset value PSoff increases and the sampling timing exceeds the eye boundary, the error number ERRcnt increases. Thus, the eye width of the eye waveform can be estimated.

  Further, the control device 20 corrects the eye waveform based on the correction value used in the data determination circuits 12a and 12i as shown in FIG. 2 or 3, and the eye after the equalization processing by the data determination circuits 12a and 12i. The waveform can be reproduced.

FIG. 6 is a diagram showing an example of eye waveform correction. In FIG. 6, the horizontal axis represents time, and the vertical axis represents voltage.
The eye waveform 25 is obtained based on the number of occurrences of errors when the value of the output data signal Do one bit before is 1. The eye waveform 26 is obtained based on the number of occurrences of errors when the value of the output data signal Do one bit before is 0.

  The control device 20 obtains the eye waveform 25a by subtracting the correction value C1 used in the data determination circuits 12a and 12i from the eye waveform 25. Further, the control device 20 adds the correction value C1 used in the data determination circuits 12a and 12i to the eye waveform 26, thereby obtaining the eye waveform 26a. The control device 20 holds a correction value C1 in advance.

  Then, the control device 20 displays the eye waveforms 25a and 26a on the display device 20a so as to equivalently present the eye waveforms after the equalization processing by the data determination circuits 12a and 12i, for example, to the user. be able to.

  By using the receiving circuit 10 of the first embodiment as described above, the eye monitor function as described above can be realized, and instead of providing a circuit similar to the data determination circuit 12a, one comparison circuit 13 is provided. Since it suffices to provide power consumption, power consumption can be reduced.

For example, when the same circuit as the data determination circuit 12a is used instead of the comparison circuit 13, a receiving circuit as shown below is obtained.
(Receiving circuit of comparative example)
FIG. 7 is a diagram illustrating a receiving circuit of a comparative example. In FIG. 7, the same elements as those shown in FIG.

  In the reception circuit 30, a DFE 32 is provided instead of the comparison circuit 13 shown in FIG. The DFE 32 is a circuit similar to the data determination circuit 12a as shown in FIG. 2 or the data determination circuit 12i as shown in FIG. In the receiving circuit 30, the threshold value that the DFE 32 compares with the data signal Di is adjusted by the offset value THoff. Since the DFE 32 operates at a half rate, the DFE 32 outputs a comparison result between the data signal Di and the threshold at a timing synchronized with the two-phase clock signals CKE1 and CKE2 that are 180 degrees out of phase.

  For this reason, the clock generation circuit 31b outputs four clock signals, and the phase adjustment circuit 31c adjusts the phases of the two clock signals, and outputs clock signals CKe1 and CKe2.

  The 2-bit comparison result output from the DFE 32 is demultiplexed into n bits by the demultiplexer 31a of the CDR circuit 31 and output as a data signal Eo. The data signal Eo is supplied to the error detection circuit 33a of the eye monitor circuit 33.

  The error detection circuit 33a performs error determination based on the data signal Eo and the output data signal Do, and the error number counter 33c counts the number of errors and outputs it as an error number ERRcnt. Further, the error check number counter 33b outputs 1 as the signal ECfin when the number of error determinations reaches a predetermined value.

  In the receiving circuit 10 shown in FIG. 1, the eye monitor function is realized by using one comparison circuit 13 instead of the DFE 32 including the plurality of comparison circuits as described above, so that power consumption can be suppressed. In the receiving circuit 30, since error determination is performed for each symbol, two clock signals CKE1 and CKE2 are used. On the other hand, in the receiving circuit 10, since the error determination is performed once every two symbols, the eye monitor function can be realized by one clock signal CKe, and the power consumption can be suppressed.

  In the above example, the receiving circuit 10 that performs the half-rate operation has been described. However, the present invention is not limited to this. For example, when the receiving circuit 10 is expanded to a receiving circuit that performs a quarter rate operation, the number of circuits is appropriately increased. For example, the data determination circuit 12a is a circuit that outputs a 4-bit comparison result at a timing synchronized with a four-phase clock signal. In that case, instead of the comparison circuit 13, for example, two comparison circuits that compare the threshold value TH with the data signal Di at a timing synchronized with a two-phase clock signal may be provided. In this case, the 2: 1 selector 15a selects the comparison result of the two comparison circuits supplied to the error detection circuit 15b and the comparison result of the data determination circuit 12a for the same symbol. Is done.

(Second Embodiment)
In the example of FIG. 1, the error detection circuit 15b performs error determination with the output data signal Do being correct, but compares the expected value obtained based on the output data signal Do with the data signal Eo to perform error determination. You may make it perform.

FIG. 8 is a diagram illustrating an example of a receiving circuit according to the second embodiment. 8, the same elements as those shown in FIG. 1 are denoted by the same reference numerals.
In the receiving circuit 40 of the second embodiment, the eye monitor circuit 41 includes an expected value generation circuit 41a.

  The expected value generation circuit 41a outputs an expected value of the comparison result output from the data determination circuit 12a. The expected value is a value of a data pattern such as 0101 that repeats 0 and 1, or a predictable data pattern value such as PRBS (Pseudo-random bit sequence). When such a data pattern value is used as the expected value, the test pattern is supplied to the receiving circuit 40 as the data signal Dr when the eye monitor function is executed. Once the expected value generation circuit 41a receives the above data pattern as a seed (for example, during initial operation), the expected value is estimated according to the data pattern thereafter. Thereby, even if an error occurs in the output data signal Do, it is possible to continue to output a correct value.

In the 2: 1 selector 15a and the error detection circuit 15b, an expected value is used instead of the output data signal Do, and an operation similar to that of the reception circuit 10 of the first embodiment is performed.
Other operations of the receiving circuit 40 are the same as those of the receiving circuit 10 shown in FIG. 1, and the receiving circuit 40 can obtain the same effects as the receiving circuit 10.

(Third embodiment)
FIG. 9 is a diagram illustrating an example of a receiving circuit according to the third embodiment.
FIG. 9 shows an example of a receiving circuit 50 that receives a data signal Dra of PAM4 (Pulse Amplitude Modulation 4) having four values per symbol and performs a half-rate operation.

The reception circuit 50 includes an equalization circuit 51, a CDR circuit 52, a comparison circuit 53, a demultiplexer (denoted as DMX in FIG. 9) 54, and an eye monitor circuit 55.
The equalization circuit 51 receives the data signal Dra of PAM4, performs equalization processing on the data signal Dra, and outputs a data signal Dia. For example, CTLE can be used as the equalization circuit 51. An amplifier may be used in place of the equalization circuit 51. In that case, the amplifier outputs the data signal Dia by amplifying the data signal Dra.

In PAM4, a 2-bit value is associated with each of four potential levels divided by three threshold values.
FIG. 10 is a diagram illustrating an example of assignment of 2-bit values in a PAM4 data signal. The horizontal axis represents time, and the vertical axis represents voltage. A waveform 56 is obtained by superimposing all transitions of the data signal Dia.

  As shown in FIG. 10, a 2-bit value is associated with each of the four potential levels divided by the threshold values V1, V2, and V3. In the example of FIG. 10, among the four potential levels, the lowest potential level is “00”, the next lowest potential level is “01”, the second highest potential level is “10”, “11” is assigned to the highest potential level. The assignment of 2-bit values is not limited to the above. Two-bit values may be assigned using gray codes such as “00”, “01”, “11”, “10”, etc. in order of increasing potential level.

In the following, each 2-bit value is called 0, 1, 2, 3 in decimal notation in order of increasing potential level.
Of the threshold values V1, V2, and V3, the central threshold value V2 is the center of change in the amplitude of the data signal Dia, and is, for example, 0V. When the voltage of the data signal Dia is changed from −1 to +1, the threshold V3 is set to +2/3, the threshold V1 is set to −2/3, and the like. That is, the difference (voltage difference) between the threshold value V1 and the threshold value V2 is equal to the difference between the threshold value V2 and the threshold value V3.

  The CDR circuit 52 includes a data determination circuit 52a for PAM4 and comparison circuits 52b1, 52b2, 52c1, 52c2, 52d1, 52d2, 52e1, and 52e2. Further, the CDR circuit 52 includes a demultiplexer 52f, a phase detection circuit 52g, a filter 52h, phase adjustment circuits 52i1 and 52i2, and a clock generation circuit 52j.

  The data determination circuit 52a includes, for example, a plurality of comparison circuits that compare the data signal Dia and the three threshold values V1 to V3, and the comparison result (data determination result) between each of the threshold values V1 to V3 and the data signal Dia. Output. Since the data determination circuit 52a performs a half rate operation, the data determination circuit 52a performs a comparison process at a timing synchronized with the clock signals CKd1 and CKd2, and outputs a comparison result of 3 × 2 = 6 bits (3 bits per symbol).

The data determination circuit 52a may have the function of the direct feedback type DFE or the speculative type DFE described above.
The comparison circuit 52b1 outputs a comparison result comparing the data signal Dia and the threshold value VHH at a timing synchronized with the clock signal CKd1. The comparison circuit 52b2 outputs a comparison result comparing the data signal Dia and the threshold value VHH at a timing synchronized with the clock signal CKd2.

  The comparison circuit 52c1 outputs a comparison result comparing the data signal Dia and the threshold value VHL at a timing synchronized with the clock signal CKd1. The comparison circuit 52c2 outputs a comparison result comparing the data signal Dia and the threshold value VHL at a timing synchronized with the clock signal CKd2.

  The comparison circuit 52d1 outputs a comparison result comparing the data signal Dia and the threshold value VLH at a timing synchronized with the clock signal CKd1. The comparison circuit 52d2 outputs a comparison result comparing the data signal Dia and the threshold value VLH at a timing synchronized with the clock signal CKd2.

  The comparison circuit 52e1 outputs a comparison result comparing the data signal Dia and the threshold value VLL at a timing synchronized with the clock signal CKd1. The comparison circuit 52e2 outputs a comparison result comparing the data signal Dia and the threshold value VLL at a timing synchronized with the clock signal CKd2.

  When the voltage of the data signal Dia changes from −1 to +1, for example, the threshold VHH is +1, the threshold VHL is +3/9, the threshold VLH is −3/9, the threshold VLL is −1, and the like. .

  The demultiplexer 52f demultiplexes the 6-bit comparison result output from the data determination circuit 52a into 3n bits and outputs the result as an output data signal Doa. Further, the demultiplexer 52f demultiplexes a total of 2 bits of the comparison results output by the comparison circuits 52b1 and 52b2 into 1 bit and outputs the result as a comparison result PHH. Further, the demultiplexer 52f demultiplexes a total of 2 bits of the comparison results output by the comparison circuits 52c1 and 52c2 by 1 bit into n bits and outputs the result as the comparison result PHL. In addition, the demultiplexer 52f demultiplexes a total of 2 bits of the comparison results output by the comparison circuits 52d1 and 52d2 into 1 bit, respectively, and outputs the result as a comparison result PLH. Further, the demultiplexer 52f demultiplexes a total of 2 bits of comparison results output by the comparison circuits 52e1 and 52e2 by 1 bit into n bits and outputs the result as a comparison result PLL. For example, n is set according to the processing capability (determined by the frequency of an operation clock signal not shown) of the phase detection circuit 52g realized by a digital circuit.

  The phase detection circuit 52g receives the 3n-bit output data signal Doa output from the demultiplexer 52f and the comparison results PHH, PHL, PLH, and PLL. Then, the phase detection circuit 52g detects a phase difference between the data signal Dia and the clock signals CKd1 and CKd2 based on the output data signal Doa and the comparison results PHH, PHL, PLH, and PLL. Then, the phase detection circuit 52g outputs a phase difference signal UD as a result of the phase difference detection.

  Similar to the phase detection circuit 12e of the reception circuit 10 of the first embodiment, the phase detection circuit 52g can also be realized by, for example, an MM type phase detection circuit. The MM type phase detection circuit that handles the data signal Dia of the PAM4 outputs a phase difference signal UD based on the comparison results PHH, PHL, PLH, PLL for two consecutive symbols and the value of the output data signal Doa.

  The filter 52h filters the phase difference signal UD to generate an adjustment signal. The filter 52h is not limited to a digital filter, and has a charge pump that adjusts the current value according to the phase difference signal UD, converts the adjusted current value into a voltage value, and outputs the voltage value as an adjustment signal. Such a circuit may be used.

  The phase adjustment circuit 52i1 receives two of the four (or three) clock signals output from the clock generation circuit 52j, and the clock signals CKd1 and CKd2 whose phases are adjusted based on the adjustment signals output from the filter 52h. Is output.

  The phase adjustment circuit 52i2 receives two (or one) clock signals output from the clock generation circuit 52j, and one clock whose phase is adjusted based on the adjustment signal output from the filter 52h and the offset value PSoff. The signal CKe is output. The offset value PSoff is supplied from a control device (not shown), for example.

The clock generation circuit 52j generates and outputs four (or three) clock signals having the same frequency, for example.
The comparison circuit 53 outputs a comparison result in which the data signal Dia is compared with the threshold value TH whose size is adjusted based on the offset value THoff at a timing synchronized with the clock signal CKe. The offset value THoff is supplied from a control device (not shown), for example.

The demultiplexer 54 demultiplexes the 1-bit comparison result output from the comparison circuit 53 into n / 2 bits and outputs the result as a data signal Eoa.
The eye monitor circuit 55 thins out the comparison result by the data determination circuit 52a obtained for each symbol of the data signal Dia, and selects the comparison result in the symbol from which the comparison result by the comparison circuit 53 is obtained. Then, the eye monitor circuit 55 compares the selected comparison result with the comparison result of the comparison circuit 53 to determine the presence or absence of an error based on the offset values PSoff and THoff, and the error count ERRcnt [3: 0] is output. Further, when a predetermined number of error determinations are completed, the eye monitor circuit 55 outputs 1 as a signal ECfin indicating that.

The eye monitor circuit 55 includes a 6: 1 selector 55a, an error detection circuit 55b, a selector 55c, an error check number counter 55d, and an error number counter 55e.
The 6: 1 selector 55a receives the output data signal Doa and the selection signal SEL. Based on the selection signal SEL, the 6: 1 selector 55a outputs one bit of the comparison result of 3 bits per symbol output by the data determination circuit 52a to one of the odd or even symbols of the data signal Dia. Select from signal Doa. As a result, an n / 2-bit data signal is output from the 6: 1 selector 55a. That is, the 6: 1 selector 55a has a function of thinning out the comparison result by the data determination circuit 52a. The frequency with which the data determination circuit 52a outputs the comparison result is symbol by symbol. On the other hand, the frequency at which the comparison circuit 53 outputs the comparison result is once every two symbols. The data determination circuit 52a outputs a comparison result of 3 bits per symbol, whereas the comparison circuit 53 outputs a comparison result of 1 bit per symbol. Therefore, the 6: 1 selector 55a having such a thinning function is used so that the values of corresponding bits can be compared with the same symbol.

  The selection signal SEL is supplied from, for example, a control device (not shown). For example, the control device supplies a different selection signal SEL to the 6: 1 selector 55a according to the magnitude of the offset value THoff (that is, the potential level of the threshold value TH).

In determining which selection signal SEL is output according to the magnitude of the offset value THoff, the control device performs, for example, the following detection in advance.
For example, the control device supplies a data signal Dra whose value is fixed at 0 to the receiving circuit 50. Then, the control device changes the offset value THoff and detects the offset value THoff at which the comparison result of the comparison circuit 53 is inverted. The threshold value TH adjusted with the detected offset value THoff becomes an amplitude level (DC level) of zero. When such detection is performed, the control device is provided with an input terminal to which the output terminal of the comparison circuit 53 is connected.

  Similarly, the control device supplies the data signal Dra whose values are fixed to 1, 2, and 3 to the receiving circuit 50, changes the offset value THoff, and the comparison result of the comparison circuit 53 is inverted. An offset value THoff is detected. The threshold value TH adjusted with each detected offset value THoff becomes the amplitude level (DC level) of 1, 2, and 3.

  Then, the control device supplies, for example, the following selection signal SEL to the 6: 1 selector 55a based on the magnitude of the offset value THoff during the eye monitoring operation using the receiving circuit 50.

  When the offset value THoff is a value that adjusts the threshold value TH between a DC level of 0 and a DC level of 1, the control device, for example, selects a bit indicating a comparison result between the data signal Dia and the threshold value V3. The selection signal SEL is supplied to the 6: 1 selector 55a. When the offset value THoff is a value that adjusts the threshold value TH between a DC level of 1 and a DC level of 2, the control device, for example, selects a bit indicating a comparison result between the data signal Dia and the threshold value V2. The selection signal SEL is supplied to the 6: 1 selector 55a. When the offset value THoff is a value that adjusts the threshold value TH between the DC level of 2 and the DC level of 3, the control device, for example, selects a bit indicating the comparison result between the data signal Dia and the threshold value V1. The selection signal SEL is supplied to the 6: 1 selector 55a.

  The error detection circuit 55b has an n / 2-bit data signal Eoa output from the demultiplexer 54 and an n / 2-bit data having a bit corresponding to each bit of the data signal Eoa by the function of the 6: 1 selector 55a. Receive data signals. Then, the error detection circuit 55b compares the value of each bit of the data signal Eoa with the value of the bit of the data signal output by the 6: 1 selector 55a corresponding to each bit, and determines whether or not they match. Determine.

  That is, the error detection circuit 55b uses the offset values PSoff and THoff to determine whether or not the data signal Eoa does not match the output data signal Doa (whether an error occurs). The error detection circuit 55b outputs a signal indicating that error determination has been performed each time error determination is performed, and outputs a signal indicating that an error has occurred when an error has occurred.

  The error detection circuit 55b receives the start signal ST, and when the start signal ST changes from 0 to 1, the error detection circuit 55b detects the phase synchronization (lock) of the data signal output from the 6: 1 selector 55a and the data signal Eoa. After the lock is detected, error determination is started. The start signal ST is supplied from a control device (not shown), for example.

  The selector 55c receives a signal indicating that an error output from the error detection circuit 55b has occurred. Then, the selector 55c divides the signal indicating that an error has occurred in a certain symbol for each value of the comparison result by the data determination circuit 52a in the symbol before the symbol, and outputs it separately. FIG. 9 shows an example of the selector 55c corresponding to the case where the data determination circuit 52a is DFE and the number of taps of the DFE is 1. In this case, the selector 55c is a 1: 4 selector that outputs a signal indicating that an error has occurred separately, depending on whether the value of the output data signal Doa one symbol before is 0-3.

  The error check number counter 55d receives the signal indicating that the error determination output from the error detection circuit 55b has been performed, and counts the number of error determinations (number of error checks). Further, the error check number counter 55d outputs 1 as the signal ECfin when the count value reaches a predetermined value.

  The error number counter 55e receives a signal indicating that an error output from the selector 55c has occurred, and separately counts the number of error occurrences depending on whether the value of the output data signal Doa one symbol before is 0 to 3. . Then, the error number counter 55e outputs the counted result as the error number ERRcnt [3: 0].

Note that (when considering the effects of ISI by the previous symbol or two symbols) number of taps DFE is n (n ≧ 2) in which case, the selector 55c is 1: 4 becomes ⁿ selector, the error number counter 55e is output There are 4 ⁿ types of errors.

11 and 12 are diagrams illustrating examples of threshold adjustment.
11 and 12 show adjustment examples of offset values PSoff and THoff in two consecutive symbols m and m + 1 of the data signal Dia. The horizontal axis represents time, and the vertical axis represents voltage. A waveform 56 shows all transitions of the data signal Dia. Timings t10, t13, and t15 indicate timings synchronized with the clock signal CKe, timings t11 and t14 indicate timings synchronized with the clock signal CKd1, and timings t12 and t16 indicate timings synchronized with the clock signal CKd2.

  For example, when the offset value THoff is increased by ΔTHoff1 at timing t10, the threshold value TH in the comparison circuit 53 is increased from the threshold value TH3 by the threshold value TH4.

  Further, when the offset value THoff reaches the maximum value at timing t13 (in the example of FIG. 12, the value of the offset value THoff at which the threshold value TH reaches the threshold value VHH), the offset value PSoff is increased by ΔPSoff1. The offset value THoff is set to the minimum value (in the example of FIG. 12, the value of the offset value THoff at which the threshold value TH becomes the threshold value VLL).

  As described above, the selection signal SEL changes based on the potential level of the threshold value TH. For example, when the threshold TH is the potential level of the thresholds TH3 and TH4, the selection signal SEL for selecting a bit indicating the comparison result between the threshold V1 and the data signal Dia is supplied to the 6: 1 selector 55a.

(Example of an eye monitor using the receiving circuit 50)
Similar to the case of using the receiving circuit 10 of the first embodiment, the case of using the receiving circuit 50 of the third embodiment includes the control device 20 and the display device 20a as shown in FIG. An eye monitor is realized by the system. The flow of the eye monitor operation of the receiving circuit 50 controlled by the control device 20 is also the same as the flowchart shown in FIG. 5, for example.

  When the data determination circuit 52a is a direct type DFE or speculative DFE, the control device 20 corrects the eye waveform based on the correction value used in the data determination circuit 52a, and after the equalization processing by the data determination circuit 52a The eye waveform can be reproduced.

When the data determination circuit 52a performs the equalization processing of the data signal Dia of the PAM4 with a 1-tap DFE, four correction values are used depending on whether the value one symbol before is 0 to 3.
FIG. 13 is a diagram illustrating an example of a threshold value used in a data determination circuit that is a 1-tap DFE. In FIG. 13, the horizontal axis represents time, and the vertical axis represents voltage.

  The threshold values V10, V11, V12, and V13 are values obtained by adjusting the threshold value V1 with four correction values. The threshold values V20, V21, V22, and V23 are values obtained by adjusting the threshold value V2 with four correction values. The threshold values V30, V31, V32, and V33 are values obtained by adjusting the threshold value V3 with four correction values.

  When the data determination circuit 52a is a 1-tap speculative DFE, the data determination circuit 52a outputs the following comparison result for the data signal Dia of the symbol m + 1 according to the data determination result for the symbol m. When the data determination result at symbol m is 0, data determination circuit 52a outputs a comparison result between threshold values V10, V20, and V30 and data signal Dia at symbol m + 1. When the data determination result at the symbol m is 1, the data determination circuit 52a outputs a comparison result between the threshold values V11, V21, and V31 and the data signal Dia at the symbol m + 1. When the data determination result at the symbol m is 2, the data determination circuit 52a outputs a comparison result between the threshold values V12, V22, V32 and the data signal Dia at the symbol m + 1. When the data determination result at the symbol m is 3, the data determination circuit 52a outputs a comparison result between the threshold values V13, V23, and V33 and the data signal Dia at the symbol m + 1.

  When the data determination circuit 52a is a direct feedback type 1-tap DFE, any one of four correction values corresponding to the data determination result at the symbol m is added to the data signal Dia at the symbol m + 1. Then, a comparison result between the data signal Dia to which the correction value is added and the threshold values V1 to V3 is output. This is because the comparison result between three threshold values V10 to V33 shown in FIG. 13 adjusted based on any one of four correction values and the data signal Dia in the symbol m + 1 is output. Equivalent to. As the number of DFE taps increases, the correction value increases, and the number of thresholds increases accordingly.

  When obtaining the eye waveform based on the number of errors ERRcnt [3: 0] output from the receiving circuit 50, the control device 20 corrects the eye waveform based on the correction value as described above. Thereby, the eye waveform after the equalization processing by the data determination circuit 52a can be equivalently presented to the user, for example.

  When the offset value THoff is increased linearly, the increase in the threshold value TH may be nonlinear depending on the characteristics of the comparison circuit 53. In such a case, the characteristics of the comparison circuit 53 can be detected by adding the following circuit.

FIG. 14 is a diagram illustrating an example of a circuit that detects the characteristics of the comparison circuit.
In the circuit shown in FIG. 14, the reference voltage Vref generated by the reference voltage generation circuit 57 is supplied to the comparison circuit 53 a having the same characteristics as the comparison circuit 53.

The reference voltage generation circuit 57 outputs a reference voltage Vref having a magnitude based on the setting signal Vrset supplied from the control device 20, for example.
FIG. 15 is a diagram illustrating an example of a reference voltage generation circuit.

  The reference voltage generation circuit 57 includes variable resistors 57a and 57b connected in series between the power supply VDD and the ground GND. A reference voltage Vref is output from a node between the variable resistors 57a and 57b.

  Although not shown, each of the variable resistors 57a and 57b is, for example, an element in which a plurality of resistive elements with switches are connected in parallel, and the number of switches to be turned on can be changed based on the setting signal Vrset. The magnitude of the reference voltage Vref can be changed.

  When detecting the characteristics of the comparison circuit 53a, the control device 20 detects the comparison result (output signal Out) by the comparison circuit 53a when the offset value THoff is changed. When the control device 20 increases the offset value THoff, the point where the output signal Out changes from 0 to 1 is the intersection of the reference voltage Vref and the threshold value TH. The control device 20 linearly changes the reference voltage Vref according to the setting signal Vrset, and changes the offset value THoff as described above each time the reference voltage Vref is changed, and detects the intersection as described above. Thereby, the nonlinearity of the comparison circuit 53a can be obtained. This is because the threshold voltage TH at the intersection changes nonlinearly because the reference voltage Vref changes linearly.

  The control device 20 may correct the eye waveform in consideration of the nonlinearity of the comparison circuit 53a. For example, when the control device 20 increases the offset value THoff linearly, if the threshold value TH increases non-linearly, the number of errors tends to increase and the eye of the eye waveform may become narrower. Therefore, for example, when receiving the error number ERRcnt [3: 0] output from the eye monitor circuit 55, the control device 20 reduces the number according to the degree of nonlinearity of the comparison circuit 53a and corrects the eye waveform. .

  Note that the comparison circuit 53 of the reception circuit 50 may be used as the comparison circuit 53a. In that case, when detecting the characteristics of the comparison circuit 53, a switch for connecting the comparison circuit 53 and the reference voltage generation circuit 57 is provided.

Further, the correction of the eye waveform according to the characteristics of the comparison circuit 53 can be performed in the same manner even when the receiving circuit 10 of the first embodiment is used.
By using the receiving circuit 50 of the third embodiment as described above, the eye monitor function as described above can be realized. Further, instead of providing a circuit similar to the data determination circuit 52a, a single comparison circuit 53 may be provided, so that power consumption can be suppressed. In addition, since the error determination is performed once every two symbols in the receiving circuit 50, an eye monitor function can be realized with one clock signal CKe, and power consumption can be suppressed.

  In the above example, the receiving circuit 50 that performs the half-rate operation has been described. However, the present invention is not limited to this. For example, when realizing a receiving circuit that performs a full rate operation, the data determination circuit 52a is a circuit that outputs 3 bits, and there is one comparison circuit that compares the threshold values VLL to VHH with the data signal Dia. Further, a 3: 1 selector is used instead of the 6: 1 selector 55a.

Further, when the receiving circuit 50 is expanded to a receiving circuit that performs a quarter rate operation, a comparison circuit or the like is appropriately added.
Further, a plurality of comparison circuits may be provided instead of one comparison circuit 53. For example, two comparison circuits that compare two threshold values corresponding to any two of the threshold values V1, V2, and V3 and the data signal Dia may be provided. For example, in that case, the two thresholds are adjusted simultaneously by the offset value THoff. The 6: 1 selector 55a may be a 3: 1 selector.

(Fourth embodiment)
FIG. 16 is a diagram illustrating an example of a receiving circuit according to the fourth embodiment. In FIG. 16, the same elements as those of the receiving circuit 50 shown in FIG.

  In the reception circuit 60 according to the fourth embodiment, the data determination circuit 61a of the CDR circuit 61 includes a decoder 61a1. The decoder 61a1 decodes the four values of PAM4 based on the comparison result obtained by comparing the three threshold values with the data signal Dia. For example, when the data signal Dia is larger than the threshold value V1 and smaller than the threshold value V2, the decoder 61a1 outputs “01” as a decoding result. Since the receiving circuit 60 performs a half-rate operation, the data determination circuit 61a outputs a decoding result for two symbols, that is, a 4-bit value.

  The demultiplexer 61b of the CDR circuit 61 outputs n-bit comparison results PHH, PHL, PLH, and PLL, and demultiplexes the 4-bit comparison results output from the data determination circuit 61a into 2n bits to output the data signal Dob. Output as.

  The expected value generation circuit 62a of the eye monitor circuit 62 outputs a 2n-bit expected value based on the output data signal Dob. The expected value is a data pattern value such as 0101 that repeats 0 and 1, or a predictable data pattern value such as PRBS, for example. When such a data pattern value is used as the expected value, the test pattern is supplied to the receiving circuit 60 as the data signal Dra when the eye monitor function is executed. Once the expected value generation circuit 62a receives the above data pattern as a seed (for example, at the time of initial operation), the expected value is estimated and then correct even if an error occurs in the output data signal Dob. You can continue to output values.

  The 4: 1 selector 62b receives the 2n-bit expected value and the selection signal SEL. Based on the selection signal SEL, the 4: 1 selector 62b converts one bit out of the two-bit decoding result output by the data determination circuit 61a for one of the odd or even symbols of the data signal Dia into the expected value. Select from. As a result, an n / 2-bit data signal is output from the 4: 1 selector 62b.

  As shown in FIG. 10, when a 2-bit value is associated with each of the four potential levels, the selection signal SEL changes as follows according to the magnitude of the threshold value TH, for example. When the threshold value TH is a magnitude between a DC level of 0 and a DC level of 1, the selection signal SEL is a signal that causes the 4: 1 selector 62b to select the least significant bit of the decoding result of 2 bits per symbol. It becomes. Further, when the threshold value TH is between the DC level of 1 and the DC level of 2, the selection signal SEL selects the most significant bit from the decoding result of 2 bits per symbol by the 4: 1 selector 62b. Signal. When the threshold value TH is a magnitude between the DC level of 2 and the DC level of 3, the selection signal SEL is a signal that causes the 4: 1 selector 62b to select the least significant bit of the decoding result of 2 bits per symbol. It becomes.

  Other operations of the receiving circuit 60 are the same as those of the receiving circuit 50 shown in FIG. 9, and the receiving circuit 60 can obtain the same effects as the receiving circuit 50. Further, in the receiving circuit 60, since the number of bits of the output signal (decoded result) of the data determination circuit 61a is reduced, the circuit configuration of the demultiplexer 61b and the phase detection circuit 52g can be simplified.

Note that the selector 55c may output a signal indicating the occurrence of an error separately for each expected value one symbol before generated by the expected value generating circuit 62a.
Further, the expected value generation circuit 62a may not be provided, and the output data signal Dob (decode result) may be supplied to the 4: 1 selector 62b.

(Fifth embodiment)
FIG. 17 is a diagram illustrating an example of a receiving circuit according to the fifth embodiment. In FIG. 17, the same elements as those of the receiving circuit 60 shown in FIG.

  The CDR circuit 71 of the receiving circuit 70 of the fifth embodiment includes a VCO (Voltage Controlled Oscillator) instead of the clock generation circuit 52j and the phase adjustment circuit 52i1 of the CDR circuit 61 of the receiving circuit 60 of the fourth embodiment. ) 71a is provided. Further, the CDR circuit 71 includes a frequency dividing circuit 71b and a phase adjusting circuit 71c.

  The VCO 71a outputs clock signals CKd1 and CKd2 whose phases are adjusted based on the adjustment signal output from the filter 52h. That is, the VCO 71a has the functions of the clock generation circuit 52j and the phase adjustment circuit 52i1 of the CDR circuit 61 of the reception circuit 60 of the fourth embodiment.

The frequency dividing circuit 71b divides the clock signals CKd1 and CKd2 by half and outputs a four-phase clock signal.
The phase adjustment circuit 71c adjusts the phase of one of the four-phase clock signals based on the offset value PSoff, and supplies it to the comparison circuit 53 as the clock signal CKe1.

The demultiplexer 72 demultiplexes the 1-bit comparison result output from the comparison circuit 53 into n / 4 bits and outputs the result as a data signal Eob.
In the eye monitor circuit 73, the 8: 1 selector 73a receives the 2n-bit expected value and the selection signal SEL. Based on the selection signal SEL, the 8: 1 selector 73a selects one bit out of the decoding result of 2 bits per symbol output by the data determination circuit 61a for any one of the four consecutive symbols of the data signal Dia. Is selected from the expected values. As a result, an n / 4-bit data signal is output from the 8: 1 selector 73a.

  The error detection circuit 73b has an n / 4-bit data signal Eob output from the demultiplexer 72 and an n / 4-bit data having a bit corresponding to each bit of the data signal Eob by the function of the 8: 1 selector 73a. Receive data signals. Then, the error detection circuit 73b determines whether or not the value of each bit of the data signal Eob matches the value of the bit of the data signal output from the 8: 1 selector 73a corresponding to each bit. .

  That is, the error detection circuit 73b uses the offset values PSoff and THoff to determine whether or not the data signal Eob does not match the output data signal Dob (whether an error occurs). The error detection circuit 73b outputs a signal indicating that error determination has been performed every time error determination is performed, and outputs a signal indicating that an error has occurred when an error has occurred.

  The error detection circuit 73b receives the start signal ST, and when the start signal ST changes from 0 to 1, the error detection circuit 73b detects the phase synchronization (lock) between the data signal output from the 8: 1 selector 73a and the data signal Eob. After the lock is detected, error determination is started.

  Other operations of the receiving circuit 70 are the same as those of the receiving circuit 50 shown in FIG. In the receiving circuit 70, since the comparison circuit 53 performs data determination once per four symbols, the frequency of data determination is reduced compared to the reception circuit 50, and power consumption can be further reduced.

  In the above description, the frequency dividing circuit 71b divides the clock signals CKd1 and CKd2 to half the frequency. However, the frequency dividing circuit 71b is not limited to this and may divide the frequency to ¼ frequency. In that case, the 8: 1 selector 73a may be a 16: 1 selector.

  The receiving circuits 50, 60, and 70 of the third to fifth embodiments have been described as receiving the data signal Dra of PAM4. However, these receiving circuits 50, 60, and 70 are replaced with PAM8 and the like. The present invention can be extended to a receiving circuit that receives a multi-value data signal. In that case, since the threshold value for comparison with the data signal increases, the number of circuits such as comparison circuits increases accordingly. Further, the ratio of the input to the output of the selector (for example, 6: 1 selector 55a in FIG. 9) is changed. In the receiving circuit that receives the data signal Dra of PAM8, for example, a 14: 1 selector is used instead of the 6: 1 selector 55a, and a 1: 8 selector is used instead of the selector 55c.

As described above, one aspect of the receiving circuit and the eye monitor system of the present invention has been described based on the embodiments. However, these are merely examples, and the present invention is not limited to the above description.
The following additional notes are further disclosed with respect to the plurality of embodiments described above.

(Supplementary note 1) A first comparison result obtained by comparing the data signal with a first threshold at a first timing that receives the data signal and is synchronized with the first clock signal, and the data signal at the first timing And detecting a phase difference between the data signal and the first clock signal based on a second comparison result obtained by comparing the first clock signal with a plurality of second threshold values, and determining the phase of the first clock signal based on the phase difference. A CDR circuit for adjusting
The data signal and a third threshold whose size is adjusted based on a first offset value are synchronized with a second clock signal whose phase is adjusted based on the phase difference and the second offset value. A comparison circuit that outputs a third comparison result compared at the second timing,
The first comparison result obtained for each symbol of the data signal or the first value obtained based on the first comparison result is thinned out to obtain the third comparison result. Selecting the fourth comparison result or the second value in the symbol, and comparing the third comparison result with the fourth comparison result or the second value, so that the first offset value or the An eye monitor circuit for determining the presence or absence of an error due to the second offset value and outputting the number of occurrences of the error;
A receiving circuit.

(Appendix 2) The eye monitor circuit
An error detection circuit for determining the presence or absence of the error by comparing the first comparison result with the fourth comparison result or the second value;
The fourth comparison result or the second value supplied to the error detection circuit by thinning out the first comparison result or the first value obtained for each symbol of the data signal is selected. A selector,
The receiving circuit according to claim 1, further comprising:

  (Supplementary Note 3) The selector may select the first comparison result based on a difference between a frequency at which the first comparison result is obtained in the CDR circuit and a frequency at which the comparison circuit outputs the third comparison result. The receiving circuit according to appendix 2, wherein the first value is thinned out, and the fourth comparison result or the second value supplied to the error detection circuit is selected.

(Supplementary Note 4) When the data signal is a multilevel signal having n (n ≧ 4) values per symbol, the first threshold value includes a plurality of fourth threshold values corresponding to n,
The selector selects the fourth comparison result or the second value obtained by comparing any one of the plurality of fourth thresholds with the data signal based on the potential level of the third threshold. The receiving circuit according to appendix 2 or 3, which is supplied to the error detection circuit.

  (Supplementary Note 5) The eye monitor circuit determines the occurrence of the error in the first symbol for each value of the first comparison result in the second symbol before the first symbol, or in the first symbol. The counter further includes a counter that counts each value of 1 and outputs the number of occurrences of the error for each value of the first comparison result in the second symbol or for each first value. The receiving circuit according to any one of 1 to 4.

  (Appendix 6) The appendix 6 further includes an expected value generation circuit that receives the first comparison result in a predictable data pattern and outputs the first value in accordance with the data pattern. Receiver circuit.

(Supplementary note 7) The reception circuit according to Supplementary note 4, wherein the CDR circuit decodes the first value which is each value of the n value based on the first comparison result and supplies the first value to the eye monitor circuit. .
(Supplementary Note 8) A first comparison result obtained by comparing the data signal with a first threshold at a first timing that receives the data signal and is synchronized with the first clock signal, and the data signal at the first timing And detecting a phase difference between the data signal and the first clock signal based on a second comparison result obtained by comparing the first clock signal with a plurality of second threshold values, and determining the phase of the first clock signal based on the phase difference. The phase of the CDR circuit is adjusted based on the phase difference and the second offset value, and the CDR circuit for performing the adjustment of the data, the data signal, and the third threshold value whose magnitude is adjusted based on the first offset value. A comparison circuit for outputting a third comparison result compared at a second timing synchronized with the second clock signal, and the first comparison result obtained for each symbol of the data signal or the first Comparison results The first value obtained based on the result is thinned out to select the fourth comparison result or the second value in the first symbol from which the third comparison result is obtained, and the third comparison result and the An eye monitor circuit that determines whether there is an error due to the first offset value or the second offset value by comparing a fourth comparison result or the second value, and outputs the number of occurrences of the error And a receiving circuit comprising:
The number of error occurrences obtained each time the first offset value and the second offset value are adjusted, the number of occurrences of the error is received, and the first offset value or the second offset value is adjusted. And a control device for displaying the eye waveform of the data signal on a display device,
An eye monitor system.

(Supplementary Note 9) The eye monitor circuit determines the occurrence of the error in the first symbol for each value of the first comparison result in the second symbol before the first symbol, or in the first symbol. The number of occurrences of the error for each value of the first comparison result or the first value in the second symbol is output separately for each value of
The control device is configured to calculate the number of occurrences of the error for each value of the first comparison result in the second symbol or the first value, and the first comparison result for the second symbol. The eye monitor system according to appendix 8, wherein the eye waveform is corrected on the basis of each value or a correction value for each first value.

DESCRIPTION OF SYMBOLS 10 Receiving circuit 11 Equalization circuit 12 CDR circuit 12a Data determination circuit 12b1, 12b2, 12c1, 12c2, 13 Comparison circuit 12d, 14 Demultiplexer 12e Phase detection circuit 12f Filter 12g1, 12g2 Phase adjustment circuit 12h Clock generation circuit 15 Eye monitor circuit 15a 2: 1 selector 15b error detection circuit 15c selector 15d error check number counter 15e error number counter 16 waveform CKd1, CKd2, CKE clock signal Dr, Di, Eo data signal Do output data signal ECfin signal ERRcnt [1: 0] error signal m, m + 1 symbol PH, PL comparison result PSoff, THoff offset value SEL selection signal ST start signal UD phase difference signal VH, VL, TH, TH1, TH2 Value

Claims (8)

A first comparison result obtained by comparing the data signal with a first threshold at a first timing in synchronization with the first clock signal, and the data signal and a plurality of second signals at the first timing. A phase difference between the data signal and the first clock signal is detected based on a second comparison result obtained by comparing a threshold value of 2, and the phase of the first clock signal is adjusted based on the phase difference. A CDR circuit;
The data signal and a third threshold whose size is adjusted based on a first offset value are synchronized with a second clock signal whose phase is adjusted based on the phase difference and the second offset value. A comparison circuit that outputs a third comparison result compared at the second timing,
The first comparison result obtained for each symbol of the data signal or the first value obtained based on the first comparison result is thinned out to obtain the third comparison result. Selecting the fourth comparison result or the second value in the symbol, and comparing the third comparison result with the fourth comparison result or the second value, so that the first offset value or the An eye monitor circuit for determining the presence or absence of an error due to the second offset value and outputting the number of occurrences of the error;
A receiving circuit. The eye monitor circuit is
An error detection circuit for determining the presence or absence of the error by comparing the first comparison result with the fourth comparison result or the second value;
The fourth comparison result or the second value supplied to the error detection circuit by thinning out the first comparison result or the first value obtained for each symbol of the data signal is selected. A selector,
The receiving circuit according to claim 1.   The selector selects the first comparison result or the first comparison based on a difference between a frequency at which the first comparison result is obtained in the CDR circuit and a frequency at which the comparison circuit outputs the third comparison result. The receiving circuit according to claim 2, wherein a value is thinned out and the fourth comparison result or the second value supplied to the error detection circuit is selected. When the data signal is a multi-level signal having n (n ≧ 4) values per symbol, the first threshold value includes a plurality of fourth threshold values corresponding to n,
The selector selects the fourth comparison result or the second value obtained by comparing any one of the plurality of fourth thresholds with the data signal based on the potential level of the third threshold. The receiving circuit according to claim 2, wherein the receiving circuit is supplied to the error detection circuit.   The eye monitor circuit detects occurrence of the error in the first symbol for each value of the first comparison result or for each first value in a second symbol before the first symbol. 5. The counter further includes a counter that outputs the number of occurrences of the error for each value of the first comparison result in the second symbol or for each of the first values. The receiving circuit according to any one of the above.   The receiving circuit according to claim 1, further comprising an expected value generation circuit that receives the first comparison result with a predictable data pattern and outputs the first value according to the data pattern. .   The receiving circuit according to claim 4, wherein the CDR circuit decodes the first value, which is each value of the n value, based on the first comparison result, and supplies the first value to the eye monitor circuit. A first comparison result obtained by comparing the data signal with a first threshold at a first timing in synchronization with the first clock signal, and the data signal and a plurality of second signals at the first timing. A phase difference between the data signal and the first clock signal is detected based on a second comparison result obtained by comparing a threshold value of 2, and the phase of the first clock signal is adjusted based on the phase difference. A CDR circuit, the data signal, and a third threshold whose magnitude is adjusted based on the first offset value, and a second whose phase is adjusted based on the phase difference and the second offset value. A comparison circuit for outputting a third comparison result compared at a second timing synchronized with the clock signal, and the first comparison result or the first comparison result respectively obtained for each symbol of the data signal; Based on The first value obtained is thinned out, and the fourth comparison result or the second value in the first symbol from which the third comparison result is obtained is selected, and the third comparison result and the fourth comparison are selected. An eye monitor circuit that determines the presence or absence of an error due to the first offset value or the second offset value by comparing the result or the second value, and outputs the number of occurrences of the error; A receiving circuit;
The number of error occurrences obtained each time the first offset value and the second offset value are adjusted, the number of occurrences of the error is received, and the first offset value or the second offset value is adjusted. And a control device for displaying the eye waveform of the data signal on a display device,
An eye monitor system.

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