JP2018152373A - Semiconductor laser - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor laser capable of using optical transition of unipolar carriers.SOLUTION: A semiconductor laser comprises: a mesa structure comprising a light-emitting region including a plurality of quantum well structures arranged in a first axis direction crossing a principal surface of a substrate and having an upper surface and a side surface and extending in a waveguide axis direction on the principal surface of the substrate; an upper semiconductor region being provided on the upper surface of the light-emitting region and having first conductivity, and a metal electrode being provided on the side surface of the light-emitting region and extending in the first axis direction. The metal electrode and the light-emitting region are arranged in the waveguide axis direction on the principal surface of the substrate. The metal electrode is electrically connected to the side surface of the light-emitting region.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor laser.

  Patent Document 1 discloses a quantum cascade laser.

JP-A-8-279647

  The light emission of the quantum cascade laser uses optical cascading (cascading optical transition of unipolar carriers) using light emitting layers arranged in multiple stages. In order to enable cascading optical transitions, the energy levels of the cascading light emitting layers are matched between adjacent light emitting layers using the application of an external voltage. The use of such cascaded optical transitions increases the optical gain to enable laser oscillation in the subband transition wavelength region, while requiring a large externally applied voltage. The cascade connection of the light emitting layers in the quantum cascade laser is an obstacle to lowering the operating voltage.

  One aspect of the present invention aims to provide a semiconductor laser that makes it possible to use optical transitions of unipolar carriers.

  A semiconductor laser according to one aspect of the present invention includes a light emitting region including a plurality of quantum well structures arranged in a direction of a first axis intersecting a main surface of a substrate and having an upper surface and a side surface, A mesa structure extending in the direction of the waveguide axis on the surface; an upper semiconductor region having first conductivity provided on the upper surface of the light emitting region; and the first semiconductor layer provided on the side surface of the light emitting region. A metal electrode extending in a direction of an axis, wherein the metal electrode and the light emitting region are arranged in a direction of the waveguide axis on the main surface of the substrate, and the metal electrode is formed in the light emitting region. It is electrically connected to the side surface.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to one aspect of the present invention, it is possible to provide a semiconductor laser that makes it possible to use optical transitions of unipolar carriers.

FIG. 1 is a drawing schematically showing a semiconductor laser according to the present embodiment. FIG. 2 is a drawing schematically showing the semiconductor laser according to the present embodiment. FIG. 3 is a view showing a structure of a light emitting region for the semiconductor laser according to the present embodiment. FIG. 4 is a drawing schematically showing an energy level and a layer structure in the quantum well structure according to the first embodiment. FIG. 5 is a drawing schematically showing an energy level and a layer structure in the quantum well structure according to the second embodiment. FIG. 6 is a drawing schematically showing the supply of carriers from the emitter region to the light emitting region of the semiconductor laser according to the present embodiment. FIG. 7 is a drawing schematically showing the supply of carriers from the emitter region to the light emitting region of the semiconductor laser according to the present embodiment. FIG. 8 is a drawing schematically showing main steps in the method of manufacturing the semiconductor laser according to the present embodiment. FIG. 9 is a drawing schematically showing main steps in the method of manufacturing the semiconductor laser according to the present embodiment. FIG. 10 is a drawing schematically showing main steps in the method of manufacturing the semiconductor laser according to the present embodiment. FIG. 11 is a drawing schematically showing main steps in the method of manufacturing the semiconductor laser according to the present embodiment. FIG. 12 is a drawing schematically showing main steps in the method of manufacturing the semiconductor laser according to the present embodiment. FIG. 13 is a drawing schematically showing main steps in the method of manufacturing the semiconductor laser according to the present embodiment.

  A specific example will be described.

  A semiconductor laser according to a specific example includes: (a) a light emitting region including a plurality of quantum well structures arranged in a direction of a first axis intersecting a main surface of a substrate and having an upper surface and a side surface; A mesa structure extending in the direction of the waveguide axis on the surface; (b) an upper semiconductor region having first conductivity provided on the upper surface of the light emitting region; and (c) on the side surface of the light emitting region. A metal electrode extending in the direction of the first axis, wherein the metal electrode and the light emitting region are arranged in the direction of the waveguide axis on the main surface of the substrate, and the metal electrode Is electrically connected to the side surface of the light emitting region.

  According to the semiconductor laser, the upper semiconductor region has the first conductivity, and the light emitting region is not emitted by recombination of electrons and holes, but is a subband of a unipolar carrier that is one of electrons and holes. Light is generated using transitions. The upper semiconductor region provides carriers to the light emitting region through the upper surface of the light emitting region. According to the inventor's knowledge, the use of the upper surface of the light emitting region allows carriers from the upper semiconductor region to spread over a stack of a plurality of quantum well structures arranged in the direction of the first axis. Carriers in individual quantum well structures can generate light during movement in the quantum well structure by optical transitions. The transitioned carrier flows into the metal electrode through the side surface of the light emitting region.

  In the semiconductor laser according to the specific example, the quantum well structure includes a first well layer, a second well layer, a first barrier layer, and a second barrier layer, and the first barrier layer includes the first well layer. The first well layer separates from the second well layer, and the first well layer separates the first barrier layer from the second barrier layer.

  According to this semiconductor laser, this quantum well structure facilitates providing a higher energy level and a lower energy level to carriers of a single polarity. In addition, when this quantum well structure can further provide an energy level for relaxation, the energy level for relaxation is higher for unipolar carriers that have transitioned from an upper energy level to a lower energy level. It promotes relaxation in a time shorter than the energy level relaxation time.

  In the semiconductor laser according to the specific example, the light emitting region includes a plurality of unit cells arranged in the direction of the first axis, and the unit cells include the first well layer, the second well layer, and the first well layer. The first barrier layer includes a barrier layer and the second barrier layer, and the thickness of the first barrier layer is smaller than the thickness of the second barrier layer.

  According to this semiconductor laser, since the thickness of the first barrier layer is smaller than the thickness of the second barrier layer, the first well layer and the second well layer in the unit cell are separated by the second barrier layer in the unit cell. It is more tightly coupled than other well layers that are separated.

  In the semiconductor laser according to the specific example, the quantum well structure includes a barrier layer extending along a plane intersecting the direction of the first axis, and a dopant is added to a part or all of the barrier layer. Yes.

  According to this semiconductor laser, the doped barrier layer is useful for implantation into the well layer.

  The semiconductor laser according to a specific example further includes an emitter electrode that is in contact with the upper semiconductor region, and a high resistivity layer provided on the upper surface of the light emitting region and having an opening, and the upper semiconductor region includes the The light emitting region is contacted through the opening of the high resistivity layer, the upper semiconductor region has an opening reaching the high resistivity layer, and the metal electrode is on a side surface of the upper semiconductor region. Provided.

  According to this semiconductor laser, the metal electrode can extend from the side surface of the light emitting region to the side surface of the upper semiconductor region beyond the boundary between the side surface of the light emitting region and the side surface of the upper semiconductor region, and can accept carriers from the light emitting region. it can. The opening in the upper semiconductor region allows the metal electrode to be isolated from the emitter electrode.

  The semiconductor laser according to the specific example further includes a back electrode provided on the back surface of the substrate, the substrate has conductivity, and the metal electrode is electrically connected to the substrate.

  According to this semiconductor laser, the metal electrode is connected to the back electrode through the conductive substrate.

  The semiconductor laser according to a specific example further includes an insulating film covering a side surface of the mesa structure, the insulating film has an opening provided on the side surface of the mesa structure, and the metal electrode It connects to the said side surface of the said light emission area | region through opening.

  According to this semiconductor laser, the insulating film covering the side surface of the mesa structure guides the carrier provided to the light emitting region through the upper surface of the light emitting region in the direction of the waveguide axis and guides the light guided through the mesa structure. To do.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, embodiments of the semiconductor laser according to the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

  FIG. 1 is a drawing schematically showing a semiconductor laser 11a (11) according to the present embodiment. 1 (a) is a plan view showing the semiconductor laser 11a (11), and FIG. 1 (b) is taken along the line Ib-Ib shown in FIG. 1 (a). It is drawing which shows the obtained cross section. (C) part of FIG. 1 is drawing which shows the cross section taken along the Ic-Ic line | wire shown by the (a) part of FIG. FIG. 2 is a drawing schematically showing the semiconductor laser 11b (11) according to the present embodiment. 2 (a) is a plan view showing the semiconductor laser 11b (11), and FIG. 2 (b) is taken along the line IIb-IIb shown in FIG. 2 (a). It is drawing which shows the obtained cross section. Part (c) of FIG. 2 is a drawing showing a cross section taken along line IIc-IIc shown in part (a) of FIG. A coordinate system S is shown in FIGS. 1 and 2 for easy understanding. FIG. 3 is a view showing a structure of a light emitting region for the semiconductor laser according to the present embodiment. The semiconductor laser can have, for example, a Fabry-Perot type or a distributed feedback type.

  Referring to FIGS. 1 and 2, the semiconductor laser 11 (11 a, 11 b) according to the present embodiment includes a substrate 13, a light emitting region 15, an emitter region 17, and a metal electrode 19. The substrate 13 has a main surface 13a. The light emitting region 15 is provided on the main surface 13 a of the substrate 13. As shown in FIGS. 1 and 2, the light emitting region 15 includes a plurality of quantum well structures 21, and each of the quantum well structures 21 is provided on the main surface 13 a of the substrate 13. Specifically, the quantum well structure 21 includes a unit cell 15a for the quantum well structure 21, as shown in FIG. The plurality of unit cells 15a in the light emitting region 15 are arranged in the direction of the first axis Ax1 (in this embodiment, the Y axis of the coordinate system S) intersecting the main surface 13a. Specifically, the quantum well structure 21 has a plurality of semiconductor layers (21a, 21b, 21c, 21d) such as a well layer and a barrier layer. These semiconductor layers (21a to 21d) are arranged in the direction of the first axis Ax1 intersecting the main surface 13a.

  The main surface 13a includes a first area 13b, a second area 13c, and one or more third areas 13d. The first area 13b and the third area 13d are arranged in the direction of the second axis Ax2 (X axis of the coordinate system S) intersecting the first axis Ax1. The second area 13c extends in the direction of the second axis Ax2 adjacent to the first area 13b and the third area 13d. The first area 13b and the third area 13d extend from one side of the second area 13c in the direction of the third axis Ax3 (Z axis of the coordinate system S) intersecting the first axis Ax1 and the second axis Ax2. In the present embodiment, the first area 13b of the main surface 13a is provided between two third areas 13d, and these third areas 13d extend along the first area 13b.

  The light emitting region 15 includes a first side surface 15b, a second side surface 15c, an upper surface 15d, a lower surface 15e, a third side surface 15f, and a fourth side surface 15g. Specifically, the light emitting region 15 extends in the direction of the third axis Ax3 from one of the emission surface and the reflection surface to the other on the main surface 13a. In this embodiment, the first side surface 15b of the light emitting region 15 extends in the direction of the first axis Ax1 from the boundary between the first area 13b and the second area 13c. The third side surface 15f and the fourth side surface 15g of the light emitting region 15 extend in the direction of the first axis Ax1 from the boundary between the first area 13b and the third area 13d.

  The emitter region 17 includes an upper semiconductor region 23, and the upper semiconductor region 23 is provided on the upper surface 15 d of the light emitting region 15. In the present embodiment, the upper semiconductor region 23 of the emitter region 17 has the first conductivity. The light emitting region 15 and the emitter region 17 are arranged on the main surface 13 a of the substrate 13 in the direction of the first axis Ax1. Specifically, the light emitting region 15 is provided between the emitter region 17 and the substrate 13.

  The metal electrode 19 extends in the direction of the first axis Ax1 on the first side surface 15b of the light emitting region 15. The metal electrode 19 and the light emitting region 15 are arranged on the main surface 13a of the substrate 13 in the direction of the waveguide axis (third axis Ax3). The metal electrode 19 is provided on the first side surface 15 b of the light emitting region 15 and is electrically connected to the first side surface 15 b of the light emitting region 15. In the present embodiment, the metal electrode 19 extends from the first side surface 15b of the light emitting region 15 over the semiconductor region on the second area 13c and can contact the semiconductor region on the second area 13c. The semiconductor region on the second area 13c can have conductivity. By providing the emitter region 17 on the upper surface 15d of the light emitting region 15 on the first area 13b, the metal electrode 19 on the second area 13c can be separated from the emitter region 17.

  The emitter region 17 is disposed on the upper surface 15 d of the light emitting region 15 on the main surface 13 a of the substrate 13. The emitter region 17 can comprise one or more semiconductors. The metal electrode 19 is disposed on the first side surface 15b of the light emitting region 15 on the second area 13c. The conductivity type of the carrier provided to the metal electrode 19 by the light emitting region 15 is the same as the conductivity type of the carrier provided to the light emitting region 15 by the semiconductor of the emitter region 17, and the semiconductor laser 11 (11a, 11b) Use a unipolar carrier.

  According to the semiconductor laser 11 (11a, 11b), the upper semiconductor region 23 has the first conductivity, and the light emitting region 15 is not emitted by recombination of electrons and holes, but one of electrons and holes. The light is generated using the subband transition of the unipolar carrier. The upper semiconductor region 23 provides carriers to the light emitting region 15 through the upper surface 15 d of the light emitting region 15. According to the inventor's knowledge, according to the use of the upper surface 15d of the light emitting region 15, carriers from the upper semiconductor region 23 spread over a stack of a plurality of quantum well structures 21 arranged in the direction of the first axis Ax1. Enable. Carriers in individual quantum well structures 21 can generate light by optical transitions during movement in quantum well structures 21. The transitioned carrier flows into the metal electrode 19 extending in the direction of the first axis Ax1 via the first side surface 15b of the light emitting region 15.

  The light emitting region 15 and the emitter region 17 extend in the direction of the third axis Ax3 on the main surface 13a of the substrate 13, and the metal electrode 19 has the second axis Ax2 along the light emitting region 15 on the second area 13c. It extends in the direction and covers the first side surface 15 b of the light emitting region 15. The average refractive index of the semiconductor in the emitter region 17 is smaller than the average refractive index of the light emitting region 15, and the arrangement of the light emitting region 15 and the emitter region 17 forms a waveguide structure. Specifically, the emitter region 17 is in contact with the upper surface 15 d of the light emitting region 15, and provides a first conductivity type carrier (either one of electrons or holes) to the light emitting region 15. The metal electrode 19 is in contact with the first side surface 15 b of the light emitting region 15 and receives the first conductivity type carrier (the carrier) from the light emitting region 15. The light emitting region 15 and the metal electrode 19 extend in the direction of the waveguide axis, and the metal electrode 19 can reflect light propagating through the waveguide related to the light emitting region 15. The light propagating through the waveguide is emitted from the second side surface 15 c of the light emitting region 15.

  The semiconductor laser 11 (11a, 11b) includes a first electrode 31a provided on the emitter region 17, and a back electrode 31c can be provided on the back surface 13e of the substrate 13 if necessary. The first electrode 31a and the back electrode 31c can be electrically connected to the emitter region 17 and the metal electrode 19, respectively. Specifically, the first electrode 31a and the back electrode 31c can be connected to the emitter region 17 respectively. The first conductive type semiconductor and the back surface 13e of the first conductive type semiconductor substrate 13 are in ohmic contact. In the present embodiment, the emitter region 17 is included in the mesa structure MS and extends on the light emitting region 15 in the mesa structure MS in the direction of the waveguide axis. The emitter region 17 carries the contact layer 28 a and makes contact with the light emitting region 15. The emitter region 17 on the light emitting region 15 can separate the first electrode 31a on the mesa structure MS from the upper surface 15d of the light emitting region 15 that propagates a laser beam having a relatively long wavelength.

  In order to insulate and isolate the first electrode 31 a from the metal electrode 19, the semiconductor laser 11 (11 a, 11 b) can include a separation structure 25, and the separation structure 25 is provided on the light emitting region 15. The separation structure 25 can limit the current path from the first electrode 31 a to the metal electrode 19 to the light emitting region 15. The isolation structure 25 further includes a current aperture 25a provided on the first area 13b. The current aperture 25a of the separation structure 25 makes it possible to supply carriers from the emitter region 17 to the upper surface 15d of the light emitting region 15 away from the first side surface 15b of the light emitting region 15.

  In this semiconductor laser 11, the light emitting region 15 and the emitter region 17 on the first area 13b are arranged in the direction of the first axis Ax1, and the light emitting region 15 on the first area 13b and the metal on the second area 13c. The electrodes 19 are arranged in the direction of the second axis Ax2 that intersects the first axis Ax1. Further, the current aperture 25 a (26 a) of the separation structure 25 extends in the direction of the third axis Ax 3 on the upper surface 15 d of the light emitting region 15. Unipolar carriers are supplied from the emitter region 17 over the quantum well structure 21 of the light emitting region 15, and these unipolar carriers are transmitted from the upper energy level to the lower energy level of the subband in the quantum well structure 21 of the light emitting region 15. It contributes to light emission by optical transition to. Due to optical transition in the light emitting region 15, unipolar carriers at lower energy levels flow into the metal electrode 19. The semiconductor laser 11 utilizes optical transitions of unipolar carriers when emitting light, and the arrangement of the emitter region 17, the light emitting region 15, and the metal electrode 19 emits cascading of unipolar carriers (cascading optical transition). Not needed. The semiconductor laser 11 can reduce the operating voltage compared to the quantum cascade laser using the optical transition of unipolar carriers.

  The semiconductor laser 11 (11a, 11b) can include a lower optical cladding layer 29 provided on the main surface 13a of the substrate 13. The lower optical cladding layer 29 is provided on the first area 13b, the second area 13c, and the third area 13d, and in the first area 13b, the mesa structure MS includes the semiconductor stack for the emitter region 17 and the light emitting region 15. Is installed. The lower optical cladding layer 29 is located between the lower surface 15e of the light emitting region 15 and the substrate 13, and can have good conductivity. In the present embodiment, the metal electrode 19 makes contact with the lower optical cladding layer 29 in the second area 13c. The lower optical cladding layer 29 receives carriers from the light emitting region 15 through the metal electrode 19. Although the lower optical cladding layer 29 is in contact with the lower surface 15 e of the light emitting region 15, the carriers from the light emitting region 15 flow along a path reaching the lower optical cladding layer 29 through the metal electrode 19. In this embodiment, the lower optical cladding layer 29 can have the same conductivity type as that of the upper semiconductor region 23. The carriers from the light emitting region 15 reach the back electrode 31 c through the metal electrode 19, the lower optical cladding layer 29, and the conductive substrate 13.

  The refractive index (or average refractive index) of the emitter region 17 and the refractive index of the lower optical cladding layer 29 are smaller than the average refractive index of the light emitting region 15. The arrangement of the light emitting region 15, the emitter region 17, and the lower optical cladding layer 29 forms a waveguide structure. The light generated in the light emitting region 15 is optically confined by the emitter region 17 and the lower optical cladding layer 29 in the vertical direction and optically confined in the light emitting region 15 in the horizontal direction.

  The emitter region 17 is connected to the upper surface 15d of the light emitting region 15 through the opening of the high resistivity layer (27, 26). The high specific resistance layers (27, 26) are provided between the emitter region 17 and the light emitting region 15.

  A specific structure of the semiconductor laser 11 will be described.

(First structure)
The semiconductor laser 11a will be described with reference to FIG. In the first area 13b of the main surface 13a of the substrate 13, the lower optical cladding layer 29, the light emitting region 15, and the separation structure 25 are mounted in this order. The isolation structure 25 includes an upper optical cladding layer 27, an emitter region 17, an isolation groove 25c, a first island 25e, and a second island 25f. The upper optical cladding layer 27 has an opening 27a. The opening 27a of the upper optical cladding layer 27 extends from the upper surface 15d of the light emitting region 15 in the direction of the first axis Ax1. A semiconductor layer for the emitter region 17 is provided on the upper optical cladding layer 27 and in the opening 27a. The separation groove 25c extends from the surface of the contact layer 28a in the direction of the first axis Ax1, and terminates in the upper optical cladding layer 27. The semiconductor of the upper optical cladding layer 27 has high specific resistance or semi-insulation, and the semiconductor layers for the emitter region 17 and the contact layer 28a have conductivity. The separation groove 25c reaching the upper optical cladding layer 27 extends in the direction of the second axis Ax2 so as to cross the mesa structure MS, and the semiconductor region (separation structure 25) on the light emitting region 15 of the mesa structure MS Divided into one island 25e and second island 25f. Specifically, the first island 25e, the separation groove 25c, and the second island 25f are sequentially arranged in the direction of the third axis Ax3. The metal electrode 19 makes contact with the side surface of the first island 25e, and the first electrode 31a makes contact with the upper surface of the second island 25f. The isolation trench 25c can electrically isolate the other from one of the first island 25e and the second island 25f, and serves to electrically isolate the metal electrode 19 included in the collector region from the emitter region 17. The first island 25e terminates on the upper edge of the first side surface 15b, and the second island 25f terminates on the upper edge of the second side surface 15c.

  The side surface of the mesa structure MS includes the side surface of the first island 25e (the side surface of the emitter region 17, the contact layer 28a, and the upper optical cladding layer 27), and the first side surface 15b of the light emitting region 15, and the side surface of the first island 25e. The metal electrode 19 is provided on the first side surface 15 b of the light emitting region 15. In this embodiment, the metal electrode 19 is in contact with the side surface of the mesa structure MS and extends in the direction of the first axis Ax1, and in addition to the first side surface 15b of the light emitting region 15, the emitter region 17 (33a, 33b) and the side surface of the semiconductor layer for the contact layer 28a (the side surface of the first island 25e). This extension allows the metal electrode 19 to make contact over the entire first side surface 15 b of the light emitting region 15.

  The insulating coating film 37 covers the side surface and top surface of the mesa structure MS and the side surface and bottom surface of the separation groove 25c, while the first opening 37a is formed on the side surface of the first island 25e and the first side surface 15b of the light emitting region 15. Have. The metal electrode 19 is in contact with the first side surface 15b of the light emitting region 15 through the first opening 37a. The insulating coating film 37 on the side surface of the mesa structure MS extends in the direction of the third axis Ax3 along the side surface of the light emitting region 15, the side surface of the upper semiconductor region 23, and the side surface of the contact layer 28a. The insulating coating film 37 has a second opening 37b on the upper surface of the second island 25f (on the upper surface 15d of the light emitting region 15. The first electrode 31a is in contact with the contact layer 28a through the second opening 37b. .

  In the present embodiment, the substrate 13 has conductivity and provides a path for carriers from the light emitting region 15. The carrier reaches the back electrode 31 c through the conductive substrate 13.

(Second structure)
The semiconductor laser 11b will be described with reference to FIG. In the first area 13b of the main surface 13a of the substrate 13, the lower optical cladding layer 29, the light emitting region 15, and the separation structure 25 are mounted in this order. The isolation structure 25 includes a contact layer 28a, an emitter region 17, and an isolation groove 25d, and further includes an oxide confinement structure 26 in place of the upper optical cladding layer 27 of the first structure. The oxide confinement structure 26 includes an aperture semiconductor region 26a and an insulating oxide region 26b. The upper surface 15d of the light emitting region 15 is in contact with the aperture semiconductor region 26a and the insulating oxide region 26b. In the present embodiment, the aperture semiconductor region 26a extends from the upper edge of the second side surface 15c to the inside of the upper surface 15d of the light emitting region 15, and the insulating oxide region 26b extends from the upper edge of the first side surface 15b. It extends inside the upper surface 15d. The aperture semiconductor region 26a and the insulating oxide region 26b are arranged in the direction from the second side surface 15c to the first side surface 15b (the direction of the third axis Ax3). This arrangement makes it possible to inject carriers inside the light emitting region 15 away from the first side surface 15b of the light emitting region 15 on which the metal electrode 19 is mounted. Carriers from the first electrode 31a reach the light emitting region 15 through the aperture semiconductor region 26a. The aperture semiconductor region 26a is made of a semiconductor having a high Al composition that enables oxidation in the manufacturing process. By this oxidation process, the semiconductor having a high Al composition is oxidized to form an insulating oxide region 26b. A semiconductor with a high Al composition can provide a high band level relative to the band level of the light emitting region 15, and allows carriers to be injected into the light emitting region 15 from a high level in terms of the emitter.

  The isolation groove 25d extends from the surface of the contact layer 28a in the direction of the first axis Ax1 and reaches the insulating oxide region 26b. The insulating oxide region 26b has high insulation, while the semiconductor layer for the emitter region 17 and the contact layer 28a has conductivity. The isolation groove 25d that reaches the insulating oxide region 26b extends in the direction of the second axis Ax2 so as to cross the mesa structure MS, and serves as a semiconductor region (isolation structure 25) on the light emitting region 15 of the mesa structure MS. It is divided into a first island 25e and a second island 25f. Specifically, the first island 25e, the separation groove 25d, and the second island 25f are sequentially arranged in the direction of the third axis Ax3. The metal electrode 19 makes contact with the side surface of the first island 25e, and the first electrode 31a makes contact with the upper surface of the second island 25f. The isolation trench 25d can electrically isolate the other from one of the first island 25e and the second island 25f, and serves to electrically isolate the metal electrode 19 included in the collector region from the emitter region 17. The first island 25e (aperture semiconductor region 26a) terminates on the upper edge of the first side surface 15b, and the second island 25f (insulating oxide region 26b) terminates on the upper edge of the second side surface 15c.

  The side surface of the mesa structure MS includes the side surface of the first island 25e (the side surface of the emitter region 17, the contact layer 28a, and the insulating oxide region 26b) and the first side surface 15b of the light emitting region 15. The metal electrode 19 is provided on the side surface and the first side surface 15 b of the light emitting region 15. In this embodiment, the metal electrode 19 is in contact with the side surface of the mesa structure MS and extends in the direction of the first axis Ax1, and in addition to the first side surface 15b of the light emitting region 15, the emitter region 17 (26a, 35b) and the side surface of the semiconductor layer for the contact layer 28a (side surface of the first island 25e). This extension allows the metal electrode 19 to make contact over the entire first side surface 15 b of the light emitting region 15.

  The insulating coating film 37 covers the side surface and top surface of the mesa structure MS and the side surface and bottom surface of the separation groove 25d, while the first opening 37a is formed on the side surface of the first island 25e and the first side surface 15b of the light emitting region 15. Have. The metal electrode 19 contacts the first side surface 15b (end surface) of the light emitting region 15 through the first opening 37a. The insulating coating films 37 on both side surfaces of the mesa structure MS extend in the direction of the third axis Ax3 along both side surfaces of the light emitting region 15, both side surfaces of the upper semiconductor region 23, and both side surfaces of the contact layer 28a. . The insulating coating film 37 has a second opening 37b on the upper surface of the second island 25f (on the upper surface 15d of the light emitting region 15. The first electrode 31a is in contact with the contact layer 28a through the second opening 37b. .

  In the present embodiment, the substrate 13 has conductivity and provides a path for carriers from the light emitting region 15. The carrier reaches the back electrode 31 c through the conductive substrate 13.

(Third structure)
If necessary, the first structure is such that the emitter region 17 on the first area 13b is in contact with the upper surface 15d of the light emitting region 15, and the first semiconductor layer 33a is provided on the first semiconductor layer 33a. Two semiconductor layers 33b can be provided. As shown in FIG. 2, the first semiconductor layer 33a includes a semiconductor having a conduction band energy equal to or higher than the upper energy level E3 (high in the direction of the potential according to the carrier polarity). The second semiconductor layer 33 b includes a semiconductor having a refractive index smaller than the equivalent refractive index of the light emitting region 15. The conduction band energy level of the first semiconductor layer 33a enables carrier injection from the emitter region 17 to the upper energy level E3 of the light emitting region 15 without requiring a large externally applied voltage.

The structure of the semiconductor laser 11.
Light emitting region 15: 50-period superlattice structure with four layers of undoped AllnAs / undoped InGaAs / undoped AllnAs / undoped InGaAs as unit units.
Emitter region 17: laminated structure of Si-doped InP / undoped AlInAs, or Si-doped InP / Si-doped AlGaInAs / undoped AlInAs, or Si-doped InP / undoped AlGaPSb.
Metal electrode 19: Ti / Pt / Au (titanium / platinum / gold).
Emitter region 17 width: 5 micrometers.
Emitter region 17 thickness: 2 micrometers.
Width of mesa structure MS: 5 micrometers.
Mesa structure MS height: 3 micrometers.
The thickness of the core layer of the light emitting region 15 is 0.8 micrometers.
Upper optical cladding layer 27 (current blocking layer): 0.2 micrometer, Fe-doped InP.
Distance between first side surface 15b and second side surface 15c and opening 27a: 20 micrometers.
Contact layer 28a: 0.1 micrometer.
Lower optical cladding layer 29: 1 micrometer.
Resonator length (distance between first side surface 15n and second side surface 15c): 500 micrometers.
Separation groove (25d) width: 10 micrometers.
Aperture semiconductor region 26a: AlGaAs (Al composition 95%), thickness 0.01 μm.
Insulating oxide region 26b: Group III oxide (for example, aluminum oxide), thickness 0.01 μm, length 20 μm.

  FIG. 3 is a drawing schematically showing a quantum well structure and energy levels for the semiconductor laser according to the present embodiment. The vertical coordinate axis (vertical axis) indicates the energy level of the carrier, and the remaining two coordinate axes (horizontal axis) indicate the X, Z, and Y axes for spatial coordinates. Although the description with reference to FIG. 3 is performed with respect to electron carriers, this description can be read as holes based on knowledge of semiconductor physics.

  1 to 3, the quantum well structure 21 of the light emitting region 15 includes a unit cell 15a, and the unit cell 15a includes, for example, a first well layer 21a, a second well layer 21b, and a first barrier layer. 21c and a second barrier layer 21d. The second barrier layer 21d separates the first well layer 21a from the second well layer 21b. The first well layer 21a separates the first barrier layer 21c from the second barrier layer 21d. The unit cell 15a has a well structure having a well depth (a band edge energy difference between the barrier layer and the well layer) and a well width (well layer thickness) that can provide a plurality of energy levels. Prepare.

  According to the arrangement of the first well layer 21a, the second well layer 21b, the first barrier layer 21c, and the second barrier layer 21d, the unit cell 15a of the quantum well structure 21 has an upper energy level E3 for electrons and The lower energy level E2 can be provided, and in addition to the upper energy level E3 and the lower energy level E2, a relaxation energy level E1 that enables relaxation of electrons can be generated.

  According to the semiconductor laser 11, as shown in FIG. 3, the quantum well structure 21 facilitates providing the upper energy level E3 and the lower energy level E2 to a carrier having a single polarity. Further, in the quantum well structure 21 that can further provide the relaxation energy level E1, the relaxation energy level E1 is a relaxation of the upper energy level E3 by unipolar carriers that have transitioned from the upper energy level E3 to the lower energy level E2. Promotes relaxation in less than an hour.

  Carriers (electrons) are injected from the emitter region 17 into the light emitting region 15 in the stacking direction of the unit cells 15 a in the light emitting region 15. Electrons injected from the conduction band level E17 of the emitter region 17 undergo a light emission transition from the upper energy level E3 to the lower energy level E2. The energy of this transition corresponds to the laser oscillation wavelength. The electrons that have transitioned to the lower energy level E2 are quickly relaxed to the relaxation energy level E1, and are extracted from the relaxation energy level E1 to the metal electrode 19 in the collector region. The quantum well structure 21 that realizes such energy levels facilitates generation of carrier inversion distribution.

  In the unit cell 15a, the first well layer 21a, the second well layer 21b, the first barrier layer 21c, and the second barrier layer 21d are arranged in the Y-axis direction. Regarding the energy level of carriers in the quantum well potential, the energy level in the Y-axis direction is quantized in the band structure of the unit cell 15a to form discrete energy levels. In contrast, the energy levels in the X-axis and Z-axis directions are not quantized, and the carrier conduction in the in-plane directions of the X-axis and Z-axis can be approximated to a two-dimensional free electron model. Understood as a mechanism. In the semiconductor laser 11, the quantization level (E 3, E 2) that contributes to light emission by flowing carriers in the in-plane direction (plane by the X axis and Z axis) of the semiconductor stacking direction (Y axis) for the quantum well structure. To achieve electrical conduction. On the other hand, in the device structure of the quantum cascade laser different from the semiconductor laser 11, carriers flow in the direction in which the energy level is quantized, that is, in the stacking direction of the semiconductor for the quantum well structure.

  The plurality of unit cells 15a are arranged in cascade in the direction of the first axis Ax1 to form the light emitting region 15. The emitter region 17 supplies carriers in parallel to the individual unit cells 15a in the direction of the first axis Ax1. The individual unit cells 15a emit light in parallel in response to the supply of carriers to the upper energy level (E3) and the transition to the lower energy level (E2). The lower energy level (E2) carriers are quickly relaxed and transition to the energy level (E1). The energy level (E1) carriers flow into the metal electrode 19 in the collector region.

  In the stacked unit cell 15a, since the thickness TB1 of the second barrier layer 21d is smaller than the thickness TB2 of the first barrier layer 21c, the first well layer 21a and the second well layer 21b in the unit cell 15a are The first barrier layer 21d is separated from the well layer of the adjacent unit cell 15a by the second barrier layer 21d, and the first well layer 21a and the second well layer 21b are more closely coupled to each other than the well layer in the adjacent unit cell 15a. To do. The upper energy level is generated for each unit cell 15a.

  If necessary, a semiconductor having an intermediate bandgap between the InP material and the AlInAs material between InP and AlInAs in the emitter region is grown, for example, an InP / AlGaInAs / AlInAs stack is formed. Can be formed. This additional semiconductor layer can reduce the hetero-barrier and realize driving at a lower voltage.

Example 1
The structure of the quantum well structure will be described with reference to FIG. In the following description, electrons are used as carriers. Similarly, holes can be used as carriers instead of electrons. In order to increase the transition probability from the upper energy level E3 to the lower energy level E2, it is preferable to lower the carrier density on the lower energy level E2 by extracting carriers. An example of the quantum well structure 21 may include a plurality of (for example, two) well layers (21a, 21b) and one or a plurality of barrier layers (21d) separating the well layers. The barrier layer (21d) is thinner than the barrier layer (21c), and the wave functions of electrons in the well layers (21a, 21b) are transferred to the well layers (21b, 21a) via the barrier layers (21d), respectively. Soak up and bond together. This structure is referred to as a “coupled quantum well”. The coupled quantum well has a well structure that is symmetrical to the left and right with respect to the center line (center in the thickness direction) of the barrier layer (21d). In such a structure, a relaxation energy level E1 that is as low as the LO phonon energy from the lower energy level E2 can be formed, and electrons that have undergone a light-emission transition from the upper energy level E3 to the lower energy level E2 can be quickly generated. To the relaxation energy level E1 by phonon scattering (resonance scattering). In addition, the coupled quantum well can increase the emission transition probability by increasing the overlap between the wave function of the upper energy level E3 and the wave function of the lower energy level E2, thereby increasing the laser gain.
Specific examples of coupled quantum wells.
Well layer / barrier layer: undoped InGaAs / undoped AllnAs.
Well layer (21a) thickness: 4 nm.
Inner barrier layer (21d) thickness: 2 nm.
Well layer (21b) thickness: 4 nm.
Outer barrier layer (21c) thickness: 10 nm.
Energy difference related to oscillation (difference between upper energy level E3 and lower energy level E2): 270 meV (oscillation wavelength: 4.6 micrometers).
Optical gain: 96 cm ⁻¹ / period.
Epop (difference between lower energy level E2 and relaxation energy level E1): 35.6 meV.
Substrate 13: InP substrate.
Moreover, the light emitting region 15 does not require an injection layer in the quantum cascade laser. Therefore, the degree of freedom in designing the quantum well structure is great. For example, in a four-layer design including the AlInAs thickness of the outer barrier layer, a lattice mismatch is introduced that introduces tensile stress in the barrier layer and compressive stress in the well layer, and By substantially canceling the tensile and compressive stress as a whole of the quantum well structure, a large conduction band gap difference (formation of a deep quantum well) can be formed while maintaining good crystallinity. As a result, it is possible to provide improvement in temperature characteristics and expansion of the oscillation wavelength range by suppressing carrier leakage.

(Example 2)
As shown in FIG. 5, a dopant having the same polarity as the polarity of carriers can be added to at least a part of the barrier layer of the quantum well structure. By this addition, the injection efficiency into both well layers can be improved. For example, in a 10 nm thick AlInAs barrier layer, the thin layer regions 21 ca and 21 cc in contact with the well layer can be undoped, and a dopant-added thin layer region 21 cb can be provided therebetween. The doping concentration is preferably about 10 ¹⁷ cm ⁻³ or less in order to avoid loss due to free carrier absorption. This dopant-added thin layer region can enhance the in-plane conductivity in the semiconductor stack of the light emitting region, and can provide carriers to the well layer at a position away from the emitter region in the in-plane direction.

(Example 3)
The semiconductor laser 11 according to the present embodiment injects carriers into the plurality of quantum well structures 21 in the light emitting region 15 from the emitter region 17 in the direction of the first axis Ax1, and provides carriers in each quantum well structure 21. . Carriers in the quantum well structure 21 are transported in a direction parallel to the in-plane direction of the quantum well layer.
When electrons are injected into a device having such a structure, the electron distribution in the light emitting region is estimated by simulation.
In order to estimate the carrier transport in the in-plane direction, a device model that performs numerical experiments by simulation is shown below.
Cavity length L1: 500 micrometers.
Opening width W of the emitter region: 10 micrometers.
Mesa piece width from the center of the opening of the emitter region on the light emitting region in the mesa structure to one of the upper edges of the upper surface of the mesa: 10 micrometers.
The mesa piece width from the center of the opening of the emitter region on the light emitting region in the mesa structure to the other of the upper edge of the upper surface of the mesa is 10, 20, 50 and 100 micrometers.
Electrons drift from the opening of the emitter region by an electric field and are injected into the light emitting region.
Light emitting region: AlInAs / GaInAs multiple quantum well structure.
Model name, vertical conductivity, horizontal conductivity, vertical / horizontal conductivity ratio.
1st model, 4.3E-5, 1.7E-2, 2.53E-3.
Second model, 1.5E-5, 1.7E-2, 8.74E-4.
3rd model, 1.7E-6, 1.7E-2, 9.84E-5.
The notation “2.53E-3” indicates 2.53 × 10 ⁻³ .
The longitudinal / lateral electrical conductivity ratio is a value obtained by dividing the electrical conductivity in the vertical direction by the electrical conductivity in the horizontal direction.
About the current density in the horizontal direction.
According to the calculation result of the model having a mesa width of 100 micrometers, the electron flow density distribution in the lateral direction becomes larger as the electrical conductivity ratio in the longitudinal direction and the lateral direction of the quantum well increases. Further, according to the calculation result of the model having a mesa width of 20 micrometers, the electron current density at the collector electrode is not significantly different in the depth direction at an electrical conductivity ratio of about 3 digits.
About the current density in the vertical direction.
According to the calculation result of the model having a mesa width of 100 micrometers, the electron current density distribution in the vertical direction is distributed just below the emitter electrode. According to the calculation result of the model having a mesa width of 20 micrometers, the downward distribution decreases as the electrical conductivity ratio of the quantum well in the vertical direction and the horizontal direction increases, but the electrical conductivity of about 3 digits. Even in the ratio, electrons are distributed sufficiently downward.

  The semiconductor laser 11 according to the present embodiment is different from the quantum cascade laser in that carriers in the quantum well structure 21 are transported in a direction parallel to the in-plane direction of the quantum well layer. Does not have an inherent hetero barrier. Due to the absence of the hetero-barrier, the semiconductor laser according to the present embodiment can be driven at a low voltage, and the operating voltage does not increase due to the stacking of the quantum well structures 21, so that the quantum well structure 21 can be driven. A large laser gain can be achieved by multiplexing in parallel. Further, the semiconductor laser according to the present embodiment does not generate a loss due to tunnel transport in the quantum cascade laser, and therefore, a significant reduction in power consumption is expected as compared with the quantum cascade laser.

  Unlike the quantum cascade laser including the injection layer for the cascade between the multi-stage quantum wells, the structure of the present embodiment does not include the injection layer, so the current injection side (emitter) and the extraction side (collector electrode) The voltage drop between the two electrodes is the sum of the voltage drop related to the energy of the oscillation wavelength and the voltage drop due to the series resistance of the element. In order to increase the optical gain, the unit cell of the quantum well structure in the light emitting region adopts a structure in which multiple layers are stacked. However, the voltage increase that increases with the number of stacked layers is not generated in the operating mechanism in the structure of this embodiment. Therefore, the operating voltage of the element is greatly reduced.

  Since the quantum cascade laser uses a cascade stack of unit cells for light emission and cascade carrier injection in the stack direction, carrier loss occurs in the carrier injection layer in the quantum cascade laser. On the other hand, the element structure according to the present embodiment does not require a carrier injection layer and does not cause carrier loss in the carrier injection layer. In the element structure according to the present embodiment, the degree of freedom in design related to the stacked structure of the light emitting layer is increased, and the device characteristics can be improved, specifically, the threshold current, the operating voltage, and the power consumption can be reduced. An electrode can be constructed from the upper surface of the wafer as a planar device without a large step. This structure enables an integrated element in which the semiconductor laser according to the present embodiment is integrated with other devices and the semiconductor lasers according to the present embodiment are arranged in an array. Furthermore, the semiconductor laser according to this embodiment. If the carrier injection layer is not included, the epi layer thickness of the light emitting layer can be reduced, and non-destructive optical characteristics such as photoluminescence can be evaluated in-line after epi growth, contributing to reduction in manufacturing time and cost. .

The supply of carriers from the emitter region to the light emitting region will be described with reference to FIG. Part (a) of FIG. 6 is a drawing schematically showing a non-biased band structure in the emitter region 17 and the light emitting region 15. 6B is a drawing schematically showing a band structure under the forward external bias Vb (bias for applying a high potential to the emitter) in the emitter region 17 and the light emitting region 15. FIG. 6 (a) and 6 (b), an array of unit cells 15a is drawn in order to show that the light emitting region 15 has a superlattice structure. The unit cell 15a is shown in part (c) of FIG. In FIG. 6A and FIG. 6B, “Ef1” indicates a Fermi level or a pseudo Fermi level, and “Ec1” indicates a conduction band. The level of the conduction band of the first semiconductor layer 33a is higher than the level of the conduction band of the second semiconductor layer 33b.
Emitter region structure.
First semiconductor layer 33a: undoped AlGaPSb, thickness 20 nm.
Second semiconductor layer 33b: Si-doped InP, thickness 200 nm.

  As shown in FIG. 6B, an external bias is applied to the semiconductor laser to reduce the heterobarrier between the first semiconductor layer 33a and the second semiconductor layer 33b. In response to the lowering of the heterobarrier, high energy carriers C (electrons) are injected from the emitter region 17 into the superlattice structure of the light emitting region 15 through the heterobarrier by thermal carrier emission. The injected carriers lose energy while drifting or diffusing in the light emitting region 15 at a level in the conduction band corresponding to the energy of each carrier, and fall into various unit cells 15a. Light is generated by optical transition from a high energy level (E3) to a low energy level (E2) while drifting inside the unit cell 15a toward the outside of the light emitting region 15. Carriers of energy level (E2) quickly relax to a lower energy level (E1).

The supply of carriers from the emitter region to the light emitting region will be described with reference to FIG. Part (a) of FIG. 7 is a drawing schematically showing a band structure under no bias in the emitter region 17 and the light emitting region 15. Part (b) of FIG. 7 is a drawing schematically showing a band structure under the forward external bias Vb in the emitter region 22 and the light emitting region 15. In FIG. 7, in order to show that the light emitting region 15 has a superlattice structure composed of the array of unit cells 15a, the array of unit cells 15a is drawn. Part (c) of FIG. 7 shows the level of the level E4 in the unit cell 15a and the light emitting region 15. In FIGS. 7A and 7B, “Ef1” indicates a Fermi level or a pseudo-Fermi level, and “Ec1” indicates a conduction band. The emitter region 22 includes a first semiconductor layer 32 a including a tunneling structure 32 in contact with the upper surface of the light emitting region 15.
Structure of the emitter region 18.
First semiconductor layer 32a: undoped AlGaPSb / GaInAs.
Second semiconductor layer 32b: Si-doped InP, thickness 200 nm.
The tunneling structure 32 has the following structure, for example.
AlGaPSb (thickness 5 nm) / GaInAs (thickness 2 nm) / AlGaPSb (thickness 5 nm).

  As shown in part (b) of FIG. 7, an external bias Vb is applied to the semiconductor laser to reduce the heterobarrier between the first semiconductor layer 32a and the second semiconductor layer 32b. When the level of the conduction band of the second semiconductor layer 32 b is in the vicinity of the discrete energy level (E4) in the light emitting region 15, the conduction band of the second semiconductor layer 32 b through the tunneling structure 32 leads to the superlattice structure of the light emitting region 15. Carriers C are injected into the energy level (E4) by tunneling T. The injected carriers lose energy while drifting or diffusing in the light emitting region 15 at a level (for example, level E4) in the conduction band according to the energy of each carrier, and fall into various unit cells 15a. . Light is generated by optical transition from the high energy level (E3) to the low energy level (E2) while drifting in the unit cell 15a to the metal electrode 19 in the collector region. Carriers of energy level (E2) quickly relax to a lower energy level (E1).

  The outline of the manufacturing method will be described with reference to FIGS. In step S101, an epitaxial substrate is formed. 8A shows a cross section taken along the waveguide axis WG1, and FIG. 8B shows the section VIIIb-VIIIb shown in FIG. 8A. A cross section taken is shown. Part (a) of FIG. 8 shows a cross section taken along the line VIIIa-VIIIa shown in part (b) of FIG. As shown in FIGS. 8A and 8B, an Fe-doped InP substrate 61 is prepared. Crystal growth can be performed, for example, by MBE or MOCVD. On the main surface 61a of the InP substrate 61, an InP layer 63 is grown for the lower optical cladding layer. The InP layer 63 can be, for example, Si-doped InP. On the InP layer 63, for example, a superlattice structure 65 for a light emitting region having a stack of unit cells having the above four-layer structure is grown. An InP layer 67 is grown on the superlattice structure 65 for the current block and the upper optical cladding layer. The InP layer 67 includes an iron-doped InP film and / or a Zn-doped InP. Through these steps, the upper semiconductor stack 69 is formed.

  In step S102, an opening for the emitter is formed. Part (c) of FIG. 8 shows a cross section taken along the waveguide axis WG1, and part (d) of FIG. 8 follows the line VIIId-VIIId shown in part (c) of FIG. A cross section taken is shown. (C) part of FIG. 8 shows the cross section taken along the VIIIc-VIIIc line | wire shown by the (d) part of FIG. As shown in FIGS. 8C and 8D, a first SiN mask 71 that defines an opening for the emitter is formed on the main surface 69 a of the upper semiconductor stack 69. Using the first SiN mask 71, the InP layer 67 for the current block and the upper optical cladding layer is etched to form the current block layer 67a from the InP layer 67. The current blocking layer 67a has an opening 67c for the emitter, and the upper surface of the superlattice structure 65 appears in the opening 67c. After the etching, the first SiN mask 71 is removed.

  In step S103, regrowth is performed for the emitter and contact. 9A shows a cross section taken along the waveguide axis WG1, and FIG. 9B shows the section IXb-IXb shown in FIG. 9A. A cross section taken is shown. Part (a) of FIG. 9 shows a cross section taken along the line IXa-IXa shown in part (b) of FIG. 9. As shown in FIGS. 9A and 9B, after the opening 67c is formed by etching, the upper and side surfaces of the current blocking layer 67a, the opening 67c, and the superlattice structure 65 are formed for the emitter region. A Si-doped AlInAs layer 79a and a Si-doped InP layer 79b are sequentially grown on the upper surface of the Si-doped InP layer 79b. A second semiconductor stack 73 including the semiconductor stack is formed. The thickness of the Si-doped AlInAs layer 79a is preferably thick enough to prevent electrons from tunneling, for example, greater than 10 nm. The Si-doped InP layer 79b is grown so as to fill the opening 67c of the current blocking layer 67a, and the upper surface of the Si-doped InP layer 79b is substantially flat. By this regrowth, the opening 67c is embedded to form a semiconductor product including the second semiconductor stack 73 having a substantially flat surface.

  In step S104, a semiconductor mesa for the laser waveguide is formed. 9C shows a cross section taken along the waveguide axis WG1, and FIG. 9D shows the section IXd-IXd shown in FIG. 9C. A cross section taken is shown. (C) part of FIG. 9 shows the cross section taken along the IXc-IXc line | wire shown by the (d) part of FIG. As shown in FIGS. 9C and 9D, a second SiN mask 77 for forming a semiconductor mesa is formed on the main surface 73a of the second semiconductor stack 73 using photolithography and etching. To do. The second semiconductor stack 73 is etched using the second SiN mask 77 to form a stripe mesa 75 extending in the Z-axis direction. The stripe mesa 75 includes a lower optical cladding layer 63b, a superlattice structure 65b, a current blocking layer 67b, a Si-doped AlInAs layer 79c, a Si-doped InP layer 79d, and a Si-doped InGaAs layer 81b. The formation of the stripe mesa 75 gives the first side surface 65c to the superlattice structure 65b. The superlattice structure 65b includes an upper surface 65d and a lower surface 65e in addition to the first side surface 65c. The second side surface opposite to the first side surface 65c is formed by cleavage performed after the metallization step. The stripe mesa 75 is formed on the first area 61b of the main surface 61a. The second semiconductor stack 73 on the second area 61c and the third area 61d of the main surface 61a is etched. The first area 61b and the second area 61c are arranged in the direction of the waveguide axis WG1 (Z-axis of the coordinate system S), and the first area 61b and the third area 61d intersect the waveguide axis WG1. They are arranged in the direction of (X axis of coordinate system S). The first area 61b and the third area 61d extend from one side of the second area 61c in the direction of the waveguide axis WG1, and the first area 61b and the third area 61d are adjacent to each other. The stripe mesa 75 includes an upper surface 75a, a first side surface 75b that intersects the waveguide axis, and a second side surface 75c and a third side surface 75d that extend in the direction of the waveguide axis. After the stripe mesa 75 is formed, the second SiN mask 77 is removed.

  In step S105, a collector / emitter separation structure is formed. 10A shows a cross section taken along the waveguide axis WG1, and FIG. 10B shows the Xb-Xb line shown in FIG. 10A. A cross section taken is shown. Part (a) of FIG. 10 shows a cross section taken along the line Xa-Xa shown in part (b) of FIG. As shown in FIGS. 10A and 10B, a third SiN mask 83 for forming an isolation groove is formed on the main surface of the stripe mesa 75 using photolithography and etching. The third SiN mask 83 has an opening 83a that defines a separation groove. The stripe mesas 75 are etched using the third SiN mask 83 to form the isolation grooves 85a, the first islands 85b, and the second islands 85c. The isolation groove 85a passes through the Si-doped AlInAs layer 79c, the Si-doped InP layer 79d, and the Si-doped InGaAs layer 81c, reaches the current block layer 67b, and terminates in the current block layer 67b. After forming the isolation trench 85a, the third SiN mask 83 is removed.

  In step S106, a passivation film is formed. Part (c) of FIG. 10 shows a cross section taken along the waveguide axis WG1, and part (d) of FIG. 10 follows the Xd-Xd line shown in part (c) of FIG. A cross section taken is shown. (C) part of FIG. 10 shows the cross section taken along the Xc-Xc line | wire shown by the (d) part of FIG. As shown in FIGS. 10C and 10D, after forming the isolation groove 85a, an inorganic insulating protective film 87 such as a silicon oxide film is formed. The inorganic insulating protective film 87 includes, for example, silicon oxide. The inorganic insulating protective film 87 includes a first opening 87a located on the upper surface 75a and a second opening 87b located on the first side surface 75b. The Si-doped InGaAs layer 81b appears in the first opening 87a, and the entire first side surface 75b of the stripe mesa 75 and the surface of the second area 61c appear in the second opening 87b. Specifically, a silicon oxide film for the inorganic insulating protective film 87 is grown by chemical vapor deposition. A resist mask 89 having openings (89a, 89b) defining the first opening 87a and the second opening 87b is formed on the silicon oxide film, and the first opening 87a and the second opening are etched by using the resist mask 89. Openings 87b are formed in the silicon oxide film. The Si-doped InGaAs layer 81c appears in the first opening 87a, and the entire first side surface 75b of the stripe mesa 75 and the surface of the second area 61c appear in the second opening 87b. After the etching, the resist mask 89 is removed.

  In step S107, metal films for the emitter and collector are formed. Part (a) of FIG. 11 shows a cross section taken along the waveguide axis WG1, and part (b) of FIG. 11 follows the line XIb-XIb shown in part (a) of FIG. A cross section taken is shown. (A) part of FIG. 11 shows the cross section taken along the XIa-XIa line | wire shown by the (b) part of FIG. As shown in FIGS. 11A and 11B, a first electrode 91a and a metal electrode 91b are formed in the first opening 87a and the second opening 87b, respectively. Specifically, the first electrode 91a and the metal electrode 91b are formed using a lift-off method. The lift-off mask 93 has respective openings (93a, 93b) aligned with the first opening 87a and the second opening 87b. After the lift-off mask 93 is formed, a metal film 91 for the first electrode 91a and the metal electrode 91b is deposited, and the lift-off mask 93 and the metal deposit 91d on the lift-off mask 93 are removed to form the first electrode 91a. And the metal electrode 91b is formed.

  In step S108, a metal body is formed on the back surface of the InP substrate 61. Part (c) of FIG. 11 shows a cross section taken along the waveguide axis WG1, and part (d) of FIG. 11 follows the line XId-XId shown in part (c) of FIG. A cross section taken is shown. (C) part of FIG. 11 shows the cross section taken along the XIc-XIc line | wire shown by the (d) part of FIG. As shown in FIGS. 11C and 11D, after the first electrode 91a and the metal electrode 91b are formed, the back electrode 91c is formed on the back surface of the InP substrate 61. If necessary, the back electrode 91c may be formed after the back surface of the InP substrate 61 is polished. A laser bar is formed by cleavage from the substrate product thus produced.

  The outline of another manufacturing method will be described with reference to FIGS. In step S201, an epitaxial substrate is prepared. 12 (a) shows a cross section taken along the waveguide axis WG1, and FIG. 12 (b) shows the XIIb-XIIb line shown in FIG. 12 (a). A cross section taken is shown. The (a) part of FIG. 12 shows the cross section taken along the XIIa-XIIa line | wire shown by the (b) part of FIG. As shown in FIGS. 12A and 12B, a Si-doped InP substrate 61 is prepared. On the main surface 61a of the InP substrate 61, an InP layer 63 is grown for the lower optical cladding layer. The InP layer 63 can be, for example, Si-doped InP. On the InP layer 63, for example, a superlattice structure 65 for a light emitting region having a stack of unit cells having the above four-layer structure is grown. A compound semiconductor having a high Al composition for insulation isolation is grown on the superlattice structure 65. The compound semiconductor can comprise, for example, AlGaAs and / or AlInAs, whose Al composition is greater than 0.9. In this embodiment, a Si-doped AlInAs layer 79a for the emitter region is grown on the superlattice structure 65. A Si-doped InP layer 79b is grown on the Si-doped AlInAs layer 79a, and a Si-doped InGaAs layer 81 for a contact layer is grown on the Si-doped InP layer 79b. In addition to the underlying semiconductor stack, an emitter region and A semiconductor stack 82 including a contact layer is formed. These crystal growths can be performed by, for example, the MBE method or the MOCVD method.

  In step S202, a semiconductor mesa is formed. 12C shows a cross section taken along the waveguide axis WG1, and FIG. 12D shows the XIId-XIId line shown in FIG. 12C. A cross section taken is shown. (C) part of FIG. 12 shows the cross section taken along the XIIc-XIIc line | wire shown by the (d) part of FIG. As shown in FIGS. 12C and 12D, a second SiN mask 77 for forming a semiconductor mesa is formed on the main surface 82a of the semiconductor stack 82 using photolithography and etching. The semiconductor stack 82 is etched using the second SiN mask 77 to form a stripe mesa 76 extending in the Z-axis direction. The stripe mesa 76 includes a lower optical cladding layer 63b, a superlattice structure 65b, a Si-doped AlInAs layer 79c, a Si-doped InP layer 79d, and a Si-doped InGaAs layer 81b. In addition to the upper surface 65d and the lower surface 65e, the superlattice structure 65b is provided with the first side surface 65c by the formation of the stripe mesa 76. The superlattice structure 65b includes: The second side surface opposite to the first side surface 65c is formed by cleavage after the metallization step. The stripe mesa 76 is formed on the first area 61b of the main surface 61a. Specifically, the second semiconductor stack 73 on the second area 61c and the third area 61d of the main surface 61a is etched. The first area 61b and the second area 61c, and the third area 61d and the second area 61c are arranged in the direction of the waveguide axis WG1 (Z axis of the coordinate system S), and the first area 61b and the third area 61d are Are arranged in the direction of a cross axis WG2 (X axis of the coordinate system S) intersecting the waveguide axis WG1. The first area 61b and the third area 61d extend from one side of the second area 61c in the direction of the waveguide axis WG1, and the first area 61b and the third area 61d are adjacent to each other. The stripe mesa 75 includes an upper surface 76a, a first side surface 76b intersecting the waveguide axis, and a second side surface 76c and a third side surface 76d extending in the direction of the waveguide axis. After the stripe mesa 75 is formed, the second SiN mask 77 is removed.

  In step S <b> 203, an oxidized constriction structure is formed in the stripe mesa 76. Part (a) of FIG. 13 shows a cross section taken along the waveguide axis WG1, and part (b) of FIG. 13 follows the line XIIIb-XIIIb shown in part (a) of FIG. A cross section taken is shown. Part (a) of FIG. 13 shows a cross section taken along line XIIIa-XIIIa shown in part (b) of FIG. As shown in FIGS. 13A and 13B, an oxidized constriction structure 70 is formed in the stripe mesa 76. Prior to this oxidation, an inorganic insulating protective mask 78 is formed to cover the second side surface 76c and the third side surface 76d of the stripe mesa 76. In order to form the protective mask 78, an inorganic insulating film such as silicon nitride is deposited, and the protective mask 78 is formed from the inorganic insulating film by photolithography and etching. After forming the protective mask 78, the first side surface 76b of the stripe mesa 76 is exposed to an oxidizing atmosphere (for example, high-temperature steam), and the high Al composition compound semiconductor, for example, the Si-doped AlInAs layer 79c in the stripe mesa 76 is striped. The first side surface 76b is oxidized. By this oxidation, an oxidized constriction structure 70 is formed from the Si-doped AlInAs layer 79c. The oxide confinement structure 70 includes a semiconductor aperture region 70a of Si-doped AlInAs and an oxide region 70b of a group III oxide. The oxide region 70b of the group III oxide extends from the first side surface 76b of the stripe mesa 76 in the direction of the waveguide axis. The length of the oxide region 70b of the oxide confinement structure 70 is the length of the stripe mesa 76. From the 1st side surface 76b, it is 20 micrometers, for example. The semiconductor aperture region 70a has a higher band level than the band level of the superlattice structure 65a, and this difference in band level causes carrier injection from the semiconductor aperture region 70a to the superlattice structure 65a. Make good. After the oxidation, the protective mask 78 is removed.

  In step S204, a collector / emitter separation structure is formed. Part (c) of FIG. 13 shows a cross section taken along the waveguide axis WG1, and part (d) of FIG. 13 follows the line XIIId-XIIId shown in part (c) of FIG. A cross section taken is shown. (C) part of FIG. 13 shows the cross section taken along the XIIIc-XIIIc line | wire shown by the (d) part of FIG. As shown in FIGS. 13C and 13D, a third SiN mask 83 for forming an isolation groove on the upper surface 76a of the stripe mesa 76 is formed on the InP substrate 61 by using photolithography and etching. It is formed on the main surface 61a. The third SiN mask 83 has an opening 83a that defines a separation groove. The stripe mesas 76 are etched using the third SiN mask 83 to form isolation grooves 86a, first islands 86b, and second islands 86c. The isolation groove 86a penetrates the contact layer 81b and the Si-doped InP layer 79d, reaches the oxide region 70b of the oxide confinement structure 70, and terminates at the upper surface of the oxide region 70b. After forming the isolation groove 86a, the third SiN mask 83 is removed.

  After removing the third SiN mask 83, Steps S106 to S108 are sequentially performed to form the inorganic insulating protective film 87, the first electrode 91a, and the metal electrode 91b, and the back electrode 91c is formed on the back surface of the InP substrate 61. Form. A laser bar is formed by cleavage from the substrate product thus produced.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. The present invention is not limited to the specific configuration disclosed in the present embodiment. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

  As described above, according to the present embodiment, it is possible to provide a semiconductor laser that makes it possible to use optical transitions of unipolar carriers.

DESCRIPTION OF SYMBOLS 11, 11a, 11b ... Semiconductor laser, 13 ... Board | substrate, 13b ... 1st area, 13c ... 2nd area, 13d ... 3rd area, 15 ... Light emission area | region, 15a ... Unit cell, 17 ... Emitter area | region, 19 ... Metal electrode , 21 ... quantum well structure, 23 ... upper semiconductor region, 25 ... isolation structure.

Claims (7)

A semiconductor laser,
A light emitting region including a plurality of quantum well structures arranged in a direction of a first axis intersecting a main surface of the substrate and having an upper surface and a side surface, and extending in a direction of a waveguide axis on the main surface of the substrate; A mesa structure to
An upper semiconductor region provided on the upper surface of the light emitting region and having first conductivity;
A metal electrode provided on the side surface of the light emitting region and extending in the direction of the first axis;
With
The metal electrode and the light emitting region are arranged in the direction of the waveguide axis on the main surface of the substrate,
The semiconductor laser, wherein the metal electrode is electrically connected to the side surface of the light emitting region. The quantum well structure includes a first well layer, a second well layer, a first barrier layer, and a second barrier layer,
The first barrier layer separates the first well layer from the second well layer;
The semiconductor laser according to claim 1, wherein the first well layer separates the first barrier layer from the second barrier layer. The light emitting region includes a plurality of unit cells arranged in the direction of the first axis,
The unit cell includes the first well layer, the second well layer, the first barrier layer, and the second barrier layer,
The semiconductor laser according to claim 2, wherein a thickness of the first barrier layer is smaller than a thickness of the second barrier layer.   The quantum well structure includes a barrier layer extending along a plane intersecting the direction of the first axis, and a dopant is added to a part or all of the barrier layer. 4. The semiconductor laser as described in any one of 3 above. An emitter electrode in contact with the upper semiconductor region;
A high resistivity layer provided on the upper surface of the light emitting region and having an opening;
Further comprising
The upper semiconductor region is in contact with the light emitting region through the opening of the high resistivity layer,
The upper semiconductor region has an opening reaching the high resistivity layer;
The semiconductor laser according to claim 1, wherein the metal electrode is provided on a side surface of the upper semiconductor region. Further comprising a back electrode provided on the back surface of the substrate,
The substrate has electrical conductivity;
The semiconductor laser according to claim 1, wherein the metal electrode is electrically connected to the substrate. Further comprising an insulating film covering a side surface of the mesa structure;
The insulating film has an opening provided on a side surface of the mesa structure;
The semiconductor laser according to claim 1, wherein the metal electrode is connected to the side surface of the light emitting region through the opening of the insulating film.

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