JP2018137377A - Solar cell element and method for manufacturing solar cell element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve photoelectric conversion efficiency in a PERC-type solar cell element.SOLUTION: A solar cell element comprises a semiconductor substrate, a passivation layer, and a collector electrode layer. The semiconductor substrate includes a first surface and a second surface facing the direction opposite to the first surface. The passivation layer is located on the second surface, and includes one or more through holes. The collector electrode layer is located so as to cover the passivation layer, and has translucency. The semiconductor substrate includes a first semiconductor region of first conductivity type located on the second surface side, and a second semiconductor region of second conductivity type different from the first conductivity type located on the first surface side. A part of the collector electrode layer is located inside at least one through hole of the one or more through holes.SELECTED DRAWING: Figure 3

Description

  The present disclosure relates to a solar cell element and a method for manufacturing the solar cell element.

  As the solar cell element, there is a PERC (Passivated Emitter and Rear Cell) type solar cell element (see, for example, Patent Document 1). The PERC type solar cell element has a structure in which a passivation layer such as an oxide film or a nitride film and a current collecting electrode including a metal such as aluminum disposed on the passivation layer are stacked on the back surface of the semiconductor substrate. Have

Japanese Patent Laid-Open No. 2006-139762

  The PERC type solar cell element has room for improvement in terms of improving the photoelectric conversion efficiency.

  A solar cell element and a method for manufacturing the solar cell element are disclosed.

  One embodiment of the solar cell element includes a semiconductor substrate, a passivation layer, and a collecting electrode layer. The semiconductor substrate has a first surface and a second surface facing in a direction opposite to the first surface. The passivation layer is located on the second surface and has one or more through holes. The current collecting electrode layer is positioned so as to cover the passivation layer and has a light transmitting property. The semiconductor substrate includes a first conductivity type first semiconductor region located on the second surface side and a second conductivity type second semiconductor type different from the first conductivity type located on the first surface side. 2 semiconductor regions. A part of the current collecting electrode layer is located inside at least one through hole of the one or more through holes.

  One aspect of a method for manufacturing a solar cell element includes preparing a semiconductor substrate, forming an impurity-containing layer, forming a third semiconductor region, removing the impurity-containing layer, and a passivation layer. And forming a collecting electrode layer. The semiconductor substrate has a first surface and a second surface facing in a direction opposite to the first surface, and includes a first semiconductor region and a second semiconductor region. The first semiconductor region is located in the region on the second surface side and has a first conductivity type. The second semiconductor region is located in the region on the first surface side and has a second conductivity type different from the first conductivity type. Forming the impurity-containing layer includes forming the impurity-containing layer containing an element that becomes an impurity of the first conductivity type on the second surface. The third semiconductor region is formed by heating the semiconductor substrate on which the impurity-containing layer is formed on the second surface, thereby contacting the impurity-containing layer of the semiconductor substrate. Forming the third semiconductor region having a concentration of the first conductivity type impurity higher than that of the first semiconductor region in a surface layer portion on the second surface side. Removing the impurity-containing layer includes removing the impurity-containing layer from the second surface. Forming the passivation layer includes forming the passivation layer so as to have one or more through holes on the second surface. Forming the collecting electrode layer includes forming the collecting electrode layer having translucency so as to cover the passivation layer.

  For example, the collector electrode layer located on the back side of the PERC type solar cell element has translucency. Thereby, for example, light incident from the back surface can also be used for photoelectric conversion. As a result, for example, the photoelectric conversion efficiency in the PERC type solar cell element can be improved.

FIG. 1 is a plan view showing an external appearance of an example of a solar cell element according to the first to fourth embodiments as viewed from the front side. FIG. 2 is a plan view showing an appearance of an example of the solar cell element according to the first to fourth embodiments as viewed from the back side. FIG. 3 is a cross-sectional view of the solar cell element according to the first embodiment corresponding to a cross section taken along line III-III in FIGS. 1 and 2. FIG. 4 is a flowchart showing an example of the flow of the manufacturing process of the solar cell element. FIG. 5 is a flowchart showing an example of a flow of a first step of preparing a semiconductor substrate. FIG. 6A to FIG. 6F are cross-sectional views illustrating states in the middle of manufacturing solar cell elements. FIG. 7A to FIG. 7E are cross-sectional views illustrating states in the middle of manufacturing solar cell elements. FIG. 8 is a cross-sectional view of the solar cell element according to the second embodiment corresponding to the cross section taken along the line III-III in FIGS. 1 and 2. FIG. 9 is a cross-sectional view of the solar cell element according to the third embodiment corresponding to a cross section taken along line III-III in FIGS. 1 and 2. FIG. 10 is a cross-sectional view of the solar cell element according to the third embodiment corresponding to the cross section taken along the line III-III in FIGS. 1 and 2. FIG. 11 is a cross-sectional view of a solar cell element according to the fourth embodiment corresponding to a cross section taken along line III-III in FIGS. 1 and 2. FIG. 12 is a cross-sectional view of the solar cell element according to the fifth embodiment corresponding to the cross section taken along line III-III in FIGS. 1 and 2. FIG. 13 is a cross-sectional view of the solar cell element according to the sixth embodiment corresponding to the cross section taken along line III-III in FIGS. 1 and 2. FIG. 14 is a cross-sectional view of the solar cell element according to the seventh embodiment corresponding to the cross section taken along line III-III in FIGS. 1 and 2. FIG. 15 is a cross-sectional view of the solar cell element according to the seventh embodiment corresponding to the cross section taken along line III-III in FIGS. 1 and 2.

  Hereinafter, each embodiment will be described with reference to the drawings. In the drawings, parts having similar configurations and functions are denoted by the same reference numerals, and redundant description is omitted in the following description. Since the drawings are schematically shown, for example, some of the components may be omitted in the cross-sectional view. 1 to 3 and FIGS. 8 to 15 are provided with a right-handed XYZ coordinate system. In the XYZ coordinate system, the first direction along the front surface 10a of the solar cell element 10 is the + X direction, the second direction orthogonal to the first direction along the front surface 10a is the + Y direction, and the first direction and the first direction The direction perpendicular to both of the two directions and along the normal line of the front surface 10a is the + Z direction.

<1. First Embodiment>
<1-1. Schematic configuration of solar cell element>
A schematic configuration of the solar cell element 10 according to the first embodiment will be described with reference to FIGS. 1 to 3. The solar cell element 10 according to the first embodiment is a PERC type solar cell element.

  As shown in FIGS. 1 to 3, the solar cell element 10 includes a first surface (also referred to as a front surface) 10a for mainly receiving sunlight and a second surface located on the opposite side of the front surface 10a. 10b (also referred to as the back surface). In the first embodiment, the front surface 10a faces the + Z direction, and the back surface 10b faces the −Z direction. For example, the + Z direction is set to a direction facing the sun going south.

  The solar cell element 10 according to the first embodiment can not only generate power by photoelectric conversion based on the light irradiated on the front surface 10a but also generate power by photoelectric conversion based on the light irradiated on the back surface 10b. . The light irradiated on the front surface 10a includes, for example, sunlight directly irradiated from the sun. The light irradiated on the back surface 10b includes, for example, sunlight reflected by the ground or the like. For this reason, in a normal use environment, for example, the amount of light received by the back surface 10b is smaller than the amount of light received by the front surface 10a.

  The solar cell element 10 includes, for example, a semiconductor substrate 1, an antireflection film 2, a passivation layer 3, a front electrode 4, a back electrode 5, and a collecting electrode layer 6.

<1-1-1. Semiconductor substrate>
The semiconductor substrate 1 has a first surface 1a and a second surface 1b facing in a direction opposite to the first surface 1a. The first surface 1 a is located on the front surface 10 a side of the solar cell element 10. For this reason, the 1st surface 1a is a surface for mainly receiving sunlight. In the example of FIGS. 1 to 3, the first surface 1a faces the + Z direction. The second surface 1 b is located on the back surface 10 b side of the solar cell element 10. In the example of FIGS. 1 to 3, the second surface 1 b faces the −Z direction. The first surface 1a and the second surface 1b constitute a surface of the semiconductor substrate 1 along the XY plane. The semiconductor substrate 1 has a thickness along the + Z direction.

  The semiconductor substrate 1 has a first semiconductor region R1 and a second semiconductor region R2. The first semiconductor region R1 is made of, for example, a semiconductor having the first conductivity type. The second semiconductor region R2 is made of, for example, a semiconductor having a second conductivity type different from the first conductivity type. The first semiconductor region R1 is located at a portion of the semiconductor substrate 1 on the second surface 1b side. The second semiconductor region R2 is located in a portion on the first surface 1a side of the semiconductor substrate 1. In the example of FIG. 3, the semiconductor substrate 1 is mainly constituted by the first semiconductor region R1. The second semiconductor region R2 is located in the surface layer portion of the semiconductor substrate 1 on the first surface 1a side on the first semiconductor region R1.

  Here, for example, it is assumed that the semiconductor substrate 1 is a silicon substrate. In this case, for example, a polycrystalline or single crystal silicon substrate is employed as the silicon substrate. For example, a thin substrate having a thickness of 250 μm or less or 150 μm or less is applied to the silicon substrate. In addition, the silicon substrate has, for example, a substantially rectangular (including square) board surface in plan view. If the semiconductor substrate 1 having such a shape is employed, a gap between the solar cell elements 10 may be reduced when a solar cell module is manufactured by arranging a plurality of solar cell elements 10.

  Further, for example, when the first conductivity type is p-type and the second conductivity type is n-type, the p-type silicon substrate is formed on a polycrystalline or single crystal silicon crystal as a dopant element, for example. Further, it can be manufactured by containing an impurity element such as boron or gallium. In this case, for example, an n-type second semiconductor region R2 can be generated by diffusing impurities such as phosphorus as a dopant in the surface layer portion on the first surface 1a side of the p-type silicon substrate. At this time, the semiconductor substrate 1 in which the p-type first semiconductor region R1 and the n-type second semiconductor region R2 are stacked can be formed. The semiconductor substrate 1 has a pn junction located at the interface between the first semiconductor region R1 and the second semiconductor region R2. Thereby, for example, the semiconductor substrate 1 can generate power by photoelectric conversion according to the incidence of sunlight.

  As shown in FIG. 3, the first surface 1a of the semiconductor substrate 1 may have, for example, a fine concavo-convex structure (texture) for reducing the reflectance of irradiated light. At this time, the height of the convex portion of the texture is, for example, about 0.1 μm to 10 μm. The distance between the vertices of adjacent convex portions is, for example, about 0.1 μm to 20 μm. In the texture, for example, the concave portion may have a substantially spherical shape, or the convex portion may have a pyramid shape. Here, the “height of the convex portion” refers to, for example, a straight line passing through the bottom surface of the concave portion in FIG. It is the distance from the top of the convex part.

Furthermore, the semiconductor substrate 1 has a third semiconductor region R3. The third semiconductor region R3 is located in the surface layer portion of the semiconductor substrate 1 on the second surface 1b side. The conductivity type of the third semiconductor region R3 may be the same as the first conductivity type (p-type in this embodiment) included in the first semiconductor region R1. The concentration of the first conductivity type impurity (also referred to as impurity concentration) contained in the third semiconductor region R3 is higher than that of the first semiconductor region R1. In other words, the concentration of the dopant element contained in the third semiconductor region R3 is higher than the concentration of the dopant element contained in the first semiconductor region R1. For example, the third semiconductor region R3 forms an internal electric field on the second surface 1b side of the semiconductor substrate 1. Thereby, in the vicinity of the 2nd surface 1b of the semiconductor substrate 1, the recombination of the minority carrier which arises by the photoelectric conversion according to light irradiation in the semiconductor substrate 1 can be reduced. As a result, the photoelectric conversion efficiency of the solar cell element 10 is unlikely to decrease. The third semiconductor region R3 can be formed, for example, by diffusing an impurity element (dopant element) such as aluminum in the surface layer portion of the semiconductor substrate 1 on the second surface 1b side. At this time, the concentration of the dopant element contained in the first semiconductor region R1 is set to about 5 × 10 ¹⁵ atoms / cm ³ to 1 × 10 ¹⁷ atoms / cm ^3, and the concentration of the dopant element contained in the third semiconductor region R3 is set to be about 5 × 10 ¹⁵ atoms / cm ^3. It can be about 1 × 10 ¹⁸ atoms / cm ³ to about 5 × 10 ²¹ atoms / cm ³ . The third semiconductor region R3 is also referred to as a BSF (Back Surface Field) layer, for example. The third semiconductor region R3 only needs to exist in a portion between the first semiconductor region R1 and a through hole H1 of the passivation layer 3 to be described later, for example.

<1-1-2. Antireflection film>
The antireflection film 2 can reduce the reflectance of light irradiated on the front surface 10 a of the solar cell element 10. As a material for the antireflection film 2, for example, silicon oxide, aluminum oxide, silicon nitride, or the like can be employed. The antireflective film 2 has a refractive index and a thickness that are low in reflectance (also referred to as low reflection conditions) with respect to light in a wavelength range that can be absorbed by the semiconductor substrate 1 and contribute to power generation. The value can be appropriately set to a value that can be realized. For example, the refractive index of the antireflection film 2 may be about 1.8 to 2.5, and the thickness of the antireflection film 2 may be about 20 nm to 120 nm.

<1-1-3. Passivation layer>
The passivation layer 3 is located on at least the second surface 1 b of the semiconductor substrate 1. The passivation layer 3 can reduce recombination of minority carriers generated by photoelectric conversion in response to light irradiation in the semiconductor substrate 1. As the material for the passivation layer 3, for example, at least one selected from aluminum oxide, zirconium oxide, hafnium oxide, silicon oxide, silicon nitride, silicon oxynitride, and the like is employed. In this case, the passivation layer 3 can be formed by, for example, an atomic layer deposition (ALD) method.

  Here, for example, it is assumed that the first conductivity type is p-type, the second conductivity type is n-type, and aluminum oxide is employed as the material of the passivation layer 3. In this case, for example, aluminum oxide has a negative fixed charge. For this reason, minority carriers (electrons in this case) generated on the second surface 1b side of the semiconductor substrate 1 due to the field effect from the interface (second surface 1b) between the p-type first semiconductor region R1 and the passivation layer 3. Be kept away. Thereby, recombination of minority carriers in the vicinity of the second surface 1b of the semiconductor substrate 1 can be reduced. As a result, the photoelectric conversion efficiency in the solar cell element 10 can be improved. The thickness of the passivation layer 3 is, for example, about 5 nm to 200 nm. The passivation layer 3 may be located also on the 1st surface 1a of the semiconductor substrate 1, for example. Moreover, the passivation layer 3 may be located also on the end surface 1c which connects the 1st surface 1a and the 2nd surface 1b of the semiconductor substrate 1, for example.

  Further, the passivation layer 3 has, for example, one or more through holes H1. The one or more through holes H1 include, for example, at least one current collecting through hole H1n (n is an integer from 1 to N, N is a natural number). The current collecting through hole H1n is a current collecting through hole in which a part of a current collecting electrode layer 6 described later is located. Thereby, for example, the collector electrode layer 6 can be directly connected to the second surface 1 b of the semiconductor substrate 1. In this case, for example, electricity obtained by photoelectric conversion according to light irradiation in the semiconductor substrate 1 is efficiently collected by the collecting electrode layer 6. Here, for example, if the third semiconductor region R3 is present in a portion between the first semiconductor region R1 and at least one current collecting through hole H1n of the passivation layer 3, the light-transmitting property is obtained. The ohmic contact between the current collecting electrode layer 6 having the above and the semiconductor substrate 1 can be good.

  By the way, the at least one current collection through hole H1n may include, for example, two or more current collection through holes H1n including the first through hole H11 and the second through hole H12. In this case, for example, the third semiconductor region R3 includes the first region A1 located between the first semiconductor region R1 and the first through hole H11, and the first semiconductor region R1 and the second through hole H12. A configuration including the second region A2 located between the first region A1 and the third region A3 connecting the first region A1 and the second region A2 is conceivable. Here, for example, the third region A3 is located between the first semiconductor region R1 and the passivation layer 3. In such a configuration, for example, the passivation layer 3 is formed on the third semiconductor region R3, so that crystal defects in the third semiconductor region R3 can be passivated. Thereby, for example, the field effect by the third semiconductor region R3 is enhanced. As a result, for example, minority carrier recombination in the vicinity of the second surface 1b in the semiconductor substrate 1 can be reduced. Therefore, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved.

  Here, for example, the field effect of the third semiconductor region R3 increases as the area of the third semiconductor region R3 located along the second surface 1b between the first semiconductor region R1 and the passivation layer 3 increases. Is strengthened. For example, when the back surface 10b is viewed in plan, a group of third semiconductor regions R3 may exist so as to overlap three or more current collecting through holes H1n. Further, for example, when the rear surface 10b is viewed in plan, the lump of the third semiconductor region R3 is the most from the current collecting through hole H1n (first through hole H11) that is located on the most -X side in the passivation layer 3. The current collecting through hole H1n (Nth through hole H1N) located on the + X side may be present so as to overlap. Further, for example, when the back surface 10b is viewed in plan, the lump of the third semiconductor region R3 is located on the most + Y side from the current collecting through hole H1n located on the most -Y side in the passivation layer 3. You may exist so that it may overlap to through-hole H1n for current collection. In the example of FIG. 3, the third semiconductor region R <b> 3 exists along substantially the entire second surface 1 b of the semiconductor substrate 1. For this reason, when the back surface 10b is viewed in plan, the third semiconductor region R3 in a lump exists so as to overlap with all the current collecting through holes H1n existing in the passivation layer 3.

  In the example of FIG. 3, there are 10 rows of through holes H1n for current collection arranged in the + X direction. Each current collecting through hole H1n includes 15 current collecting through holes H1n arranged in the + Y direction. Here, the diameter of each current collection through-hole H1n is, for example, about 0.05 mm to 0.5 mm. Further, the interval between the current collecting through holes H1n in each row is, for example, about 0.3 mm to 1 mm. Furthermore, the interval between the current collecting through holes H1n in adjacent rows is also set to, for example, about 0.3 mm to 1 mm.

  The one or more through holes H1 may include, for example, an output through hole H1o. The output through hole H1o is an output through hole in which a second bus bar electrode 5a described later is located.

<1-1-4. Surface electrode>
The surface electrode 4 is located on the first surface 1 a of the semiconductor substrate 1. For example, as shown in FIGS. 1 and 3, the surface electrode 4 includes a first bus bar electrode 4a and a plurality of linear first finger electrodes 4b. In the example of FIGS. 1 and 3, there are three first bus bar electrodes 4 a and many (here, 18) first finger electrodes 4 b on the front surface 10 a.

  The first bus bar electrode 4 a is an electrode for taking out electricity obtained by photoelectric conversion according to light irradiation on the semiconductor substrate 1 to the outside of the solar cell element 10. The first bus bar electrode 4a has, for example, an elongated linear shape when the front surface 10a is viewed in plan. The length (also referred to as width) of the first bus bar electrode 4a in the short direction is, for example, about 1.3 mm to 2.5 mm. At least a part of the first bus bar electrode 4a intersects, for example, the first finger electrode 4b. For this reason, the 1st bus-bar electrode 4a and the 1st finger electrode 4b are electrically connected.

  The first finger electrode 4b can collect electricity obtained by photoelectric conversion in the semiconductor substrate 1 according to light irradiation. Each first finger electrode 4b has a width of about 50 μm to 200 μm, for example. For this reason, the width of each first finger electrode 4b is smaller than the width of the first bus bar electrode 4a. The plurality of first finger electrodes 4b are positioned so as to be aligned with an interval of about 1 mm to 3 mm, for example.

  The thickness of the surface electrode 4 is, for example, about 10 μm to 40 μm. The surface electrode 4 can be formed by, for example, applying a metal paste containing silver as a main component into a desired shape by screen printing or the like and then firing the metal paste. Here, the main component means a component whose content ratio (also referred to as content) is 50% by mass or more. Further, for example, the auxiliary electrode 4c having the same shape as the first finger electrode 4b may be positioned along the Y direction of the peripheral edge of the semiconductor substrate 1 to electrically connect the first finger electrodes 4b to each other. .

<1-1-5. Back electrode>
The back electrode 5 is located on the back surface 10 b side of the solar cell element 10. In other words, the back surface electrode 5 is located between the second surface 1b and the back surface 10b of the semiconductor substrate 1. As shown in FIG. 2 and FIG. 3, the back electrode 5 has a second bus bar electrode 5 a and a plurality of second finger electrodes 5 b. In the example of FIG. 2 and FIG. 3, there are three second bus bar electrodes 5a and six second finger electrodes 5b on the back surface 10b.

  The second bus bar electrode 5 a is an electrode for taking out electricity obtained by photoelectric conversion in the solar cell element 10 to the outside of the solar cell element 10. For example, the second bus bar electrode 5a has an elongated linear shape when the back surface 10b is viewed in plan. Here, as shown in FIGS. 2 and 3, for example, if the second bus bar electrode 5a is electrically connected to a collecting electrode layer 6 described later, the electricity collected by the collecting electrode layer 6 is It can be efficiently output to the outside via the second bus bar electrode 5a. Thereby, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved. For example, the second bus bar electrode 5a may be directly connected to the third semiconductor region R3 via the output through hole H1o of the passivation layer 3. In this case, due to good ohmic contact between the second bus bar electrode 5a and the semiconductor substrate 1, electricity generated by photoelectric conversion in the semiconductor substrate 1 can be efficiently collected by the second bus bar electrode 5a. For this reason, for example, the series resistance component in the solar cell element 10 is reduced. As a result, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved.

  Each second bus bar electrode 5a may have a configuration including a plurality of portions arranged in a straight line, as shown in FIGS. 2 and 3, for example, or by a linear integral portion. It may be configured. In the example of FIG. 2, each second bus bar electrode 5a has a configuration in which four portions are arranged in a straight line. The thickness of the second bus bar electrode 5a is, for example, about 10 μm to 30 μm. The width of the second bus bar electrode 5a is, for example, about 1.3 mm to 7 mm. Here, for example, when the second bus bar electrode 5a contains silver as a main component, the second bus bar electrode 5a is coated with a metal paste (also referred to as silver paste) containing silver as a main component in a desired shape by screen printing or the like. Then, it can be formed by firing. In the example of FIG. 2, a part of the second bus bar electrode 5a intersects the second finger electrode 5b. In this case, the second bus bar electrode 5a and the second finger electrode 5b are electrically connected.

  The plurality of second finger electrodes 5b can collect electricity obtained by photoelectric conversion according to light irradiation in the semiconductor substrate 1, for example. Each 2nd finger electrode 5b is located in the back surface 10b side of the solar cell element 10, for example on the current collection electrode layer 6 mentioned later. For example, at least some of the plurality of second finger electrodes 5b are directly connected to the second bus bar electrode 5a. At this time, the remaining portions of the plurality of second finger electrodes 5b are electrically connected to the second bus bar electrode 5a via other second finger electrodes 5b, for example. Due to the presence of the second finger electrode 5b, the series resistance component of the solar cell element 10 is unlikely to increase even when the resistance of the collector electrode layer 6 is not sufficiently low. Thereby, for example, the film thickness of the collector electrode layer 6 can be reduced. As a result, for example, it is difficult for the current collecting electrode layer 6 to absorb light, and the options for the material of the current collecting electrode layer 6 can be further expanded.

  Each second finger electrode 5b has an elongated shape having a width of about 50 μm to 200 μm, for example. For this reason, the width of each second finger electrode 5b is smaller than the width of the second bus bar electrode 5a. The plurality of second finger electrodes 5b include, for example, a portion located so as to extend along the longitudinal direction of the second bus bar electrode 5a, a portion located so as to intersect the second bus bar electrode 5a, Can be included. If such a configuration is adopted, for example, even if the back electrode 5 is present, the light irradiated on the back surface 10b is likely to enter the semiconductor substrate 1.

<1-1-6. Current collecting electrode>
The current collecting electrode layer 6 can collect electricity obtained by photoelectric conversion according to light irradiation in the semiconductor substrate 1, for example. The current collecting electrode layer 6 is positioned so as to cover the passivation layer 3 from the back surface 10b side, for example. In the example of FIGS. 2 and 3, the current collecting electrode layer 6 is located over substantially the entire back surface 10b where the second bus bar electrode 5a is not located. For example, as shown in FIG. 3, a part of the current collecting electrode layer 6 is located inside the at least one current collecting through hole H1n. Moreover, the current collection electrode layer 6 has electroconductivity and translucency, for example. Here, the translucency which the current collection electrode layer 6 has should just be a property which permeate | transmits the light of the wavelength range utilized for photoelectric conversion in the semiconductor substrate 1, for example. Thus, for example, if the current collecting electrode layer 6 positioned on the back surface 10b side of the PERC type solar cell element 10 has translucency, the incident light from the back surface 10b is applied to the semiconductor substrate 1. Is done. For this reason, incident light from the back surface 10 b can be used for photoelectric conversion in the semiconductor substrate 1. As a result, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved.

As the collector electrode layer 6, for example, one having a thickness of about 1 μm to 3 μm and a light transmittance of about 70% to 90% is employed. Examples of the material of the collecting electrode layer 6 include indium tin oxide (ITO), tin oxide (SnO ₂ ), or zinc oxide (ZnO) to which an element selected from aluminum, gallium, boron, and the like is added. An oxide having conductivity and translucency, such as) is employed. Here, for example, if the material of the collector electrode layer 6 contains ITO, the electrical resistivity of ITO is lower than that of tin oxide or the like, so that the series resistance component in the solar cell element 10 is reduced. The As a result, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved.

<1-2. Manufacturing method of solar cell element>
Next, an example of the manufacturing method of the solar cell element 10 is demonstrated based on FIG.4, FIG.5, FIG.6 (a) to FIG.6 (f) and FIG.7 (a) to FIG.7 (e). Here, the solar cell element 10 can be manufactured by sequentially performing the first step ST1 to the twelfth step ST12 shown in FIG.

  First, in the first step ST1, the semiconductor substrate 1 is prepared. Here, the semiconductor substrate 1 has, for example, a first surface 1a and a second surface 1b, and a first semiconductor region R1 and a second semiconductor region R2. The second surface 1b is a surface facing in the opposite direction to the first surface 1a. The first semiconductor region R1 is a first conductivity type region located in a region on the second surface 1b side of the semiconductor substrate 1. The second semiconductor region R2 is a region having a second conductivity type different from the first conductivity type located in the region of the semiconductor substrate 1 on the first surface 1a side.

  In the first step ST1, for example, the first A step ST1A to the first E step ST1E shown in FIG. 5 are sequentially performed. Here, an example in which the first conductivity type is p-type and the second conductivity type is n-type will be described.

  In the first A step ST1A, for example, a pretreatment for etching the surface of the semiconductor substrate 1 using a sodium hydroxide aqueous solution as shown in FIG. 6A is performed. Here, the semiconductor substrate 1 is produced by, for example, slicing a p-type semiconductor (for example, silicon) ingot produced using an existing CZ method or casting method into a thickness of 250 μm or less. . Then, the mechanically damaged layer and the contaminated layer of the cut surface of the semiconductor substrate 1 are removed by the pretreatment for the semiconductor substrate 1. At this time, for example, a region from the surface of the semiconductor substrate 1 to a depth of about 5 μm to 15 μm may be removed by etching.

  In the first B step ST1B, for example, as shown in FIG. 6B, unevenness (texture) is formed on the first surface 1a of the semiconductor substrate 1. The texture can be formed by, for example, dry etching using a reactive ion etching (RIE) method or the like.

In the first C step ST1C, for example, as shown in FIG. 6C, the n-type second semiconductor region R2 is formed in the surface layer portion on the first surface 1a side of the textured semiconductor substrate 1. Here, the second semiconductor region R2 is formed using, for example, a vapor phase thermal diffusion method or a coating thermal diffusion method. For example, in the vapor phase thermal diffusion method, first, in an atmosphere having a diffusion gas mainly containing phosphorus oxychloride (POCl ₃ ) or the like, the semiconductor substrate 1 is applied to the semiconductor substrate 1 for 5 minutes to 30 in a temperature range of about 600 ° C. to 800 ° C. A heat treatment for about a minute is performed to form phosphorous glass on the surface of the semiconductor substrate 1. Thereafter, heat treatment is performed on the semiconductor substrate 1 for about 10 to 40 minutes in a relatively high temperature range of about 800 to 900 ° C. in an atmosphere of an inert gas such as argon or nitrogen. At this time, phosphorus diffuses from the phosphor glass into the semiconductor substrate 1, and the second semiconductor region R2 is formed in the surface layer portion of the semiconductor substrate 1 on the first surface 1a side. The second semiconductor region R2 is formed to have a depth of about 0.1 μm to 2 μm and a sheet resistance value of about 40Ω / □ to 200Ω / □, for example. At this time, the region other than the second semiconductor region R2 of the semiconductor substrate 1 becomes the first semiconductor region R1. Further, in the coating thermal diffusion method, for example, paste-like phosphorous pentoxide (P ₂ O ₅ ) is applied to the surface of the semiconductor substrate 1, and phosphorus is heated to form a surface layer on the first surface 1 a side of the semiconductor substrate 1. By diffusing into the portion, the second semiconductor region R2 can be formed in the surface layer portion on the first surface 1a side of the semiconductor substrate 1.

  In the first D step ST1D, for example, a process of exposing the first semiconductor region R1 having a p-type conductivity type on the second surface 1b of the semiconductor substrate 1 (also referred to as a pn isolation process) is performed. Here, for example, the second semiconductor region formed on the second surface 1b side of the semiconductor substrate 1 is removed by etching. At this time, for example, the second semiconductor region formed on the second surface 1b side can be removed by immersing the portion on the second surface 1b side of the semiconductor substrate 1 in an aqueous solution of hydrofluoric acid. Here, for example, the second semiconductor region formed on the end surface 1c of the semiconductor substrate 1 may also be removed. Thereafter, for example, the phosphor glass attached to the first surface 1a side of the semiconductor substrate 1 when forming the second semiconductor region R2 is removed by etching. In this way, if the second semiconductor region formed on the second surface 1b side is removed by etching with the phosphor glass remaining on the first surface 1a side, the second semiconductor region R2 on the first surface 1a side is removed. Removal and damage can be reduced.

In the first E step ST1E, for example, as shown in FIG. 6D, the antireflection film 2 is formed on the first surface 1a of the semiconductor substrate 1. The antireflection film 2 is formed by using, for example, PECVD method or sputtering method. For example, when the PECVD method is used, the semiconductor substrate 1 is heated in advance to a temperature higher than the temperature during the formation of the antireflection film 2. Thereafter, a mixed gas of silane (SiH ₄ ) and ammonia (NH ₃ ) is diluted with nitrogen (N ₂ ) gas. Then, the reaction pressure of these gases is set to about 50 Pa to 200 Pa, and the plasma generated by glow discharge decomposition is deposited on the first surface 1 a of the heated semiconductor substrate 1. Thereby, the antireflection film 2 mainly containing silicon nitride is formed on the first surface 1 a of the semiconductor substrate 1. At this time, for example, the film formation temperature is set to about 350 ° C. to 650 ° C., and the preheating temperature of the semiconductor substrate 1 is set to about 50 ° C. higher than the film formation temperature. Further, the frequency band of the high frequency power source necessary for glow discharge is set to about 10 kHz to 500 kHz, for example. The gas flow rate is appropriately determined according to the size of the reaction chamber and the like. The gas flow rate is set to a range of, for example, about 150 ml / min (sccm) to 6000 ml / min (sccm). At this time, a value (B / A) obtained by dividing the flow rate B of ammonia gas by the flow rate A of silane gas is set to a range of 0.5 to 1.5, for example.

  Next, in the second step ST2, for example, as shown in FIG. 6E, a layer (impurity) containing an element that becomes a p-type impurity as the first conductivity type on the second surface 1b of the semiconductor substrate 1 is formed. L1) is also formed. Here, for example, when the element that becomes a p-type impurity is aluminum, a metal paste (also referred to as an aluminum paste) containing a metal powder containing aluminum as a main component, an organic vehicle, and glass frit is used as the semiconductor substrate 1. By applying on the second surface 1b, the impurity-containing layer L1 can be formed. Here, for example, the impurity-containing layer L1 can be formed by applying an aluminum paste to a desired region on the second surface 1b of the semiconductor substrate 1 using screen printing or the like. At this time, for example, an aluminum paste applied on the second surface 1b may be dried.

  Next, in the third step ST3, for example, as shown in FIG. 6F, a third semiconductor region R3 is formed in a portion located on the second surface 1b side of the semiconductor substrate 1. Here, for example, by heating the semiconductor substrate 1 on which the impurity-containing layer L1 is formed on the second surface 1b, the surface layer portion on the second surface 1b side in contact with the impurity-containing layer L1 in the semiconductor substrate 1 In addition, the third semiconductor region R3 can be formed. For example, the third semiconductor region R3 has a higher concentration of impurities of the first conductivity type than the first semiconductor region R1. At this time, for example, the aluminum paste is baked in a heating furnace with a heating time of several tens of seconds to several tens of minutes so that the maximum temperature is about 600 ° C. to 850 ° C. Thereby, for example, aluminum diffuses into a portion in contact with the impurity-containing layer L1 in the surface layer portion located on the second surface 1b side of the semiconductor substrate 1. As a result, for example, the surface layer portion in which the third semiconductor region R3 in which the concentration of the aluminum element as the impurity element of the first conductivity type is higher than the first semiconductor region R1 is located on the second surface 1b side of the semiconductor substrate 1 Formed.

  Next, in the fourth step ST4, for example, as shown in FIGS. 6F to 7A, the impurity-containing layer L1 is removed from the second surface 1b of the semiconductor substrate 1. Here, for example, by immersing the second surface 1b of the semiconductor substrate 1 in hydrochloric acid, the impurity-containing layer L1 can be removed by dissolution. Thereby, for example, the third semiconductor region R3 can be exposed on the second surface 1b of the semiconductor substrate 1.

The formation of the third semiconductor region R3 may be performed by thermally diffusing boron into the second surface 1b of the semiconductor substrate 1 using, for example, boron tribromide (BBr ₃ ), or by ion implantation of boron. May be. However, as described above, when the third semiconductor region R3 is formed by forming the impurity-containing layer L1 with an aluminum paste or the like and removing the impurity-containing layer L1 after firing, an expensive device is not required. A favorable third semiconductor region R3 can be formed by a simple method.

  Thus, even when the current-collecting electrode layer 6 having translucency is formed on the back surface 10b side of the solar cell element 10 by the second step ST2 to the fourth step ST4, for example, the semiconductor substrate 1 The third semiconductor region R3 can be formed on the second surface 1b side. Thereby, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved. In addition, for example, in the second step ST2, the size of the impurity-containing layer L1 formed on the second surface 1b is appropriately adjusted, so that the third region is formed in a relatively wide region on the second surface 1b side of the semiconductor substrate 1. The semiconductor region R3 can be easily formed.

  Next, in the fifth step ST5, for example, the third semiconductor region R3 is purified. Here, for example, the second surface 1b of the semiconductor substrate 1 is immersed in a 1% by mass hydrofluoric acid aqueous solution for about 10 seconds to 60 seconds. Thereby, the passive compound of aluminum and silicon that was not dissolved in hydrochloric acid in the fourth step ST4 can be removed. The fifth step ST5 may be omitted. However, for example, if this fifth step ST5 is executed, the series resistance component of the solar cell element 10 can be reduced.

  Next, in the sixth step ST6, for example, as shown in FIG. 7B, the passivation layer 3 is formed on the second surface 1b of the semiconductor substrate 1. Here, for example, the passivation layer 3 can be formed by forming an aluminum oxide layer having a thickness of about 5 nm to 20 nm on the second surface 1b by using the ALD method. At this time, for example, the passivation layer 3 may be formed on the entire periphery including the end surface 1 c of the semiconductor substrate 1.

  In the step of forming the passivation layer 3 by the ALD method, first, the semiconductor substrate 1 on which the third semiconductor region R3 is formed is placed in the chamber of the film forming apparatus. Then, in a state where the semiconductor substrate 1 is heated to a temperature range of about 100 ° C. to about 250 ° C., a series of steps in which the next step A to step D are sequentially performed are repeated a plurality of times, so that aluminum oxide having a desired film thickness is obtained. Can be formed.

  [Step A] An aluminum material such as trimethylaluminum (TMA) for forming aluminum oxide is supplied onto the semiconductor substrate 1 together with a carrier gas such as Ar gas or nitrogen gas. Thereby, the aluminum raw material is adsorbed on the second surface 1 b of the semiconductor substrate 1. The TMA supply time is, for example, about 15 milliseconds to 3000 milliseconds.

  [Step B] The aluminum material in the chamber is removed by purifying the inside of the chamber of the film forming apparatus with nitrogen gas. Further, aluminum materials other than the components chemically adsorbed at the atomic layer level among the aluminum materials physically adsorbed and chemically adsorbed on the semiconductor substrate 1 are removed. The time for purging the inside of the chamber with nitrogen gas is, for example, about 1 second to several tens of seconds.

  [Step C] By supplying an oxidizing agent such as water or ozone gas into the chamber of the film forming apparatus, the alkyl group contained in TMA is removed and replaced with an OH group. Thereby, an atomic layer of aluminum oxide is formed on the semiconductor substrate 1. The time for supplying the oxidizing agent into the chamber is, for example, about 750 milliseconds to 1100 milliseconds.

  [Step D] By purifying the inside of the chamber of the film forming apparatus with nitrogen gas, the oxidizing agent in the chamber is removed. At this time, for example, an oxidant that has not contributed to the reaction during the formation of atomic layer level aluminum oxide on the second surface 1b of the semiconductor substrate 1 is removed. Here, the time for purifying the inside of the chamber with nitrogen gas is, for example, about 1 second to several tens of seconds.

  Next, in the seventh step ST7, for example, as shown in FIG. 7C, at least one current collection through hole H1n is formed in the passivation layer 3. Thereby, for example, the passivation layer 3 can be formed on the second surface 1b of the semiconductor substrate 1 so as to have at least one current collecting through hole H1n. Here, at least one current collecting through hole H1n is formed by removing a desired local portion of the passivation layer 3 by, for example, laser beam irradiation or etching using an acid resistant resist mask. be able to. As a laser beam irradiation method, for example, a method using a YAG laser is employed. Etching using an acid-resistant resist mask includes, for example, forming an acid-resistant resist pattern on the passivation layer 3 by screen printing or the like, and then performing etching using phosphoric acid on the passivation layer 3 to collect current. The through hole H1n for use can be formed. In this method, the surface of the third semiconductor region R3 is hardly damaged. Here, for example, if the third semiconductor region R3 is formed in a relatively wide region on the second surface 1b side of the semiconductor substrate 1, the current collecting through hole H1n of the passivation layer 3 and the third semiconductor region R3 Precise alignment with the portion where the is formed becomes unnecessary. Thereby, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be easily improved.

  Next, in the eighth step ST8, for example, a conductive paste for forming the surface electrode 4 is applied on the antireflection film 2 formed in the first E step ST1E. Also, a conductive paste for forming the second bus bar electrode 5a is applied on the passivation layer 3 formed in the sixth step ST6 to the seventh step ST7. Here, as the conductive paste, for example, a silver paste containing a metal powder containing silver as a main component, an organic vehicle, and glass frit is employed. Here, for example, the conductive paste can be applied in a desired shape by screen printing or the like. At this time, for example, after applying the conductive paste, the conductive paste may be dried by evaporating the solvent at a predetermined temperature.

  Next, in the ninth step ST9, for example, the conductive paste applied in the eighth step ST8 is baked. Here, for example, the conductive paste can be fired under the condition that the maximum temperature is about 600 ° C. to 850 ° C. and the heating time is about several tens of seconds to several tens of minutes in a firing furnace. At this time, for example, the conductive paste on the antireflection film 2 fires through the antireflection film 2 and is electrically connected to the second semiconductor region R2. Further, for example, the conductive paste on the passivation layer 3 is fired through the passivation layer 3 and electrically connected to the third semiconductor region R3. Thereby, as shown in FIG. 7D, the surface electrode 4 and the second bus bar electrode 5a can be formed.

  Next, in the tenth step ST10, for example, as shown in FIG. 7E, the light-collecting collecting electrode layer 6 is formed so as to cover the passivation layer 3. Here, for example, ITO can be deposited by sputtering or the like. The thickness of the collector electrode layer 6 is, for example, about 1 μm to 3 μm. At this time, the current collecting electrode layer 6 is formed on the passivation layer 3 and in the current collecting through hole H1n, for example. Here, for example, the current collecting electrode layer 6 may not be formed on the second bus bar electrode 5a using a mask, or the current collecting electrode layer 6 formed on the second bus bar electrode 5a may be polished or the like. May be removed. Here, for example, the collector electrode layer 6 may be formed on the second bus bar electrode 5a. In this case, for example, if ultrasonic soldering is used, a wiring material composed of a strip-shaped copper foil or the like can be bonded onto the second bus bar electrode 5a.

  Next, in the eleventh step ST11, for example, a conductive paste for forming the second finger electrode 5b is applied to the elongated region on the current collecting electrode layer 6 formed in the tenth step ST10. Here, as the conductive paste, for example, a thermosetting conductive resin is employed. As the thermosetting conductive resin, for example, a filler containing one or more of silver particles, copper particles, and metal particles obtained by coating copper particles with silver, epoxy resin, phenol resin, etc. What was mixed with the thermosetting resin of the seed | species or more is employ | adopted. At this time, for example, the conductive paste is applied so as to be in contact with the second bus bar electrode 5a.

  Next, in the twelfth step ST12, for example, by heating the conductive paste applied in the eleventh step ST11, as shown in FIG. 1 and FIG. The finger electrode 5b is formed. Here, for example, if a thermosetting conductive resin is used as the conductive paste, it is about 100 ° C. to 150 ° C. compared to a temperature of about 700 ° C. to 800 ° C. which is the firing temperature of the metal paste. The second finger electrode 5b is formed by heating to a relatively low temperature. For this reason, it becomes difficult to produce the malfunction which the electrical resistance of the current collection electrode layer 6 increases by heating, for example. Thereby, for example, the series resistance component in the solar cell element is reduced. As a result, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved. Here, the heating time is, for example, 30 minutes to 60 minutes.

<1-3. Summary of First Embodiment>
In the solar cell element 10 according to the first embodiment, for example, the collecting electrode layer 6 located on the back surface 10b side has translucency. For this reason, the incident light from the back surface 10b can be utilized for photoelectric conversion. As a result, for example, the photoelectric conversion efficiency can be improved as compared with the case where the current collecting electrode layer on the back surface side does not have translucency mainly composed of aluminum or the like.

  In the method for manufacturing the solar cell element 10 according to the first embodiment, for example, the impurity-containing layer L1 is temporarily formed on the second surface 1b of the semiconductor substrate 1, and the surface layer portion on the second surface 1b side of the semiconductor substrate 1 is heated. The impurity element is diffused into the third semiconductor region R3, thereby forming the third semiconductor region R3. Thereafter, for example, the impurity-containing layer L1 is removed from the second surface 1b, and the passivation layer 3, the back electrode 5 and the collecting electrode layer 6 are formed on the second surface 1b. By such a process, for example, even when the light-collecting collecting electrode layer 6 is formed on the back surface 10b side of the solar cell element 10, the third semiconductor region is formed on the second surface 1b side of the semiconductor substrate 1. R3 can be easily formed. Thereby, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be easily improved.

  Further, for example, by appropriately adjusting the size of the impurity-containing layer L1 formed on the second surface 1b, the third semiconductor region R3 can be easily formed in a relatively wide region on the second surface 1b side of the semiconductor substrate 1. Can be formed. At this time, for example, precise alignment between the current collecting through hole H1n of the passivation layer 3 and the portion where the third semiconductor region R3 is formed becomes unnecessary. Thereby, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be easily improved.

<2. Other embodiments>
The present disclosure is not limited to the above-described first embodiment, and various changes and improvements can be made without departing from the scope of the present disclosure.

<2-1. Second Embodiment>
With the solar cell element 10 according to the first embodiment as a basic configuration, for example, as shown in FIG. 8, a protective layer 7A located between the passivation layer 3 and the collector electrode layer 6 is added. The solar cell element 10A may be employed. The protective layer 7A can protect the passivation layer 3, for example. In this case, the current collecting electrode layer 6 is positioned so as to cover the passivation layer 3 from above the protective layer 7A, for example. Here, for example, the presence of the protective layer 7A makes it difficult for the passivation layer 3 to deteriorate when the back electrode 5 is formed, when the collecting electrode layer 6 is formed, and when the solar cell element 10A is used. As a result, for example, the electric field effect by the passivation layer 3 can be improved, and the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved.

  As the material of the protective layer 7A, for example, one or more selected from silicon oxide, silicon nitride, silicon oxynitride, and the like are employed. The protective layer 7A is located on the passivation layer 3 in a state having a desired pattern. The protective layer 7A has, for example, a through hole that penetrates the protective layer 7A in the thickness direction (here, the + Z direction) so as to communicate with the through hole H1 of the passivation layer 3. The thickness of the protective layer 7A is, for example, about 0.5 μm to 10 μm. The thickness of the protective layer 7A is appropriately changed according to the composition of an insulating paste to be described later for forming the protective layer 7A, the shape of the second surface 1b of the semiconductor substrate 1, the formation conditions of the collecting electrode layer 6, and the like. Is done.

  The protective layer 7A is, for example, after the insulating paste is applied on the passivation layer 3 formed on the second surface 1b of the semiconductor substrate 1 so as to have a desired pattern by a coating method such as a screen printing method. It is formed by drying. Here, for example, if the protective layer 7A is formed on the end surface 1c of the semiconductor substrate 1 directly or via another layer, generation of leakage current in the solar cell element 10A can be reduced.

  As the insulating paste, for example, a paste containing a siloxane resin, an organic solvent, and a plurality of fillers is employed. A siloxane resin is a siloxane compound having a Si—O—Si bond. Specifically, the siloxane resin may be a low molecular weight resin having a molecular weight of 10,000 or less, which is generated by hydrolyzing alkoxysilane or silazane or the like and performing condensation polymerization.

  The insulating paste can be generated as follows, for example.

  First, a siloxane resin precursor, water, an organic solvent, and a catalyst are mixed in a container and stirred to prepare a mixed solution. As the precursor of the siloxane resin, for example, a silane compound containing an Si—O bond or a silazane compound containing an Si—N bond, which has a property of becoming a siloxane resin by hydrolysis and condensation polymerization, can be employed. Water is a liquid for hydrolyzing the precursor of the siloxane resin. The organic solvent is a solvent for producing a paste containing a siloxane resin from a siloxane resin precursor. The catalyst can control the reaction rate when the siloxane resin precursor undergoes hydrolysis and condensation polymerization. As the catalyst, for example, one or more inorganic acids or one or more organic acids of hydrochloric acid, nitric acid, sulfuric acid, boric acid, phosphoric acid, hydrofluoric acid, and acetic acid are used. Further, as the catalyst, for example, one or more inorganic bases or one or more organic bases among ammonia, sodium hydroxide, potassium hydroxide, barium hydroxide, calcium hydroxide, pyridine and the like may be used. Further, the catalyst may be, for example, a combination of an inorganic acid and an organic acid, or a combination of an inorganic base and an organic base.

  Next, for example, by-products including alcohol and water generated by hydrolysis during the production of the mixed solution are removed from the mixed solution by evaporating by heating in a temperature range from room temperature to 90 ° C., for example. . Here, when the insulating paste is applied by a spray method using a mask or the like, the by-product may not be removed from the mixed solution.

  Next, for example, a filler containing silicon oxide, aluminum oxide, titanium oxide, or the like is added to the mixed solution from which by-products have been removed. At this time, for example, the mixed solution may be stirred. Further, for example, a filler may be mixed when a siloxane resin precursor, water, an organic solvent, and a catalyst are mixed in a container.

  Then, for example, the viscosity of the mixed solution is stabilized by storing the mixed solution at room temperature. Thereby, an insulating paste is generated.

  Further, for example, the protective layer 7A may be formed on the passivation layer 3 using a dry process such as a PECVD method using a mask. For example, when a silicon nitride film or the like is formed as the protective layer 7A by the PECVD method or the like, the film thickness is about 5 nm to 50 nm.

<2-2. Third Embodiment>
For example, as shown in FIG. 9, the solar cell element 10 </ b> B in which the third semiconductor region R <b> 3 is a relatively small third semiconductor region R <b> 3 </ b> B as the basic configuration of the solar cell elements 10, 10 </ b> A according to the above embodiments. May be adopted. In the example of FIG. 9, the third semiconductor region R3B is formed only in a portion between the first semiconductor region R1 and each through hole H1. Furthermore, the solar cell element 10C having the semiconductor substrate 1C from which the third semiconductor region R3 is omitted as shown in FIG. May be. However, as described above, for example, the larger the portion where the third semiconductor region R3 is formed along the second surface 1b of the semiconductor substrate 1, the more the field effect by the third semiconductor region R3 can be improved. Further, for example, if at least a part of the third semiconductor regions R3 and R3B is located between the first semiconductor region R1 and the passivation layer 3, the passivation layer formed on the third semiconductor regions R3 and R3B. 3 can passivate crystal defects in the third semiconductor regions R3 and R3B. Thereby, for example, the field effect by the third semiconductor region R3 is enhanced. As a result, minority carrier recombination in the vicinity of the second surface 1b in the semiconductor substrate 1 can be reduced. Therefore, for example, the photoelectric conversion efficiency in the PERC type solar cell elements 10 and 10A can be improved.

<2-3. Fourth Embodiment>
For example, as shown in FIG. 11, the second bus bar electrode 5aD in which the second bus bar electrode 5a does not penetrate the passivation layer 3 has the basic configuration of the solar cell elements 10, 10A, 10B, and 10C according to the above embodiments. The solar cell element 10 </ b> D having the back surface electrode 5 </ b> D may be employed. In the example of FIG. 11, for example, the second bus bar electrode 5aD is directly connected to the collector electrode layer 6, but is not directly connected to the third semiconductor region R3. Thereby, for example, the area of the passivation layer 3 can be increased. As a result, for example, the photoelectric conversion efficiency in the solar cell element 10D can be improved.

<2-4. Fifth Embodiment>
A solar cell having a back electrode 5E in which the second finger electrode 5b is omitted as shown in FIG. 12, for example, with the solar cell elements 10, 10A, 10B, 10C, and 10D according to the above embodiments as a basic configuration. The element 10E may be employed. However, for example, if the second finger electrode 5b is present, the width and length of the second bus bar electrode 5a can be reduced. Thereby, for example, the portion where the second bus bar electrode 5a penetrates the passivation layer 3 is reduced. As a result, for example, deterioration or reduction of the passivation layer 3 can be reduced. Therefore, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved by the electric field effect of the passivation layer 3.

<2-5. Sixth Embodiment>
The solar cell elements 10, 10A, 10B, 10C, 10D, and 10E according to each of the above embodiments have a back surface electrode 5F in which the second bus bar electrode 5a is omitted, as shown in FIG. 13, for example, The solar cell element 10F may be employed. At this time, for example, the second finger electrode 5b may be omitted. In the case of such a structure, by using ultrasonic soldering, a wiring material composed of a strip-shaped copper foil or the like can be joined to the collecting electrode layer 6 made of ITO or the like. However, for example, if the second bus bar electrode 5a is present, the electricity collected by the current collecting electrode layer 6 can be efficiently output to the outside via the second bus bar electrode 5a. As a result, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved.

<2-6. Seventh Embodiment>
With the solar cell elements 10, 10A, 10B, 10C, 10D, and 10F according to the second, third, fourth, and sixth embodiments as basic configurations, for example, as shown in FIG. 14, the second finger electrode 5b A solar cell element 10G having a back electrode 5G which is a second finger electrode 5bG located between the passivation layer 3 and the collector electrode layer 6 may be employed. In the example of FIG. 14, the second finger electrode 5bG of the back electrode 5G is located on the protective layer 7A. In this case, for example, the second finger electrode 5bG may be directly connected to the third semiconductor region R3 via the current collecting through hole H1n. Such a second finger electrode 5bG can be formed, for example, in an elongated region on the protective layer 7A before the current collecting electrode layer 6 is formed.

  Further, for example, as shown in FIG. 15, the protective layer 7A may be omitted. In the example of FIG. 15, the solar cell element 10 </ b> H having the back electrode 5 </ b> H that is the second finger electrode 5 b </ i> H in which the second finger electrode 5 b </ i> G is positioned between the passivation layer 3 and the collector electrode layer 6 is employed. ing. Specifically, the second finger electrode 5 b H of the back electrode 5 H is located on the passivation layer 3. Also in this case, for example, the second finger electrode 5bH may be directly connected to the third semiconductor region R3 via the current collecting through hole H1n.

  Such a second finger electrode 5bH is formed in an elongated region on the passivation layer 3 before the current collecting electrode layer 6 is formed, for example. In this case, for example, after applying a conductive paste for forming the second finger electrode 5bH to the elongated region on the passivation layer 3, the conductive paste is heated, whereby the second elongated layer is formed on the passivation layer 3. The finger electrode 5bH can be formed. At this time, for example, if a thermosetting conductive resin is used as the conductive paste, the temperature is about 100 ° C. to 150 ° C. compared to the temperature of 700 ° C. to 800 ° C. which is the firing temperature of the metal paste. The second finger electrode 5bH is formed by heating to a relatively low temperature. For this reason, for example, the fire-through of the passivation layer 3 with the conductive paste for forming the second finger electrode 5bH is unlikely to occur. Thereby, for example, reduction and deterioration of the passivation layer 3 can be reduced. As a result, for example, the electric field effect due to the passivation layer 3 is difficult to be reduced. Therefore, for example, the photoelectric conversion efficiency in the PERC type solar cell element 10 can be improved. In addition, for example, since the second finger electrodes 5bG and 5bH are protected by the current collecting electrode layer 6, deterioration such as oxidation of the second finger electrodes 5bG and 5bH hardly occurs, and the weather resistance performance of the solar cell elements 10G and 10H is improved. improves.

<3. Other>
In the first, second, third, fourth, sixth, and seventh embodiments, for example, as a conductive paste for forming the second finger electrodes 5b, 5bG, and 5bH, a specific wavelength such as ultraviolet rays is used. A photo-curing conductive resin that cures in response to light irradiation may be employed. In this case, for example, the second finger electrodes 5b, 5bG, 5bH can be formed without heating. Thereby, for example, the decrease and deterioration of the passivation layer 3 and the deterioration of the collecting electrode layer 6 are less likely to occur.

  It goes without saying that all or a part of each of the above embodiments and various modifications can be appropriately combined within a consistent range. For example, in the above description, in the first B step ST1B, the texture is formed only on the first surface 1a of the semiconductor substrate 1, but the texture is also formed on the second surface 1b, and the back surface 10b side of the solar cell element is formed. The reflection of light may be reduced.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 1a 1st surface 1b 2nd surface 3 Passivation layer 4 Surface electrode 4a 1st bus-bar electrode 4b 1st finger electrode 5, 5D, 5E, 5F, 5G, 5H Back surface electrode 5a, 5aD 2nd bus-bar electrode 5b, 5bG , 5bH Second finger electrode 6 Current collecting electrode layer 7A Protective layer 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H Solar cell element A1 1st area A2 2nd area A3 3rd area H1 Through hole H11 First through hole H12 Second through hole H1n Current collecting through hole H1o Output through hole L1 Impurity-containing layer R1 First semiconductor region R2 Second semiconductor region R3 Third semiconductor region

Claims (11)

A semiconductor substrate having a first surface and a second surface facing away from the first surface;
A passivation layer located on the second surface and having one or more through holes;
A current-collecting electrode layer located so as to cover the passivation layer and having translucency,
The semiconductor substrate includes a first conductivity type first semiconductor region located on the second surface side and a second conductivity type second semiconductor type different from the first conductivity type located on the first surface side. 2 semiconductor regions,
A part of said current collection electrode layer is a solar cell element located in the inside of at least 1 through-hole of said 1 or more through-holes. The solar cell element according to claim 1,
The semiconductor substrate is located between the first semiconductor region and the at least one through hole, and has a third conductivity type impurity concentration higher than that of the first semiconductor region. A solar cell element further comprising a region. The solar cell element according to claim 2,
The at least one through hole includes a first through hole and a second through hole,
The third semiconductor region is located between the first semiconductor region and the first through hole, and the first region located between the first semiconductor region and the second through hole. A solar cell element including a second region and a third region located between the first semiconductor region and the passivation layer and connecting the first region and the second region. The solar cell element according to any one of claims 1 to 3, wherein
A solar cell element, further comprising: a bus bar electrode connected to the collector electrode layer and positioned linearly when the collector electrode layer is viewed in plan. The solar cell element according to claim 2 or 3, wherein
A bus bar electrode connected to the current collecting electrode layer and positioned in a straight line when the current collecting electrode layer is viewed in plan, further comprising:
The one or more through holes further include an output through hole in which the bus bar electrode is located,
The bus bar electrode is a solar cell element connected to the third semiconductor region through the output through hole. The solar cell element according to claim 4 or 5, wherein
A solar cell element comprising: an elongated finger electrode located on the current collecting electrode layer or between the passivation layer and the current collecting electrode layer and connected to the bus bar electrode. The solar cell element according to any one of claims 1 to 6,
The first conductivity type is p-type;
The second conductivity type is n-type;
The material for the passivation layer is a solar cell element containing aluminum oxide. The solar cell element according to any one of claims 1 to 7,
The solar cell element further provided with the protective layer located between the said passivation layer and the said current collection electrode layer. The solar cell element according to any one of claims 1 to 8,
A material for the current collecting electrode layer is a solar cell element containing indium tin oxide. A first semiconductor region having a first conductivity type and a first surface and a second surface facing in a direction opposite to the first surface and located in a region on the second surface side And preparing a semiconductor substrate including a second semiconductor region located in the region on the first surface side and having a second conductivity type different from the first conductivity type;
Forming an impurity-containing layer containing an element which becomes the impurity of the first conductivity type on the second surface;
By heating the semiconductor substrate on which the impurity-containing layer is formed on the second surface, the surface layer portion on the second surface side that is in contact with the impurity-containing layer of the semiconductor substrate has the first surface Forming a third semiconductor region having a concentration of the first conductivity type impurity higher than that of the semiconductor region;
Removing the impurity-containing layer from the second surface;
Forming a passivation layer on the second surface so as to have one or more through holes;
Forming a translucent collecting electrode layer so as to cover the passivation layer. It is a manufacturing method of the solar cell element according to claim 10,
Applying a thermosetting conductive resin to an elongated region on the passivation layer or the collecting electrode layer;
A method of manufacturing a solar cell element, further comprising: forming elongate finger electrodes on the passivation layer or the collecting electrode layer by heating the thermosetting conductive resin.

Images