JP2018137255A - Method of manufacturing electronic device - Google Patents

Method of manufacturing electronic device Download PDF

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JP2018137255A
JP2018137255A JP2017028591A JP2017028591A JP2018137255A JP 2018137255 A JP2018137255 A JP 2018137255A JP 2017028591 A JP2017028591 A JP 2017028591A JP 2017028591 A JP2017028591 A JP 2017028591A JP 2018137255 A JP2018137255 A JP 2018137255A
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substrate
hole
electrode
manufacturing
holes
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孝英 臼井
Takahide Usui
孝英 臼井
閑野 義則
Yoshinori Kanno
義則 閑野
富田 努
Tsutomu Tomita
努 富田
新一 荒木
Shinichi Araki
新一 荒木
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New Japan Radio Co Ltd
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New Japan Radio Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method capable of easily manufacturing a through electrode.SOLUTION: When forming an isolation region for insulating a through electrode composed of a substrate from the surrounding substrate, the interior of the through hole is filled with an oxide and a part of the substrate left between through holes is insulated by forming a plurality of through-holes in an isolation region formation region and performing thermal oxidization. Furthermore, an extension part is formed at the end of the through hole, and a part of the substrate left between the through holes is surely insulated.SELECTED DRAWING: Figure 3

Description

本発明は、貫通電極を備えた電子デバイスの製造方法に関する。   The present invention relates to a method for manufacturing an electronic device including a through electrode.

近年、電子機器の小型化が進み、搭載される電子デバイスについても小型化、薄型化が望まれている。電子デバイスを小型化する一つの方法として、シリコン基板を貫通するTSV(Through Silicon Via)と呼ばれる貫通電極によって電子デバイスの電気的な接続を形成する方法が提案されている。   In recent years, electronic devices have been downsized, and electronic devices to be mounted are also desired to be downsized and thinned. As one method for reducing the size of an electronic device, a method of forming an electrical connection of an electronic device by a through electrode called TSV (Through Silicon Via) that penetrates a silicon substrate has been proposed.

従来の貫通電極について説明する。図5は従来の貫通電極の断面図で、基板21を貫通するように形成された貫通孔22の内壁面は絶縁膜23により被覆され、基板21と絶縁分離されている。貫通孔22内には、メッキ法等を用いて形成された銅などの金属24が埋め込まれており、この金属24が貫通電極となり表面側電極25と裏面側電極26とが接続する構造となっている。このような貫通電極は、貫通孔22内に金属24を充填する必要があるため、貫通孔の径を小さくしたアスペクト比の大きな貫通電極を形成することは難しく、電子デバイスの小型化には限界があった。   A conventional through electrode will be described. FIG. 5 is a cross-sectional view of a conventional through electrode. An inner wall surface of a through hole 22 formed so as to penetrate the substrate 21 is covered with an insulating film 23 and insulated from the substrate 21. A metal 24 such as copper formed using a plating method or the like is embedded in the through hole 22, and the metal 24 serves as a through electrode to connect the front surface side electrode 25 and the back surface side electrode 26. ing. Since such a through electrode needs to be filled with the metal 24 in the through hole 22, it is difficult to form a through electrode having a small aspect ratio and a large aspect ratio. was there.

そこで、アスペクト比の大きな貫通電極を形成する別の例について説明する。この種の貫通電極は、次のように形成される。まず、シリコンからなる基板21を用意し、貫通電極形成予定領域を取り囲むように、例えば平面形状が円形のトレンチ溝27を形成する(図6)。このトレンチ溝27は、シリコン基板21を貫通しておらず、トレンチ溝27の下部に残るシリコン基板21により、トレンチ溝27で囲まれたシリコン基板21aを支持する構造となっている。   Therefore, another example of forming a through electrode having a large aspect ratio will be described. This type of through electrode is formed as follows. First, a substrate 21 made of silicon is prepared, and a trench groove 27 having a circular planar shape, for example, is formed so as to surround a through electrode formation scheduled region (FIG. 6). The trench groove 27 has a structure in which the silicon substrate 21 a surrounded by the trench groove 27 is supported by the silicon substrate 21 that does not penetrate the silicon substrate 21 and remains below the trench groove 27.

その後、このトレンチ溝27を絶縁材料で充填するため、熱酸化を行う。この熱酸化によりトレンチ溝27の内壁面に露出するシリコンが酸化され、トレンチ溝27は絶縁材料のシリコン酸化膜28で充填される(図7)。トレンチ溝21で囲まれたシリコン基板の一部は、このシリコン酸化膜28によっても支持される構造となる。トレンチ溝27内に充填される絶縁材料は、シリコン酸化膜に加えて、例えばCVD法により形成する絶縁材料であっても良い。   Thereafter, thermal oxidation is performed to fill the trench groove 27 with an insulating material. The silicon exposed to the inner wall surface of the trench groove 27 is oxidized by this thermal oxidation, and the trench groove 27 is filled with a silicon oxide film 28 of an insulating material (FIG. 7). A part of the silicon substrate surrounded by the trench groove 21 has a structure supported also by the silicon oxide film 28. The insulating material filled in the trench groove 27 may be an insulating material formed by, for example, a CVD method in addition to the silicon oxide film.

シリコン基板21の裏面側を研磨し、トレンチ溝27の裏面側を露出させる。シリコン酸化膜28で囲まれたシリコン基板21aの表面側および裏面側に図示しない表面側電極と裏面側電極を形成することで貫通電極として利用することが可能となる(図8)(特許文献2参照)。このような構造の貫通電極は、貫通孔に金属を充填する必要がないので、アスペクト比の大きな貫通電極を形成することが可能となる。   The back surface side of the silicon substrate 21 is polished to expose the back surface side of the trench groove 27. By forming a front side electrode and a back side electrode (not shown) on the front side and the back side of the silicon substrate 21a surrounded by the silicon oxide film 28, it can be used as a through electrode (FIG. 8) (Patent Document 2). reference). Since the through electrode having such a structure does not need to fill the through hole with a metal, a through electrode having a large aspect ratio can be formed.

特開2011−119750号公報JP 2011-119750 A 特許第4944605号公報Japanese Patent No. 4944605

以上説明したように、シリコン基板の一部を貫通電極として利用することでアスペクト比の大きな貫通電極を形成することが可能となる。しかしながら、このように深いトレンチ溝27を酸化する場合、表面側はシリコン酸化膜28が十分に充填されているものの、トレンチ溝27の底面付近はシリコン酸化膜28の厚さが薄くなり空洞が残ってしまう。このような状態で、シリコン基板21の裏面側を研磨すると、分離されたシリコン基板21aに応力が加わり、シリコン酸化膜28が破損し、絶縁不良が発生するという問題があった。また、研磨工程を必要とするため、製造コストの増加につながってしまうという問題もあった。   As described above, a through electrode having a large aspect ratio can be formed by using a part of the silicon substrate as the through electrode. However, when the deep trench groove 27 is oxidized in this way, the silicon oxide film 28 is sufficiently filled on the front surface side, but the thickness of the silicon oxide film 28 is thin and the cavity remains in the vicinity of the bottom surface of the trench groove 27. End up. When the back side of the silicon substrate 21 is polished in such a state, there is a problem that stress is applied to the separated silicon substrate 21a, the silicon oxide film 28 is damaged, and an insulation failure occurs. In addition, since a polishing step is required, there is a problem that the manufacturing cost is increased.

本発明は、上記問題点を解消し、簡便に貫通電極を製造することができる製造方法を提供することを目的とする。   An object of this invention is to provide the manufacturing method which can eliminate the said problem and can manufacture a penetration electrode simply.

上記目的を達成するため、本願請求項1に係る発明は、基板を貫通する分離領域を備え、該分離領域で囲まれた前記基板の一部が貫通電極となる電子デバイスの製造方法において、前記基板を用意する工程と、前記分離領域形成予定領域に、前記基板の一部を残して分離した複数の貫通孔を形成する工程と、少なくとも前記貫通孔内および隣接する前記貫通孔間に残る前記基板の一部を熱酸化して、前記基板の酸化物を含む絶縁材料により前記貫通孔を充填するとともに、前記貫通孔間に残る基板の一部を酸化し、前記分離領域を形成する工程と、を含むことを特徴とする。   In order to achieve the above object, an invention according to claim 1 of the present application includes a separation region penetrating a substrate, wherein the part of the substrate surrounded by the separation region is a through electrode. A step of preparing a substrate, a step of forming a plurality of through holes separated by leaving a part of the substrate in the separation region formation scheduled region, and at least the inside of the through hole and between the adjacent through holes A step of thermally oxidizing a part of the substrate to fill the through hole with an insulating material containing an oxide of the substrate and oxidizing a part of the substrate remaining between the through holes to form the isolation region; , Including.

本願請求項2に係る発明は、請求項1記載の電子デバイスの製造方法において、前記貫通孔の端部に延長部を付加し、該延長部を隣接する貫通孔あるいは隣接する貫通孔の延長部に対向配置するように、前記複数の貫通孔を形成する工程と、前記延長部と前記隣接する貫通孔あるいは隣接する貫通孔の延長部との間に残る前記基板の一部を熱酸化し、前記分離領域を形成する工程と、を含むことを特徴とする。   The invention according to claim 2 of the present application is the method for manufacturing an electronic device according to claim 1, wherein an extension is added to an end of the through hole, and the extension is adjacent to the through hole or an extension of the adjacent through hole. A portion of the substrate remaining between the step of forming the plurality of through-holes and the extension and the adjacent through-hole or the extension of the adjacent through-hole is thermally oxidized so as to be opposed to Forming the isolation region.

本願請求項3に係る発明は、請求項1または2いずれか記載の電子デバイスの製造方法において、前記基板はシリコンからなることを特徴とする。   The invention according to claim 3 of the present application is the method of manufacturing an electronic device according to claim 1 or 2, wherein the substrate is made of silicon.

本発明の製造方法によれば、分離領域を形成する際、基板の一部を残して分離した複数の貫通孔を形成することで、トレンチ溝ではなく貫通孔としても、貫通電極となる基板を支持することが可能となる。そのため、基板の表面側と裏面側の両方の開口から貫通孔内を熱酸化することができ、基板の表面側と裏面側から熱酸化が進み、貫通孔内を厚い酸化物で充填できる。その結果、貫通電極と周囲の基板との間に十分な絶縁性を確保することが可能となる。   According to the manufacturing method of the present invention, when forming the isolation region, by forming a plurality of through holes separated by leaving a part of the substrate, a substrate that becomes a through electrode can be formed as a through hole instead of a trench groove. It becomes possible to support. For this reason, the inside of the through hole can be thermally oxidized from both the opening on the front side and the back side of the substrate, the thermal oxidation proceeds from the front side and the back side of the substrate, and the inside of the through hole can be filled with a thick oxide. As a result, sufficient insulation can be ensured between the through electrode and the surrounding substrate.

また、隣接する貫通孔の間に残る基板は、通常の熱酸化による簡便に絶縁化でき、貫通電極と周囲の基板との間の絶縁性が十分に確保できる。   In addition, the substrate remaining between adjacent through holes can be easily insulated by ordinary thermal oxidation, and sufficient insulation can be ensured between the through electrode and the surrounding substrate.

また本発明の製造方法によれば、貫通孔の端部に延長部を備える構造とし、隣接する貫通孔あるいは隣接する貫通孔の延長部に対向するように配置して熱酸化することで、この間の基板を確実に酸化物に変えることができ、貫通電極と周囲の基板との間の分離領域を確実に形成することができる。   Further, according to the manufacturing method of the present invention, the structure is provided with an extension at the end of the through hole, and is disposed so as to oppose the adjacent through hole or the extension of the adjacent through hole. The substrate can be reliably changed to an oxide, and a separation region between the through electrode and the surrounding substrate can be reliably formed.

本発明の第1の実施例の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the 1st Example of this invention. 本発明の第1の実施例の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the 1st Example of this invention. 本発明の第1の実施例の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the 1st Example of this invention. 本発明の第2の実施例の製造方法の説明図である。It is explanatory drawing of the manufacturing method of the 2nd Example of this invention. 従来の貫通電極の説明図である。It is explanatory drawing of the conventional penetration electrode. 従来の別の貫通電極の製造方法の説明図である。It is explanatory drawing of the manufacturing method of another conventional penetration electrode. 従来の別の貫通電極の製造方法の説明図である。It is explanatory drawing of the manufacturing method of another conventional penetration electrode. 従来の別の貫通電極の製造方法の説明図である。It is explanatory drawing of the manufacturing method of another conventional penetration electrode.

本発明に係る電子デバイスの製造方法は、基板からなる貫通電極を周囲の基板から絶縁する分離領域を形成する際、分離領域形成予定領域に複数の貫通孔を形成して熱酸化することで、貫通孔の内部を酸化物で充填するとともに、貫通電極間に残した基板の一部を絶縁化することを特徴とする。さらに貫通孔の端部に延長部を形成し、確実に貫通電極間に残した基板の一部絶縁化することを特徴としている。以下、実施例について詳細に説明する。   In the method for manufacturing an electronic device according to the present invention, when forming a separation region that insulates a through electrode made of a substrate from a surrounding substrate, a plurality of through holes are formed in the separation region formation scheduled region and thermally oxidized, The inside of the through hole is filled with an oxide, and a part of the substrate left between the through electrodes is insulated. Furthermore, an extended portion is formed at the end of the through hole, and a part of the substrate left between the through electrodes is surely insulated. Hereinafter, examples will be described in detail.

本発明の第1の実施例について説明する。まず、厚さ420μm、抵抗率0.001〜0.01Ω・cmの低抵抗単結晶シリコンからなる基板1を用意する。表面に図示しない分離領域形成予定領域を開口するエッチングマスクを形成し、基板1を深くエッチングし分離領域となる貫通孔2を形成する(図1)。   A first embodiment of the present invention will be described. First, a substrate 1 made of low-resistance single crystal silicon having a thickness of 420 μm and a resistivity of 0.001 to 0.01 Ω · cm is prepared. An etching mask is formed on the surface to open a separation region formation scheduled region (not shown), and the substrate 1 is deeply etched to form a through hole 2 serving as a separation region (FIG. 1).

ここで本発明では、図2に模式的に示すように、分離領域形成予定領域を分割するように複数の貫通孔2を形成する。図2において、(a)は分離領域が円形で、貫通孔2が4個に分離されている場合、(b)は分離領域が長方形で、貫通孔2が4個に分離されている場合を示している。貫通孔2が分離されているため、貫通孔2で囲まれた領域の基板1aは、貫通孔2の外側の基板1と4か所の基板1bを介して一体となり支持されており、図1の図面下方へ基板1aが離脱しない構造となっている。   Here, in the present invention, as schematically shown in FIG. 2, the plurality of through holes 2 are formed so as to divide the separation region formation scheduled region. 2A shows a case where the separation region is circular and the through-hole 2 is separated into four pieces, and FIG. 2B shows a case where the separation region is rectangular and the through-hole 2 is separated into four pieces. Show. Since the through hole 2 is separated, the substrate 1a in the region surrounded by the through hole 2 is integrally supported via the substrate 1 outside the through hole 2 and the four substrates 1b. The structure is such that the substrate 1a does not leave below the figure.

その後、従来例で説明したように、貫通孔2の表面側および裏面側が開口した状態で熱酸化を行う。この熱酸化により貫通孔2内はシリコン酸化膜で充填される。また本発明では、貫通孔2と隣接する別の貫通孔2との間に残る基板1bも同時に酸化され、連続する分離領域3が形成される。この分離領域3で囲まれた基板が貫通電極となる(図3)。なお、貫通孔2内に充填する絶縁材料は、基板の酸化物のみである必要はなく、例えばCVD法により別の絶縁材料を埋め込む工程を追加しても何ら問題はない。   Thereafter, as described in the conventional example, thermal oxidation is performed in a state where the front surface side and the back surface side of the through hole 2 are opened. By this thermal oxidation, the inside of the through hole 2 is filled with a silicon oxide film. In the present invention, the substrate 1b remaining between the through hole 2 and another adjacent through hole 2 is also oxidized at the same time to form a continuous separation region 3. The substrate surrounded by the separation region 3 becomes a through electrode (FIG. 3). Note that the insulating material filled in the through hole 2 need not be only the oxide of the substrate, and there is no problem even if a step of embedding another insulating material by, for example, the CVD method is added.

貫通電極には、通常の電子デバイスの製造工程に従い、図示しない表面側電極と裏面側電極を形成することで、所望の電子デバイスを形成することができる。   In the through electrode, a desired electronic device can be formed by forming a front-side electrode and a back-side electrode (not shown) according to a normal manufacturing process of the electronic device.

以上説明したように本発明は、基板1bを残し貫通孔2を形成し、その後、熱酸化により連続する分離領域3を形成する方法であるから、基板1の研磨を必要とせず、基板のエッチング工程と、熱酸化工程のみで、先に説明した図8に相当する形状を簡便に形成することが可能となる。   As described above, the present invention is a method in which the through hole 2 is formed while leaving the substrate 1b, and then the continuous separation region 3 is formed by thermal oxidation. Therefore, the substrate 1 is not polished and the substrate is etched. The shape corresponding to FIG. 8 described above can be easily formed by only the process and the thermal oxidation process.

次に、本発明の第2の実施例について説明する。先に説明した第1の実施例では、図3に示すように、隣接する貫通孔2の間に残る基板(図2の基板1b)は、貫通孔2の端部から酸化物の生成が進行し、一体となるためくびれが生じる場合がある。この部分は、基板1の酸化物からなり、貫通孔2の幅より狭い場合でも絶縁性には何ら問題とはならない。しかしながら、酸化物の間に基板の一部が残ってしまうと絶縁性を確保できない。そこで、基板1bの絶縁性を確保するため、隣接する貫通孔2の対向幅を増やす方法を採用することとした。   Next, a second embodiment of the present invention will be described. In the first embodiment described above, as shown in FIG. 3, the generation of oxide proceeds from the end of the through hole 2 in the substrate remaining between the adjacent through holes 2 (substrate 1 b in FIG. 2). However, since it is integrated, there may be a constriction. This portion is made of an oxide of the substrate 1 and does not cause any problem in insulation even when the width is smaller than the width of the through hole 2. However, if a part of the substrate remains between the oxides, insulation cannot be ensured. Therefore, in order to ensure the insulation of the substrate 1b, a method of increasing the opposing width of the adjacent through holes 2 is adopted.

具体的には図4に示すように、貫通孔2の端部に延長部5を形成し、基板1bの熱酸化により形成される酸化物の間に隙間が生じないようにする。延長部5は、図4(a)〜(c)に示すように、貫通孔2の端部それぞれに延長部5を設け、延長部5と隣接する延長部5が対向するように配置する。また図4(d)に示すように、隣接する貫通孔2の一方の貫通孔2の端部のみに延長部5を設け、この延長部5を延長部のない貫通孔2に対向するように配置してもよい。このように構成することで、基板1bの幅(貫通孔2が対向する幅)が広くなり、基板1bを確実に酸化膜で埋めることが可能となる。   Specifically, as shown in FIG. 4, an extension 5 is formed at the end of the through hole 2 so that no gap is formed between oxides formed by thermal oxidation of the substrate 1b. As shown in FIGS. 4A to 4C, the extension portion 5 is provided such that the extension portion 5 is provided at each end of the through hole 2 and the extension portion 5 adjacent to the extension portion 5 is opposed to the extension portion 5. Further, as shown in FIG. 4D, an extension 5 is provided only at the end of one through-hole 2 of the adjacent through-hole 2, and this extension 5 is opposed to the through-hole 2 without the extension. You may arrange. By configuring in this way, the width of the substrate 1b (width through which the through hole 2 faces) is increased, and the substrate 1b can be reliably filled with an oxide film.

以上本発明の実施例について説明したが、本発明は上記実施例に限定されるものではない。たとえば、貫通孔2の配置や数、延長部の形状等は種々変更可能である。また、本発明の貫通電極は、表面に集積回路を備えた基板上に形成される貫通電極に限らず、半導体基板の一部を除去してキャビティ部を形成し、このキャビティ部に別の半導体装置を収容することができる構造の半導体装置の蓋部として用いることも可能である。さらにまた、使用する基板は、シリコンに限定されるものはないが、通常の電子デバイスの製造工程を適用できる点で、シリコンが好ましい。   Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, the arrangement and number of the through holes 2, the shape of the extension, and the like can be variously changed. Further, the through electrode of the present invention is not limited to the through electrode formed on the substrate having the integrated circuit on the surface, but a part of the semiconductor substrate is removed to form a cavity, and another semiconductor is formed in the cavity. It can also be used as a lid of a semiconductor device having a structure that can accommodate the device. Furthermore, the substrate to be used is not limited to silicon, but silicon is preferable in that a normal manufacturing process of an electronic device can be applied.

1:基板、2:貫通孔、3:分離領域、4:貫通電極、5:延長部
21:基板、22:貫通孔、23:絶縁膜、24:金属、25:表面側電極、26:裏面側電極、27:トレンチ溝、28:シリコン酸化膜
1: Substrate, 2: Through hole, 3: Separation region, 4: Through electrode, 5: Extension part 21: Substrate, 22: Through hole, 23: Insulating film, 24: Metal, 25: Front side electrode, 26: Back side Side electrode, 27: trench groove, 28: silicon oxide film

Claims (3)

基板を貫通する分離領域を備え、該分離領域で囲まれた前記基板の一部が貫通電極となる電子デバイスの製造方法において、
前記基板を用意する工程と、
前記分離領域形成予定領域に、前記基板の一部を残して分離した複数の貫通孔を形成する工程と、
少なくとも前記貫通孔内および隣接する前記貫通孔間に残る前記基板の一部を熱酸化して、前記基板の酸化物を含む絶縁材料により前記貫通孔を充填するとともに、前記貫通孔間に残る基板の一部を酸化し、前記分離領域を形成する工程と、を含むことを特徴とする電子デバイスの製造方法。
In a method for manufacturing an electronic device comprising a separation region penetrating a substrate, wherein a part of the substrate surrounded by the separation region is a through electrode,
Preparing the substrate;
Forming a plurality of through-holes separated by leaving a part of the substrate in the separation region formation planned region;
At least a part of the substrate remaining in the through hole and between the adjacent through holes is thermally oxidized to fill the through hole with an insulating material containing an oxide of the substrate and to remain between the through holes. And a step of forming a part of the substrate to form the isolation region.
請求項1記載の電子デバイスの製造方法において、
前記貫通孔の端部に延長部を付加し、該延長部を隣接する貫通孔あるいは隣接する貫通孔の延長部に対向配置するように、前記複数の貫通孔を形成する工程と、
前記延長部と前記隣接する貫通孔あるいは隣接する貫通孔の延長部との間に残る前記基板の一部を熱酸化し、前記分離領域を形成する工程と、を含むことを特徴とする電子デバイスの製造方法。
In the manufacturing method of the electronic device of Claim 1,
Adding an extension to the end of the through-hole, and forming the plurality of through-holes so as to face the adjacent through-hole or the extension of the adjacent through-hole; and
And a step of thermally oxidizing a part of the substrate remaining between the extension and the adjacent through hole or an extension of the adjacent through hole to form the isolation region. Manufacturing method.
請求項1または2いずれか記載の電子デバイスの製造方法において、
前記基板はシリコンからなることを特徴とする電子デバイスの製造方法。
In the manufacturing method of the electronic device in any one of Claim 1 or 2,
The method of manufacturing an electronic device, wherein the substrate is made of silicon.
JP2017028591A 2017-02-20 2017-02-20 Method of manufacturing electronic device Pending JP2018137255A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317474A (en) * 1997-04-03 1999-11-16 Yamatake Corp Circuit boar and manufacture thereof
JP2010123599A (en) * 2008-11-17 2010-06-03 Alps Electric Co Ltd Method for manufacturing silicon through-electrode substrate and silicon through-electrode substrate
JP2011176100A (en) * 2010-02-24 2011-09-08 Toyota Motor Corp Through electrode, microstructure and methods for manufacturing them
WO2017004063A1 (en) * 2015-07-02 2017-01-05 Kionix, Inc. Electronic systems with through-substrate interconnects and mems device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317474A (en) * 1997-04-03 1999-11-16 Yamatake Corp Circuit boar and manufacture thereof
JP2010123599A (en) * 2008-11-17 2010-06-03 Alps Electric Co Ltd Method for manufacturing silicon through-electrode substrate and silicon through-electrode substrate
JP2011176100A (en) * 2010-02-24 2011-09-08 Toyota Motor Corp Through electrode, microstructure and methods for manufacturing them
WO2017004063A1 (en) * 2015-07-02 2017-01-05 Kionix, Inc. Electronic systems with through-substrate interconnects and mems device

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