JP2018133507A - Schottky barrier diode, manufacturing method therefor, manufacturing method for semiconductor device, and power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a high efficiency percentage of a SiC-SBD chip.SOLUTION: The schottky barrier diode includes: a first conductivity type silicon carbide substrate; a first conductivity type drift layer formed on a top surface of the silicon carbide substrate; a cathode electrode formed on an undersurface of the silicon carbide substrate; a schottky electrode schottky-connected with a drift layer; and an anode electrode in electrical contact with the schottky electrode. The schottky electrode and the anode electrode are formed into a pair, divided into a plurality of segments relative to one cathode electrode, and each of the segments is electrically isolated.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a technique for improving a chip yield rate of a Schottky barrier diode.

  BACKGROUND ART A vertical Schottky barrier diode (SBD) in which a current flows in the thickness direction of a semiconductor layer is used for various applications because it has a high switching speed and can achieve a high breakdown voltage. In addition, in order to enable higher breakdown voltage and lower loss, silicon carbide is being adopted as a material constituting the SBD. Silicon carbide has a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the SBD, it is possible to achieve a higher breakdown voltage of the SBD, a reduction in on-resistance, and the like (for example, Patent Document 1).

JP 2017-11060 A

  In the conventional SiC-SBD chip, abnormalities may occur in the Schottky junction between the anode electrode and the semiconductor layer due to crystal defects in the substrate or the epitaxial layer (drift layer). When an abnormality occurs in the Schottky junction, the reverse direction characteristic, that is, the leakage current characteristic becomes poor, the yield rate of the chip decreases, and the chip cost increases. In view of the above-described problems, an object of the present invention is to improve the yield rate of SiC-SBD chips.

  A Schottky barrier diode according to the present invention includes a first conductivity type silicon carbide substrate, a first conductivity type drift layer formed on an upper surface of the silicon carbide substrate, and a cathode electrode formed on the lower surface of the silicon carbide substrate. A Schottky electrode that is in Schottky junction with the drift layer, and an anode electrode that is in electrical contact with the Schottky electrode. Divided into segments, each segment is electrically separated.

  In the Schottky barrier diode according to the present invention, the Schottky electrode and the anode electrode are paired and divided into a plurality of segments for one cathode electrode, and each segment is electrically separated. With this configuration, the leakage current characteristics can be measured for each segment, so if an abnormality occurs in the Schottky junction in any segment, the segment that has an abnormality in the Schottky junction from the leakage current characteristics for each segment And a segment having no abnormality can be identified. Therefore, by assembling a semiconductor device using only segments having no abnormality, it is possible to improve the yield rate of Schottky barrier diode chips.

It is a top view of the SiC-SBD chip concerning the premise technique of the present invention. It is AA sectional drawing of FIG. 3 is a plan view of the SiC-SBD chip according to the first embodiment. FIG. It is BB sectional drawing of FIG. 7 is a cross-sectional view showing a trench formation step of the SiC-SBD chip according to the first embodiment. FIG. It is a top view of the SiC-SBD chip concerning Embodiment 1 in which abnormality occurred in the Schottky junction of the segment. It is a figure which shows the leakage current characteristic for every segment of the SiC-SBD chip which concerns on Embodiment 1. FIG. It is a figure which shows the upper side figure of the SiC-SBD chip | tip with which the segment of good judgment was wire-bonded. 6 is a plan view of an SiC-SBD chip according to a second embodiment. FIG. It is CC sectional drawing of FIG. 6 is a plan view of an SiC-SBD chip according to a third embodiment. FIG. It is DD sectional drawing of FIG. 6 is a cross-sectional view of a SiC-SBD chip according to a fourth embodiment. FIG. It is a block diagram which shows the structure of the power conversion system to which the power converter device concerning this Embodiment is applied.

  In this specification, the semiconductor conductivity type will be described assuming that the first conductivity type is N-type and the second conductivity type is P-type. However, this is an example, and the conductivity type may be reversed. That is, the first conductivity type may be the P type and the second conductivity type may be the N type.

<A. Prerequisite technology>
FIG. 1 is a plan view of a SiC-SBD chip 100 according to the prerequisite technology of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA of FIG.

As shown in FIG. 2, the SiC-SBD chip 100 includes an N ⁺ type silicon carbide (SiC) substrate 1, an N ⁻ type drift layer 2, a Schottky electrode 3, an anode electrode 4, and a cathode electrode 5. Yes.

  Silicon carbide substrate 1 is provided to ensure the mechanical strength of the device. Drift layer 2 is provided on the upper surface of silicon carbide substrate 1 to ensure a breakdown voltage. Schottky electrode 3 is provided on the upper surface of drift layer 2 and forms a Schottky junction with drift layer 2. The material of the Schottky electrode 3 is, for example, Ti. The anode electrode 4 is formed on the drift layer 2 so as to cover the Schottky electrode 3. The material of the anode electrode 4 is, for example, Al or AlSi. Cathode electrode 5 is provided on the lower surface of silicon carbide substrate 1 and is in ohmic contact with silicon carbide substrate 1.

  As shown in FIG. 1, in the SiC-SBD chip 100, a region outside the anode electrode 4 is a termination junction region 6.

  If there is a crystal defect in silicon carbide substrate 1 or drift layer 2, an abnormality may occur in the Schottky junction between anode electrode 4 and drift layer 2 due to the crystal defect. When an abnormality occurs in the Schottky junction, the reverse direction characteristic, that is, the leakage current characteristic becomes poor, and there is a problem that the yield rate of the SiC-SBD chip 100 is reduced and the chip cost is increased. Therefore, the present invention has been devised as follows.

<B. Embodiment 1>
FIG. 3 is a plan view of the SiC-SBD chip 101 which is the Schottky barrier diode according to the first embodiment, and FIG. 4 is a cross-sectional view taken along the line BB in FIG. As shown in FIG. 3, in the SiC-SBD chip 101, the Schottky electrode 3 and the anode electrode 4 are divided into nine segments 41 to 49 as a pair. Each segment 41-49 consists of the Schottky electrode 3 and the anode electrode 4, and is arrange | positioned spaced apart.

  As shown in FIG. 4, a trench 7 is formed in the drift layer 2 below the segments 41 to 49 from the upper surface of the drift layer 2 to a predetermined depth. In other words, the Schottky electrode 3 and the anode electrode 4 are divided into segments 41 to 49 along the trench 7. Although nine segments 41 to 49 are shown in FIG. 3, the number of divisions of the Schottky electrode 3 and the anode electrode 4 is not limited to this.

  The configuration of the SiC-SBD chip 101 other than that described above is the same as that of the SiC-SBD chip 100 according to the base technology.

  When the leakage current characteristic of the SiC-SBD chip 101 is inspected, a voltage is applied between the cathode electrode 5 and the anode electrode 4 (hereinafter simply referred to as “between the cathode and the anode”). At this time, the depletion layer spreads from the Schottky electrode 3 to the drift layer 2, but the spread of the depletion layer in the lateral direction of the drift layer 2 is suppressed by the trench 7. Here, the lateral direction of the drift layer 2 refers to a direction perpendicular to the thickness direction of the drift layer 2. For example, in FIG. 4, the depletion layer generated in the drift layer 2 below the segment 47 does not extend to the drift layer 2 below the segment 48. Accordingly, the segments 41 to 49 are electrically separated from each other.

  Thus, in the SiC-SBD chip 101, the cathode electrode 5 is not divided, and the anode electrode 4 and the Schottky electrode 3 are electrically separated into a plurality of segments 41 to 49. That is, SiC-SBD chip 101 is formed on the first conductivity type n-type silicon carbide substrate 1, n-type drift layer 2 formed on the upper surface of silicon carbide substrate 1, and lower surface of silicon carbide substrate 1. Cathode electrode 5, Schottky electrode 3 in Schottky junction with drift layer 2, and anode electrode 4 in electrical contact with Schottky electrode 3, and Schottky electrode 3 and anode electrode 4 are a pair. Thus, one cathode electrode 5 is divided into a plurality of segments 41 to 49, and the segments 41 to 49 are electrically separated. Therefore, when there is an abnormality in the Schottky junction of the SiC-SBD chip 101, it is possible to detect which segment 41 to 49 has an abnormality in the Schottky junction.

  The depth of the trench 7 is determined from the viewpoint of suppressing the lateral expansion of the depletion layer generated in the drift layer 2 when a voltage is applied between the cathode and the anode. Here, the width of the depletion layer in the drift layer 2 depends on the thickness of the drift layer 2 and the carrier concentration. Therefore, the depth of the trench 7 is set according to the thickness of the drift layer 2 and the carrier concentration. For example, when the rated voltage of the SIC-SBD chip 101 is applied between the cathode and the anode, if the width of the depletion layer is approximately the same as the thickness of the drift layer 2, the depth of the trench 7 is equal to the thickness of the drift layer 2. It is desirable that they are comparable. Further, when the rated voltage of the SiC-SBD chip 101 is applied between the cathode and the anode, if the depletion layer extends beyond the drift layer 2 to the silicon carbide substrate 1, the trench 7 penetrates the drift layer 2 and is carbonized. It is desirable to reach the silicon substrate 1.

  Next, a method for manufacturing the SiC-SBD chip 101 will be described. First, drift layer 2 is epitaxially grown on the upper surface of silicon carbide substrate 1. Then, the Schottky electrode 3 is formed in a place other than the termination junction region 6 on the upper surface of the drift layer 2. Further, the anode electrode 4 is formed on the upper surface of the Schottky electrode 3. Thereafter, by removing predetermined portions of the Schottky electrode 3 and the anode electrode 4 by photolithography, the Schottky electrode 3 and the anode electrode 4 are divided into a plurality of segments 41 to 49 as shown in FIG.

  Next, as shown in FIG. 5, the upper surface of the drift layer 2 is irradiated with laser from between the plurality of segments 41 to 49 to form trenches 7 in the drift layer 2. In this way, the SiC-SBD chip 101 shown in FIG. 4 is obtained. The trench 7 can be formed by etching in addition to the laser processing described above, but the deep trench 7 can be formed in a shorter processing time than etching by the laser processing. Therefore, it becomes possible to electrically separate the segments 41 to 49 stably.

  FIG. 6 shows a top view of the SiC-SBD chip 101 in which an abnormality has occurred in the Schottky junction of the segment 41. In P of the segment 41 shown in FIG. 6, it is assumed that an abnormality due to crystal defects occurs in the Schottky junction. A voltage is applied between the cathode and anode of the SiC-SBD chip 101 in FIG. 6 to determine whether or not the reverse direction characteristics, that is, the leakage current characteristics, of the segments 41 to 49 are good. FIG. 7 shows the leakage current characteristics obtained at this time. In FIG. 7, the solid line graph indicates the leakage current characteristics of the segments 42 to 49, and the alternate long and short dash line graph indicates the leakage current characteristics of the segment 41. From FIG. 7, it can be seen that the leakage current of the segment 41 is larger than the leakage current of the segments 42 to 49. Therefore, it can be seen that the Schottky junction of the segment 41 is abnormal, and the segment 41 is determined to be defective. The segments 42 to 49 are determined to be good.

  FIG. 8 shows a top view of the SiC-SBD chip 101 wire-bonded only to the good-decision segments 42 to 49. In FIG. 8, the bonding wires 8 are connected to the segments 42 to 49, but the bonding wires 8 are not connected to the segments 41. Thereby, the segment 41 with a bad reverse direction characteristic can be electrically opened. In this state, a semiconductor device as a final product such as a power module is assembled.

  As described above, in the method of manufacturing the semiconductor device according to the first embodiment, a voltage is applied between the cathode electrode 5 and the anode electrode 4 of the SiC-SBD 101, and the reverse characteristics are good or bad for each of the segments 41 to 49. And a process for assembling the semiconductor device using only the segments determined to be good. This makes it possible to use a SiC-SBD chip having crystal defects as a good product. Therefore, the non-defective product rate of the SiC-SBD chip is improved, and the cost can be further reduced.

  The structure of the present embodiment may be applied to a JBS (Junction Schottky Barrier) structure using an SiC wafer.

<C. Second Embodiment>
FIG. 9 is a plan view of SiC-SBD 102 according to the second embodiment, and FIG. 10 is a cross-sectional view taken along the line CC in FIG. In the SiC-SBD 102, in addition to the configuration of the SiC-SBD 101, an insulating protective film 9 that is an insulating film is provided between the segments 41 to 49 in the trench 7 and the upper portion of the trench 7, and the other configurations are as follows. It is the same as SiC-SBD101.

  The material of the insulating protective film 9 is, for example, polyimide or polyimide amide. The insulating protective film 9 stabilizes the electric field strength of each divided region of the Schottky electrode 3 and the anode electrode 4 and more stably electrically separates the divided regions of the Schottky electrode 3 and the anode electrode 4. it can.

<D. Embodiment 3>
FIG. 11 is a top view of the SiC-SBD chip 103 according to the third embodiment, and FIG. 12 is a DD cross-sectional view of FIG. SiC-SBD chip 103 is replaced with trench 7 in SiC-SBD chip 101 of the first embodiment, in drift layer 2 below each segment 41 to 49, P layer 10 which is an impurity region of the second conductivity type. Is embedded. Other configurations of the SiC-SBD chip 103 are the same as those of the SiC-SBD chip 101.

  The P layer 10 is formed from the upper surface of the drift layer 2 to a predetermined depth by ion implantation of Al or the like.

  When inspecting the leakage current characteristic of the SiC-SBD chip 103, a voltage is applied between the cathode and the anode. At this time, the depletion layer spreads from the Schottky electrode 3 to the drift layer 2, but the spread of the depletion layer in the lateral direction of the drift layer 2 is suppressed by the P layer 10. Accordingly, the segments 41 to 49 are electrically separated from each other.

  As described above, when the cathode electrode 5 is not divided and the anode electrode 4 and the Schottky electrode 3 are electrically separated into a plurality of segments 41 to 49, the Schottky junction of the SiC-SBD chip 103 is abnormal. It becomes possible to detect which segment 41 to 49 has an abnormality in the Schottky junction. Further, unlike the first or second embodiment, the processing cost for forming the trench 7 is unnecessary.

  The depth of the P layer 10 is determined from the viewpoint of suppressing the lateral expansion of the depletion layer generated in the drift layer 2 when a voltage is applied between the cathode and the anode. Here, the width of the depletion layer in the drift layer 2 depends on the thickness of the drift layer 2 and the carrier concentration. Therefore, the depth of the P layer 10 is set according to the thickness of the drift layer 2 and the carrier concentration. For example, when the rated voltage of the SiC-SBD chip 103 is applied between the cathode and the anode, the depth of the P layer 10 is the thickness of the drift layer 2 if the width of the depletion layer is approximately the same as the thickness of the drift layer 2. It is desirable to be the same level. Further, when the rated voltage of the SiC-SBD chip 103 is applied between the cathode and the anode, if the depletion layer extends beyond the drift layer 2 to the silicon carbide substrate 1, the P layer 10 is carbonized in addition to the drift layer 2. It is desirable to form also on the silicon substrate 1.

  The structure of the present embodiment may be applied to a JBS structure using a SiC wafer.

<E. Embodiment 4>
A plan view of SiC-SBD 104 according to the fourth embodiment is the same as FIG. FIG. 13 is a cross-sectional view of SiC-SBD 104 corresponding to the BB cross-sectional view of FIG. 3. SiC-SBD 104 has a configuration in which trench 7 is formed in P layer 10 which is the impurity region of the second conductivity type of SiC-SBD 103 according to Embodiment 3, and the other configuration is the same as that of SiC-SBD 103. . In other words, SiC-SBD 104 has a configuration in which a P layer is formed on the inner wall surface of trench 7 of SiC-SBD 101 according to the first embodiment. In FIG. 13, the P layer formed on the inner wall surface of the trench 7 is referred to as a P layer 11.

  After forming SiC-SBD 103 according to the third embodiment, trench 7 is formed in P layer 11 to obtain SiC-SBD 104. As a method of forming the trench 7 in the P layer 11, the laser processing shown in FIG. 5 can be used. Alternatively, after forming SiC-SBD 101 according to the first embodiment, ions such as Al are implanted from the region between segments 41 to 49 to form P layer 11 on the inner wall surface of trench 7, that is, the bottom surface and the side surface. Thereby, SiC-SBD104 is obtained.

  When inspecting the leakage current characteristics of the SiC-SBD 104, a voltage is applied between the cathode and the anode. At this time, the depletion layer spreads from the Schottky electrode 3 to the drift layer 2, but the spread of the depletion layer in the lateral direction of the drift layer 2 is suppressed by both the P layer 11 and the trench 7. Therefore, the SiC-SBD 104 according to the first embodiment that does not have the P layer 11 or the SiC-SBD 103 according to the third embodiment that does not have the trench 7 has a lateral direction of the drift layer 2 in the SiC-SBD 104. The effect of suppressing the spread of the depletion layer is high, and the segments 41 to 49 can be electrically separated more stably.

<F. Embodiment 5>
In the present embodiment, the SiC-SBD chips 101 to 104 according to the above-described first to fourth embodiments are applied to a power conversion device. Although the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as a fifth embodiment.

  FIG. 14 is a block diagram illustrating a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

  The power conversion system illustrated in FIG. 14 includes a power supply 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good. The power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.

  The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 14, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit 203 outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And.

  The load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

  Hereinafter, details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes. Each free-wheeling diode of the main conversion circuit 201 is configured by the semiconductor module 202 corresponding to any of the SiC-SBDs 101 to 104 of the first to fourth embodiments described above. The six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

  The main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. However, the drive circuit may be built in the semiconductor module 202, or a drive circuit may be provided separately from the semiconductor module 202. The structure provided may be sufficient. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When the switching element is kept off, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).

  The control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

  In the power conversion device according to the present embodiment, the SiC-SBDs 101 to 104 according to the first to fourth embodiments are applied as the freewheeling diode of the main conversion circuit 201, so that the costs related to the SiC-SBD are reduced. Can do.

  In the present embodiment, the example in which the present invention is applied to the two-level three-phase inverter has been described. However, the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power converter is used. However, a three-level or multi-level power converter may be used. When power is supplied to a single-phase load, the present invention is applied to a single-phase inverter. You may apply. In addition, when power is supplied to a direct current load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.

  In addition, the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor. For example, the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 silicon carbide substrate, 2 drift layer, 3 Schottky electrode, 4 anode electrode, 5 cathode electrode, 6 termination junction region, 7 trench, 8 bonding wire, 9 insulating protective film, 10, 11 P layer, 41-49 segment, 100 to 104 SiC-SBD chip, 200 power conversion device, 201 main conversion circuit, 202 semiconductor module, 203 control circuit, 300 load.

Claims (9)

A first conductivity type silicon carbide substrate;
A drift layer of a first conductivity type formed on the upper surface of the silicon carbide substrate;
A cathode electrode formed on the lower surface of the silicon carbide substrate;
A Schottky electrode that forms a Schottky junction with the drift layer;
An anode electrode in electrical contact with the Schottky electrode;
With
The Schottky electrode and the anode electrode are paired and divided into a plurality of segments for one cathode electrode,
Each said segment is electrically separated,
Schottky barrier diode. A trench was formed in the drift layer below each of the segments;
The Schottky barrier diode according to claim 1. Further comprising an insulating film formed between the trench and each of the segments;
The Schottky barrier diode according to claim 2. A second conductivity type impurity region formed on the inner wall surface of the trench;
The Schottky barrier diode according to claim 2. An impurity region of a second conductivity type formed in the drift layer below each of the segments;
The Schottky barrier diode according to claim 1. A method for manufacturing a Schottky barrier diode according to any one of claims 2 to 4,
Forming the Schottky electrode on the upper surface of the drift layer;
Forming the anode electrode on the upper surface of the Schottky electrode;
Dividing the Schottky electrode and the anode electrode into a plurality of segments by removing predetermined portions of the Schottky electrode and the anode electrode; and
Irradiating a laser on the upper surface of the drift layer from between each segment to form the trench in the drift layer, and
Manufacturing method of Schottky barrier diode. A method for manufacturing a semiconductor device using the Schottky barrier diode according to any one of claims 1 to 5,
A determination step of applying a voltage between the cathode electrode and the anode electrode of the Schottky barrier diode and determining whether the reverse direction characteristic is good or bad for each segment;
An assembly step of assembling a semiconductor device using only the segments determined to be good in the determination step,
A method for manufacturing a semiconductor device. The assembly process includes
Including a step of wire bonding only to the segments determined to be good in the determination step,
A method for manufacturing a semiconductor device according to claim 7. A main conversion circuit having the Schottky barrier diode according to any one of claims 1 to 5 for converting and outputting input power;
A control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit,
Power conversion device.

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