JP2020088257A - Semiconductor device, manufacturing method of the same, using method of the same, and power conversion device - Google Patents

Abstract

To provide a technique capable of improving a semiconductor device.SOLUTION: The semiconductor device includes: a main electrode; and a plurality of first electrodes for electrically connecting a control circuit for controlling the semiconductor device and the semiconductor device. The first electrodes have a control electrode for controlling the semiconductor device and a second electrode electrically connected to the main electrode.SELECTED DRAWING: Figure 6

Description

The present invention relates to a semiconductor device.

Patent Document 1 describes a technique relating to a semiconductor device.

JP, 2011-199150, A

Improvements are desired for semiconductor devices.

Therefore, the present invention has been made in view of the above points, and an object thereof is to provide a technique capable of improving a semiconductor device.

One aspect of a semiconductor device according to the present invention includes a main electrode, a control circuit for controlling the semiconductor device, and a plurality of first electrodes for electrically connecting the semiconductor device, and the plurality of first electrodes. The electrode has a control electrode for controlling the semiconductor device, and a second electrode electrically connected to the main electrode.

Further, according to one aspect of a method for manufacturing a semiconductor device of the present invention, a main electrode, a control circuit for controlling the semiconductor device, and a plurality of first electrodes for electrically connecting the semiconductor device are formed. A first step and a second step of electrically connecting a second electrode of the plurality of first electrodes other than a control electrode for controlling the semiconductor device to the main electrode.

Moreover, one mode of the method of using the semiconductor device according to the present invention includes first and second steps. The semiconductor device includes a main electrode, a control circuit for controlling the semiconductor device, and a plurality of first electrodes for electrically connecting the semiconductor device. The first step manufactures a device including the semiconductor device in which a second electrode of the plurality of first electrodes other than a control electrode for controlling the semiconductor device is electrically connected to the main electrode. The second step is a step of manufacturing a device including the semiconductor device in which the control circuit and the plurality of first electrodes are electrically connected, and the control circuit.

Further, according to one aspect of a semiconductor device of the present invention, a semiconductor layer having first and second main surfaces, a first main electrode on the first main surface, and a first electrode on the first main surface are provided. A second main electrode on the second main surface, and a current from the second main electrode located below the first main electrode and the first electrode in the semiconductor layer to the first main electrode. And a cell region for flowing.

According to the present invention, the semiconductor device can be improved.

It is a top view which shows an example of the structure of a semiconductor chip. It is a back view which shows an example of the structure of a semiconductor chip. It is a figure which shows an example of the circuit structure of a semiconductor chip. It is a top view which shows an example of the structure of a semiconductor chip. It is a top view which shows an example of the structure of a semiconductor chip. It is a figure for demonstrating an example of the manufacturing method of a semiconductor module. It is a figure for demonstrating an example of the manufacturing method of a semiconductor module. It is a figure for demonstrating an example of the manufacturing method of a semiconductor module. It is a top view which shows an example of the structure of a semiconductor chip. It is a top view which shows an example of the structure of a semiconductor chip. It is a figure which shows an example of the cross-section of a semiconductor chip. It is a figure which shows an example of the cross-section of a semiconductor chip. It is a figure which shows an example of an electric conduction possible area|region of a semiconductor chip, and an electric conduction impossible area. It is a top view which shows an example of the structure of a semiconductor chip. It is a figure which shows an example of the cross-section of a semiconductor chip. It is a figure which shows an example of the cross-section of a semiconductor chip. It is a figure which shows an example of the flow of the electric current in a semiconductor chip. It is a figure which shows an example of the energizable area|region of a semiconductor chip. It is a top view which shows an example of the structure of a semiconductor chip. It is a top view which shows an example of the structure of a semiconductor chip. It is a figure which shows an example of a structure of a power conversion system.

Embodiment 1.
1 and 2 are a top view and a back view showing an example of the structure of the semiconductor chip 1 according to the present embodiment, respectively. The semiconductor chip 1 is, for example, a power semiconductor chip used for controlling power equipment such as automobiles and air conditioners. The semiconductor chip 1 can also be said to be a semiconductor device. Hereinafter, the structure of the semiconductor chip 1 will be described using the first direction DR1 and the second direction DR2 shown in FIGS. The first direction DR1 and the second direction DR2 are directions perpendicular to the thickness direction of the semiconductor chip 1. The first direction DR1 is a direction perpendicular to the second direction DR2. The usage of the semiconductor chip 1 is not limited to the above.

As shown in FIGS. 1 and 2, the semiconductor chip 1 includes a semiconductor layer 14, a first main electrode 2, a second main electrode 9, and electrodes 3 to 6. The electrodes 3 to 6 are electrodes for electrically connecting the control circuit for controlling the semiconductor chip 1 and the semiconductor chip 1. The electrode 3 is a control electrode for controlling the semiconductor chip 1. Each of the first main electrode 2, the second main electrode 9 and the electrodes 3 to 6 may be referred to as an electrode pad. In the present embodiment and the first and second embodiments described later, the term “control circuit” simply means a control circuit that controls the semiconductor chip 1.

The semiconductor layer 14 is composed of a plurality of layers and has a first main surface 14a on the upper surface side and a second main surface 14b on the back surface side. The first main electrode 2 and the electrodes 3 to 6 are located on the first main surface 14a. The second main electrode 9 is located on the second main surface 14b. The plurality of electrodes 3 to 6 are arranged in a line, for example, along the first direction DR1. The plurality of electrodes 3 to 6 are located on the peripheral end portion of the first main surface 14a. Specifically, the plurality of electrodes 3 to 6 are located on one end of both ends in the second direction DR2 with respect to the first main surface 14a. Each of the plurality of electrodes 3 to 6 is aligned with the first main electrode 2 in the second direction DR2. The second main electrode 9 is located on the second main surface 14b so as to occupy most of the second main surface 14b. The second main electrode 9 is located on a portion of the second main surface 14b other than the peripheral end portion. Each of the first main electrode 2 and the electrodes 3 to 6 faces the second main electrode 9 via the semiconductor layer 14.

FIG. 3 is a diagram showing an example of a circuit configuration of the semiconductor chip 1. As shown in FIG. 3, the circuit configuration of the semiconductor chip 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor) 110 as a main circuit of the semiconductor chip 1 and a current detection for detecting a main current flowing through the semiconductor chip 1. IGBT 111 and a temperature detection diode 112 for detecting the temperature of the semiconductor chip 1. The gate 103 and collector 109 of the IGBT 110 are connected to the gate and collector of the current detection IGBT 111, respectively.

In this example, the first main electrode 2 and the second main electrode 9 are electrodes that function as the emitter 102 and the collector 109 of the IGBT 110, respectively. The electrode 3 is an electrode that functions as the gate 103 of the IGBT 110. Since the IGBT 110 can be controlled by controlling the potential of the gate 103, it can be said that the electrode 3 is a control electrode for controlling the IGBT 110. The electrode 4 is an electrode that functions as an emitter of the current detection IGBT 111. The electrodes 5 and 6 are electrodes that respectively function as an anode and a cathode of the temperature detecting diode 112.

Hereinafter, the first main electrode 2 and the second main electrode 9 may be referred to as the emitter electrode 2 and the collector electrode 9, respectively. Further, the electrode 3 may be referred to as the gate electrode 3.

The control circuit for controlling the semiconductor chip 1 having the above-described configuration gives a control signal to the gate electrode 3 to cause the semiconductor chip 1 to perform a switching operation, for example. Thereby, the main current flowing through the semiconductor chip 1, that is, the main current flowing through the IGBT 110 is controlled by the control circuit. The main current flows in the thickness direction of the semiconductor chip 1. Specifically, the main current flows from the collector electrode 9 on the back surface side to the emitter electrode 2 on the upper surface side.

Further, the control circuit detects the main current flowing through the semiconductor chip 1 based on the current flowing through the electrode 4 that functions as the emitter of the current detecting IGBT 111. Then, when the detected main current is equal to or higher than the threshold value, the control circuit gives a control signal to the gate electrode 3 to forcibly turn off the semiconductor chip 1 (in other words, the IGBT 110). Thereby, the semiconductor chip 1 can be protected from overcurrent.

Further, the control circuit detects the forward voltage of the temperature detecting diode 112 by using the electrodes 5 and 6 which function as the anode and the cathode of the temperature detecting diode 112, respectively. Then, the control circuit detects the temperature of the semiconductor chip 1 based on the detected forward voltage. When the detected temperature is equal to or higher than the threshold value, the control circuit gives a control signal to the gate electrode 3 to forcibly turn off the semiconductor chip 1 (in other words, the IGBT 110). Thereby, the semiconductor chip 1 can be protected from overheating.

The arrangement of the electrodes 3 to 6 is not limited to the above example. For example, as shown in FIG. 4, the electrodes 3 to 6 may be arranged at the corners of the four corners of the first main surface 14a, respectively. Further, the role of the electrode for connecting the control circuit and the semiconductor chip 1 is not limited to the above example. That is, the electrode for connecting the control circuit and the semiconductor chip 1 may be connected to a circuit different from the above example. The number of electrodes for connecting the control circuit and the semiconductor chip 1 is not limited to the above example, and may be less than four or more than four. FIG. 5 is a top view showing an example of the structure of the semiconductor chip 1 when the number of electrodes for connecting the control circuit and the semiconductor chip 1 is five. In the example of FIG. 5, the semiconductor chip 1 includes electrodes 3 to 7 as electrodes for connecting the control circuit and the semiconductor chip 1. Gate electrode 3 is arranged at the center of first main surface 14a, and emitter electrode 2 is arranged so as to take in gate electrode 3. The electrodes 4 to 7, like the electrodes 3 to 6 shown in FIG. 1, are arranged at the peripheral end of the first main surface 14a.

<Example of usage of semiconductor chip>
Here, a method of manufacturing two types of semiconductor modules using the semiconductor chip 1 will be described. Specifically, of the semiconductor chip 1 and the control circuit, both the method of manufacturing a semiconductor module including only the semiconductor chip 1 (hereinafter, also referred to as a first semiconductor module) and the semiconductor chip 1 and the control circuit are provided. A method of manufacturing a semiconductor module (hereinafter sometimes referred to as a first semiconductor module) provided with the semiconductor module will be described. It can be said that the semiconductor module is also a semiconductor device like the semiconductor chip 1.

<Method of manufacturing first semiconductor module>
6 and 7 are views for explaining an example of a method of manufacturing the first semiconductor module 250. After the semiconductor chip 1 is manufactured, the collector electrode 9 of the semiconductor chip 1 is attached to the die pad portion 200a of the plate-shaped conductive member 200 for the collector electrode by using an alloy such as solder, as shown in FIG. To join. As a result, the semiconductor chip 1 is mounted on the plate-shaped conductive member 200.

In addition, the gate electrode 3 is connected to the plate-shaped conductive member 201 for the gate electrode using the conductive wire 210. Further, the emitter electrode 2 is connected to the plate-shaped conductive member 202 for the emitter electrode using the wire 210. In the example of FIG. 6, the plate-shaped conductive member 202 and the emitter electrode 2 are connected via three wires 210. The plate-shaped conductive members 201 and 202 are also called leads or lead terminals.

Here, the first semiconductor module 250 does not include a control circuit, and therefore, among the plurality of electrodes 3 to 6 for connecting the control circuit and the semiconductor chip 1, electrodes other than the electrode 3 are included. Nos. 4 to 6 are unused. In this example, as shown in FIG. 6, a wire 210 is used to connect each of the unused electrodes 4 to 6 to the plate-shaped conductive member 202 for the emitter electrode. As a result, the electrodes 4 to 6 have the same potential as the emitter electrode 2.

After the structure shown in FIG. 6 is obtained, as shown in FIG. 7, the insulating resin or the insulating resin is used so that the lead portion 200b of the plate-shaped conductive member 200 and the plate-shaped conductive members 201 and 202 are exposed. The package 220 made of gel covers the structure shown in FIG. 6 and the entire semiconductor chip 1 is sealed with the package 220. As a result, the first semiconductor module 250 is completed.

In the first semiconductor module 250, for example, a high voltage is applied to the plate-shaped conductive member 200 for the collector electrode, and the potential of the plate-shaped conductive member 202 for the emitter electrode becomes the reference potential. As shown in FIG. 6, by connecting not only the emitter electrode 2 but also the electrodes 4 to 6 to the plate-shaped conductive member 202 for the emitter electrode, there is an electrode whose potential is not fixed in the electrodes 4 to 6. Will not do.

The gate electrode 3 may be connected to the plate-shaped conductive member 201 by using the DLB (Direct Lead Bonding) technique. Similarly, the emitter electrode 2 and the electrodes 4 to 6 may be connected to the plate-shaped conductive member 202 using DLB technology.

<Method of manufacturing second semiconductor module>
FIG. 8 is a diagram for explaining an example of a method of manufacturing the second semiconductor module 400. The second semiconductor module 400 includes the semiconductor chip 1 and a semiconductor chip 301 on which a control circuit is formed. The semiconductor chip 301 can also be called a control IC (integrated circuit). Electrodes 303 to 306 that are electrically connected to the electrodes 3 to 6 of the semiconductor chip 1 are located on one main surface 301a of the semiconductor chip 301. The arrangement of the electrodes 303 to 306 is not limited to the example shown in FIG.

In the case of manufacturing the second semiconductor module 400, after the semiconductor chips 1 and 301 are manufactured, the semiconductor chip 1 is mounted on the plate-shaped conductive member and the semiconductor chip 301 is mounted on the plate-shaped conductive member in the same manner as above. Will be installed in. Then, as shown in FIG. 8, the electrodes 3 to 6 of the semiconductor chip 1 are connected to the electrodes 303 to 306 of the semiconductor chip 301, respectively, using the wires 210, for example. As a result, the control circuit of the semiconductor chip 301 is electrically connected to the IGBT 110, the current detection IGBT 111, and the temperature detection diode 112 of the semiconductor chip 1. Then, a package is formed so as to cover the semiconductor chips 1 and 301, and the second semiconductor module 400 is completed.

In the second semiconductor module 400, the semiconductor chip 301 detects the temperature of the semiconductor chip 1 and the main current flowing through the semiconductor chip 1, and controls the switching operation of the semiconductor chip 1 based on the detected temperature and main current.

As described above, in the first semiconductor module 250 including the control circuit, among the plurality of electrodes 3 to 6 for connecting the control circuit and the semiconductor chip 1, the unused electrodes 4 to 6 are the first main electrode 2 Is electrically connected to. This stabilizes the potentials of the electrodes 4 to 6.

On the other hand, when the unused electrodes 4 to 6 are connected to the first main electrode 2, and the potentials of the electrodes 4 to 6 are unstable, the electrodes 4 to 6 have electrical characteristics of the semiconductor chip 1. May be affected. For example, a circuit connected to the electrodes 4 to 6 having an unstable potential may function as an antenna and serve as a noise source. In this example, the potential of the current detection IGBT 111 connected to the electrode 4 and the potential of the temperature detection diode 112 connected to the electrodes 5 and 6 are not stable, and these serve as an antenna on the circuit to generate noise. May be a source.

In the first semiconductor module 250 according to this example, since the potentials of the electrodes 4 to 6 are stable, the possibility that the electrodes 4 to 6 affect the electrical characteristics of the semiconductor chip 1 is reduced. For example, it is possible to reduce the possibility that the current detection IGBT 111 and the temperature detection diode 112 serve as a noise transmission source. Therefore, the first semiconductor module 250 can be improved. As a result, like the semiconductor module including the semiconductor chip 1Z not including the electrodes 4 to 6 (that is, the semiconductor chip 1Z not including the current detection IGBT 111 and the temperature detection diode 112) as shown in FIG. , The first semiconductor module 250 can be used.

Further, as in the present example, when the electrodes 4 to 6 are unused, the electrodes 4 to 6 are electrically connected to the first main electrode 2 so that two types of semiconductor chips 1 of the same type are used. The semiconductor module (the first semiconductor module 250 and the second semiconductor module 400) can be manufactured. Therefore, it is possible to shorten the manufacturing period of the semiconductor module, reduce the inventory in the wafer process, reduce the inventory of chips, and the like. As a result, the productivity of the semiconductor module can be improved.

In the above example, all of the electrodes 3 to 6 are electrically connected to the first main electrode 2, but even if only some of the electrodes 3 to 6 are electrically connected to the first main electrode 2. Good. Even in this case, since the possibility that the electrode electrically connected to the first main electrode 2 affects the electrical characteristics of the semiconductor chip 1 is reduced, the semiconductor chip 1 can be improved. it can.

Embodiment 2.
Before describing the structure of the semiconductor chip 1 according to the present embodiment, an example of the cross-sectional structure of the semiconductor chip 1 according to the first embodiment will be described. 11: is a figure which shows an example of the cross-section structure in the arrow AA of the semiconductor chip 1 concerning Embodiment 1 shown in FIG. FIG. 12 is a diagram showing an example of a cross-sectional structure of the semiconductor chip 1 according to the first embodiment shown in FIG. 10 taken along the line BB. In FIG. 10, the distance AA and the distance BB are the same. Although the structure below the electrode 6 is shown in FIG. 12, the structure below the electrodes 3 to 5 is similar to that in FIG.

The above-mentioned semiconductor layer 14 is, for example, an N-type semiconductor substrate. Hereinafter, the semiconductor layer 14 may be referred to as the semiconductor substrate 14. As shown in FIGS. 11 and 12, the emitter electrode 2 is located on the first main surface 14 a of the semiconductor substrate 14. The collector electrode 9 is located on the second main surface 14b of the semiconductor substrate 14. A P-type diffusion region 16 is located in the surface layer portion of the semiconductor substrate 14 on the second main surface 14b side. In the semiconductor substrate 14, the N type diffusion region 15 is located above the diffusion region 16. The diffusion regions 15 and 16 are sometimes referred to as a buffer layer and a collector layer, respectively.

As shown in FIG. 11, below the emitter electrode 2 (more specifically, directly below), the P-type diffusion region 13 is located in the surface layer portion of the semiconductor substrate 14 on the first main surface 14a side. Below the emitter electrode 2 in the semiconductor substrate 14, an N-type region 140 is formed between the diffusion region 13 and the diffusion region 15. The N-type region 140 is a portion of the semiconductor substrate 14 where no diffusion region is formed. The diffusion region 13 is sometimes called a carrier layer.

On the other hand, below the electrodes 3 to 6, as shown in FIG. 12, a P-type diffusion region 24 exists in the semiconductor substrate 14. The diffusion region 24 exists from the first main surface 14a to the N-type region 140 above the diffusion region 15.

Further, below the emitter electrode 2, there are a plurality of structures 17 in the semiconductor substrate 14. Each structure 17 includes a trench type gate structure 21 and a pair of N type diffusion regions 18. The diffusion region 18 is sometimes called an emitter layer. The plurality of structures 17 are arranged along the second direction DR2 while extending along the first direction DR2. The plurality of structures 17 are located below the emitter electrode 2 but not below the electrodes 3-6.

The gate structure 21 of each structure 17 extends along the first direction DR1. The gate structure 21 of each structure 17 extends from the first main surface 14a to the second main surface 14b side in the semiconductor substrate 14. The gate structure 21 includes a gate electrode 19 and a gate insulating film 20. The gate electrode 19 extends from the first main surface 14a toward the second main surface 14b and reaches the inside of the N-type region 140 of the semiconductor substrate 14. The gate electrode 19 of each gate structure 21 is electrically connected to the electrode 3. Thereby, when a voltage is applied to the electrode 3, a voltage is applied to the gate electrode 19 of each gate structure 21.

The gate insulating film 20 covers the side surface and the bottom surface of the gate electrode 19. The upper surface of the gate electrode 19 is exposed from the first main surface 14 a and covered with the insulating film 23. The pair of diffusion regions 18 are located in the surface layer portion on the upper surface side of the diffusion region 13. The pair of diffusion regions 18 extend along the first direction DR1 and sandwich the upper end of the gate structure 21 in the second direction DR2. The upper surface of each diffusion region 18 is exposed from the first main surface 14a. A part of the upper surface of the diffusion region 18 is covered with the insulating film 23. The emitter electrode 2 is located on the first main surface 14a so as to cover the insulating film 23 on each gate electrode 19 while being in contact with each diffusion region 18.

As shown in FIG. 12, the insulating film 23 is formed not only in the region where the emitter electrode 2 is present but also in the region where the electrodes 3 to 6 are present on the first main surface 14a. The electrodes 3 to 6 are located on the first main surface 14a via the insulating film 23.

As shown in FIG. 11, the semiconductor chip 1 includes a plurality of cell regions 22 that are located in the semiconductor substrate 14 and that allow a current to flow from the collector electrode 9 to the emitter electrode 2. It can be said that the cell region 22 has a cell structure. The plurality of cell regions 22 are located below the emitter electrode 2, but not below the electrodes 3 to 6. In other words, the plurality of cell regions 22 are located directly below the emitter electrode 2, but not immediately below the electrodes 3 to 6. Each cell region 22 exists from the first main surface 14a to the second main surface 14b.

Each cell region 22 includes structure 17. In addition, each cell region 22 includes a part of the diffusion region 13, the N-type region 140, the diffusion region 15, and the diffusion region 16. Specifically, the cell region 22 includes a portion below the pair of diffusion regions 18 in the diffusion region 13, a portion below the pair of diffusion regions 18 in the N-type region 140, and a pair of portions in the diffusion region 15. A portion below the diffusion region 18 and a portion below the pair of diffusion regions 18 in the diffusion region 16 are included.

In the semiconductor chip 1 according to the first embodiment having the above-mentioned structure, when a voltage is applied to the gate electrode 19 of each cell region 22 via the electrode 3, the P-type diffusion region 13 in each cell region 22 is applied. The conductivity type of the portion around the gate insulating film 20 is inverted to the N type. Thereby, in each cell region 22, a path through which a current flows is formed from the second main surface 14b to the first main surface 14a. When a high potential is applied to the collector electrode 9 and a low potential is applied to the emitter electrode 2 in this state, a current 50 flows from the collector electrode 9 to the emitter electrode 2 in each cell region 22, as shown in FIG. .. As a result, the main current flows in the thickness direction DR3 of the semiconductor chip 1. On the other hand, in each cell region 22, when the potential of the gate electrode 19 is set to 0 V, the conductivity type of the diffusion region 13 around the gate insulating film 20 remains P-type. Therefore, a path through which a current flows is not formed in the semiconductor substrate 14, and the main current does not flow in the semiconductor chip 1.

In this way, by controlling the voltage applied to the gate electrode 19 of each cell region 22, it is possible to control whether or not to pass the main current to the semiconductor chip 1.

In the semiconductor chip 1 according to the first embodiment, the cell region 22 does not exist below the electrodes 3 to 6 (specifically immediately below). Therefore, in the semiconductor chip 1 according to the first embodiment, the main current can flow in the thickness direction DR3 only in the portion below the emitter electrode 2.

FIG. 13 shows that in the semiconductor substrate 14 included in the semiconductor chip 1 according to the first embodiment, the energizable region 30 in which the main current can flow in the thickness direction and the non-energizable region 31 in which the main current cannot flow in the thickness direction. It is a figure which shows and. In the semiconductor substrate 14 of the first embodiment, the cell region 22 exists below the emitter electrode 2, but the cell region 22 does not exist below the electrodes 3 to 6. Therefore, the lower part of the emitter electrode 2 becomes the energizable region 30, and the lower part of the electrodes 3 to 6 becomes the non-energizable region 31. In the energizable region 30 of the semiconductor substrate 14, the plurality of gate structures 21 extending along the first direction DR1 are formed in stripes so as to be arranged along the second direction DR2. Further, in the energizable region 30, a plurality of diffusion regions 18 extending along the first direction DR1 are formed in stripes so as to be aligned along the second direction DR2.

In the semiconductor chip 1 according to the first embodiment, the main current cannot flow in the portion below the electrodes 3 to 6 in the thickness direction (in other words, the vertical direction). Therefore, in order to flow a larger amount of main current to the semiconductor chip 1, it is necessary to increase the chip area of the semiconductor chip 1.

Therefore, in the present embodiment, a semiconductor chip capable of flowing a larger amount of main current will be described.

FIG. 14 is a top view showing an example of the structure of the semiconductor chip 1A according to this embodiment. FIG. 15 is a diagram showing an example of a cross-sectional structure of the semiconductor chip 1A taken along the line CC of FIG. FIG. 16 is a diagram showing an example of a cross-sectional structure of the semiconductor chip 1A taken along the line DD in FIG. The structure of the semiconductor chip 1A will be described below, focusing on the differences from the semiconductor chip 1 according to the first embodiment.

The semiconductor chip 1A includes an emitter electrode 40 instead of the emitter electrode 2. As shown in FIG. 14, the emitter electrode 40 includes three convex portions 41a, 41b, 41c. The convex portions 41a, 41b, 41c are located between the electrodes 3 and 4, between the electrodes 4 and 5, and between the electrodes 5 and 6, respectively. As shown in FIG. 15, the semiconductor chip 1A includes an insulating film 41 for insulating the electrodes 3 to 6 and the emitter electrode 6.

As shown in FIGS. 15 and 16, the structure below the emitter electrode 40 of the semiconductor chip 1A is the same as the structure below the emitter electrode 2 of the semiconductor chip 1 according to the first embodiment. In the semiconductor chip 1A, the cell region 22 is also formed below the convex portions 41a, 41b, 41c of the emitter electrode 40. 16 shows the structure below the convex portion 41a, the structure below the convex portions 41b and 41c is the same as that in FIG.

The structure below the electrodes 3 to 6 in the semiconductor chip 1A is different from that in the first embodiment. As shown in FIG. 15, the structure below the electrodes 3 to 6 is similar to the structure below the emitter electrode 40. Therefore, in the semiconductor chip 1A, the cell region 22 also exists below the electrodes 3 to 6. Although the structure below the electrode 3 is shown in FIG. 15, the structure below the electrodes 4 to 6 is similar to that in FIG.

Below each of the electrodes 3 to 6, for example, a plurality of cell regions 22 exist. As shown in FIG. 15, below the electrode 3, the entire upper surface of the diffusion region 18 of the cell region 22 is covered with the insulating film 23. As a result, the electrode 3 does not come into contact with the diffusion region 18 (emitter layer). Similarly, below the electrodes 4 to 6, the entire upper surface of the diffusion region 18 of the cell region 22 is covered with the insulating film 23. As a result, the electrodes 4 to 6 do not come into contact with the diffusion region 18.

In the semiconductor chip 1A, below the emitter electrode 40 and the electrodes 3 to 6, a plurality of cell regions 22 extending along the first direction DR1 are formed in stripes so as to be aligned along the second direction DR2. There is. Therefore, when focusing on one cell region 22 below the electrode 3, the cell region 22 passes from below the electrode 3 to below the projections 41 a, 41 b, and 41 c of the emitter electrode 40 and below the electrode 6. Exist continuously until.

In the semiconductor chip 1A having the above structure, below the emitter electrode 40, a current 50 flows from the collector electrode 9 to the emitter electrode 40 in the thickness direction DR3, as in the first embodiment (see FIG. 15).

On the other hand, below each of the electrodes 3 to 6, the current flowing from the collector electrode 9 to the diffusion region 18 along the thickness direction DR3 does not have the emitter electrode 40 above the diffusion region 18, It cannot flow in the thickness direction as it is. The current flowing to the diffusion region 18 flows in the diffusion region 18 along the first direction DR1, and flows from the portion where the emitter electrode 40 is present above the diffusion region 18 to the emitter electrode 40.

FIG. 17 is a diagram showing an example of a direction in which a main current flows in the semiconductor chip 1A. As shown in FIG. 17, in the portion where the emitter electrode 40 exists, the main current flows to the emitter electrode 40 along the direction 60 from the back side to the front side of the paper surface. On the other hand, in the portion where the electrodes 3 to 6 are present, the main current flows along the thickness direction up to the diffusion region 18. After that, the main current flows in the diffusion region 18 in the direction of arrow 61. The main current flowing to the diffusion region 18 below the electrode 3 flows to the convex portion 41 a of the emitter electrode 40. The main current flowing to the diffusion region 18 below the electrode 4 flows to the convex portions 41a and 41b. The main current flowing to the diffusion region 18 below the electrode 5 flows to the convex portions 41b and 41c. The main current flowing to the diffusion region 18 below the electrode 6 flows to the convex portion 41c.

As described above, in the semiconductor chip 1A, since the cell region 22 exists below the electrodes 3 to 6, the semiconductor substrate 14 has a thickness not only below the emitter electrode 40 but also below the electrodes 3 to 6. The main current can flow in the direction DR3. Therefore, as compared with the semiconductor chip 1 according to the first embodiment, a larger amount of main current can flow in the semiconductor chip 1A. From a different point of view, when the semiconductor chip 1 according to the embodiment and the semiconductor chip 1A have the same amount of main current flowing in the thickness direction DR3, the semiconductor chip 1A is better than the semiconductor chip 1 according to the embodiment. However, the chip area can be reduced. Therefore, improvement of the semiconductor chip 1A can be realized.

FIG. 18 is a diagram showing a current-carrying region 32 in the semiconductor substrate 14 of the semiconductor chip 1A in which a main current can flow in the thickness direction. The energizable area 32 is larger than the energizable area 30 shown in FIG. In the semiconductor chip 1 according to the first embodiment, assuming that the area of the current-carrying region 30 is α and the area of the current-carrying region 31 is β, the area of the current-carrying region 30 of the semiconductor chip 1 can be (α+β). it can. Therefore, when the semiconductor chip 1A achieves the same current density as that of the semiconductor chip 1 of the first embodiment, the chip area can be reduced by β. As a result, the chip cost can be reduced when manufacturing the semiconductor chip 1A.

In addition, the size of the first semiconductor module 250 and the second semiconductor module 400 is reduced by manufacturing the above-described first semiconductor module 250 and the second semiconductor module 400 using the semiconductor chip 1A according to the present embodiment. be able to. From a different point of view, it is possible to increase the current that can be passed through the first semiconductor module 250 and the second semiconductor module 400.

Embodiment 3.
FIG. 19 is a top view showing an example of the structure of the semiconductor chip 1B according to this embodiment. The semiconductor chip 1B is obtained by changing the shape of the emitter electrode 40 and the arrangement of the electrodes 3 to 6 in the semiconductor chip 1A described above. The structure of the semiconductor chip 1B will be described below, focusing on the differences from the semiconductor chip 1A according to the second embodiment.

In the semiconductor chip 1B, the emitter electrode 40 is divided into two partial electrodes 42 and 43. The electrodes 3 to 6 are sandwiched between the two partial electrodes 42 and 43. The electrodes 3 to 6 are arranged in a line along the second direction DR2. The electrodes 3 to 6 are located on the central portion of the first main surface 14a in the first direction DR1. In the semiconductor chip 1B, as in the semiconductor chip 1A, the plurality of cell regions 22 extending along the first direction DR1 are provided below the emitter electrode 40 (partial electrodes 42 and 43) and the electrodes 3 to 6 in the second region. They are lined up along the direction DR2.

In the semiconductor chip 1A according to the second embodiment, as shown in FIG. 17, the main current flowing in the diffusion region 18 below the electrodes 3 and 4 is located between the electrodes 3 and 4. It flows to the convex portion 41 a of the emitter electrode 40. For this reason, current may concentrate on the narrow convex portion 41a, and the short-circuit resistance of the convex portion 41a may decrease. Further, the main current flowing in the diffusion region 18 below the electrodes 4 and 5 flows into the convex portion 41b located between the electrodes 4 and 5. For this reason, current may be concentrated on the convex portion 41b, and the short circuit resistance of the convex portion 41b may be reduced. Further, the main current flowing in the diffusion region 18 below the electrodes 5 and 6 flows to the convex portion 41 c located between the electrodes 5 and 6. For this reason, current may be concentrated on the convex portion 41c, and the short circuit resistance of the convex portion 41c may be reduced.

As described above, in the semiconductor chip 1A, since the emitter electrode 40 has the portion sandwiched between the other electrodes, there is a possibility that the current is concentrated in the portion and an uneven current density occurs in the emitter electrode 40. .. As a result, the short circuit resistance of the emitter electrode 40 may decrease.

On the other hand, in the semiconductor chip 1B according to the present embodiment, the emitter electrode 40 does not have a portion sandwiched between the other electrodes, so that there is a possibility of uneven current density in the emitter electrode 40. Can be reduced. Therefore, the short circuit resistance of the emitter electrode 40 is improved, and as a result, the semiconductor chip 1A is improved. In the semiconductor chip 1B according to the present embodiment, the main current flowing to the diffusion region 18 below the electrodes 3 to 6 flows in the diffusion region 18 in the direction of arrow 62. The main current flowing to the diffusion region 18 below the electrode 3 flows to the partial electrodes 42 and 43 that sandwich the electrode 3. Similarly, the main current flowing to the diffusion region 18 below the electrode 4, the main current flowing to the diffusion region 18 below the electrode 5, and the main current flowing to the diffusion region 18 below the electrode 6. Flows to the partial electrodes 42 and 43.

Further, by manufacturing the above-described first semiconductor module 250 and second semiconductor module 400 using the semiconductor chip 1B according to the present embodiment, the short-circuit tolerance of the first semiconductor module 250 and the second semiconductor module 400 is improved. can do.

The structure of the semiconductor chip 1B is not limited to the above example. For example, as shown in FIG. 20, the emitter electrode 40 may surround the electrodes 3-6. Even in this case, since the emitter electrode 40 does not have a portion sandwiched between other electrodes, it is possible to reduce the possibility that the current density of the emitter electrode 40 is uneven.

In the above first to third embodiments, the semiconductor chips 1, 1A, 1B are provided with the IGBT, but other types of semiconductor elements may be provided instead of the IGBT. For example, the semiconductor chips 1, 1A, 1B may include MOS (metal-oxide-semiconductor) transistors. In this case, for example, the first main electrodes 2 and 40 are source electrodes, and the second main electrode 9 is a drain electrode.

Fourth Embodiment
In the present embodiment, the semiconductor device (semiconductor chip or semiconductor module) according to the first to third embodiments described above is applied to a power conversion device. Although the application of the semiconductor device according to the first to third embodiments is not limited to a specific power conversion device, the semiconductor device according to the first to third embodiments will be described below as a fourth embodiment in a three-phase inverter. The case where is applied will be described.

FIG. 21 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

The power conversion system shown in FIG. 21 includes a power supply 500, a power conversion device 600, and a load 700. The power supply 500 is a DC power supply and supplies DC power to the power converter 600. The power source 500 can be configured by various types, for example, a DC system, a solar battery, a storage battery, or a rectifier circuit or an AC/DC converter connected to an AC system. Good. Further, the power supply 500 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.

The power conversion device 600 is a three-phase inverter connected between the power source 500 and the load 700, converts DC power supplied from the power source 500 into AC power, and supplies AC power to the load 700. As shown in FIG. 21, the power conversion device 600 includes a main conversion circuit 601 that converts DC power into AC power and outputs the AC power, and a drive circuit 602 that outputs a drive signal that drives each switching element of the main conversion circuit 601. And a control circuit 603 which outputs a control signal for controlling the drive circuit 602 to the drive circuit 602.

The load 700 is a three-phase electric motor driven by the AC power supplied from the power conversion device 600. The load 700 is not limited to a specific use, and is an electric motor mounted in various electric devices, and is used as, for example, a hybrid car, an electric car, a railway vehicle, an elevator, or an electric motor for an air conditioner.

Hereinafter, the details of the power conversion device 600 will be described. The main conversion circuit 601 includes a switching element and a free wheeling diode (not shown). When the switching element switches, the DC power supplied from the power supply 500 is converted into AC power and supplied to the load 700. Although there are various concrete circuit configurations of the main conversion circuit 601, the main conversion circuit 601 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and respective switching elements. It can consist of six freewheeling diodes in anti-parallel. The semiconductor device according to any of the first to third embodiments described above is applied to each switching element of the main conversion circuit 601. The six switching elements are connected in series every two switching elements to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 601 are connected to the load 700.

The drive circuit 602 generates a drive signal for driving the switching element of the main conversion circuit 601, and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 601. Specifically, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrodes of the respective switching elements according to a control signal from a control circuit 603 described later. When maintaining the switching element in the ON state, the drive signal is a voltage signal (ON signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

The control circuit 603 controls the switching element of the main conversion circuit 601 so that desired electric power is supplied to the load 700. Specifically, the time (ON time) in which each switching element of the main conversion circuit 601 should be in the ON state is calculated based on the power to be supplied to the load 700. For example, the main conversion circuit 601 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, at each time point, a control command (control signal) is output to the drive circuit 602 so that an ON signal is output to a switching element which is to be in an ON state and an OFF signal is output to a switching element which is to be in an OFF state. The drive circuit 602 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal. The above-described control circuit that controls the semiconductor chips 1, 1A, and 1B described in the first to third embodiments includes, for example, the drive circuit 602 and the control circuit 603.

In the power conversion device according to the present embodiment, the semiconductor device according to the first to third embodiments is applied as the switching element of the main conversion circuit 601, so that the power conversion device can be improved.

In the present embodiment, an example in which the semiconductor device according to the first to third embodiments is applied to the two-level three-phase inverter has been described, but the application of the semiconductor device according to the first to third embodiments is limited to this. However, the present invention can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when supplying power to a single-phase load, a single-phase inverter is used. The semiconductor devices according to 1 to 3 may be applied. Further, when supplying power to a DC load or the like, it is possible to apply the semiconductor device according to the first to third embodiments to a DC/DC converter or an AC/DC converter.

Further, the power conversion device to which the semiconductor device according to the first to third embodiments is applied is not limited to the case where the above-mentioned load is an electric motor, and, for example, an electric discharge machine, a laser machine, or an induction heating cooker. It can also be used as a power supply device for a non-contactor power feeding system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

In the present invention, the respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or omitted within the scope of the invention.

1, 1A, 1B semiconductor chip, 2, 40 first main electrode, 9 second main electrode, 3 to 6 electrodes, 202 plate-shaped conductive member, 250 first semiconductor module, 400 second semiconductor module, 600 power converter, 601 Main conversion circuit, 602 drive circuit, 603 control circuit.

Claims (8)

A semiconductor device,
A main electrode,
A control circuit for controlling the semiconductor device and a plurality of first electrodes for electrically connecting the semiconductor device,
The plurality of first electrodes,
A control electrode for controlling the semiconductor device,
A semiconductor device having a second electrode electrically connected to the main electrode. The semiconductor device according to claim 1, wherein
A semiconductor device in which all of the plurality of first electrodes other than the control electrode are the second electrodes. The semiconductor device according to any one of claims 1 and 2, wherein:
A semiconductor device further comprising a conductive member to which the main electrode and the second electrode are wire-bonded. A method of manufacturing a semiconductor device, comprising:
A first step of forming a main electrode, a control circuit for controlling the semiconductor device, and a plurality of first electrodes for electrically connecting the semiconductor device;
A method of manufacturing a semiconductor device, comprising: a second step of electrically connecting a main electrode with a second electrode of the plurality of first electrodes other than a control electrode for controlling the semiconductor device. A method of using a semiconductor device, comprising:
The semiconductor device is
A main electrode,
A control circuit for controlling the semiconductor device, and a plurality of first electrodes for electrically connecting the semiconductor device,
Of the plurality of first electrodes, a first step of manufacturing a device including the semiconductor device in which a second electrode other than a control electrode for controlling the semiconductor device and the main electrode are electrically connected,
A method of using a semiconductor device, comprising: a second step of manufacturing a device including the semiconductor device, in which the control circuit and the plurality of first electrodes are electrically connected, and the control circuit. A semiconductor layer having first and second major surfaces;
A first main electrode on the first main surface,
A first electrode on the first major surface,
A second main electrode on the second main surface,
A semiconductor device comprising: the first main electrode and a cell region located below the first electrode in the semiconductor layer, for flowing a current from the second main electrode to the first main electrode. The semiconductor device according to claim 6, wherein
Further comprising a second electrode on the first major surface,
The first main electrode is a semiconductor device having no portion sandwiched between the first and second electrodes. A main conversion circuit which has the semiconductor device according to any one of claims 1 to 3, claim 6 and claim 7, and which converts and outputs input power.
A drive circuit for outputting a drive signal for driving the semiconductor device to the semiconductor device;
And a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

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