JP2018133506A - Thermoelectric module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve high durability, high productivity, high thermoelectric effect, and good appearance in a thermoelectric module that includes two terminals that conduct both ends of a series selectric circuit and the outside thereof and is formed by conducting a plurality of thermoelectric elements constituted by two different types of semiconductor chips electrically connected via an electrode formed on one substrate of a pair of opposing substrates through an electrode formed on the other substrate and is disposed such that the two different types of semiconductor chips are arranged in a lattice array of odd number×odd number.SOLUTION: Two different types of semiconductor chips are arranged alternately in a lattice array, the two types of semiconductor chips constituting a thermoelectric element are adjacent to each other in the axial direction of the lattice array, the semiconductor chips arranged at the four corners of the lattice array are all of the same type, and a semiconductor chip is not arranged in one place where a semiconductor chip of the same type as a semiconductor chip arranged at a corner is to be arranged in a region which is not the outermost periphery of the lattice array.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a thermoelectric module. More specifically, the present invention relates to a thermoelectric module that can achieve high durability, high productivity, high thermoelectric effect, and good appearance.

  For example, in technical fields such as temperature control and exhaust heat utilization, for example, Peltier elements that convert electrical energy into thermal energy using the Peltier effect and thermoelectric elements such as Seebeck elements that convert thermal energy into electrical energy using the Seebeck effect. Utilization of elements is expected. A thermoelectric element is composed of a joint of different kinds of metals or semiconductors, and performs energy conversion between electric energy and thermal energy, and is typically a combination of a p-type semiconductor chip and an n-type semiconductor chip. Is used. Furthermore, for the purpose of obtaining a greater effect, a so-called “thermoelectric module” having a configuration in which a plurality of thermoelectric elements are connected in series between two substrates facing each other is widely adopted.

  However, in the thermoelectric module having the above-described configuration, deformation such as warpage of the thermoelectric module due to the thermal stress caused by the temperature difference between the front and back during operation (hereinafter sometimes referred to as “thermal deformation”). May occur, and the thermoelectric element (semiconductor chip constituting the thermoelectric element) and the electrode may be peeled off or the thermoelectric element may be damaged. Further, when an impact is applied from the outside, the thermoelectric element may be broken or the thermoelectric element may be cracked.

  Therefore, in this technical field, a pair of substrates, a plurality of semiconductor chips arranged on the pair of substrates, a wiring conductor that electrically connects the plurality of semiconductor chips, and the pair of substrates are provided. Various techniques have been proposed for the purpose of reducing thermal deformation and improving impact resistance in a thermoelectric module including an external connection terminal electrically connected to the wiring conductor.

  First, a plurality of semiconductor chips are arranged in a lattice shape, and the semiconductor chips are not arranged at the four corners of the lattice-like arrangement in which thermal stress and / or impact tends to concentrate, thereby causing a semiconductor chip caused by thermal deformation. It is known that the durability as a thermoelectric module is improved by preventing peeling and destruction from the insulating substrate (see, for example, Patent Document 1). However, in this case, as compared with the case where semiconductor chips are also arranged at the four corners, the effect as a thermoelectric element (for example, the Peltier effect and Seebeck effect, etc., which may hereinafter be referred to as “thermoelectric effect”) may be contributed. Since the number of elements to be reduced decreases, it may be difficult to exhibit the expected performance as the entire thermoelectric module. In addition, since the number of semiconductor chips as members connecting the pair of substrates is reduced, the mechanical strength of the entire thermoelectric module is reduced. Furthermore, since the semiconductor chip is not arranged at the four corners, an impression as if there is a defect such as a defect of the semiconductor chip is given, which is not preferable in appearance.

  Next, some of the semiconductor chips (particularly, semiconductor chips arranged at the corners) are formed by reinforcing elements whose difference from the average thermal expansion coefficient of the semiconductor chips is within 20% and higher than the average hardness of the semiconductor chips by 10% or more. It is also known to improve the impact resistance of a thermoelectric module by replacement (see, for example, Patent Document 2). However, in order to manufacture such a thermoelectric module, it is necessary to replace only a part (corner portion) of the semiconductor chip with a strengthening element, so that the above configuration causes a complicated manufacturing process, There is a risk that productivity may be significantly reduced.

  According to Patent Document 2, it is said that the impact resistance can be further improved by not electrically connecting the reinforcing element to the circuit formed by the thermoelectric element. However, in this case, the number of elements contributing to the thermoelectric effect is reduced. Furthermore, depending on the material constituting the reinforcing element, the reinforcing element may act as a heat conduction path connecting the pair of substrates. As a result, the temperature difference between the front and back of the thermoelectric module is reduced, and it may be difficult to exhibit the desired performance as the entire thermoelectric module.

  Next, for the purpose of preventing damage to the thermoelectric element due to thermal deformation of the substrate accompanying the operation of the thermoelectric module, a central region having an area equal to or larger than four semiconductor chips in the opposing surfaces of the pair of substrates is provided. It is also known that semiconductor chips are arranged densely in areas other than the central area where no semiconductor chips are arranged (see, for example, Patent Document 3). According to this, by shortening the distance between the base point of the warp due to thermal stress and the outer periphery of the substrate, reducing the displacement amount and force of the warp generated on the outer periphery of the substrate, and dispersing them in the individual thermoelectric elements, Damage to the thermoelectric element due to warping of the substrate can be reduced. However, in this case, since the number of elements contributing to the effect as the thermoelectric element is reduced as compared with the case where the semiconductor chip is also arranged in the central region, it is difficult to exert the desired performance as the entire thermoelectric module. There is a risk of becoming.

  Further, in Patent Document 3, semiconductor chips are arranged in an odd number × odd number of lattices, and electrodes are drawn from the semiconductor chips arranged at both corners on one side of the outer periphery of the array. Several configurations have been disclosed. Thus, when odd-numbered semiconductor chips are alternately arranged and densely arranged on one side of the outer periphery of the lattice-like arrangement, the semiconductor chips at both ends are of the same type (that is, p-type and p-type or n-type and n-type). ). On the other hand, the two electrodes drawn out from the thermoelectric module need to be connected to different types of semiconductor chips. Therefore, in the said thermoelectric module, it is estimated that the semiconductor chip of the same kind is arrange | positioned adjacently at least in a part of arrangement | sequence. If the arrangement is partly disturbed (not alternating), the manufacturing process becomes complicated, and the productivity of the thermoelectric module may be significantly reduced.

  Furthermore, the bonding strength between the semiconductor chip and the electrode includes, for example, the bonding between the semiconductor chip and the electrode, such as the bonding strength between the semiconductor chip material and the bonding layer member provided on the surface thereof by plating or the like. The bonding strength between the members is included. For this reason, the bonding strength between the semiconductor chip and the electrode may differ depending on the type of semiconductor chip (that is, p-type or n-type). Therefore, from the viewpoint of reducing thermal stress caused by the temperature difference between the front and back of the thermoelectric module during operation and / or damage to the thermoelectric element caused by external impact, a lattice shape in which thermal stress and / or impact tends to concentrate. It is desirable to arrange a type of semiconductor chip having a higher bonding strength with the electrodes at the four corners of the array. In this case, the types of semiconductor chips arranged at the four corners should be the same. However, as described above, in the above configuration, different types of semiconductor chips are arranged at two adjacent corners, and electrodes are drawn from the respective semiconductor chips. Therefore, in the above configuration, it is impossible to dispose a semiconductor chip of a higher bonding strength with the electrode at all four corners, and the thermoelectric element is damaged due to thermal deformation and / or external impact. It is difficult to increase the durability of the thermoelectric module by reducing the temperature.

  As described above, in the technical field, a thermoelectric module having high durability, high productivity, high thermoelectric effect, and good appearance has not been achieved yet.

Japanese Patent No. 4288935 JP 2004-235367 A Japanese Patent No. 5465829

  As described above, in this technical field, there is a demand for a thermoelectric module that can achieve high durability, high productivity, high thermoelectric effect, and good appearance.

  The present invention has been made in view of the above problems, and an object thereof is to provide a thermoelectric module that can achieve high durability, high productivity, high thermoelectric effect, and good appearance.

  That is, the thermoelectric module according to the present invention (hereinafter sometimes referred to as “the present invention module”) is formed on a pair of substrates facing each other and at predetermined locations on the surfaces facing each other. A plurality of thermoelectric elements composed of two different semiconductor chips electrically connected via the electrodes formed on one of the pair of substrates and the electrode formed on one of the pair of substrates are the other of the pair of substrates A series electric circuit formed by being conducted in the same direction through the electrodes formed on each other, and two terminals for conducting both ends of the series electric circuit and the outside. The two different types of semiconductor chips are arranged in an odd number × odd number of lattice arrangement.

Further, the module of the present invention is configured to satisfy the requirements (a) to (d) listed below.
(A) The two different types of semiconductor chips are alternately arranged in both of two orthogonal axial directions of the lattice arrangement.
(B) Two different types of semiconductor chips constituting the thermoelectric element are adjacent to each other in any one of two orthogonal axial directions of the lattice arrangement.
(C) The four semiconductor chips arranged at the four corners of the lattice array are all of the same type.
(D) In the central region that is not the outermost periphery of the grid-like arrangement, the semiconductor chip is arranged at one place where the same type of semiconductor chip as the semiconductor chip arranged at the corner is to be arranged. Not.

  By satisfying the above requirements (a) to (d), the module of the present invention can achieve high durability, high productivity, and high thermoelectric effect. In addition, since the semiconductor chips are densely arranged on the outermost periphery of the lattice-like arrangement (a portion where no semiconductor chips are arranged is not provided), a good appearance can be achieved.

  Other objects, other features, and attendant advantages of the present invention will be readily understood from the description of each embodiment of the present invention described with reference to the following drawings.

It is a schematic diagram which shows the example of the arrangement | sequence of the semiconductor chip in the thermoelectric module which concerns on a prior art. In the example of the 5 × 5 lattice arrangement of the semiconductor chips in the thermoelectric module (first module) according to the first embodiment of the present invention, the locations where the semiconductor chips are not disposed and both ends of the series electric circuit of the thermoelectric elements and the outside It is a schematic diagram which shows the candidate of the location which arrange | positions the two terminals for conducting. It is a schematic diagram which shows the example of the 5 * 5 lattice-like arrangement | sequence of the semiconductor chip in a 1st module. It is a schematic diagram which shows the example of the arrangement | sequence of several different 2 types of semiconductor chips in the thermoelectric module which concerns on various Examples of this invention and various comparative examples applicable to a prior art.

<< Problems of Thermoelectric Modules Related to the Prior Art >>
Before describing thermoelectric modules according to various embodiments of the present invention, the problems of thermoelectric modules according to the prior art will be summarized below.

  In a thermoelectric module in which semiconductor chips are arranged in a lattice shape, when a semiconductor chip is not disposed at a corner, thermal stress and / or impact is concentrated on the corner to prevent the thermoelectric module from being damaged. Since the number of contributing elements is reduced, the performance of the thermoelectric module is lowered and the mechanical strength is lowered. Further, for example, an impression as if there is a defect such as a defect of a semiconductor chip is given, which is not preferable in appearance.

  Replacing some (especially corner) semiconductor chips with reinforcing elements prevents thermal stress and / or impact from concentrating on the corners and damaging the thermoelectric module, resulting in a complicated manufacturing process. The productivity of the thermoelectric module is reduced. Further, when the reinforcing elements are not electrically connected, not only the number of elements contributing to the thermoelectric effect is reduced but also the reinforcing elements act as a heat conduction path, leading to a decrease in performance of the thermoelectric module.

  In the case where damage to the thermoelectric element due to the warp of the substrate is reduced by providing a portion where the semiconductor chip is not arranged in the central region of the lattice arrangement, the number of elements contributing to the effect as the thermoelectric element is also reduced.

  FIG. 1 is a schematic diagram showing an example of the arrangement of semiconductor chips in a thermoelectric module according to the prior art. In FIG. 1, a hatched square and a white square represent different types of semiconductor chips, respectively, and a thick bent line represents a pattern of a series electric circuit formed by electrically connecting these semiconductor chips. Represent. A black square represents a portion where a semiconductor chip is not disposed (hereinafter, sometimes referred to as “non-arranged portion”).

  An actual thermoelectric module is formed at a predetermined location on a pair of substrates sandwiching the array, and the opposing surfaces of these substrates, in addition to the array of two different types of semiconductor chips as shown in FIG. And two terminals for conducting both ends of the series electric circuit and the outside as constituent elements. However, in FIG. 1, these components are not shown for the purpose of facilitating the explanation. Also, in the drawings referred to after FIG. 1, some or all of these components may be omitted as necessary.

  In a thermoelectric module having an odd number × odd number of grid-like arrangement, when a terminal is pulled out from a semiconductor chip arranged at a corner, both ends of a series electric circuit formed by connecting a plurality of thermoelectric elements in the same direction, Different types of semiconductor chips need to be arranged. Therefore, for example, as shown in FIG. 1A, semiconductor chips of the same type are arranged next to each other at least in a part of the arrangement. When the arrangement of the semiconductor chips is partially disturbed (not alternating) as described above, the manufacturing process is complicated and the productivity of the thermoelectric module is lowered. Further, since the types of the semiconductor chips at the four corners of the grid array are not the same, the bonding strength between the semiconductor chip and the electrodes at the corners cannot be made uniform, and the thermoelectric element caused by thermal stress and / or impact It becomes difficult to reduce the breakage of the.

  When disposing different types of semiconductor chips at both ends of the series electric circuit without disturbing the arrangement of the semiconductor chips as described above, for example, as shown in FIG. It is necessary to omit (not arrange) any one of the semiconductor chips. In this case, since the non-arranged portions are provided at the corners, the performance and mechanical strength of the thermoelectric module are lowered, or an impression as if there is a defect is given.

  On the other hand, when a terminal is drawn out from a semiconductor chip arranged at a corner in a thermoelectric module having a grid-like arrangement that is not an odd number × odd number, for example, as shown in FIG. Different types. Therefore, it is not necessary to disturb the arrangement of the semiconductor chips as described above. However, also in this case, since the types of the semiconductor chips at the four corners of the grid array are not the same, the bonding strength between the semiconductor chip and the electrodes at the corners cannot be made uniform, and thermal stress and / or impact It becomes difficult to reduce the breakage of the thermoelectric element due to the above.

  As described above, it is difficult to achieve high durability, high productivity, high thermoelectric effect, and good appearance in the conventional thermoelectric module.

<< First Embodiment >>
The thermoelectric module according to the first embodiment of the present invention (hereinafter sometimes referred to as “first module”) will be described below with reference to the drawings.

<Constitution>
The first module is electrically connected via a pair of substrates opposed to each other, electrodes formed respectively at predetermined locations on the opposed surfaces of the pair of substrates, and the electrodes formed on one of the pair of substrates. Series electricity formed by electrically connecting a plurality of thermoelectric elements composed of two differently connected semiconductor chips in the same direction via the electrodes formed on the other substrate of the pair of substrates A circuit and two terminals for conducting both ends of the series electric circuit and the outside.

  The shape and size of the substrate are appropriately determined according to, for example, the use of the first module. Further, the number of thermoelectric elements (that is, the number of semiconductor chips) incorporated in the first module is appropriately determined according to, for example, the magnitude of the thermoelectric effect required in the application of the first module. However, from the viewpoint of weight reduction and / or size reduction of the first module, it is desirable that more thermoelectric elements are arranged densely (that is, with as little gap as possible) between smaller substrates.

The materials and configurations of the two different types of semiconductor chips can also be appropriately selected according to, for example, the magnitude of the thermoelectric effect required in the application of the first module. Specifically, a combination of a p-type semiconductor chip (for example, Bi _1.5 Sb _0.5 Te ₃ ) and an n-type semiconductor chip (for example, Bi ₂ Te ₃ ) can be used.

  The electrodes formed at predetermined locations on the opposing surfaces of the pair of substrates are made of a good conductor (for example, copper or the like), and are joined to the semiconductor chip by soldering, for example. Typically, the pair of substrates is a kind of so-called “wiring substrate”.

  As described above, the thermoelectric element incorporated in the first module is configured by two different types of semiconductor chips that are electrically connected via the electrodes formed on one of the pair of substrates. The plurality of thermoelectric elements are electrically connected (electrically connected) in the same direction via electrodes formed on the other substrate of the pair of substrates. That is, the thermoelectric element has a so-called “π-type” structure.

  The two different types of semiconductor chips are arranged in an odd number × odd number of lattice arrangement. The number of semiconductor chips constituting each side of the grid-like arrangement is also appropriately determined according to, for example, the magnitude of the thermoelectric effect required in the application of the first module.

  Further, the first module is configured to satisfy the requirements (a) to (d) listed below.

  (A) The two different types of semiconductor chips are alternately arranged in both of two orthogonal axial directions of the lattice arrangement. In other words, the two different types of semiconductor chips are arranged so as to correspond to a so-called “checkered pattern” in the lattice arrangement.

  (B) Two different types of semiconductor chips constituting the thermoelectric element are adjacent to each other in any one of two orthogonal axial directions of the lattice arrangement. Technically, it is also possible to form a thermoelectric element by electrically connecting two different types of semiconductor chips located in an oblique direction (diagonal direction) in a lattice arrangement. It is also possible to form a thermoelectric element by electrically connecting two different types of semiconductor chips via wiring that bypasses other semiconductor chips. However, such a configuration increases the manufacturing cost of the first module due to, for example, an increase in the substrate area for laying the wiring, an increase in electrical resistance due to the addition of the wiring, and a reduction in the arrangement density of the semiconductor chips. And / or it may lead to a decrease in performance, which is not desirable.

  (C) The four semiconductor chips arranged at the four corners of the lattice array are all of the same type. Specifically, the four semiconductor chips arranged at the four corners of the lattice array are all p-type or all n-type.

  (D) In the central region that is not the outermost periphery of the grid-like arrangement, the semiconductor chip is arranged at one place where the same type of semiconductor chip as the semiconductor chip arranged at the corner is to be arranged. Not. Here, the “outermost circumference of the grid array” refers to an area where the semiconductor chips constituting the four sides of the grid array are arranged, and the “center area” is surrounded by the outermost circumference in the grid array. Refers to the area.

  In other words, the semiconductor chip is arranged at all the locations where the semiconductor chip is to be arranged in the central region and the outermost periphery except the portion where the semiconductor chip is not arranged (non-placed portion) as described above. Yes. In the present specification, such a state is referred to as a “closely arranged state”.

  By the way, theoretically, the number of non-arranged portions is not necessarily one. One purpose of providing the non-arranged portion is to “make the same number of two different types of semiconductor chips included in the first module”. Another purpose of providing the non-arranged portion is “a plurality of different adjacent semiconductor chips arranged alternately (in a checkered pattern) in an odd-numbered × odd-numbered lattice arrangement alternately and in series. It is possible to form a series electric circuit composed of thermoelectric elements. As long as these objects are achieved, the number of non-arranged portions in the central region is not limited to one.

  Specifically, when no non-arranged portion is provided in an odd number × odd number of lattice arrangement, the number of semiconductor chips of the same type as the semiconductor chips arranged at the corners is different from the number of semiconductor chips of a different type. One more. Therefore, the number of non-arranged portions provided at the locations where the same type of semiconductor chips as the semiconductor chips at the corners are to be disposed is equal to the number of non-arranged portions provided at the locations where different types of semiconductor chips are to be disposed. It is sufficient to increase the number by one. Specifically, for example, in the central region, two non-arranged locations for the same type of semiconductor chip as the corner portion and one non-arranged location for a semiconductor chip of a different type from the corner portion may be provided, Three of the former may be provided and two of the latter may be provided.

  However, since the number of elements that contribute to the thermoelectric effect decreases as the number of places where semiconductor chips are not arranged (non-placed places) is increased, the performance of the thermoelectric module is lowered or the mechanical strength is lowered. . From such a viewpoint, it is desirable that the number of non-arranged portions is as small as possible. Accordingly, in the first module, only one non-arranged portion for the same type of semiconductor chip as the corner portion is provided in the central region.

  The position where the non-arranged portion is provided in the central region of the first module is not particularly limited as long as it is “a portion where a semiconductor chip of the same type as the semiconductor chip disposed at the corner portion is to be disposed”. Further, in accordance with the position of the non-arranged place determined as described above, a plurality of different two types of semiconductor chips are alternately electrically connected to form a series electric circuit, and both ends of the series electric circuit. The arrangement of the two terminals for conducting to the outside can be determined as appropriate.

  For example, FIG. 2 shows an example of a 5 × 5 grid arrangement of semiconductor chips in the first module, 2 for connecting a portion where no semiconductor chip is arranged and both ends of a series electric circuit of thermoelectric elements to the outside. It is a schematic diagram which shows the candidate of the location which arrange | positions one terminal. In FIG. 2, a hatched square and a white square represent different types of semiconductor chips, respectively. In the following description regarding FIG. 2, it is assumed that a hatched square represents a p-type semiconductor chip, and an open square represents an n-type semiconductor chip. These two different types of semiconductor chips are alternately arranged in both of two orthogonal axial directions of the lattice arrangement. The p-type semiconductor chips (squares with diagonal lines) are arranged at the four corners of the outermost periphery and the midpoints of each side and the four corners and the center of the central region, and the n-type semiconductor chips (open squares) are Arranged between p-type semiconductor chips.

  In the above case, the candidates for the non-arranged places in the central region are the five places where the same type (p-type) semiconductor chip as the corner is arranged. That is, in the first module shown in FIG. 2, the semiconductor chip is not arranged at any one of the five locations indicated by the squares in which the four sides are drawn by bold lines and shaded.

  In addition, a candidate for a placement location (terminal conduction location) of a semiconductor chip that is conducted with two terminals for conducting both ends of a series electric circuit formed by a plurality of thermoelectric elements and the outside is indicated by two upward arrows. Pointed. In this example, it is assumed that two terminals are pulled out from one side of the outer peripheral portion located downward in the drawing. In this case, there are six terminal conduction locations including the three terminal conduction location candidates shown in (1) to (3) and three terminal conduction locations in which the left and right sides thereof are reversed.

  2 shows an example in which two terminals are drawn from one side of the outer peripheral portion, the two terminals may be drawn individually from different sides. However, from the viewpoint of weight reduction and / or size reduction of the first module, a configuration in which two terminals are drawn from one side of the outer peripheral portion is desirable (details will be described later).

<effect>
According to the requirement (a), two different types of semiconductor chips are always alternately arranged in all parts of the lattice arrangement (except where the semiconductor chip is not arranged by the configuration (d)). The productivity of the module of the present invention can be increased. In addition, since two different types of semiconductor chips are evenly distributed by such an arrangement, the distribution of mechanical strength in the plane of the lattice-like arrangement becomes more uniform. As a result, the thermal stress and / or impact acting on the first module can be more evenly distributed, so that the durability of the first module can be enhanced.

  In addition, because of the requirement (b) above, two different types of semiconductor chips constituting the thermoelectric element are adjacent to each other in either of two orthogonal axial directions of the lattice-like arrangement. The shape of the electrode to be electrically connected can be simplified and the length can be minimized. As a result, the manufacturing process can be simplified, and the productivity of the first module can be increased.

  Furthermore, due to the requirement (c) above, the four semiconductor chips arranged at the four corners of the grid array are all of the same type. Accordingly, the thermal stress caused by the temperature difference between the front and back of the thermoelectric module during operation and / or the mechanical strength at the four corners of the grid array where the external impact tends to be concentrated can be made equal. In addition, it is possible to avoid the influence due to the impact from being concentrated on some corners. As a result, the durability of the first module can be increased.

  In addition, due to the requirement (d) above, no semiconductor chip is arranged at one place where a semiconductor chip of the same type as the semiconductor chip arranged at the corner is to be arranged in the central region of the lattice arrangement. Accordingly, a series electric circuit formed by a plurality of thermoelectric elements can be formed using a plurality of different two types of semiconductor chips arranged alternately in an odd number × odd number of lattice arrangement. That is, a high thermoelectric effect can be achieved by arranging a plurality of thermoelectric elements densely.

  On the other hand, since there is no portion (non-placement portion) where the semiconductor chip is not arranged as described above on the outermost periphery of the lattice-like arrangement, the first module has an impression as if there is a defect such as a chip of the semiconductor chip. And good appearance can be achieved.

  As described above, according to the first module, high durability, high productivity, high thermoelectric effect, and good appearance can be achieved.

  Here, for reference, a specific example of the lattice arrangement of the semiconductor chips in the first module is shown. FIG. 3 is a schematic diagram illustrating a plurality of examples (specifically, four of (a) to (d)) of a 5 × 5 lattice array of semiconductor chips in the first module. Also in FIG. 3, as in FIG. 1 described above, the hatched square and the white square represent different types of semiconductor chips, respectively, and the thick bent line is obtained by electrically connecting these semiconductor chips. The pattern of the series electric circuit formed is represented. A black square represents a portion where a semiconductor chip is not disposed (non-arranged portion).

  As illustrated in FIG. 3, the first module can be configured as a thermoelectric module arranged in a 5 × 5 grid array, and the various effects described above can be achieved. In the first module illustrated in FIG. 3, a 5 × 5 semiconductor chip array is used as described above. However, for example, 7 × 7 and 9 × 9, 5 × An odd-numbered × odd-numbered grid-like arrangement other than five may be employed. Further, for example, a grid-like array in which the number of semiconductor chips constituting adjacent sides of the grid-like array is an odd number, such as 5 × 7 and 7 × 9, may be employed.

<< Second Embodiment >>
The thermoelectric module according to the second embodiment of the present invention (hereinafter sometimes referred to as “second module”) will be described below with reference to the drawings.

  As described above, the bonding strength between the semiconductor chip and the electrode may differ depending on the type of semiconductor chip (that is, p-type or n-type). Therefore, from the viewpoint of reducing thermal stress caused by the temperature difference between the front and back of the thermoelectric module during operation and / or damage to the thermoelectric element caused by external impact, the lattice in which thermal stress and / or impact tends to concentrate. It is desirable to arrange a kind of semiconductor chip having higher bonding strength with the electrodes at the four corners of the array.

<Constitution>
Therefore, the second module has the same configuration as the first module described above, and the bonding strength between the semiconductor chip and the electrode arranged at the corner of the grid array is arranged at the corner of the grid array. The semiconductor chip of a different type from the semiconductor chip to be formed is configured to have a higher bonding strength than the electrode.

  In other words, the second module is configured such that, of two different types of semiconductor chips, the semiconductor chip having the higher bonding strength with the electrode is arranged at the corners of the grid array. For example, when the bonding strength between the p-type semiconductor chip and the electrode is higher than the bonding strength between the n-type semiconductor chip and the electrode, the second module is arranged so that the p-type semiconductor chip is arranged at the corner of the grid array. Composed. Conversely, when the bonding strength between the n-type semiconductor chip and the electrode is higher than the bonding strength between the p-type semiconductor chip and the electrode, the second module is arranged so that the n-type semiconductor chip is arranged at the corner of the grid array. Is configured. A high bonding strength between the semiconductor chip and the electrode corresponds to a high mechanical strength of the bonding layer between the semiconductor chip and the electrode.

<effect>
According to the second module, semiconductor chips of a type having higher bonding strength with the electrodes are arranged at the four corner portions of the lattice-like arrangement in which thermal stress and / or impact tend to concentrate. Therefore, the thermal stress due to the temperature difference between the front and back of the thermoelectric module during operation and / or damage to the thermoelectric element due to external impact is more effectively reduced, and the durability of the thermoelectric module is more effectively improved. Can be increased.

<< Third Embodiment >>
The thermoelectric module according to the third embodiment of the present invention (hereinafter sometimes referred to as “third module”) will be described below with reference to the drawings.

  Incidentally, the mechanical strength of the semiconductor chip itself may also differ depending on the type of semiconductor chip (ie, p-type or n-type). Therefore, from the viewpoint of reducing thermal stress caused by the temperature difference between the front and back of the thermoelectric module during operation and / or damage to the thermoelectric element caused by external impact, the lattice in which thermal stress and / or impact tends to concentrate. It is desirable to dispose semiconductor chips of higher mechanical strength at the four corners of the array.

<Constitution>
Therefore, the third module has the same configuration as the first module or the second module described above, and the mechanical strength of the semiconductor chip arranged at the corner of the grid-like array is the corner of the grid-like array. It is comprised so that it may be higher than the mechanical strength of the said semiconductor chip of a different kind from the said semiconductor chip arrange | positioned.

  In other words, the third module is configured such that the semiconductor chip having higher mechanical strength among the two different types of semiconductor chips is arranged at the corners of the grid-like arrangement. For example, when the mechanical strength of the p-type semiconductor chip is higher than the mechanical strength of the n-type semiconductor chip, the third module is configured such that the p-type semiconductor chip is disposed at the corners of the grid array. On the other hand, when the mechanical strength of the n-type semiconductor chip is higher than the mechanical strength of the p-type semiconductor chip, the third module is configured so that the n-type semiconductor chip is arranged at the corner of the grid array. .

<effect>
According to the third module, a semiconductor chip of a higher mechanical strength is arranged at the four corners of the lattice-like array where thermal stress and / or impact tends to concentrate. Therefore, the thermal stress due to the temperature difference between the front and back of the thermoelectric module during operation and / or damage to the thermoelectric element due to external impact is more effectively reduced, and the durability of the thermoelectric module is more effectively improved. Can be increased.

<< 4th Embodiment >>
Hereinafter, a thermoelectric module according to a fourth embodiment of the present invention (hereinafter may be referred to as a “fourth module”) will be described with reference to the drawings.

  As described above, in the first module, in the central region that is not the outermost periphery of the lattice arrangement of semiconductor chips, one location where a semiconductor chip of the same type as the semiconductor chip disposed at the corner is to be disposed. The semiconductor chip is not arranged in. That is, the above-mentioned “non-arranged portion” is provided in the central region. Accordingly, a series electric circuit formed by a plurality of thermoelectric elements can be formed using a plurality of different two types of semiconductor chips arranged alternately in an odd number × odd number of lattice arrangement. That is, a high thermoelectric effect can be achieved by arranging a plurality of thermoelectric elements densely.

  In addition, an odd number × odd number of lattice-like arrays are formed by a plurality of two different types of semiconductor chips alternately arranged in this way, so that the same kind of semiconductor chips are placed on all four corners of the lattice-like array. Can be arranged. Accordingly, the thermal stress caused by the temperature difference between the front and back of the thermoelectric module during operation and / or the mechanical strength at the four corners of the grid array where the external impact tends to be concentrated can be made equal. In addition, it is possible to avoid the influence due to the impact from being concentrated on some corners. As a result, the durability of the thermoelectric module can be increased.

  However, by providing the non-arranged portions as described above, the number of semiconductor chips as members for connecting the pair of substrates is reduced, so that the mechanical strength of the entire thermoelectric module is reduced to some extent. As a countermeasure against this problem, for example, a thermoelectric module is formed by arranging a semiconductor chip or other member electrically insulated from a series electric circuit formed by thermoelectric elements at a non-arranged position and bonding it to a pair of substrates. It is conceivable to prevent a decrease in the mechanical strength as a whole.

  However, when the thermal conductivity of the semiconductor chip or other member arranged at the non-arranged portion is high as described above, the non-arranged portion acts as a heat conduction path connecting the pair of substrates, and the front and back of the thermoelectric module There is a risk that it will be difficult to achieve the desired performance as the whole thermoelectric module. In order to reduce such a problem, it is desirable that the thermal conductivity in the non-arranged portion is relatively low.

<Constitution>
Therefore, in the fourth module, in the same configuration as the thermoelectric module of any one of the first module to the third module described above, is nothing arranged at the place where the semiconductor chip is not arranged in the central region? Alternatively, a member having a thermal conductivity lower than that of the semiconductor chip is disposed.

  When nothing is arranged in the central region where the semiconductor chip is not arranged (non-arranged part), there is a gap in the part, and the heat conduction through the part is slower than the heat conduction through the semiconductor chip. On the other hand, when a member having a thermal conductivity lower than that of the semiconductor chip is arranged at the non-arranged portion in the central region, the heat conduction through the portion is slower than the heat conduction through the semiconductor chip.

<effect>
As is clear from the above, according to the fourth module, the non-arranged portion acts as a heat conduction path connecting the pair of substrates, the temperature difference between the front and back of the thermoelectric module is reduced, and the thermoelectric module as a whole is placed. The problem that it is difficult to exhibit the performance of the period can be avoided.

<< 5th Embodiment >>
Hereinafter, a thermoelectric module according to a fifth embodiment of the present invention (hereinafter may be referred to as a “fifth module”) will be described with reference to the drawings.

  As described above, two terminals for electrically connecting both ends of a series electric circuit of thermoelectric elements formed by electrically connecting a plurality of different two types of semiconductor chips alternately to the outside are these semiconductors. It may be drawn from only one side of the outer periphery of the chip-like array of chips, or may be drawn individually from different sides. However, when pulling out two terminals individually from different sides, a space for drawing out the terminals at each side is required, so from the viewpoint of reducing the weight and / or miniaturization of the thermoelectric module, A configuration in which two terminals are drawn out is desirable.

  In the above case, in the module of the present invention, since two different types of semiconductor chips are alternately arranged in an odd number × odd number of lattice arrangement, semiconductors arranged at both ends of one side of the outer peripheral part, that is, at corners. The types of chips are the same.

<Constitution>
Therefore, the fifth module has the same configuration as the thermoelectric module of any one of the first module to the fourth module described above, and the two terminals constitute the same side of the outermost periphery of the grid array. Of the two different types of semiconductor chips are electrically connected to the end face on the same substrate side, and at least one of the two different types of semiconductor chips respectively connected to the two terminals is other than the corners of the lattice arrangement Is arranged.

  In the above, the end face of the semiconductor chip through which the two terminals are conducted is also the end face of the thermoelectric element constituted by two different types of semiconductor chips. Further, the arrangement of the two terminals is not particularly limited as long as both of them are not arranged at the corners of the grid-like arrangement. For example, both of the two terminals may be arranged at a corner other than the corner of the grid arrangement, or one of the two terminals is arranged at a corner of the grid arrangement and the other of the two terminals is a grid arrangement. You may arrange | position other than the corner | angular part.

<effect>
According to the above, in the module of the present invention in which two different types of semiconductor chips are alternately arranged in an odd-numbered / odd-numbered grid-like arrangement, two ends for connecting the both ends of the series electric circuit of thermoelectric elements to the outside are connected. The weight and / or size of the thermoelectric module can be achieved while securing the terminals.

  Here, several specific examples will be described and described with respect to the arrangement of a plurality of two different types of semiconductor chips in the thermoelectric module according to various embodiments of the present invention.

  FIG. 4 is a schematic diagram showing an example of the arrangement of a plurality of two different types of semiconductor chips in thermoelectric modules according to various examples of the present invention and various comparative examples corresponding to the prior art. In any of the examples shown in FIG. 4, the semiconductor chips are arranged in a 5 × 5 lattice pattern. In addition, as described above, an actual thermoelectric module is formed at a predetermined location on a pair of substrates sandwiching the array, and the opposing surfaces of these substrates, in addition to an array of two different types of semiconductor chips. Two terminals for connecting both ends of the series electric circuit of the electrode and the thermoelectric element to the outside are included as components. However, in FIG. 4, for the purpose of facilitating the explanation and the like, it is formed on the upper substrate (front side in FIG. 4) of the pair of substrates sandwiching the arrangement of the semiconductor chips, on the upper substrate. The electrodes are omitted unless otherwise specified.

  First, in Example 1, a p-type semiconductor chip is arranged at all four corners of a lattice arrangement of semiconductor chips, and the semiconductor chip is arranged at a position where the p-type semiconductor chip is to be arranged in the central region. Otherwise, p-type semiconductor chips and n-type semiconductor chips are alternately arranged. In addition, one of the semiconductor chips in which two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside are conducted is arranged at a place other than the corners of the grid array.

  Next, in the second embodiment, similarly to the first embodiment, the p-type semiconductor chip is arranged at all four corners of the lattice arrangement of the semiconductor chips, and the p-type semiconductor chip is arranged in the central region. The semiconductor chip is not disposed at the power point, and the p-type semiconductor chip and the n-type semiconductor chip are alternately arranged in other areas. However, all the semiconductor chips in which the two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside are conducted are arranged at locations other than the corners of the grid array.

  Next, in the third embodiment, similarly to the first embodiment, the p-type semiconductor chip is arranged at all four corners of the lattice arrangement of the semiconductor chips, and the p-type semiconductor chip is arranged in the central region. The semiconductor chip is not disposed at the power point, and the p-type semiconductor chip and the n-type semiconductor chip are alternately arranged in other areas. However, the position of the non-arranged portion in the central region is different from that in the first embodiment. In addition, one of the semiconductor chips in which two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside are conducted is arranged at a place other than the corners of the grid array.

  Next, the fourth embodiment has the same configuration as the first embodiment. However, lead wires are connected to the two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside.

  Next, the fifth embodiment has a configuration similar to that of the first embodiment. However, of the two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside, the terminal that is conducted to the semiconductor chip arranged at a place other than the corner of the grid-like arrangement is: The electrode extends to the corner by an electrode extending to the nearest corner, and a lead wire is connected to the electrode and the other electrode.

  Next, Example 6 has the same configuration as that of Example 5. However, in the sixth embodiment, a post for wire bonding wiring is connected instead of the lead wire in the fifth embodiment.

  The thermoelectric modules according to the first to sixth embodiments described above satisfy all the requirements (1) to (4) described above. Therefore, high durability, high productivity, high thermoelectric effect and good appearance can be achieved.

  On the other hand, in the thermoelectric module according to the comparative example 1 which is one example of the thermoelectric module according to the prior art, the types of the semiconductor chips arranged at the four corners of the lattice arrangement of the semiconductor chips are not the same, and the p-type The semiconductor chips and the n-type semiconductor chips are not alternately arranged, and the two semiconductor terminals for conducting the two terminals for conducting the both ends of the series electric circuit of the thermoelectric element and the outside are both in a grid-like arrangement. It is arranged in the part. The thermoelectric module according to Comparative Example 1 corresponds to the thermoelectric module according to the related art shown in FIG. In order to form a pattern of a series electric circuit similar to that shown in FIG. 1A, it is formed on the upper substrate (front side in FIG. 4) of the pair of substrates sandwiching the array of semiconductor chips. Therefore, it is necessary to electrically connect the p-type semiconductor chip and the n-type semiconductor chip so as to straddle the non-arranged portion with the electrodes (see the quadrangle indicated by the broken line in FIG. 4). Since the wiring for electrically connecting the semiconductor chips that are not adjacent to each other as described above becomes long, there is a possibility that the performance of the thermoelectric module may be deteriorated due to an increase in electric resistance, which is not desirable.

  Next, in the thermoelectric module according to Comparative Example 2, which is another example of the thermoelectric module according to the related art, the semiconductor chip is not disposed at one corner of the lattice arrangement of the semiconductor chips. In addition, one of the two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside is disposed at a position adjacent to the corner where the semiconductor chip is not disposed as described above. Conducted.

  Next, in the thermoelectric module according to Comparative Example 3 which is still another example of the thermoelectric module according to the related art, two terminals for conducting both ends of the series electric circuit of the thermoelectric element and the outside are conducted. All the semiconductor chips are arranged at the corners of the grid array. However, no semiconductor chip is arranged at one corner of the lattice arrangement of the semiconductor chips.

  The thermoelectric modules according to Comparative Examples 1 to 3 described above do not satisfy all the requirements (1) to (4) described above. Therefore, high durability, high productivity, high thermoelectric effect and good appearance cannot be achieved by the thermoelectric modules according to these conventional techniques.

  In the foregoing, for the purpose of illustrating the present invention, several embodiments and examples having specific configurations have been described with reference to the accompanying drawings. However, the scope of the present invention is illustrative only. It should be understood that the present invention should not be construed as being limited to the embodiments and examples, and that modifications can be made as appropriate within the scope of the matters described in the claims and the specification.

Claims (5)

A pair of substrates facing each other;
Electrodes formed respectively at predetermined locations on opposite surfaces of the pair of substrates;
A plurality of thermoelectric elements constituted by two different types of semiconductor chips electrically connected via the electrodes formed on one substrate of the pair of substrates are formed on the other substrate of the pair of substrates. A series electric circuit formed by conducting in the same direction through the electrodes;
Two terminals for conducting both ends of the series electric circuit and the outside;
Including
In the thermoelectric module, the two different types of semiconductor chips are arranged in an odd number × odd number of lattice arrangement,
The two different types of semiconductor chips are alternately arranged in both of two orthogonal axial directions of the lattice arrangement,
Two different types of semiconductor chips constituting the thermoelectric element are adjacent in any one of two orthogonal axial directions of the grid-like arrangement,
The four semiconductor chips arranged at the four corners of the lattice-like array are all the same type,
In the central region that is not the outermost periphery of the lattice-like arrangement, the semiconductor chip is not disposed at one place where the same type of semiconductor chip as the semiconductor chip disposed at the corner is to be disposed,
Thermoelectric module. The thermoelectric module according to claim 1,
The bonding strength between the semiconductor chip and the electrode arranged at the corner of the grid array is different from that of the semiconductor chip and the electrode arranged at the corner of the grid array. Higher than bonding strength,
Thermoelectric module. The thermoelectric module according to claim 1 or 2, wherein
The mechanical strength of the semiconductor chips arranged at the corners of the grid-like array is higher than the mechanical strength of the semiconductor chips of a type different from the semiconductor chips arranged at the corners of the grid-like array,
Thermoelectric module. The thermoelectric module according to any one of claims 1 to 3, wherein
In the central region, nothing is arranged at a place where the semiconductor chip is not arranged, or a member having a thermal conductivity lower than the thermal conductivity of the semiconductor chip is arranged,
Thermoelectric module. The thermoelectric module according to any one of claims 1 to 4, wherein
The two terminals are electrically connected to end surfaces on the same substrate side of two different types of semiconductor chips out of the semiconductor chips constituting the same side of the outermost periphery of the lattice-like arrangement,
At least one of the two different types of semiconductor chips respectively connected to the two terminals is disposed at a portion other than the corners of the lattice arrangement,
Thermoelectric module.

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