JP2018128963A - Video server, broadcasting system, and method for memory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video server device, a broadcasting system, and a method for memory control which can reduce lowering of a through-put.SOLUTION: The video server according to an embodiment includes: a memory device, a server control unit, and an output unit. The memory device has a plurality of memory units. The server control unit records acquired content data into a memory unit and reads the content data. An output unit outputs content data. Each of the memory units has a first area, a second area, and a memory control unit, the first and second areas being divided by different data buses. The memory control unit allocates the first area and the second area in turn when writing data into a memory unit, and transfers writing data to one of the first and second areas in a predetermined reference period of time and reads reading data from the other area at same time.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a video server, a broadcasting system, and a memory control method.

In recent years, video servers equipped with flash memory are known. In a conventional video server, it is necessary to increase the throughput for recording and reproduction of content data such as material data. For example, within one clock of a synchronization signal, data of a data unit is included in a memory unit including a plurality of flash memories. Writing and reading were performed.
However, when the flash memory is, for example, an MLC (Multi Level Cell) NAND (Nand) flash memory, the frequency of performing the read retry process is high, so that the throughput may decrease in the conventional video server. there were.

JP2013-73669A

  The problem to be solved by the present invention is to provide a video server, a broadcasting system, and a memory control method capable of reducing a decrease in throughput.

  The video server according to the embodiment includes a memory device, an acquisition unit, a server control unit, and an output unit. The memory device has a plurality of memory units. The acquisition unit acquires content data. The server control unit records the content data acquired by the acquisition unit in the memory unit included in the memory device, and reads the content data recorded in the memory unit from the memory unit. The output unit outputs the content data read from the memory device by the server control unit. Each of the plurality of memory units has a plurality of semiconductor memories and a memory control unit. The plurality of semiconductor memories are at least a first area and a second area connected to different data buses, and transfer of write data and transfer of read data can be executed in parallel by the different data buses. It is divided into a first area and a second area. The memory control unit alternately assigns the first area and the second area when writing data to the memory unit, and sets the first area and the second area in a predetermined reference period. In parallel with transferring the write data to one of the areas, read data is read from the other area.

The block diagram which shows an example of the broadcast system and video server of embodiment. FIG. 3 is a block diagram illustrating an example of a memory unit according to the embodiment. The flowchart which shows an example of operation | movement of the video server of embodiment. 6 is a flowchart illustrating an example of write processing of the memory unit according to the embodiment. 6 is a flowchart illustrating an example of read processing of the memory unit according to the embodiment. 6 is a timing chart illustrating an example of the operation of the memory unit according to the embodiment. 6 is a timing chart illustrating an example of an operation including read retry processing of the memory unit according to the embodiment.

  Hereinafter, a video server, a broadcasting system, and a memory control method according to embodiments will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating an example of a broadcast system 1 and a video server 10 according to the present embodiment.
As shown in FIG. 1, the broadcast system 1 includes an operation terminal 2, a camera device 3, a playback deck 4, an editing device 5, a broadcast facility 6, a monitor device 7, and a video server 10.
For example, the broadcast system 1 records content data (material data) such as video data transmitted from an external device such as the camera device 3, the playback deck 4, and the editing device 5, and the recorded content data is broadcast equipment 6. Output to etc.

  The operation terminal 2 is, for example, a host control device, a maintenance terminal, or the like, and transmits various data to the video server 10 in accordance with a user operation. Here, the various data are, for example, control commands, reproduction lists, and the like. The control command is, for example, an instruction for selecting content data to be reproduced, a reproduction start instruction (on-air instruction), an end instruction (eg, reproduction end instruction), or the like.

  The camera device 3 shoots an image based on an operation by a user and records audio through a microphone (not shown). The camera device 3 generates content data by associating (synchronizing) the captured image data (video data) with the recorded audio data. The camera device 3 transmits the generated content data to the video server 10 based on an operation by the user.

  The playback deck 4 transmits content data recorded on various recording media (recording media) to the video server 10 based on an operation by the user. Here, the various recording media are, for example, a flash memory (semiconductor element memory), a tape medium, or a hard disk. The various recording media may be movie films or audio cassettes, for example. Further, the playback deck 4 may transmit the content data to the video server 10 using, for example, a baseband signal.

The editing device 5 transmits (transfers) the edited content data to the video server 10 based on an operation by the user. The editing device 5 may transmit the content data in, for example, an MXF (Material eXchange Format) file format.
In the present embodiment, the camera device 3, the playback deck 4, and the editing device 5 are examples of a transmission device that transmits content data to the video server 10.

For example, the video server 10 records (records) content data of an on-air broadcast program from a transmission device such as the camera device 3, the playback deck 4, and the editing device 5, and selectively selects the corresponding content data in accordance with an on-air instruction. Play (send). The video server 10 performs content data write control or read control in accordance with an instruction based on a user operation.
The video server 10 includes an acquisition unit 11, a memory device 12, an output unit 13, and a server control unit 14.

  For example, the acquisition unit 11 acquires content data such as a video signal transmitted from the camera device 3, the playback deck 4, the editing device 5, and the like, and executes a recording process for encoding the acquired content data. The acquisition unit 11 executes this recording process based on the control of the server control unit 14 described later, and outputs the encoded content data to the memory device 12. Here, the content data includes, for example, video data, audio data, and the like.

  The memory device 12 is a storage device that records (stores) content data based on the control of the server control unit 14. The memory device 12 includes a memory management unit 120 and a plurality of memory units 100 (100-1, 100-2,..., 100-M). Note that the memory unit 100-1, the memory unit 100-2,..., The memory unit 100-M have the same configuration and indicate any memory unit included in the video server 10 or the memory device 12, or particularly When not distinguished, the memory unit 100 will be described.

  The memory management unit 120 is, for example, a processor including a CPU (Central Processing Unit) and the like, and comprehensively controls the memory device 12. For example, the memory management unit 120 converts the content data input to the memory device 12 into recording data including the content data and an error correction code, and stores the converted recording data in the memory unit 100. Here, the error correction code is redundant data for error correction, such as a Reed-Solomon code.

For example, the memory management unit 120 reads recording data from the memory unit 100 based on the control of the server control unit 14 and converts the read recording data into content data. The memory management unit 120 outputs the read (converted) content data to the output unit 13.
The configuration of the memory unit 100 will be described later with reference to FIG.

  The output unit 13 decodes the content data read from the memory device 12 and executes a reproduction process for outputting the decoded content data (for example, a video signal). As described above, the output unit 13 outputs the content data read from the memory device 12. The output unit 13 may output the content data read from the memory device 12 by the server control unit 14 as, for example, a file.

  The server control unit 14 is a processor including a CPU, for example, and comprehensively controls the video server 10. The server control unit 14 records the content data acquired by the acquisition unit 11 in the memory unit 100 included in the memory device 12 and reads the content data recorded in the memory unit 100 from the memory unit 100.

For example, when recording the content data, the server control unit 14 instructs the acquisition unit 11 to acquire the content data and instructs the acquisition unit 11 to encode the acquired content data. Then, the server control unit 14 instructs the memory device 12 to write content data. Thereby, the server control unit 14 causes the memory unit 100 included in the memory device 12 to record the content data acquired by the acquisition unit 11.
Further, for example, when reproducing the content data, the server control unit 14 instructs the memory device 12 to read the content data, and the output unit 13 encodes the read content data. And instructing to output the decrypted content data.

  The broadcast facility 6 receives the reproduced content data from the output unit 13 of the video server 10. The broadcasting facility 6 broadcasts the reproduced content data. The broadcasting facility 6 may broadcast content data by either wired or wireless.

  The monitor device 7 receives the reproduced content data from the output unit 13 of the video server 10. The monitor device 7 displays an image as content data on the screen as a preview. The monitor device 7 may output sound as content data from a speaker (not shown).

Next, the configuration of the memory unit 100 will be described with reference to FIG.
FIG. 2 is a block diagram illustrating an example of the memory unit 100 of the present embodiment.
As shown in FIG. 2, the memory unit 100 includes a plurality of flash memories 110 (111-1, 111-2,..., 111-N, 112-1, 112-2,..., 112- N) and a memory controller 130. The flash memory 111-1, the flash memory 111-2,..., The flash memory 111-N, and the flash memory 112-1, the flash memory 112-2,. In the case where an arbitrary flash memory included in the memory unit 100 is shown or not particularly distinguished, the flash memory 110 will be described.

The flash memory 110 is, for example, an MLC type NAND flash memory LSI (large scale integration). Here, the MLC type is, for example, a type in which a plurality of levels are stored in one memory cell. In the present embodiment, the flash memory 110 is an example of a semiconductor memory.
The plurality of flash memories 110 are divided into an area A1 (first area) and an area A2 (second area).

  The area A1 has N flash memories 110 (111-1, 111-2,..., 111-N) connected to the internal address bus BS11 and the internal data bus BS21 (an example of a data bus). ing. Further, the control signal line SL11 that supplies an R / W control signal for controlling writing and reading of the flash memory 110 in the area A1 to the flash memory 110 (111-1, 111-2,..., 111-N). Is connected. Here, N is an integer of 2 or more. For example, when the flash memory 110 has data with a data width of 8 bits and N is “4”, the internal data bus BS21 is a data bus with a width of 32 bits, and each of the 8 bits out of 32 bits. A data line is connected to each flash memory 110. With the internal data bus BS21 and the internal address bus BS11, the four flash memories 110 (111-1, 111-2,..., 111-4) can be written and read in parallel (simultaneously).

  The area A2 includes N flash memories 110 (112-1, 112-2,..., 112-N) connected to the internal address bus BS12 and the internal data bus BS22 (an example of a data bus). ing. Further, the control signal line SL12 that supplies an R / W control signal for controlling writing and reading of the flash memory 110 in the area A2 to the flash memory 110 (112-1, 112-2,..., 112-N). Is connected. Here, N is an integer of 2 or more. For example, when the flash memory 110 has data with a data width of 8 bits and N is “4”, the internal data bus BS22 is a data bus with a width of 32 bits, and each of the 8 bits out of 32 bits. A data line is connected to each flash memory 110. With the internal data bus BS22 and the internal address bus BS12, the four flash memories 110 (112-1, 112-2,..., 112-4) can write and read in parallel (simultaneously).

Note that the internal address bus BS11 and the internal address bus BS12 have the same configuration, and will be described as the internal address bus BS10 when indicating an arbitrary internal address bus provided in the memory unit 100, or when not particularly distinguished. Further, the internal data bus BS21 and the internal data bus BS22 have the same configuration, and will be described as the internal data bus BS20 when indicating any internal data bus provided in the memory unit 100, or when not particularly distinguished. Further, the control signal line SL11 and the control signal line SL12 have the same configuration, and will be described as the control signal line SL10 when an arbitrary control signal line included in the memory unit 100 is shown or not particularly distinguished.
In the example shown in FIG. 2, for convenience of explanation, one set of area A1 and area A2 is described. However, the flash memory 110 includes a plurality of sets similar to area A1 and area A2. It shall be.

  As described above, the plurality of flash memories 110 (semiconductor memories) are divided into an area A1 (first area) and an area A2 (second area) connected to at least different internal data buses BS20 (BS21, BS22). Has been. In areas A1 and A2, the transfer of write data and the transfer of read data can be executed in parallel by different internal data buses BS20 (BS21, BS22).

  The memory controller 130 controls writing and reading of data with respect to the plurality of flash memories 110 included in the memory unit 100. The memory controller 130 is an integrated circuit such as an FPGA (Field Programmable Gate Array). An external address bus BS30 and an external data bus BS40 are connected between the memory controller 130 and the memory management unit 120. The memory controller 130 receives a synchronization signal (for example, CLK (clock (clock)) from the memory management unit 120. ) Signal). In the present embodiment, the memory controller 130 is an example of a memory control unit.

  For example, when writing data to the memory unit 100, the memory controller 130 alternately allocates the areas A1 and A2 and, during a predetermined reference period, one of the areas A1 and A2 (for example, the area A1) ) To transfer the write data. The memory controller 130 reads the read data from the other area (for example, area A2) in parallel with the transfer of the write data to one area (for example, area A1). Here, the predetermined reference period is one cycle period (1 CLK period) of the synchronization signal described above.

  For example, the memory controller 130 acquires recording data from the memory management unit 120, divides the recording data into N data, and divides the divided N data into N flash memories in the area A1 or the area A2. 110 is stored. For example, when the recording data is stored in the flash memory 110 in the area A1, the memory controller 130 stores the next recording data in the flash memory 110 in the area A2 in the next writing. Further, for example, when recording data is stored in the flash memory 110 in the area A2, the memory controller 130 stores the next recording data in the flash memory 110 in the area A1 in the next writing. As described above, the memory controller 130 alternately allocates the areas A1 and A2 when writing data to the memory unit 100.

For example, the memory controller 130 can read the recording data from the flash memory 110 in the area A2 in parallel while the recording data is stored in the flash memory 110 in the area A1. For example, the memory controller 130 can read the recording data from the flash memory 110 in the area A1 in parallel while the recording data is stored in the flash memory 110 in the area A2.
In addition, the memory controller 130 determines the same reference period as the reading when there is an error that cannot be corrected in the read data (for example, recording data) in the predetermined reference period (for example, 1 CLK period). The read retry process for reading the read data again is executed.

  The memory controller 130 includes a read / write control processing unit 131, an error correction processing unit 132, and a read retry processing unit 133. Note that the memory controller 130 performs a PLL (Phase Locked) that multiplies the synchronization signal (CLK signal) in order to execute read processing, error determination processing, error correction processing, and read retry processing within the same predetermined reference period. Loop) circuit may be provided.

  The read / write control processing unit 131 acquires recording data from the memory management unit 120 via the external address bus BS30 and the external data bus BS40, and divides the recording data into N pieces of data. The read / write control processing unit 131 stores the divided N divided data in the N flash memories 110 in the area A1 or the area A2. The read / write control processing unit 131 alternately allocates the areas A1 and A2 when writing data to the memory unit 100.

  Further, the read / write control processing unit 131 reads the divided data from the other area in parallel with transferring the write data to the one area. The read / write control processing unit 131 integrates the read divided data to generate recording data. The read / write control processing unit 131 supplies the recording data to an error correction processing unit 132, which will be described later, and whether or not the read recording data has an error and whether or not the recording data can be corrected. Is obtained from the error correction processing unit 132.

If there is no error in the read recording data, the read / write control processing unit 131 outputs the recording data to the memory management unit 120 via the external data bus BS40. In addition, when the recording data can be corrected, the read / write control processing unit 131 acquires the corrected recording data from the error correction processing unit 132, and the acquired recording data is transmitted to the external data bus. The data is output to the memory management unit 120 via the BS 40. In addition, when the recording data cannot be corrected, the read / write control processing unit 131 performs recording data obtained by integrating the divided data read by the read retry processing unit 133 described later by executing the read retry processing. The data is output to the memory management unit 120 via the external data bus BS40.
The read / write control processing unit 131 acquires, for example, recording data for writing in the first half of a predetermined reference period via the external data bus BS40, and reads out in the second half of the predetermined reference period. The recorded data is output to the memory management unit 120.

  The error correction processing unit 132 determines whether there is an error in the recording data acquired from the read / write control processing unit 131. For example, the error correction processing unit 132 determines whether there is an error in the acquired recording data based on the content data and the error correction code included in the recording data. Further, when there is an error in the acquired recording data, the error correction processing unit 132 determines whether or not the recording data can be corrected. If the recording data can be corrected, the error correction processing unit 132 outputs the error-corrected recording data together with the determination result to the read / write control processing unit 131.

Further, if the recording data cannot be corrected, the error correction processing unit 132 outputs the determination result to the read / write control processing unit 131 and causes the read retry processing unit 133 to execute read retry processing. .
Further, the error correction processing unit 132 outputs the determination result to the read / write control processing unit 131 when there is no error in the acquired recording data.

  The read retry processing unit 133 executes read retry processing for rereading the recording data when the error correction processing unit 132 determines that the recording data cannot be corrected. The read retry processing unit 133 rereads the divided data corresponding to the same area and address as the previously read area and address. For example, the read retry processing unit 133 generates recording data by integrating the re-read divided data, and supplies the recording data to the read / write control processing unit 131.

Next, the operation of the video server 10 according to the present embodiment will be described with reference to the drawings.
FIG. 3 is a flowchart showing an example of the operation of the video server 10 of the present embodiment.
In FIG. 3, the video server 10 first receives content data (step S101). For example, the acquisition unit 11 of the video server 10 acquires content data such as a video signal transmitted from the camera device 3, the playback deck 4, the editing device 5, and the like, and performs a recording process for encoding the acquired content data. Run.

  Next, the server control unit 14 of the video server 10 stores the content data in the memory device 12 (step S102). For example, the memory management unit 120 of the memory device 12 converts the encoded content data input from the acquisition unit 11 to the memory device 12 into recording data including the content data and an error correction code, and converts the recorded data. Data is stored in the memory unit 100. For example, the memory management unit 120 stores recording data in one memory unit 100 of the plurality of memory units 100 (100-1, 100-2,..., 100-M).

  Next, the server control unit 14 receives a reproduction list from the operation terminal 2 (step S103). Here, the reproduction list includes, for example, information in which identification information of content data to be reproduced is associated with reproduction start time information.

  Next, the server control unit 14 reads the content data from the memory device 12 based on the reproduction list acquired from the operation terminal 2 (step S104). For example, the memory management unit 120 of the memory device 12 reads the recording data from the memory unit 100 according to the reproduction start time information based on the control according to the reproduction list of the server control unit 14, and reads the recorded recording data. Convert to content data. The memory management unit 120 outputs the read (converted) content data to the output unit 13.

  Next, the output unit 13 of the video server 10 reproduces the content data (step S105). The output unit 13 decodes the content data read from the memory device 12 and executes a reproduction process for outputting the decoded content data (for example, a video signal). The output unit 13 outputs the content data read from the memory device 12 to, for example, the broadcasting facility 6. Moreover, the server control part 14 complete | finishes a process after the process of step S105.

  In the example shown in FIG. 3 described above, the video server 10 stores the content data in the memory device 12, and then reads the content data from the memory device 12 based on the reproduction list and outputs the content data. However, the present invention is not limited to this. For example, the video server 10 may execute a process of reading content data from the memory device 12 while storing the content data in the memory device 12. In other words, the memory device 12 may execute content data writing processing and reading processing in parallel.

Next, the writing process of the memory unit 100 will be described with reference to FIG.
FIG. 4 is a flowchart showing an example of the writing process of the memory unit 100 of the present embodiment.
As shown in FIG. 4, the memory controller 130 of the memory unit 100 first acquires recording data from the external data bus BS40 (step S201). That is, the memory controller 130 acquires recording data from the memory management unit 120 of the memory device 12 via the external data bus BS40.

  Next, the memory controller 130 divides the recording data into N pieces of divided data, and alternately assigns the data to the first area (for example, area A1) and the second area (for example, area A2). The pieces of divided data are written to the flash memory 110 (step S202). That is, the read / write control processing unit 131 of the memory controller 130 acquires recording data from the memory management unit 120 via the external address bus BS30 and the external data bus BS40, and divides the recording data into N divided data. To do. The read / write control processing unit 131 stores the divided N divided data in the N flash memories 110 in the area A1 or the area A2. The read / write control processing unit 131 alternately allocates the areas A1 and A2 when writing data to the memory unit 100.

  For example, when the read / write control processing unit 131 stores N pieces of divided data in the flash memory 110 (111-1, 111-2,..., 111-N) in the area A1, the next write operation is performed. Then, the next recording data is stored in the flash memory 110 in the area A2. That is, in this case, the read / write control processing unit 131, for example, in the next predetermined reference period (1CLK period), the flash memory 110 (112-1, 112-2,..., 112-N) in the area A2. The next recording data is stored in.

In addition, the read / write control processing unit 131 stores the N divided data in the flash memory 110 (112-1, 112-2,..., 112-N) in the area A2 in the next writing. The next recording data is stored in the flash memory 110 in the area A1. That is, in this case, the read / write control processing unit 131, for example, in the next predetermined reference period (1CLK period), the flash memory 110 (111-1, 111-2,..., 111-N) in the area A1. The next recording data is stored in.
As described above, when writing data to the memory unit 100, the memory controller 130 (read / write control processing unit 131) alternately assigns the areas A1 and A2 and completes the recording (recording) of all the content data. The process of storing the recording data is repeated. After the process of step S202, the read / write control processing unit 131 ends the write process of the memory unit 100.

Next, the reading process of the memory unit 100 will be described with reference to FIG.
FIG. 5 is a flowchart illustrating an example of a read process of the memory unit 100 according to the present embodiment.
As shown in FIG. 5, the memory controller 130 of the memory unit 100 first reads N pieces of divided data corresponding to the external address bus BS30 (step S301). That is, the read / write control processing unit 131 of the memory controller 130 selects an area corresponding to the acquired address, outputs an address corresponding to the internal address bus BS10 of the selected area, and via the internal address bus BS10, N pieces of divided data are read from N pieces of flash memories 110.

  Next, the read / write control processing unit 131 integrates N pieces of divided data to generate recording data (step S302). The read / write control processing unit 131 outputs recording data obtained by integrating the N divided data to the error correction processing unit 132.

  Next, the error correction processing unit 132 of the memory controller 130 determines whether or not there is an error in the recording data (step S303). For example, the error correction processing unit 132 determines whether or not there is an error in the recording data based on the content data and the error correction code included in the recording data. If there is an error in the recording data (step S303: YES), the error correction processing unit 132 proceeds with the process to step S304. Further, when there is no error in the recording data (step S303: NO), the error correction processing unit 132 proceeds with the process to step S307.

  In step S304, the error correction processing unit 132 determines whether an error in the recording data can be corrected. For example, when the number of errors is equal to or greater than a predetermined number, the error correction processing unit 132 determines that the error in the recording data can be corrected. If the error of the recording data can be corrected (step S304: YES), the error correction processing unit 132 proceeds with the process to step S305. Further, when the error of the recording data is not correctable (step S304: NO), the error correction processing unit 132 proceeds with the process to step S306.

  In step S305, the error correction processing unit 132 performs error correction on the recording data. The error correction processing unit 132 performs error correction on the recording data by using an error correction method such as a Reed-Solomon code. The error correction processing unit 132 outputs the error-corrected recording data together with the determination result to the read / write control processing unit 131. After the process of step S305, the error correction processing unit 132 proceeds with the process to step S307.

  In step S306, the read retry processing unit 133 of the memory controller 130 executes read retry processing. That is, the read retry processing unit 133 executes read retry processing for rereading the recording data when the error correction processing unit 132 determines that the recording data cannot be corrected. The read retry processing unit 133 rereads the divided data corresponding to the same area and address as the previously read area and address. For example, the read retry processing unit 133 generates recording data by integrating the re-read divided data, and outputs the recording data to the read / write control processing unit 131.

  Next, the read / write control processing unit 131 outputs the recording data from the external data bus BS40 (step S307). That is, the read / write control processing unit 131 outputs the recording data read from the flash memory 110 to the memory management unit 120 of the memory device 12 via the external data bus BS40.

  Next, the read / write control processing unit 131 determines whether there is next recording data (step S308). When there is next recording data (step S308: YES), the read / write control processing unit 131 returns the processing to step S301 and repeats the processing from step S301 to step S307. The read / write control processing unit 131 ends the process when there is no next recording data (step S308: NO).

Note that the memory controller 130 executes the processing from step S301 to step S307 described above within one cycle period (1 CLK period) of the synchronization signal.
Further, the memory controller 130 may execute the above-described writing process of the memory unit 100 shown in FIG. 4 and the reading process of the memory unit 100 shown in FIG. 5 in parallel.

Next, with reference to FIG. 6 and FIG. 7, the operation when the writing process and the reading process of the memory unit 100 are executed in parallel will be described in detail.
FIG. 6 is a timing chart showing an example of the operation of the memory unit 100 of the present embodiment. The example illustrated in FIG. 6 illustrates an example in which the write process and the read process are executed in parallel, and the read retry process does not occur in the read process.

  In FIG. 6, items in the timing chart are “synchronization signal (CLK)” (waveform W1), “read / write control processing of area A1”, “internal data bus BS21”, “error determination of area A1, And “retry processing”, “read / write control processing of area A2”, “internal data bus BS22”, “error determination and retry processing of area A2”, and “external data bus BS40”.

“Internal data bus BS21” indicates the value of the internal data bus BS21, and “Internal data bus BS22” indicates the value of the internal data bus BS22. “External data bus BS40” indicates the value of the external data bus BS40.
In addition, in the “read / write control process for area A1” and the “read / write control process for area A2,” which of the read process and the write process is executed by the memory controller 130 for each area? Is shown.

  “Error determination and retry processing in area A1” indicates the determination result by the error correction processing unit 132 for the area A1 and whether or not the read retry processing has been executed by the read retry processing unit 133. “Error determination and retry processing in area A2” indicates the determination result by the error correction processing unit 132 for the area A2 and whether or not the read retry processing has been executed by the read retry processing unit 133. In “area A1 error determination and retry process” and “area A2 error determination and retry process”, “P” is an error that can be read or not corrected. Is shown.

  When the synchronization signal (CLK signal) rises at time T0, the read / write control processing unit 131 uses the recording data (WD1, WD2,..., WDN) acquired from the external data bus BS40 as internal data of the area A1. Output to bus BS21. Further, since the read / write control processing unit 131 sets the R / W control signal of the area A1 to a state indicating the write process, the “read / write control process of the area A1” becomes “write process”. Thereby, each of the N flash memories 110 (111-1, 111-2,..., 111-N) in the area A1 is, for example, at the falling edge of the synchronization signal (CLK) at the time T1. Data division data (WD1, WD2,..., WDN) is acquired, and the division data is stored. That is, the flash memory 111-1 stores the divided data WD1, the flash memory 111-2 stores the divided data WD2, and the flash memory 111-N stores the divided data WDN.

  When the synchronization signal (CLK signal) rises in parallel at time T0, the read / write control processing unit 131 sets the R / W control signal for area A2 to the state indicating the reading process. Thus, the “read / write control process for area A2” is the “read process”. The N flash memories 110 (112-1, 112-2,..., 112-N) in the area A2 read the stored divided data, and read the divided data (RD1, RD2,..., RDN) is output to the internal data bus BS22 in area A2. Further, the error correction processing unit 132 determines whether or not there is an error in the recording data obtained by integrating the read divided data, and whether or not the error can be corrected when there is an error. Here, the error correction processing unit 132 is an example of a case where it is determined that there is no error in the recording data or that the data can be corrected. It becomes.

  Next, when the synchronization signal (CLK signal) falls at time T1, the read / write control processing unit 131 reads the N flash memories 110 (112-1, 112-2,..., 112- in the area A2. N), the recording data (RD1, RD2,..., RDN) obtained by integrating the divided data read from N) is output to the external data bus BS40.

  When the synchronization signal (CLK signal) rises at time T2, the read / write control processing unit 131 uses the recording data (WD1, WD2,..., WDN) acquired from the external data bus BS40 as internal data in the area A2. Output to bus BS22. Further, since the read / write control processing unit 131 sets the R / W control signal for area A2 to a state indicating the write process, the “read / write control process for area A2” is “write process”. Thereby, each of the N flash memories 110 (112-1, 112-2,..., 112-N) in the area A2 is for recording at the falling edge of the synchronization signal (CLK) at time T3, for example. Data division data (WD1, WD2,..., WDN) is acquired, and the division data is stored. That is, the flash memory 112-1 stores the divided data WD1, the flash memory 112-2 stores the divided data WD2, and the flash memory 112-N stores the divided data WDN.

  When the synchronization signal (CLK) rises in parallel at time T3, the read / write control processing unit 131 sets the R / W control signal for the area A1 to a state indicating the reading process. Thus, the “read / write control process for area A1” is the “read process”. The N flash memories 110 (111-1, 111-2,..., 111-N) in the area A1 read the stored divided data, and read the divided data (RD1, RD2,..., RDN) is output to the internal data bus BS21 in area A1. Further, the error correction processing unit 132 determines whether or not there is an error in the recording data obtained by integrating the read divided data, and whether or not the error can be corrected when there is an error. Here, the error correction processing unit 132 is an example of a case where it is determined that there is no error in the recording data or that the data can be corrected. It becomes.

  Next, when the synchronization signal (CLK) falls at time T3, the read / write control processing unit 131 causes the N flash memories 110 (111-1, 111-2,..., 111-N in the area A1. The data for recording (RD1, RD2,..., RDN) obtained by integrating the divided data read out from () is output to the external data bus BS40.

The subsequent processing from time T4 to time T6 is the same as the processing from time T0 to time T2 described above, and therefore description thereof is omitted here. As described above, the read / write control processing unit 131 alternately allocates the area A1 and the area in the writing process.
Also, from time T6 to time T7, the processing from time T2 to time T4 and the processing from time T0 to time T2 are alternately repeated, and the processing from time T7 to time T9 is, for example, from time T2 to time T4. This is the same as the process.

  In addition, the memory unit 100 repeats the process (write process) from the time T0 to the time T9 until there is no more storage area in the flash memory 110 in the areas A1 and A2. When the storage area of the flash memory 110 in the area A1 and the area A2 is exhausted, the memory unit 100 performs the same group as the area A1 and the area A2 (for example, the group of the area A3 and the area A4). The same processing as in areas A1 and A2 is executed.

  For example, when the plurality of flash memories 110 are divided into six areas from area A1 to area A6, area A1, area A3, and area A5 are the first areas, area A2, area A4, Area A6 is the second area. That is, in this case, the memory unit 100 has three sets of the first area and the second area. In this case, the memory unit 100 (memory controller 130) performs the above-described processing (write processing) from time T0 to time T9, for example, a set of area A1 and area A2, a set of area A3 and area A4, and an area The process is executed in the order of a set of A5 and area A6.

  FIG. 7 is a timing chart showing an example of an operation including a read retry process of the memory unit 100 of the present embodiment. The example illustrated in FIG. 7 illustrates an example in which a write process and a read process are executed in parallel, and a read retry process occurs in the read process.

  In FIG. 7, the items in the timing chart can be the same as those in FIG. It should be noted that “E” in “area A1 error determination and retry processing” and “area A2 error determination and retry processing” indicates a case where there is an uncorrectable error. “Retry” indicates a read retry process.

Since the process from time T10 to time T12 is the same as the process from time T0 to time T2 shown in FIG. 6 described above, the description thereof is omitted here.
Further, the writing process for the area A2 from the time T12 to the time T14 is the same as the writing process for the area A2 from the time T2 to the time T4 shown in FIG.

  When the synchronization signal (CLK signal) rises in parallel at time T12, the read / write control processing unit 131 sets the R / W control signal for area A1 to the state indicating the reading process. Thus, the “read / write control process for area A1” is the “read process”. The N flash memories 110 (111-1, 111-2,..., 111-N) in the area A1 read the stored divided data, and read the divided data (RD1E, RD2E,. RDNE) is output to the internal data bus BS21 in area A1. Here, the divided data (RD1E, RD2E,..., RDNE) is divided data including an error. Further, the error correction processing unit 132 determines whether or not there is an error in the recording data obtained by integrating the read divided data, and whether or not the error can be corrected when there is an error. Here, since the error correction processing unit 132 is an example of a case where it is determined that the recording data has an error and cannot be corrected, “error determination and retry processing of area A1” is “E "

  In this case, for example, the read retry processing unit 133 executes the read retry processing at time T13. The read retry processing unit 133 rereads the divided data corresponding to the same address in the area A1. That is, the N flash memories 110 (111-1, 111-2,..., 111-N) in the area A1 read out the stored divided data and read out the divided data (RD1, RD2,... RDN) is output to the internal data bus BS21 in area A1.

  Also, at time T13, when the synchronization signal (CLK signal) falls, the read / write control processing unit 131 performs the N flash memories 110 (111-1, 111-2,. , 111-N), the recording data (RD1, RD2,..., RDN) obtained by integrating the divided data read out again is output to the external data bus BS40.

  Next, the writing process on the area A1 from the time T14 to the time T16 is the same as the writing process on the area A1 from the time T4 to the time T6 shown in FIG.

  Further, when the synchronization signal (CLK signal) rises in parallel at time T14, the read / write control processing unit 131 sets the R / W control signal of area A2 to the state indicating the reading process. Thus, the “read / write control process for area A2” is the “read process”. The N flash memories 110 (112-1, 112-2,..., 112-N) in the area A2 read the stored divided data, and read the divided data (RD1E, RD2E,..., RDNE) is output to the internal data bus BS22 in area A2. Here, the divided data (RD1E, RD2E,..., RDNE) is divided data including an error. Further, the error correction processing unit 132 determines whether or not there is an error in the recording data obtained by integrating the read divided data, and whether or not the error can be corrected when there is an error. Here, since the error correction processing unit 132 is an example of a case where it is determined that there is an error in the recording data and correction is not possible, the “error determination and retry processing of the area A2” "

  In this case, for example, at time T15, the read retry processing unit 133 executes the read retry processing. The read retry processing unit 133 rereads the divided data corresponding to the same address in the area A2. That is, the N flash memories 110 (112-1, 112-2,..., 112-N) in the area A2 read the stored divided data, and read the divided data (RD1, RD2,... RDN) is output to the internal data bus BS22 in area A2.

Further, when the synchronization signal (CLK signal) falls at time T15, the read / write control processing unit 131 performs the N flash memories 110 (112-1, 112-2,...) In the area A2 by the read retry process. , 112-N), recording data (RD1, RD2,..., RDN) obtained by integrating the divided data read again is output to the external data bus BS40.
Further, the processing from time T16 to time T19 is the same as the processing from time T6 to time T9 shown in FIG.

  As described above, the video server 10 according to the present embodiment includes the memory device 12, the acquisition unit 11, the server control unit 14, and the output unit 13. The memory device 12 has a plurality of memory units 100. The acquisition unit 11 acquires content data. The server control unit 14 records the content data acquired by the acquisition unit 11 in the memory unit 100 included in the memory device 12 and reads the content data recorded in the memory unit 100 from the memory unit 100. The output unit 13 outputs the content data read from the memory device 12 by the server control unit 14. Each of the plurality of memory units 100 includes a plurality of flash memories 110 (semiconductor memories) and a memory controller 130 (memory control unit). The plurality of flash memories 110 are a first area (for example, area A1) and a second area (for example, area A2) that are at least connected to different internal data buses BS20 (data bus), and have different internal data buses. The BS 20 divides the write data transfer and the read data transfer into a first area and a second area that can be executed in parallel. When writing data to the memory unit 100, the memory controller 130 alternately assigns the first area and the second area, and in the predetermined reference period (for example, 1 CLK period), the first area and the second area In parallel with transferring write data to one of the areas, read data is read from the other area.

  Accordingly, the video server 10 according to the present embodiment uses the first area and the second area to perform the content data writing process and the content data reading process on the memory device 12 in parallel. Can be executed. Therefore, for example, the video server 10 according to the present embodiment can execute both a normal read process and a reread read retry process in a predetermined reference period. For example, the video server 10 according to the present embodiment can reduce a decrease in throughput due to the read retry process even when an MLC NAND flash memory is used for the memory device 12. Therefore, the video server 10 according to the present embodiment can increase the throughput and reliability when, for example, an MLC NAND flash memory is used for the memory device 12.

In addition, since the video server 10 according to the present embodiment can reduce a decrease in throughput even when a read retry process occurs, for example, even when content data is transmitted to the broadcasting facility 6, the transmission is not in time. Playback never stops.
In addition, the video server 10 according to the present embodiment performs data transfer for rebuild processing (reconstruction processing) for reconstructing data when, for example, a specific memory unit 100 fails and the memory unit 100 is replaced. Similarly, a decrease in throughput can be reduced. Therefore, the video server 10 according to the present embodiment can reduce the period until recovery when the memory device 12 fails.
In addition, the video server 10 according to the present embodiment can similarly reduce a decrease in throughput in a migration process in which data is transferred to storage devices of different systems, a video server, or the like.

Further, in the present embodiment, the memory controller 130, within a predetermined reference period (for example, 1CLK period), within a predetermined reference period that is the same as the reading when there is an error that cannot be corrected in the read data. Then, retry processing (read retry processing) for reading the read data again is executed.
As a result, the video server 10 according to the present embodiment can execute both the normal reading process and the re-reading read retry process in a predetermined reference period, so that a decrease in throughput can be reduced.

In the present embodiment, each of the plurality of memory units 100 includes a plurality of sets of first areas and second areas.
As a result, the video server 10 according to the present embodiment includes a plurality of sets of the first area and the second area, thereby easily increasing the capacity of the memory unit 100 without reducing a decrease in throughput. be able to.

In the present embodiment, the output unit 13 may output the content data read from the memory device 12 by the server control unit 14 as a file.
Thereby, the video server 10 according to the present embodiment can reduce a decrease in throughput due to the read retry process even when the file is output to the outside, for example. In addition, the video server 10 according to the present embodiment can output, for example, a file corresponding to a video server of another system to the video server of another system without reducing the throughput.

In addition, the broadcasting system 1 according to the present embodiment includes the video server 10 described above, a transmission device (for example, the camera device 3, the playback deck 4, and the editing device 5) that transmits content data to the video server 10, a video server, and the like. And broadcasting equipment 6 for broadcasting the content data output from 10.
Thereby, the broadcasting system 1 according to the present embodiment has the same effect as the video server 10 described above, and can reduce a decrease in throughput due to the read retry process.

In addition, the memory control method according to the present embodiment includes a memory device 12 having a plurality of memory units 100, an acquisition unit 11 that acquires content data, and a memory unit 100 that the memory device 12 includes content data acquired by the acquisition unit 11. And a server control unit 14 that reads the content data recorded in the memory unit 100 from the memory unit 100 and an output unit 13 that outputs the content data read from the memory device 12 by the server control unit 14. A memory control method for a video server 10 comprising a memory control step. Each of the plurality of memory units 100 includes a plurality of flash memories 110. The plurality of flash memories 110 are a first area and a second area that are at least connected to different internal data buses BS20, and transfer of write data and transfer of read data are performed in parallel by different internal data buses BS20. Thus, it is divided into a first area and a second area that can be executed. In the memory control step, when the video server 10 writes data to the memory unit 100, the video server 10 alternately allocates the areas A1 and A2, and one area of the areas A1 and A2 in a predetermined reference period. In parallel with the transfer of the write data, the read data is read from the other area.
Thereby, the broadcasting system 1 according to the present embodiment has the same effect as the video server 10 described above, and can reduce a decrease in throughput due to the read retry process.

In the above embodiment, the memory controller 130 determines whether or not there is an error in the read recording data. If there is an error, the memory controller 130 executes the process of correcting the error. The form which does not process may be sufficient. In this case, the redundant data included in the recording data may be data for error detection such as parity or CRC (Cyclic Redundancy Check).
In the above-described embodiment, the read retry processing unit 133 has been described as performing one read retry process. However, the read retry process may be performed a plurality of times.

  In the above-described embodiment, the error correction processing unit 132 has been described with respect to an example in which an error correction method using Reed-Solomon codes is applied. However, the present invention is not limited to this. As the error correction code, for example, a cyclic code, a Hamming code, a BCH (Bose-Chaudhuri-Hocquenghem) code, or the like may be applied, or another error correction code may be applied.

  In the above embodiment, the memory controller 130 divides the recording data and generates the divided data. However, the memory management unit 120 may divide the data. As described above, the memory management unit 120 may execute part of the processing executed by the memory controller 130. Further, the memory controller 130 may execute part of the processing of the memory management unit 120.

In the above embodiment, the memory management unit 120 stores recording data in one memory unit 100 among the plurality of memory units 100 (100-1, 100-2,..., 100-M). Although the example to make was demonstrated, it is not limited to this. For example, the memory management unit 120 may store the divided data obtained by dividing the recording data in the plurality of memory units 100.
In the above embodiment, the memory management unit 120 and the plurality of memory units 100 (100-1, 100-2,..., 100-M) are used as memory boards (memory sets), and the memory device 12 includes a plurality of memory devices 12. The memory board (memory set) may be provided.

In the above embodiment, the video server 10 transmits (outputs) the content data to the broadcast facility 6 and the monitor device 7. However, the content data is transmitted to other devices such as video servers of other systems. You may make it transmit.
Further, in the above-described embodiment, the case where the acquisition unit 11 includes a function of encoding content data such as an acquired video signal has been described, but encoded content data may be acquired. Moreover, although the output part 13 demonstrated the case where it included the function to decode the content data (for example, video data) read from the memory device 12, you may output the encoded content data.

  In the above-described embodiment, an example in which the flash memory 110 is an MLC NAND flash memory has been described as an example of a semiconductor memory included in the memory unit 100. However, the present invention is not limited to this. The semiconductor memory included in the memory unit 100 may be an SLC (Single Level Cell) type flash memory or other rewritable semiconductor memory (for example, EEPROM, RAM, FeRAM (Ferroelectric Random Access Memory), etc.).

  According to at least one embodiment described above, the area A1 (first area) and the area A2 (second area) connected at least to different internal data buses BS20, and different internal data buses BS20, A plurality of flash memories 110 divided into an area A1 and an area A2 capable of executing write data transfer and read data transfer in parallel, and when writing data to the memory unit 100, the areas A1 and A2 And a memory controller 130 that reads the read data from the other area in parallel with the transfer of the write data to one of the areas A1 and A2 in a predetermined reference period. As a result, a decrease in throughput can be reduced.

Note that a program for realizing the function of each component included in the video server 10 in the embodiment is recorded on a computer-readable recording medium, and the program recorded on the recording medium is read into a computer system and executed. Thus, the processing in each configuration included in the video server 10 described above may be performed. Here, “loading and executing a program recorded on a recording medium into a computer system” includes installing the program in the computer system. The “computer system” here includes an OS and hardware such as peripheral devices.
Further, the “computer system” may include a plurality of computer devices connected via a network including a communication line such as the Internet, WAN, LAN, and dedicated line. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. As described above, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

  The recording medium also includes a recording medium provided inside or outside that is accessible from the distribution server in order to distribute the program. It should be noted that the program may be divided into a plurality of parts and downloaded at different timings, and the composition of the constituents of the video server 10 may be combined, or the distribution server that distributes each of the divided programs may be different. Furthermore, a “computer-readable recording medium” holds a program for a certain period of time, such as a volatile memory (RAM) inside a computer system that becomes a server or client when the program is transmitted via a network. Including things. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, what is called a difference file (difference program) may be sufficient.

  Moreover, you may implement | achieve part or all of the function mentioned above as integrated circuits, such as LSI (Large Scale Integration). Each function described above may be individually made into a processor, or a part or all of them may be integrated into a processor. Further, the method of circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. In addition, when an integrated circuit technology that replaces LSI appears due to the advancement of semiconductor technology, an integrated circuit based on the technology may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Broadcasting system, 2 ... Operation terminal, 3 ... Camera apparatus, 4 ... Playback deck, 5 ... Editing apparatus, 6 ... Broadcast equipment, 7 ... Monitor apparatus, 10 ... Video server, 11 ... Acquisition part, 12 ... Memory apparatus, DESCRIPTION OF SYMBOLS 13 ... Output part, 14 ... Server control part, 100, 100-1, 100-2, 100-M ... Memory unit, 110, 111-1, 111-2, 111-N, 112-1, 112-2, DESCRIPTION OF SYMBOLS 112-N ... Flash memory, 120 ... Memory management part, 130 ... Memory controller, 131 ... Read / write control processing part, 132 ... Error correction processing part, 133 ... Read retry processing part, A1, A2 ... Area, BS10, BS11, BS12 ... Internal address bus, BS20, BS21, BS22 ... Internal data bus, BS30 ... External address bus, BS40 ... External data bus, SL10, L11, SL12 ... control signal line

Claims (6)

A memory device having a plurality of memory units;
An acquisition unit for acquiring content data;
A server control unit that records the content data acquired by the acquisition unit in the memory unit included in the memory device and reads the content data recorded in the memory unit;
An output unit that outputs the content data read from the memory device by the server control unit,
Each of the plurality of memory units is
A first area and a second area which are at least connected to different data buses, wherein the first data area and the second data bus are capable of executing write data transfer and read data transfer in parallel by the different data bus; A plurality of semiconductor memories divided into a second area;
When writing data to the memory unit, the first area and the second area are alternately assigned, and one of the first area and the second area is assigned in a predetermined reference period. And a memory control unit for reading out the read data from the other area in parallel with the transfer of the write data. The memory control unit
The retry process for reading the read data again is performed within the predetermined reference period that is the same as the reading when there is an error that cannot be corrected in the read data that has been read in the predetermined reference period. Video server as described in Each of the plurality of memory units is
The video server according to claim 1, comprising a plurality of sets of the first area and the second area. The video server according to any one of claims 1 to 3, wherein the output unit outputs the content data read from the memory device by the server control unit as a file. The video server according to any one of claims 1 to 4,
A transmission device for transmitting the content data to a video server;
A broadcasting system for broadcasting the content data output from the video server. A memory device having a plurality of memory units; an acquisition unit for acquiring content data; and the content data acquired by the acquisition unit is recorded in the memory unit of the memory device, and the recorded in the memory unit A memory control method for a video server, comprising: a server control unit that reads content data from the memory unit; and an output unit that outputs the content data read from the memory device by the server control unit,
Each of the plurality of memory units is a first area and a second area that are at least connected to different data buses, and transfer of write data and transfer of read data are performed in parallel by the different data buses. A plurality of semiconductor memories divided into a first area and a second area that can be executed,
When writing data to the memory unit, the first area and the second area are alternately assigned, and one of the first area and the second area is assigned in a predetermined reference period. And a memory control step of reading the read data from the other area in parallel with the transfer of the write data.

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