JP2016181113A - Memory device and recording and reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device and a recording and reproducing apparatus each including a plurality of memory units each mounting a plurality of memories and capable of flexibly responding to a memory failure.SOLUTION: A memory device according to an embodiment comprises: a plurality of memory units; at least one second memory; a recording data generation unit; a recording unit; a read unit; and a restoration unit. The recording data generation unit generates, from to-be-recorded data, a plurality of pieces of recording data to be written to a plurality of first memories, as write destinations, respectively included in each memory unit. The recording unit writes the recording data to the first memories that are write destinations, respectively. The read unit reads the recording data from the first memories, respectively included in each memory unit. The restoration unit restores the to-be-recorded data from the read recording data. The recording unit writes the recording data to be written to a first memory that has failed as the write destination, to the second memory. The read unit reads the recording data from the second memory in place of the failed first memory.SELECTED DRAWING: Figure 2

Description

  Embodiments described herein relate generally to a memory device and a recording / playback device.

  There are video servers that employ flash memory as a storage medium. In such a video server, the memory unit is configured by a plurality of substrates, and the memory control unit controls these memory units, thereby improving the writing / reading speed. Further, a plurality of flash memory chips are mounted on one memory unit, and these flash memory chips are processed in parallel, thereby realizing a high throughput per memory chip.

  In such a video server, since a large number of flash memory chips are simultaneously processed in parallel, it is indispensable to cope with a failure of some flash memory chips. As a general solution, there is a method in which a surplus flash memory chip is mounted in each memory unit, and the faulty chip is replaced with a surplus flash memory chip in the same memory unit when a fault occurs. As another solution, there is a method in which the memory unit itself is made redundant, and when a failure occurs in the flash memory chip, the memory unit in which the flash memory chip in which the failure occurs is replaced with a redundant memory unit.

  However, in the former solution, it is necessary to mount an extra flash memory chip for each individual memory unit. Therefore, when a failure of a flash memory chip exceeding a surplus in the memory unit occurs in a specific memory unit, even if there is a surplus flash memory chip in another memory unit, all the faulty chips are regarded as surplus flash memory chips. It is difficult to replace. Therefore, there are cases where it is impossible to cope with a failure of the flash memory chip. In the latter solution, even if a number of failures occur in a specific memory unit, it can be replaced with another memory unit. However, when a failure occurs in a memory unit exceeding the redundant number, replacement is difficult. Therefore, even with this solution, there is a case where it is not possible to cope with a failure of the flash memory chip. Further, since the redundancy is made in units of memory units, the necessary cost may be increased.

Japanese Patent Laid-Open No. 10-161939 JP-A-5-151100

  The problem to be solved by the present invention is to provide a memory device and a recording / playback device that have a plurality of memory units each including a plurality of memories and can flexibly cope with a memory failure.

  The memory device according to the embodiment includes a plurality of memory units, one or more second memories, a recording data generation unit, a recording unit, a reading unit, and a restoration unit. The memory unit has a plurality of first memories. The recording data generation unit generates a plurality of recording data having each of a plurality of first memories included in the plurality of memory units as write destinations from the recording target data. The recording unit writes a plurality of recording data in the first memory of the writing destination. The reading unit reads recording data from each of the plurality of first memories included in each of the plurality of memory units. The restoration unit restores the recording target data from the plurality of read recording data. When the first memory fails, the recording unit writes the recording data with the failed first memory as a write destination to the second memory. The reading unit reads recording data from the second memory instead of the failed first memory.

The functional block diagram which shows the video server of embodiment. The functional block diagram which shows the memory device of the embodiment. The figure which shows the example of the error information of the embodiment. The figure which shows the example of the alternative information of the embodiment. 7 is a flowchart showing recording processing in the memory device of the embodiment. 6 is an exemplary flowchart illustrating a reproduction process in the memory device according to the embodiment. 6 is an exemplary flowchart illustrating failure determination processing in the memory device according to the embodiment; The figure which shows the example of replacement when the memory chip of one memory unit fails in the memory device of the embodiment. The figure which shows the example of replacement when the memory chip of a some memory unit fails in the memory device of the embodiment.

  Hereinafter, a memory device and a recording / playback device according to embodiments will be described with reference to the drawings.

  FIG. 1 is a functional block diagram showing the configuration of the video server 1, and only functional blocks related to this embodiment are extracted and shown. The video server 1 is an example of a recording / playback device including a memory device. In FIG. 1, the video server 1 includes a recording unit 2, a playback unit 3, a server control unit 4, and a memory device 100. For example, the video server 1 records (records) material data of an on-air broadcast program from a camera, a playback deck, a non-linear editing machine, or the like, and selectively reproduces (sends) the corresponding material data according to an on-air instruction. The video server 1 performs writing control or reading control of material data in accordance with an instruction based on a user operation.

  For example, the recording unit 2 acquires material data such as a video signal transmitted from a camera, a video deck, or the like, and executes a recording process for encoding the acquired material data. The recording unit 2 executes this recording process based on the control of the server control unit 4 described later, and outputs the encoded material data to the memory device 100. Here, the material data includes, for example, video data, audio data, and the like. In the embodiment, the recording unit 2 is an example of an acquisition unit that acquires recording target data to be recorded in the memory device 100, and the material data is an example of content data that is recording target data.

  The playback unit 3 reads and decodes the encoded material data from the memory device 100, and executes a playback process for outputting the decoded material data (for example, a video signal). Thus, the reproducing unit 3 outputs the material data read from the memory device 100. In the embodiment, the reproducing unit 3 is an example of an output unit that outputs the recording target data read from the memory device 100.

  The server control unit 4 is, for example, a processor including a CPU (Central Processing Unit) and the like, and comprehensively controls the video server 1. For example, when recording the material data, the server control unit 4 instructs the recording unit 2 to acquire the material data, and further instructs to encode the acquired material data. Then, the server control unit 4 instructs the memory device 100 to write material data. Further, for example, when reproducing the material data, the server control unit 4 instructs the memory device 100 to read the material data, and further encodes the read material data to the reproducing unit 3. It is instructed to decode the decoded data and output the decoded material data. Accordingly, the server control unit 4 performs a process of recording the material data acquired by the recording unit 2 in the memory device 100 and a process of reading the recorded material data from the memory device 100.

  The memory device 100 is a storage device that records (stores) material data based on the control of the server control unit 4. The memory device 100 includes a plurality of memory sets 5-1 to 5-P (P is an integer of 2 or more). Note that the memory sets 5-1 to 5 -P have the same configuration, and will be described as the memory set 5 when indicating any memory set included in the video server 1 or the memory device 100, or when not particularly distinguished. .

The memory set 5 includes a memory control unit 6 and a plurality of memory units 7-1, 7-2,..., 7-N (N is an integer of 2 or more). Note that the memory units 7-1 to 7-N have the same configuration, and will be described as the memory unit 7 in the case where any memory unit included in the video server 1 or the memory device 100 is shown or not particularly distinguished. . When receiving a write instruction from the server control unit 4, the memory set 5 writes the material data output from the recording unit 2 in parallel to the plurality of memory units 7 based on the control of the memory control unit 6. (Remember). Further, when receiving a read instruction from the server control unit 4, the memory set 5 reads the material data in parallel from the plurality of memory units 7 based on the control of the memory control unit 6, and reads the read material data. Output to the playback unit 3.
Here, with reference to FIG. 2, the configurations of the memory device 100 and the memory set 5 according to the present embodiment will be described in detail.

FIG. 2 is a block diagram illustrating an example of the memory device 100 according to the present embodiment.
In this figure, the memory device 100 includes a memory set 5, and as described above, the memory set 5 includes a memory control unit 6 and N memory units 7 (7-1, 7-2,... 7-N). The memory control unit 6 and each memory unit 7 are mounted on different bases, and the memory control unit 6 and each memory unit 7 are connected by a connection line. Note that the memory device 100 includes a plurality of memory sets 5, but in this drawing, the memory set 5 is simply illustrated as one memory set 5 in order to describe the configuration of the memory set 5.

  Each of the N memory units 7 has M (M is an integer of 2 or more) memory chips 71 (first memory), and can be written to and read from the plurality of memory chips 71 in parallel. Yes. Hereinafter, the m-th (m is an integer of 1 to M) memory chip 71-m included in the n-th (n is an integer of 1 to N) memory unit 7-n is referred to as a memory chip 71-mn. It describes. When the arbitrary memory chips 71-1 to 71-M included in the arbitrary memory units 7-1 to 7-N are shown or not particularly distinguished, they will be described as the memory chip 71.

  The memory control unit 6 is a processor including a CPU, for example, and controls the memory set 5 in an integrated manner. The memory control unit 6 includes a surplus memory unit 61, a storage unit 63, a recording control unit 64, a reproduction control unit 65, and a failure determination unit 66.

  The surplus memory unit 61 includes K surplus memory chips 62 (second memory) (K is an integer of 1 or more). The kth surplus memory chip 62 (k is an integer not less than 1 and not more than K) is referred to as a surplus memory chip 62-k. In the present embodiment, K <M, but K ≧ M may be acceptable. When any surplus memory chips 62-1 to 62-K are shown or not particularly distinguished, they will be described as surplus memory chips 62. The surplus memory chip 62 is used as an alternative (replacement destination) when a failure occurs in the memory chip 71.

The storage unit 63 stores error information and alternative information.
The error information is information in which normal memory chip specifying information that is information for specifying the memory chip 71 is associated with the number of occurrences of the error in the memory chip 71.
The replacement information associates the normal memory chip specifying information of the memory chip 71 determined to be faulty with the surplus memory chip specifying information that is information for specifying the surplus memory chip 62 used for the replacement of the memory chip 71. Information.

The recording control unit 64 includes a recording data generation unit 641 and a recording unit 642.
The recording data generating unit 641 distributes the material data input from the recording unit 2 to the memory set 5 to the N memory units 7 and performs parallel writing processing on the N × M recording materials. Data is generated and output to the memory units 7-1 to 7-N. For example, the recording data generating unit 641 divides the material data into a number smaller than N × M, and adds data for redundancy to the divided data to generate N × M recording data. . Note that the recording data generation unit 641 may generate N × M pieces of recording data by dividing the data generated by performing error correction coding on the material data.

  The recording unit 642 stores (records) the N × M pieces of recording data generated by the recording data generation unit 641 in parallel in the M memory chips 71 of the N memory units 7. At this time, the recording unit 642 refers to the substitute information, and specifies the data for recording to be written in the memory chip 71 indicated by the normal memory chip specifying information as the surplus memory chip specifying information associated with the normal memory chip specifying information. Write to the surplus memory chip 62 indicated by the information. Further, the recording unit 642 outputs the normal memory chip specifying information of the memory chip 71 that has failed to be written to the failure determination unit 66.

  The reproduction control unit 65 includes a reading unit 651 and a decoding unit 652 (restoring unit). The reading unit 651 reads the recording data divided from the plurality of memory units 7. At this time, the recording unit 642 refers to the substitute information and specifies the data for recording to be read from the memory chip 71 indicated by the normal memory chip specifying information as the surplus memory chip specifying information associated with the normal memory chip specifying information. Reading is performed from the surplus memory chip 62 indicated by the information.

  The decoding unit 652 decodes (restores) the material data from the recording data read by the reading unit 651 and outputs it to the reproduction unit 3. Further, when the decoding unit 652 detects the memory chip 71 in which the reading of the recording data has failed in the decoding process, the decoding unit 652 outputs the normal memory chip specifying information of the memory chip 71 to the failure determination unit 66. When the reading unit 651 can detect a failure in reading the recording data, the reading unit 651 may output the detected normal memory chip specific information of the memory chip 71 to the failure determination unit 66.

  The failure determination unit 66 receives from the recording unit 642 the normal memory chip specifying information of the memory chip 71 in which writing has failed (error). Further, the failure determination unit 66 receives the normal memory chip specifying information of the memory chip 71 that has failed to be read (error) from the decoding unit 652 (or the reading unit 651). The failure determination unit 66 updates the error information stored in the storage unit 63 based on the received normal memory chip specifying information. When the failure determination unit 66 detects, from the updated error information, the normal memory chip specifying information in which the number of error occurrences exceeds the threshold, the failure determining unit 66 determines that the memory chip 71 specified by the normal memory chip specifying information is a failure. . The failure determination unit 66 determines a surplus memory chip 62 to be used for replacement of the memory chip 71 determined to be a failure, and updates the replacement information stored in the storage unit 63.

  The surplus memory chip 62 and the memory chip 71 are electrically rewritable nonvolatile memories, for example, NAND flash memories. The surplus memory chip 62 and the memory chip 71 are examples of a semiconductor memory.

  FIG. 3 is a diagram illustrating an example of error information. The error information 81 shown in the figure is information in which the normal memory chip specifying information is associated with the number of error occurrences of the memory chip 71 specified by the normal memory chip specifying information. In the figure, the normal memory chip specifying information is indicated by a combination of the number of the memory unit 7 and the number of the memory chip 71 in the memory unit 7. A serial number may be assigned to the memory chips 71 included in the N memory units 7 and used as normal memory chip specifying information.

  FIG. 4 is a diagram illustrating an example of alternative information. The replacement information 82 shown in the figure corresponds to the normal memory chip specifying information and the surplus memory chip specifying information of the surplus memory chip 62 used in the replacement of the memory chip 71 specified by the normal memory chip specifying information. Information. In the figure, the surplus memory chip specifying information is indicated by the number of the surplus memory chip 62.

Next, the operation of the memory device 100 will be described.
FIG. 5 is a flowchart showing recording processing in the memory device 100.
The recording control unit 64 of the memory device 100 receives the write instruction from the server control unit 4. The recording data generation unit 641 generates N × M recording data from the material data input from the recording unit 2 with each of the M memory chips 71 included in each of the N memory units as a writing destination. (Step S110). The recording unit 642 refers to the substitute information stored in the storage unit 63 and determines whether there is a memory chip 71 in which a failure has occurred (step S120). If the normal memory chip specifying information is not registered in the replacement information, the recording unit 642 determines that there is no failure memory chip 71 (step S120: NO), and performs the process of step S130. That is, the recording unit 642 writes the N × M pieces of recording data generated in step S110 in parallel to the memory chip 71 of the memory unit 7 to which each of the recording data is written (step S130). ).

  On the other hand, if the normal memory chip specifying information is not registered in the replacement information, the recording unit 642 determines that there is a faulty memory chip 71 (step S120: YES), and performs the process of step S140. . That is, the recording unit 642 reads the normal memory chip specifying information and the corresponding surplus memory chip specifying information from the substitute information. The recording unit 642 specifies the memory chip 71 in which the failure has occurred based on the normal memory chip specifying information, and specifies the surplus memory chip 62 that replaces the memory chip 71 based on the surplus memory chip specifying information (step S140). . The recording unit 642 parallels the recording data to the memory chip 71 in which no failure has occurred in the memory units 7-1 to 7-N and the surplus memory chip 62 that is a substitute for the memory chip 71 in which the failure has occurred. (Step S150). In other words, the recording unit 642 writes, to the memory chip 71 that is the write destination, the record data that is written to the memory chip 71 in which the normal memory chip specifying information is not registered in the replacement information. . On the other hand, the recording unit 642 does not send, to the memory unit 7, the recording data in which the memory chip 71 in which the normal memory chip specifying information is registered as the replacement information is sent to the memory unit 7. Write to the surplus memory chip 62 instead of the chip 71.

  After the process of step S130 or after the process of step S150, the recording unit 642 determines whether there is a memory chip 71 in which writing has failed (step S160). When the recording unit 642 determines that there is no memory chip 71 in which writing has failed (step S160: NO), the process ends. On the other hand, when there is a memory chip 71 in which writing has failed (step S160: YES), the recording unit 642 outputs normal memory chip specifying information for specifying the memory chip 71 to the failure determination unit 66, and performs processing. The process ends (step S170).

FIG. 6 is a flowchart showing playback processing in the memory device 100.
The reproduction control unit 65 of the memory device 100 receives the read instruction from the server control unit 4. The reading unit 651 refers to the substitute information stored in the storage unit 63 and determines whether there is a memory chip 71 in which a failure has occurred (step S210). If the normal memory chip specifying information is not registered in the replacement information, the reading unit 651 determines that there is no faulty memory chip 71 (step S210: NO), and M of each of the N memory units. Recording data is read in parallel from the memory chips 71 (step S220).

  On the other hand, when the normal memory chip specifying information is not registered in the replacement information, the reading unit 651 determines that there is a memory chip 71 in which a failure has occurred (step S210: YES), and performs the process of step S230. . That is, the reading unit 651 reads the normal memory chip specifying information and the corresponding surplus memory chip specifying information from the substitute information. The reading unit 651 specifies the memory chip 71 in which the failure has occurred based on the normal memory chip specifying information, and specifies the surplus memory chip 62 that replaces the memory chip 71 based on the surplus memory chip specifying information (step S230). . The reading unit 651 reads the recording data in parallel from the memory chip 71 in which no failure has occurred in the memory units 7-1 to 7-N and the surplus memory chip 62 as a substitute for the memory chip 71 in which the failure has occurred. Is read (step S240).

  The decryption unit 652 decrypts the material data from the plurality of recording data read in step S220 or step S240, and outputs the material data to the reproduction unit 3 (step S250). The decryption unit 652 determines whether there is a memory chip 71 from which an error has occurred in reading (step S260). If no error is detected in the recording data in the course of the decoding process, the decoding unit 652 determines that there is no memory chip 71 that has been read out (step S260: NO), and ends the process. On the other hand, the decoding unit 652 determines that there is a memory chip 71 from which an error has occurred when the recording data having an error in the decoding process is detected (step S260: YES). The decoding unit 652 outputs the normal memory chip specifying information for specifying the memory chip 71 from which the recording data having an error is read to the failure determining unit 66, and ends the process (step S270).

FIG. 7 is a flowchart showing a failure determination process in the memory device 100.
The failure determination unit 66 receives the normal memory chip specifying information from the recording unit 642 or the reading unit 651 (step S310). The failure determination unit 66 updates the error information based on the received normal memory chip specifying information (step S320). That is, when the received normal memory chip specifying information is not registered in the error information, the failure determination unit 66 newly registers the received normal memory chip specifying information in the error information, and sets the error occurrence count “1”. Set. When the received normal memory chip specifying information has already been registered in the error information, the failure determination unit 66 sets the number of error occurrences registered corresponding to the normal memory chip specifying information to the number obtained by adding 1. Update.

  The failure determination unit 66 compares the number of error occurrences corresponding to the received normal memory chip specifying information with a threshold (step S330). If the failure determination unit 66 determines that the number of error occurrences is less than the threshold (step S330: NO), the process ends. If the failure determination unit 66 determines that the number of occurrences of the error is greater than or equal to the threshold (step S330: YES), the failure determination unit 66 determines whether the received normal memory chip specifying information has been registered in the replacement information (step S340). ). If the failure determination unit 66 determines that it has been registered in the alternative information (step S340: YES), the failure determination unit 66 ends the process.

  On the other hand, when the failure determination unit 66 determines that the received normal memory chip specifying information is not registered in the replacement information (step S340: NO), the failure determination unit 66 performs the process of step S350. That is, the failure determination unit 66 assigns a surplus memory chip 62 to be used as a substitute from the surplus memory chips 62 in which the surplus memory chip specifying information is not registered in the substitute information. The failure determining unit 66 associates the received normal memory chip specifying information with the surplus memory chip specifying information indicating the surplus memory chip 62 assigned as a substitute and registers it in the substitute information (step S350).

  Note that the memory device 100 may execute only one of the processes in steps S160 to S170 in FIG. 5 and the processes in steps S250 to S270 in FIG. That is, the memory device 100 may use only one or both of the write error to the memory chip 71 and the read error from the memory chip 71 for determining the failure.

Note that the recording data generation unit 641 may generate less than N × M recording data. For example, the recording data generation unit 641 generates N × j (j <M) pieces of recording data. The recording unit 642 stores (records) the generated N × j pieces of recording data in parallel in each of the j memory chips 71 of each of the N memory units 7 to which the recording data is written. Let At this time, the recording unit 642 writes the recording data to be written by the memory chip 71 in which the failure has occurred in the surplus memory chip 62 instead of the memory chip 71.
Further, the reading unit 651 may read the recording data from the j memory chips 71 of each of the N memory units in parallel. At this time, for the memory chip 71 in which the failure has occurred, the reading unit 651 reads the recording data from the surplus memory chip 62 that is a substitute for the memory chip 71.

Next, a specific example of redundancy by mounting excess memory in the memory control unit 6 will be described.
FIG. 8 shows an example of replacement when the memory chip 71 of one memory unit 7 in the memory device 100 fails.
The failure determination unit 66 determines that a failure has occurred because the number of errors in the memory chips 71-1-1-71-4-1 of the memory unit 7-1 has reached the threshold value. The failure determination unit 66 assigns the surplus memory chips 62-1 to 62-4 as alternative memory chips to the failed memory chips 71-1-1-1 to 71-4-1, respectively. The failure determination unit 66 writes the normal memory chip specifying information of the memory chip 71-1-1 and the surplus memory chip specifying information of the surplus memory chip 62-1 in association with each other. Similarly, the failure determining unit 66 writes the normal memory chip specifying information of the memory chip 71-2-1 and the surplus memory chip specifying information of the surplus memory chip 62-2 in association with each other, and writes them to the replacement information. The normal memory chip specifying information of 3-1 and the surplus memory chip specifying information of the surplus memory chip 62-3 are written in the substitute information in association with each other. Further, the failure determination unit 66 writes the normal memory chip specifying information of the memory chip 71-4-1 and the surplus memory chip specifying information of the surplus memory chip 62-4 in association with each other.

  When recording the material data, the recording data generation unit 641 generates N × M recording data from the material data input from the recording unit 2. The recording unit 642 refers to the replacement information, the memory chips 71-1-1 to 71-4-1 have failed, and the surplus memory chips 62-1 to 6-4 are replacement destinations (replacement). Recognize that. The recording unit 642 parallels the recording data to the memory chip 71 in which no failure has occurred in the memory units 7-1 to 7-N and the surplus memory chip 62 that is a substitute for the memory chip 71 in which the failure has occurred. Write to. In other words, the recording unit 642 sends the recording data to be written to other than the memory chips 71-1-1 to 71-4-1 to the memory chips 71 of the respective write destination memory units 7-1 to 7 -N. Write. The recording unit 642 writes the recording data to which the memory chips 71-1-1 to 71-4-1 are written into the surplus memory chips 62-1 to 62-4.

  When reproducing the material data, the reading unit 651 refers to the substitute information, the memory chips 71-1-1 to 71-4-1 have failed, and the surplus memory chips 62-1 to 6-4 are replaced. Recognize that it is the first (alternative). The reading unit 651 includes the memory chips 71 of the memory units 7-1 to 7-N other than the memory chips 71-1-1-1 to 71-4-1 and the surplus memory chips 62-1 to 62-4. Read recording data in parallel. The decoding unit 652 decodes the material data from the recording data read by the reading unit 651 and outputs it to the reproduction unit 3.

Conventionally, an excess memory chip is mounted on each of a plurality of memory units included in a memory device. For example, assume that there is a conventional memory device in which two extra memory chips are mounted in each of three memory units. On the other hand, in the present embodiment, for example, when N = 3, the surplus memory chips are not mounted in the three memory units 7 included in the memory device 100, and the six surplus memory chips 62 are provided in the memory control unit 6. Implement. In this case, the memory device 100 mounts the same number of surplus memory chips as the conventional memory device.
However, in the conventional memory device, only a failure of up to two memory chips per memory unit can be dealt with, but in the case of the memory device 100 of the present embodiment, up to six failures in one memory unit 7 can be handled. It becomes possible to respond.

FIG. 9 shows an example of replacement when the memory chips 71 of the plurality of memory units 7 in the memory device 100 fail.
The failure determination unit 66 includes the memory chip 71-1-1 of the memory unit 7-1, the memory chip 71-1-2 of the memory unit 7-2, and the memory chips 71-1-N to 7-N of the memory unit 7-N. Since the number of errors 71-4-N has reached the threshold value, it is determined that there is a failure. The failure determination unit 66 assigns the surplus memory chip 62-1 as an alternative memory chip to the memory chip 71-1-1 and assigns the surplus memory chip 62-2 as an alternative memory chip to the memory chip 71-1-2. In addition, the failure determination unit 66 assigns the surplus memory chips 62-3 to 62-6 as alternative memory chips to the memory chips 71-1-N to 71-4-N, respectively. The failure determination unit 66 writes the normal memory chip specifying information of the memory chip 71 in which the failure has occurred and the surplus memory chip specifying information of the alternative surplus memory chip 62 in association with each other and writes them in the replacement information.

  When recording the material data, the recording data generation unit 641 generates N × M recording data from the material data input from the recording unit 2. The recording unit 642 refers to the substitute information, and the memory chips 71-1-1, 71-1-2, 71-1-N to 71-4-N have failed, and the surplus memory chip 62-1 Recognize that .about.62-6 is a replacement destination (substitution). The recording unit 642 parallels the recording data to the memory chip 71 in which no failure has occurred in the memory units 7-1 to 7-N and the surplus memory chip 62 that is a substitute for the memory chip 71 in which the failure has occurred. Write to. That is, the recording unit 642 stores the recording data to be written to other than the memory chips 71-1-1, 71-1-2, 71-1 -N to 71-4 -N, and the write-destination memory unit 7. Write to each memory chip 71 of −1 to 7-N. The recording unit 642 stores the recording data to which the memory chips 71-1-1, 71-1-2, 71-1-N to 71-4-N are written as surplus memory chips 62-1 to 62-6, respectively. Write to.

  When reproducing the material data, the reading unit 651 refers to the substitute information, and the memory chips 71-1-1, 71-1-2, 71-1-N to 71-4-N have failed, It is recognized that the surplus memory chips 62-1 to 6-6 are replacement destinations (substitutions). The reading unit 651 includes the memory chips 71 of the memory units 7-1 to 7-N other than the memory chips 71-1-1, 71-1-2, 71-1-N to 71-4-N, and the surplus memory. Recording data is read in parallel from each of the chips 62-1 to 62-N. The decoding unit 652 decodes the material data from the recording data read by the reading unit 651 and outputs it to the reproduction unit 3.

As in the example described above, it is assumed that there is a conventional memory device in which two redundant memory chips are mounted in each of the three memory units. On the other hand, as in the above-described example, in the memory device 100 of the present embodiment, the surplus memory chips are not mounted on the three memory units 7 but the six surplus memory chips 62 are mounted on the memory control unit 6. . The memory device 100 is mounted with the same number of surplus memory chips as the conventional memory device.
In this case, the conventional memory device can cope with up to two failures per memory unit. However, the memory device 100 according to the present embodiment can deal with failures of up to six memory chips 71 regardless of the number of memory units. it can. Even if a failure occurs in a plurality of memory units (substrates), it is possible to cope with the failure as long as the total value of the failed memory chips 71 does not exceed the number of surplus memory chips 62. Accordingly, the degree of freedom in dealing with a failure of the memory chip is higher than that of a conventional memory device that is an alternative only in the memory unit.
Taking advantage of this high degree of freedom, even if the number of excess memory chips to be mounted on the memory control unit is reduced, it is possible to take the idea of securing redundancy that is almost the same as before.

  According to the above embodiment, the surplus memory chip 62 for replacement (for replacement) is mounted in the memory control unit 6 in advance. When a failure of the memory chip 71 occurs in the memory unit 7, the data that was to be written to the failed memory chip 71 is not sent to the memory unit 7, but the surplus mounted in the memory control unit 6. Write to the memory chip 62.

  Conventionally, the number of surplus memory chips mounted in each memory unit is the maximum simultaneous chip failure value that can be handled by one memory unit. In this embodiment, the surplus memory chips 62 are aggregated in the memory control unit 6, so that the number of surplus memory chips 62 mounted on the memory control unit 6 can be simultaneously replaced for one memory unit 7. Can be a value.

  Further, the replacement of the memory control unit 6 with the surplus memory chip 62 is not limited to the memory chip 71 of the specific memory unit 7. Therefore, even when the memory chip 71 fails in a plurality of memory units 7 at the same time, it is possible to cope with the replacement, and it is possible to use surplus memory chips more efficiently (flexibly). Therefore, even if the number of surplus memory chips is reduced as compared with the conventional method, a high failure replacement effect can be obtained.

  As described above, by replacing the failed memory chip 71 with the surplus memory chip 62 and writing data, the surplus memory chip 62 can be used efficiently. Therefore, the maximum replacement effect can be obtained with the minimum surplus memory chip, that is, with the minimum cost.

  In the above embodiment, the surplus memory unit 61 is provided in the memory control unit 6. However, the memory device 100 includes the surplus memory unit 61 (the surplus memory chip 62) in the memory unit connected to the memory control unit 6. You may comprise so that it may be provided. Even with such a configuration, the same effect as in the above embodiment can be obtained. However, in the case of the configuration including the surplus memory unit 61 in the memory control unit 6, an increase in the number of boards on which the memory unit is mounted can be suppressed, and the memory unit including the memory control unit 6 and the surplus memory unit 61 There is no need for a connecting line.

  According to at least one embodiment described above, a memory device having a plurality of memory units equipped with a plurality of memories has a surplus memory in the memory control unit, thereby flexibly responding to a failure of a part of the memory in the memory unit. can do.

Note that a program for realizing all or a part of the functions of the recording unit 2, the playback unit 3, and the server control unit 4 of the video server 1 in the embodiment is recorded on a computer-readable recording medium, and this recording is performed. The above-described processing of the video server 1 may be performed by causing a computer system to read and execute a program recorded on a medium. Here, “loading and executing a program recorded on a recording medium into a computer system” includes installing the program in the computer system. The “computer system” here includes an OS and hardware such as peripheral devices.
Further, the “computer system” may include a plurality of computer devices connected via a network including a communication line such as the Internet, WAN, LAN, and dedicated line. The “computer-readable recording medium” refers to a storage device such as a flexible medium, a magneto-optical disk, a portable medium such as a ROM and a CD-ROM, and a hard disk incorporated in a computer system. As described above, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

  The recording medium also includes a recording medium provided inside or outside that is accessible from the distribution server in order to distribute the program. It should be noted that the program may be divided into a plurality of parts and downloaded at different timings, and the composition of the video server 1 may be combined, or the distribution server that distributes each of the divided programs may be different. Furthermore, the “computer-readable recording medium” holds a program for a certain period of time, such as a volatile memory (RAM) inside a computer system that becomes a server or a client when the program is transmitted via a network. Including things. The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, what is called a difference file (difference program) may be sufficient.

  Also, some or all of the functions of the video server 1 and the memory control unit 6 described above may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each function described above may be individually made into a processor, or a part or all of them may be integrated into a processor. Further, the method of circuit integration is not limited to LSI, and may be realized by a dedicated circuit or a general-purpose processor. In addition, when an integrated circuit technology that replaces LSI appears due to the advancement of semiconductor technology, an integrated circuit based on the technology may be used.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 ... Video server, 2 ... Recording part, 3 ... Playback part, 4 ... Server control part, 5 ... Memory set, 6 ... Memory control unit, 7 ... Memory unit, 61 ... Surplus memory part, 62 ... Surplus memory chip, 63 ... storage unit, 64 ... recording control unit, 65 ... reproduction control unit, 66 ... failure determination unit, 71 ... memory chip, 641 ... recording data generation unit, 642 ... recording unit, 651 ... reading unit, 652 ... decoding unit, 100: Memory device

Claims (7)

A plurality of memory units having a plurality of first memories;
One or more second memories;
A recording data generation unit that generates a plurality of recording data with each of the plurality of first memories included in each of the plurality of memory units as write destinations from the recording target data;
A recording unit for writing a plurality of the recording data to the first memory of each writing destination;
A reading unit for reading the recording data from each of the plurality of first memories included in each of the plurality of memory units;
A restoration unit for restoring the recording target data from the plurality of recording data read by the reading unit,
When the first memory fails, the recording unit writes the recording data to the second memory with the failed first memory as a write destination,
The memory device that reads the recording data from the second memory in place of the failed first memory. A memory control unit connected to the plurality of memory units by connection lines;
The memory device according to claim 1, wherein the memory control unit includes the second memory, the recording data generation unit, the recording unit, the reading unit, and the restoration unit. A storage unit for storing replacement information indicating the second memory instead of the failed first memory;
The recording unit writes the recording data having the failed first memory as a writing destination to the alternative second memory indicated by the alternative information,
The reading unit reads the recording data from the alternative second memory indicated by the alternative information instead of the failed first memory;
The memory device according to claim 1 or 2. The recording unit writes a plurality of the recording data in parallel,
The reading unit reads a plurality of the recording data in parallel.
The memory device according to any one of claims 1 to 3.   A failure determination unit that determines the occurrence of a failure in the first memory based on one or both of the number of times that the writing of the recording data has failed and the number of times that the reading of the recording data has failed. The memory device according to any one of claims 1 to 4.   The memory device according to any one of claims 1 to 5, wherein the first memory and the second memory are semiconductor memories. A memory device according to any one of claims 1 to 6,
An acquisition unit for acquiring recording target data to be recorded in the memory device;
An output unit for outputting the recording target data read from the memory device;
Recording / playback device comprising

Images