JP2018125392A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving an electrostatic protection function without increase in layout area.SOLUTION: A semiconductor device includes: a semiconductor substrate 12; a first conductivity type first impurity region 16 which is provided in a principal surface S of the semiconductor substrate 12 and has a first impurity concentration; a first conductivity type second impurity region 14 which is provided to surround the first impurity region 16 and has a second impurity concentration lower than the first impurity concentration; and second conductivity type third impurity regions 20, 22 which are provided in the principal surface S and arranged separately from the second impurity region across a first insulation part 24-1.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device, and particularly to a semiconductor device as an electrostatic protection element that is built in a semiconductor integrated circuit and protects an internal circuit of the semiconductor integrated circuit from a surge such as ESD (Electro-Static Discharge).

  ESD generally means discharge of static electricity caused by a human body or the like. In the field of semiconductor integrated circuits, it particularly means surges that enter the inside of a semiconductor integrated circuit via external terminals of the semiconductor integrated circuit. The ESD may damage the semiconductor integrated circuit. In other words, a discharge current due to a surge applied from the outside flows in the semiconductor element inside the semiconductor integrated circuit, and the semiconductor element is damaged due to local heat generation, electric field concentration, or the like. In the case of damage due to ESD, a surge or the like reaches an internal circuit of the semiconductor integrated circuit via an input / output terminal of the semiconductor integrated circuit or an external terminal such as a power supply terminal, thereby damaging the internal circuit and Deterioration or failure occurs.

  In particular, in recent semiconductor integrated circuits represented by large scale integrated circuits (LSIs), internal elements such as transistors are increasingly becoming finer. It has become an important issue. Therefore, studies have been vigorously made from various viewpoints on an element that is built in a semiconductor integrated circuit and protects the semiconductor integrated circuit from ESD, that is, an ESD protection element.

  Conventionally, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is generally used as an ESD protection element of a semiconductor integrated circuit, but in recent years, a diode has become mainstream. In a semiconductor integrated circuit typified by an LSI, for example, a P-type transistor is implanted into a semiconductor wafer made of silicon to form a P-type transistor, and an N-type impurity is implanted to form an N-type transistor. And an N-type region, that is, a PN junction exists. By this PN junction, a so-called diode characteristic (rectifying action) is developed in which a current easily flows from the P-type region to the N-type region, but a current hardly flows from the N-type region to the P-type region. The diode ESD protection element utilizes this rectification action. In other words, an ESD protection element using a diode allows a surge current caused by ESD that has entered a semiconductor integrated circuit from a power supply terminal or an input / output terminal to flow to a power supply wiring or a substrate via a diode having directionality to the flowing current. Thus, the internal circuit of the semiconductor integrated circuit is protected.

  As a prior art of an ESD protection element using a diode, for example, an electrostatic discharge protection circuit disclosed in Patent Document 1 is known. An electrostatic discharge protection circuit according to Patent Document 1 is disposed in a semiconductor substrate at a position in contact with a first junction diode having a first conductivity type region in contact with the second conductivity type region, and on the first conductivity type region. And a first Schottky diode having a metal-based material layer. In Patent Document 1, according to the electrostatic discharge protection circuit having such a configuration, not only against an ESD surge in a high voltage region, but also by a diode pair formed by a Schottky diode and a junction diode connected in parallel. The internal circuit can be protected against an ESD surge in a low voltage range.

JP 2009-027170 A

  By the way, with the spread of small portable devices represented by smartphones and the like, there is an increasing conflicting demand for further downsizing semiconductor integrated circuits represented by LSIs and increasing resistance to ESD. On the other hand, in order to realize the performance of highly functional devices, miniaturization has progressed in the manufacturing process of LSI and the like, and the resistance to ESD has been decreasing. For example, an LSI for displaying a high-definition image on the screen of the device has a small mounting area of the device itself, so the area (layout area) of the LSI itself must be kept small. In addition, since a circuit for displaying a high-definition image is extremely complicated, a fine transistor manufactured by a state-of-the-art manufacturing process is mounted. Recent LSIs must ensure resistance to ESD under such restrictions. As a result, the realization of an ESD protection element that is smaller and has a sufficient protection function is an urgent issue.

  In this regard, the electrostatic discharge protection circuit according to Patent Document 1 uses a diode, but two types of diodes are used for the purpose of realizing an ESD protection function in a low voltage region in addition to a high voltage region. is there. Therefore, the electrostatic discharge protection circuit according to Patent Document 1 has a problem that the layout area increases.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of improving the electrostatic protection function without increasing the layout area.

  A semiconductor device according to the present invention includes a semiconductor substrate, a first impurity region of a first conductivity type having a first impurity concentration provided in a main surface of the semiconductor substrate, and the first impurity region. A second impurity region of a first conductivity type having a second impurity concentration lower than the first impurity concentration provided in a surrounding manner, and provided in the main surface, and the second impurity region and the second impurity region; And a third impurity region of the second conductivity type disposed via one insulating portion.

  According to the present invention, it is possible to provide a semiconductor device capable of improving the electrostatic protection function without increasing the layout area.

1A and 1B show an example of the configuration of a semiconductor device according to a first embodiment, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view. The operation of the semiconductor device according to the first embodiment will be described. (A) is a plan view and (b) is a cross-sectional view. It is a graph explaining the effect of the semiconductor device concerning a 1st embodiment. An example of a configuration of a semiconductor device according to a second embodiment is shown, (a) is a plan view, and (b) is a cross-sectional view. The structure of the semiconductor device which concerns on a comparative example is shown, (a) is a top view, (b) is sectional drawing.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
With reference to FIG. 1 thru | or FIG. 3, the semiconductor device 10 as an ESD protection element which concerns on this Embodiment is demonstrated. FIG. 1 is a diagram illustrating an example of the configuration of the semiconductor device 10 according to the present embodiment, FIG. 2 is a diagram illustrating the operation of the semiconductor device 10, and FIG. 3 is a diagram illustrating the effect of the semiconductor device 10. is there.

  1A is a plan view of the semiconductor device 10, and FIG. 1B is a cross-sectional view taken along line AA in FIG. 1A. As shown in FIGS. 1A and 1B, the semiconductor device 10 includes a substrate 12, an NN layer 14, an N + layer 16, a PP layer 22, a P + layer 20, insulating portions 24-1 and 24-2 ( Hereinafter, when collectively referred to as “insulating portion 24”), the electrode 18 and the electrode 26 are configured as a diode.

  As the substrate 12 according to the present embodiment, a silicon substrate is used as an example. In the present embodiment, as an example, the substrate 12 is a P-type substrate in which P-type impurities are diffused at a low concentration (denoted as “P−” in FIG. 1B). However, the type of substrate is not limited.

The N + layer 16 is a region in which N-type impurities are diffused in a high concentration in an island shape in the main surface S of the semiconductor device 10. The NN layer 14 is a region in which an N-type impurity is diffused in an island shape in the main surface S at a lower concentration than the N + layer 16. In the present embodiment, the impurity concentration of the N + layer 16 can be set to 1 × 10 ²¹ cm ⁻³ as an example, and the impurity concentration of the NN layer 14 can be set to 1 × 10 ¹⁸ cm ⁻³ as an example. N-type impurities are not particularly limited. In the semiconductor device 10 according to the present embodiment, the NN layer 14 is disposed so as to surround the N + layer 16. In other words, the NN layer 14 is arranged so as to include the N + layer 16 both in a plan view shown in FIG. 1A and in a cross-sectional view shown in FIG. The N + layer 16 and the NN layer 14 constitute an N-type region of a diode as an electrostatic protection element.

  The electrode 18 shown in FIG. 1B is made of tungsten (W), for example, and functions as an N-side electrode of the diode.

On the other hand, the P + layer 20 is a region in which P-type impurities are diffused at a high concentration in the main surface S of the semiconductor device 10. The PP layer 22 is a region formed immediately below the P + layer 20 in which P-type impurities are diffused at a lower concentration than the P + layer 20. In the present embodiment, the impurity concentration of the P + layer 20 can be set to 1 × 10 ²¹ cm ⁻³ as an example, and the impurity concentration of the PP layer 22 can be set to 1 × 10 ¹⁸ cm ⁻³ as an example. Moreover, it does not specifically limit as a P-type impurity, For example, B (boron) can be used. As shown in FIG. 1A, the P + layer 20 and the PP layer 22 are formed in a ring shape so as to surround the island-shaped N + layer 16 and the NN layer 14. The P + layer 20 and the PP layer 22 constitute a P-type region of a diode as an electrostatic protection element.

  The electrode 26 shown in FIG. 1A is made of tungsten (W), for example, and functions as a P-side electrode of the diode.

As shown in FIGS. 1A and 1B, the insulating portion 24-1 is formed surrounding the NN layer 14 so as to separate the NN layer 14 from the P + layer 20 and the PP layer 22. . The insulating portion 24-2 is formed so as to surround the P + layer 20 and the PP layer 22 so as to separate the P + layer 20 and the PP layer 22 from the surroundings. In the present embodiment, the insulating portion 24 is a silicon oxide film (SiO ₂ film) formed by an STI (Shallow Trench Isolation) method as an example. However, the present invention is not limited to this, and a silicon oxide film formed by another method, for example, a LOCOS (Local Oxidation of Silicon) method may be used.

In the semiconductor device 10 having the above configuration, a PN junction (junction) PN1 is formed at the interface between the P− region of the substrate 12 and the NN layer 14, and exhibits a rectifying action as a diode.
The semiconductor device 10 is formed in a semiconductor integrated circuit as a part of a semiconductor integrated circuit (not shown). For example, the electrode 26 is connected to the potential of the substrate 12 of the semiconductor integrated circuit, and the electrode 18 is an input / output terminal of the semiconductor integrated circuit. Connected to. In this case, the negative pulsed ESD that has entered the input / output terminal or the like flows through the path of the electrode 26 → PN junction PN1 → electrode 18, that is, the diode flows in the forward direction and is connected to the input / output terminal or the like. The circuit is protected.

  Hereinafter, the operation and effect of the semiconductor device 10 will be described in more detail with reference to FIGS. 2 and 3, but the semiconductor device 100 according to the comparative example will be described in advance with reference to FIG. 5.

  5A is a plan view of the semiconductor device 100, and FIG. 5B is a cross-sectional view taken along the line CC in FIG. 5A. As shown in FIGS. 5A and 5B, the semiconductor device 100 includes a substrate 102, an NN layer 104, an N + layer 106, a PP layer 112, a P + layer 110, insulating portions 114-1, 114-2, A diode including the electrode 108 and the electrode 116 is configured.

  The substrate 102 is a P-substrate. The N + layer 106 is a region where an N-type impurity is diffused at a high concentration. The NN layer 104 is a region formed immediately below the N + layer 106 in which N-type impurities are diffused at a lower concentration than the N + layer 106. In the semiconductor device 100, the NN layer 14 is disposed almost only below the N + layer 16. That is, as shown in FIG. 5B, in the semiconductor device 100, the insulating portion 114-1 and the N + layer 106 are disposed in contact with or substantially in contact with each other. In the semiconductor device 100, the width d13 of the insulating portion 114-1 in a plan view is about 2 μm.

  In the semiconductor device 100 having the above structure, the PN junction PN3 is formed at the interface between the p− region of the substrate 102 and the NN layer 104. When the surge current Is3 due to ESD enters from the electrode 116, the surge current Is3 is, as shown in FIG. 5B, the P + layer 110 → the PP layer 112 → the P− region of the substrate 102 → the NN layer 104 → N +. It flows to the electrode 108 through the path of the layer 106. That is, the surge current Is3 flows so as to bypass the insulating part 114-1 having a width of about 2 μm, and the main path of the surge current Is3 is a path along the insulating part 114-1. Therefore, in addition to the entire area S3 in plan view of the PN junction PN3, the distance d14 from the end of the N + layer 106 to the contact point P3 between the insulating portion 114-1 and the PN junction PN3 in sectional view, N + in plan view The distance d15 from the end of the layer 106 to the contact P3 and the substrate-side width d16 of the insulating portion 114-1 mainly affect the ESD protection function of the semiconductor device 100.

  With reference to FIG. 2, the operation of the semiconductor device 10 will be described in comparison with the semiconductor device 100 described above. As compared with the semiconductor device 100, the element shape (size) of the semiconductor device 10 is such that the planar view outline of the N + layer 16 is substantially equal to the planar view outline of the N + layer 106, and the outer periphery of the insulating portion 24-1 is the insulating portion 114. -1 is substantially equal to the outer periphery of the insulating portion 24-2, and the outer periphery and thickness of the insulating portion 24-2 are substantially equal to the outer periphery and thickness of the insulating portion 114-2. In addition, the width d3 of the insulating portion 24-1 in plan view is set to about 1 μm, which is half of the width d13 of the insulating portion 114-1 of the semiconductor device 100 in plan view. Accordingly, the distance d1 between the outer side of the insulating part 24-1 and the outer periphery of the N + layer 16 is substantially equal to the distance d13 between the outer side of the insulating part 114-1 of the semiconductor device 100 and the outer periphery of the N + layer 106. ing. Therefore, in the semiconductor device 100, the distance between the inner side of the insulating portion 114-1 and the outer periphery of the N + layer 106 is substantially 0. However, in the semiconductor device 10, the inner side of the insulating portion 24-1 and the N + layer 16. The distance d2 between the outer periphery and the outer periphery is about 1 μm.

As a result, the form of the semiconductor device 10 compared with the form of the semiconductor device 100 has the following characteristics.
(Feature 1) The area S1 in plan view of the entire PN junction PN1 is larger than the area S3 in plan view of the entire PN junction PN3 in the semiconductor device 100 (S1> S3). In other words, the area of the NN layer 14 in plan view is larger than the area of the NN layer 104 of the semiconductor device 100.
(Characteristic 2) The distance d4 from the end of the N + layer 16 to the contact P1 between the insulating part 24-1 and the PN junction PN1 is larger than the distance d14 corresponding to the distance d4 in the semiconductor device 100 (d4). > D14).
(Feature 3) The distance d5 from the end of the N + layer 16 to the contact P1 in plan view is larger than the distance d15 corresponding to the distance d5 in the semiconductor device 100 (d5> d15).
(Feature 4) The substrate-side width d6 of the insulating portion 24-1 is larger than the substrate-side width d16 of the insulating portion 114-1 of the semiconductor device 100 (d6> d16, approximately twice).

  Here, the surge current Is1 due to ESD that has entered the input / output terminal or the like of the semiconductor device 10 flows through the path of the electrode 26 → the PN junction PN1 → the electrode 18, as in the semiconductor device 100. That is, as shown in FIG. 2, the surge current Is1 due to ESD flows through the path of electrode 26 → P + layer 20 → PP layer 22 → P− region of substrate 12 → NN layer 14 → N + layer 16 → electrode 18. . At this time, since the semiconductor device 10 has the above characteristics, the electrostatic protection function against the surge current Is1 compared to the semiconductor device 100 is improved.

  That is, since the amount of current that can be passed through the semiconductor device 10 as the electrostatic protection element via the PN junction PN1 is increased by having (Feature 1), the electrostatic protection compared with the semiconductor device 100 is achieved. The function has been improved. By having (Characteristic 2), the magnitude of the electric field applied to the NN layer 14 is alleviated, so that the breakdown voltage in the reverse direction is improved, and in particular, the vicinity of the contact P1 is hardly broken. Further, the amount of current that can be passed through the semiconductor device 10 is also increasing. Thereby, the electrostatic protection function compared with the semiconductor device 100 is improved.

  In addition, since (feature 3) is provided, the current that can be supplied to the semiconductor device 10 is increased. Further, it is possible to suppress the surge current Is1 from being concentrated particularly near the contact P1. Therefore, the vicinity of the contact P1 is particularly difficult to be destroyed. Thereby, the electrostatic protection function compared with the semiconductor device 100 is improved. (Characteristic 4), when the surge current Is1 flows around the insulating portion 24-1, the path length flowing through the P− region of the substrate 12 corresponds to the path length in the semiconductor device 100. It is shorter than the length to be. For this reason, the resistance value of the resistor connected in series to the semiconductor device 10 (on-resistance (forward resistance) Ron of the semiconductor device 10 as a diode) is small. As a result, the amount of current that can flow in the semiconductor device 10 is increased compared to the semiconductor device 100 and the heat generated in the semiconductor device 10 is also reduced, so that the electrostatic protection function compared to the semiconductor device 100 is improved. doing.

  Next, the effect of the semiconductor device 10 will be described with reference to FIG. FIG. 3 is a graph in which samples of the semiconductor device 10 according to the present embodiment and the semiconductor device 100 according to the comparative example are actually manufactured, and current-voltage characteristics of the samples are plotted and compared. Here, the voltage on the horizontal axis is a voltage applied to the semiconductor device 10 or the semiconductor device 100, and the vertical axis is a measurement value obtained by measuring the current flowing through the semiconductor device 10 or the semiconductor device 100 at the applied voltage. In FIG. 3, the curve C <b> 1 indicates the current-voltage characteristics of the semiconductor device 10, and the curve C <b> 2 indicates the current-voltage characteristics of the semiconductor device 100.

  As apparent from comparison between the curves C1 and C2 shown in FIG. 3, the semiconductor device 10 has an increased amount of current that can be applied to the same applied voltage as compared to the semiconductor device 100. For example, for an applied voltage of 6 V, the current that can be passed through the semiconductor device 100 is about 5.6 A, whereas the current that can be passed through the semiconductor device 10 is about 7.1 A. Here, the straight line L1 shown in FIG. 3 represents the approximate line of the curve C1, and the straight line L2 represents the approximate line of the curve C2. The slope of the straight line L1 or the straight line L2 in terms of the voltage / current is the semiconductor device 10 or the semiconductor. This corresponds to the on-resistance Ron in the diode characteristics of the device 100. As apparent from FIG. 3, the on-resistance Ron1 obtained from the slope of the straight line L1 is smaller than the on-resistance Ron2 obtained from the slope of the straight line L2. This is mainly due to the above (feature 4) of the semiconductor device 10. As described above, since the semiconductor device 10 includes the above (feature 1) to (feature 4), the amount of current that can flow is increased and the on-resistance Ron is also reduced as compared with the semiconductor device 100. Thus, the electrostatic protection function is improved.

  As described above in detail, according to the semiconductor device 10 according to the present embodiment, it is possible to provide a semiconductor device capable of improving the electrostatic protection function without increasing the layout area. .

[Second Embodiment]
With reference to FIG. 4, a semiconductor device 50 as an ESD protection element according to the present embodiment will be described. FIG. 4A is a plan view showing an example of the configuration of the semiconductor device 50, and FIG. 4B shows a cross-sectional view taken along line BB in FIG. 4A. The semiconductor device 50 is a form in which the P-type and the N-type are interchanged in the semiconductor device 10. That is, as shown in FIGS. 4A and 4B, the semiconductor device 50 includes a substrate 52, a PP layer 54, a P + layer 56, an NN layer 62, an N + layer 60, and insulating portions 64-1, 64--. 2 (hereinafter collectively referred to as “insulating portion 64”), an electrode 58, and an electrode 66.

  As the substrate 52, a P-substrate made of silicon is used as in the semiconductor device 10. However, in the semiconductor device 50, the P-type and the N-type are interchanged with respect to the semiconductor device 10, so that the semiconductor device 50 has an N-well 68, a P-type region (P + layer 56, PP layer 54), and an N-type region (N + layer 60). , NN layer 62) is formed inside N well 68. The N well 68 is an N type well layer formed by diffusing N type impurities in the main surface S of the substrate 52.

The P + layer 56 is a region in which P-type impurities are diffused in an island shape at a high concentration in the main surface S of the semiconductor device 10. The PP layer 54 is a region in which P-type impurities are diffused in the main surface S at a lower concentration than the P + layer 56. In the present embodiment, the impurity concentration of the P + layer 56 may be 1 × 10 ²¹ cm ⁻³ as an example, and the impurity concentration of the PP layer 54 may be 1 × 10 ¹⁸ cm ⁻³ as an example. Moreover, it does not specifically limit as a P-type impurity, For example, B (boron) can be used. Similarly to the semiconductor device 10, the semiconductor device 50 is also arranged so that the PP layer 54 surrounds the P + layer 56. That is, the PP layer 54 is disposed so as to include the P + layer 56 in both the plan view shown in FIG. 4A and the cross-sectional view shown in FIG. The P + layer 56 and the PP layer 54 constitute a P-type region of a diode as an electrostatic protection element.

  The electrode 58 shown in FIG. 4B is made of tungsten (W), for example, and functions as a P-side electrode of the diode.

On the other hand, the N + layer 60 is a region in which N-type impurities are diffused at a high concentration in the main surface S of the semiconductor device 50. The NN layer 62 is a region in which an N-type impurity formed immediately below the N + layer 60 is diffused at a lower concentration than the N + layer 60. In the present embodiment, the impurity concentration of the N + layer 60 can be set to 1 × 10 ²¹ cm ⁻³ as an example, and the impurity concentration of the NN layer 62 can be set to 1 × 10 ¹⁸ cm ⁻³ as an example. The N-type impurity is not particularly limited, and for example, P (phosphorus) can be used. As shown in FIG. 4A, the N + layer 60 and the NN layer 62 are formed in a ring shape so as to surround the island-shaped P + layer 56 and the PP layer 54. The N + layer 60 and the NN layer 62 constitute an N-type region of a diode as an electrostatic protection element.

  The electrode 66 shown in FIG. 4A is made of tungsten (W), for example, and functions as an N-side electrode of the diode.

  As shown in FIGS. 4A and 4B, the insulating portion 64-1 is formed surrounding the PP layer 54 so as to separate the PP layer 54 from the N + layer 60 and the PP layer 62. . The insulating portion 64-2 is formed surrounding the N + layer 60 and the NN layer 62 so as to separate the N + layer 60 and the NN layer 62 from the surroundings. As an example, the insulating portion 64 according to the present embodiment is a silicon oxide film formed by the STI method or the LOCOS method.

  In the semiconductor device 50 having the above configuration, a PN junction (junction) PN2 is formed at the interface between the N region of the N well 68 and the PP layer 54, and exhibits a rectifying action as a diode. The semiconductor device 50 is formed in a semiconductor integrated circuit as part of a semiconductor integrated circuit (not shown). For example, the electrode 66 is connected to the potential of the N well 68 of the semiconductor integrated circuit, and the electrode 58 is an input / output terminal of the semiconductor integrated circuit. Connected to etc. In this case, the positive pulsed ESD that has entered the input / output terminal flows through the path of the electrode 58 → PN junction PN2 → electrode 66, that is, flows in the forward direction of the diode and is connected to the input / output terminal and the like. The circuit is protected. That is, as shown in FIG. 4B, the surge current Is2 due to ESD flows through the path of electrode 58 → P + layer 56 → PP layer 54 → N well 68 → NN layer 62 → N + layer 60 → electrode 66.

  The distance d7, the distance d8, the width d9, the distance d10, the distance d11, the width d12, and the contact P2 shown in FIGS. 4A and 4B are the distance d1 and the distance d2 shown in FIGS. 1A and 1B, respectively. , Width d3, distance d4, distance d5, width d6, and contact P1. Further, the entire area S2 of the PN junction PN2 of the semiconductor device 50 is substantially equal to the entire area S1 of the PN junction PN1 of the semiconductor device 10. Therefore, since the semiconductor device 50 includes the above (feature 1) to (feature 4) as in the semiconductor device 10, the amount of current that can be passed is increased and the on-resistance Ron is also reduced as compared with the semiconductor device 100. Thus, the electrostatic protection function is improved. As a result, the semiconductor device 50 according to the present embodiment also provides an effect that it is possible to provide a semiconductor device capable of improving the electrostatic protection function without increasing the layout area.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 12 Board | substrate 14 NN layer 16 N + layer 18 Electrode 20 P + layer 22 PP layer 24, 24-1, 24-2 Insulation part 26 Electrode 50 Semiconductor device 52 Substrate 54 PP layer 56 P + layer 58 Electrode 60 N + layer 62 NN Layers 64, 64-1, 64-2 Insulating portion 66 Electrode 68 N well 100 Semiconductor device 102 Substrate 104 NN layer 106 N + layer 108 Electrode 110 P + layer 112 PP layer 114-1, 114-2 Insulating portion 116 Electrodes Is1, Is2 , Is3 Surge current PN1, PN2, PN3 PN junction S Main surface

Claims (6)

A semiconductor substrate;
A first impurity region of a first conductivity type having a first impurity concentration provided in a main surface of the semiconductor substrate;
A second impurity region of a first conductivity type having a second impurity concentration lower than the first impurity concentration provided surrounding the first impurity region;
A third impurity region of a second conductivity type provided in the main surface and disposed via the second impurity region and the first insulating portion;
A semiconductor device including: The semiconductor device according to claim 1, wherein the first insulating portion is provided in the main surface and is disposed so as to surround the second impurity region. The semiconductor device according to claim 1, further comprising a second insulating portion that is disposed so as to surround the third impurity region and is provided in the main surface. The third impurity region includes a fourth impurity region having a third impurity concentration, and a fourth impurity concentration having a fourth impurity concentration lower than the third impurity concentration disposed below the fourth impurity region. 5. The semiconductor device according to claim 1, comprising five impurity regions. 5. The semiconductor device according to claim 1, wherein the semiconductor substrate is P-type, the first conductivity type is N-type, and the second conductivity type is P-type. The semiconductor substrate is P-type and includes an N-type region provided in the main surface;
The first conductivity type is P-type, the second conductivity type is N-type,
5. The semiconductor device according to claim 1, wherein the first impurity region, the second impurity region, and the third impurity region are disposed inside the N-type region. 6. .