JP2018107585A - Oscillator - Google Patents

Abstract

To provide a technology capable of switching an oscillation frequency to a designated frequency at a high speed and improving phase noise characteristics when a frequency designation signal is received from the outside in an oscillation device using a PLL. . A loop filter 4 that operates by digital processing is used as a loop filter of the PLL circuit 1, and a parameter value that determines the operating characteristics of the loop filter is good as the first parameter value to lock the PLL circuit 1 at high speed. The second parameter value that provides a good phase noise characteristic is stored in the storage unit 20 in association with the frequency. When the frequency is designated from the outside, the first parameter value and the second parameter value are read from the storage unit 20 to the registers 21 and 22, respectively, and the first parameter is first set to the loop filter 4 by switching the registers 21 and 22. After the value is set and the PLL circuit 1 is locked, the second parameter value is set. [Selection] Figure 5

Description

  The present invention relates to an oscillation device using a PLL (Phase Locked Loop).

  Some systems using an oscillation device incorporating a PLL change the parameters of the oscillation device in response to an external frequency instruction and output a frequency signal of the instructed frequency. Such a system is applicable to a radar system, a mobile phone system, a rocket control system in space development, and the like. Some systems are required to switch to a frequency according to the instruction as soon as possible after receiving an instruction from the outside.

On the other hand, it is of course required to improve the phase noise characteristics of the PLL circuit, but both the shortening of the time from when the frequency is specified until the PLL circuit is locked and good phase noise characteristics are realized. Was difficult. For example, if an analog loop filter is used as the loop filter of the PLL circuit and the circuit constant of the loop filter is set so that the PLL circuit can be locked at high speed, there may be a trade-off that the phase noise characteristics deteriorate.
Further, if a method of switching by providing, for example, two loop filters having different operating characteristics is employed, the PLL circuit is temporarily unlocked when the loop filter is switched, and as a result, high-speed lock cannot be realized.

  Patent Document 1 describes that a high-speed response can be obtained over a wide frequency band by making the characteristic frequency of a loop filter using a digital filter follow the frequency increase / decrease of an input signal. Further, in Patent Document 2, since a loop filter is conventionally a fixed constant, in order to solve the trade-off problem of giving priority to either C / N or lock time, a switched capacitor, A technique using a filter (SCF) is described. Patent Documents 1 and 2 relate to a technique for improving a portion related to a loop filter in a PLL circuit, but do not suggest the configuration of the present invention.

JP 2000-278126 A JP 2000-22532 A

  The present invention has been made under such circumstances, and in an oscillation device using a PLL, when an external frequency designation signal is received, the oscillation frequency can be switched to the designated frequency at high speed. An object of the present invention is to provide a technique that can improve the phase noise characteristics.

The present invention provides an oscillation device that outputs a signal having a frequency designated by a frequency designation signal transmitted from the outside.
A PLL circuit that operates by a digital signal and whose characteristics are adjusted by a parameter value, and includes a reference oscillation unit, a phase comparison unit, the loop filter, a voltage controlled oscillator, and a frequency divider,
The first parameter value for quickly locking the PLL circuit and the second parameter value for reducing the phase noise are stored in association with the designated frequency. A storage unit;
When the frequency designation signal is received, the first parameter value corresponding to the designated frequency stored in the storage unit is output to the loop filter, and when it is determined that the PLL circuit is locked A parameter value setting unit that outputs a second parameter value corresponding to a specified frequency stored in the storage unit to the loop filter instead of the first parameter value. And

The present invention uses a loop filter that operates by digital processing as a loop filter of a PLL circuit, and uses a first parameter value and good phase noise as a parameter value for determining the operating characteristics of the loop filter so as to lock the PLL circuit at high speed. A second parameter value that provides a characteristic is prepared. When the frequency is specified, first, the first parameter value is set in the loop filter, and after the PLL circuit is locked, the second parameter value is set in the loop filter. For this reason, it can switch to the designated frequency at high speed, and can implement | achieve a low phase noise characteristic.

1 is a block circuit diagram illustrating an overall configuration of an oscillation device according to an embodiment of the present invention. It is a block circuit diagram which shows the loop filter used for the said embodiment. It is a characteristic view which shows the phase noise characteristic of the PLL circuit used for the said embodiment. It is a characteristic view which shows the phase noise characteristic of the PLL circuit used for the said embodiment. It is a block diagram which shows the parameter output part used for the said embodiment. It is a flowchart which shows the operation | movement flow of the said embodiment.

As illustrated in FIG. 1, the oscillation device according to the embodiment of the present invention includes a PLL circuit 1 and a parameter value output unit 2 that outputs a parameter value for adjusting the operation of the PLL circuit 1.
The PLL circuit 1 includes a reference oscillation unit 31, a phase comparison unit 32, a loop filter 4, a drive circuit 33, a voltage controlled oscillator (VCO) 34, and a frequency divider 35.
The reference oscillation unit 31 includes, for example, a DDS (Direct Digital Synthesizer), and a setting signal corresponding to the designated frequency is input to the DDS so that the oscillation frequency of the voltage controlled oscillator 34 becomes the designated frequency. For example, a frequency setting value that is a parameter value P described later is input to the DDS, and a reference pulse is output from the DDS. Further, for example, a frequency divider circuit may be provided after the DDS. In this case, data for determining the frequency division ratio of the frequency divider circuit is included in the parameter value P described later.

  The phase comparison unit 32 extracts a difference (phase difference) between the phase of the reference pulse output from the reference oscillation unit 31 and the phase output from the frequency divider 35, and outputs a digital value corresponding to the phase difference. Is done. The loop filter 4 receives the digital value output from the phase comparison unit 32, performs digital processing (calculation) including integration, and inputs the processing result (calculation result) to the drive circuit 33.

The drive circuit 33 includes a digital / analog converter and an amplifier. The digital value is converted into an analog value and supplied to the voltage controlled oscillator 34 as a control voltage.
The voltage controlled oscillator 34 outputs a frequency signal having a frequency corresponding to the control voltage output from the drive circuit 33 as an output signal of the oscillation device and is sent to the frequency divider 35.
For example, a pulse swallow counter using a dual modulus prescaler is used as the frequency divider 35, and a parameter value Q for defining the operations of the prescaler that is the preceding stage counter and the two counters at the subsequent stage is input from the parameter value output unit 2. Is done.

  As shown in FIG. 2, the loop filter 4 is provided in this order in a multiplying unit (one multiplying unit) 41 that multiplies the digital phase difference data sent from the phase comparing unit 32 by a coefficient and a subsequent stage of the multiplying unit 41. The addition unit (one addition unit) 42 and the delay circuit unit 43, the multiplication unit (other multiplication unit) 44 for multiplying the phase difference data by the coefficient, the output value of the delay circuit unit 43 and the output value of the multiplication unit 44 And an adder (other adder) 45 that outputs the output value of the loop filter. The adding unit 42 adds the output value of the multiplying unit 41 and the output value of the delay circuit unit 43.

  The delay circuit unit 43 receives a parameter value corresponding to a delay time for delaying the timing for outputting the input value. This parameter value determines the integration timing of the integration circuit composed of the delay circuit unit 43 and the adder unit 42. Specifically, when the number of clocks is counted, the parameter value is held in the delay circuit unit 43. This determines whether to output the existing data. For example, the delay circuit unit 43 includes a clock pulse counter, and when the count number specified by the parameter value is reached, the data output from the adder unit 42 and held therein is output from the delay circuit unit 43. Has been.

  The coefficients input to the multipliers 41 and 44 are also parameter values. Therefore, it can be said that the loop filter 4 is a loop filter that operates by digital processing and whose operation characteristics are adjusted by the parameter values.

  3 and 4 show examples of the phase noise characteristics of the output of the PLL circuit 1 when two sets of parameter values are set in the loop filter. The set of parameter values in the loop filter 4 indicates a coefficient input to the multiplication unit 41, a coefficient input to the multiplication unit 44, and a parameter value input to the delay circuit unit 43. Setting parameter value sets in two ways means that, for example, the coefficient input to the multiplication unit 41, the coefficient input to the multiplication unit 44, and the parameter value input to the delay circuit unit 43 are set to A1, B1, and C1, respectively. Meaning that it is set to a1, b1, and c1, respectively.

  The horizontal axis is the offset frequency (a value indicating how much the frequency deviates from the set frequency). The way of viewing this graph is to show the shoulder portion of the straight line graph (1) indicating the phase noise characteristics of the entire PLL circuit 1. This means that the PLL circuit 1 is controlled up to the frequency. Therefore, in the case of FIG. 3, control is performed up to about 300 Hz (for example, if the set frequency of the voltage controlled oscillator 34 is 1 MHz, the control band is up to 1 MHz ± 300 Hz), and the PLL circuit 1 is pulled in. The time required for this is approximately 1/300 seconds. In the case of FIG. 4, control is performed up to about 30 Hz, and the time required for pulling in the PLL circuit 1 is about 1/30 second.

  On the other hand, the alternate long and short dash line graph (2) shown in FIGS. 3 and 4 shows the phase noise characteristics of the voltage controlled oscillator 34 when the PLL circuit 1 is in an open loop, and the phase noise of the entire PLL circuit 1 is as follows. , (2) can not be reduced more than the phase noise. Therefore, in FIG. 3, the phase noise characteristic of 100 Hz or more of the entire PLL circuit 1 protrudes (deteriorates) more than the phase noise characteristic indicated by (2). On the other hand, in FIG. 4, the phase noise characteristic of the entire PLL circuit 1 of 20 Hz or higher is substantially the same as the phase noise characteristic indicated by (3).

  That is, when the parameter value of the loop filter 4 is set so as to obtain the phase noise characteristic of FIG. 3, the time from when the frequency is specified until the PLL circuit 1 is locked is short, but the phase noise characteristic is poor. When the parameter value of the loop filter 4 is set so that the phase noise characteristic of FIG. 4 can be obtained, the time from when the frequency is specified until the PLL circuit 1 is locked is long, but the phase noise characteristic is improved.

Therefore, in the present embodiment, after the frequency is specified as the parameter value of the loop filter 4, the parameter value that shortens the time until the PLL circuit 1 is locked until the PLL circuit 1 is locked is used. Used parameter values that provide good phase noise characteristics.
In the following description, the coefficient input to the multiplication unit 41, the coefficient input to the multiplication unit 44, and the parameter value input to the delay circuit unit 43, which are used in the loop filter 4 until the PLL circuit 1 is locked, respectively. Coefficients that are handled as parameter value A, parameter value B, and parameter value C, and that are used in the loop filter 4 after the PLL circuit 1 is locked, the coefficients that are input to the multiplication unit 41, the coefficients that are input to the multiplication unit 44, and the delay circuit unit The parameter values input to 43 are treated as parameter value a, parameter value b, and parameter value c, respectively. Furthermore, the parameter values A, B, and C are called first parameter values, and the parameter values a, b, and c are called second parameter values.

FIG. 5 is a block diagram showing a parameter value output unit 2 that outputs a parameter value to the PLL circuit 1. Reference numeral 20 denotes a non-volatile memory such as a flash memory as a storage unit. The storage unit 20 is written with the first parameter values A, B, C and the second parameter values a, b, c. Yes. The description in the storage unit 20 shows the data storage state as an image, fk (k is an integer) is a specified frequency, Ak, Bk, and Ck are specific values of the first parameter value, ak, bk, ck are specific values of the second parameter value.

  The frequency is represented by the magnitude of the frequency combined with f. In this example, when f1, f2, f3 are designated in order from the lowest frequency, A1, B1, C1, a1, b1 are designated. , C1 are assigned and f4, f5, f6 are designated, it indicates that A4, B4, C4, a4, b4, c4 are assigned. The description in the storage unit 20 is a schematic content. Specifically, for example, when the designated frequencies are arranged from the lowest, for example, a plurality of frequency bands (f1 to f3, f4 including a plurality of continuous frequencies). Each of .about.f6) indicates that a common parameter value is assigned.

  P described in the right column of the storage unit 20 is a parameter value corresponding to the set frequency of the reference pulse output from the reference oscillation unit 31, and Q is used to determine the frequency division ratio of the frequency divider 35. Is the parameter value. As the parameter values P and Q, parameter values Pk and Qk corresponding to each of the designated frequencies are written.

21 is a first register that holds the first parameter values Ak, Bk, and Ck read from the storage unit 20, and 22 is a second parameter value ak, bk that is read from the storage unit 20. , Ck is a second register. The registers 21 and 22 also hold parameter values Pk and Qk read from the storage unit 20.
An address output circuit 23 is configured to output the address of the storage unit 20 corresponding to the designated frequency when frequency channel information including a frequency designation signal is input from the outside to the receiving unit 25 of the oscillation device. Has been.

  The storage unit 20 reads out parameter values corresponding to the address output from the address output unit 23, that is, corresponding to the designated frequency, and distributes these parameter values to the registers 21 and 22 as described above. Written (held).

Reference numeral 24 denotes a timer which operates when frequency channel information is input to the receiving unit 25 of the oscillation device and times up after a predetermined time has elapsed. The predetermined time is estimated from the time when the first parameter values Ak, Bk, Ck and the parameter values Pk, Qk are input (set) to the PLL circuit 1 until the PLL circuit 1 is locked. It corresponds to time. That is, in this example, it can be said that the time-up signal that is output when the timer 24 times out is a signal that is output when it is determined that the PLL circuit 1 is locked.
A switching unit 26 switches the connection source connected to the PLL circuit 1 between the first register 21 and the second register 22. The switching unit 26 is switched to the first register 21 side by the reception confirmation signal output from the receiving unit 25 when the frequency channel information is input to the receiving unit 25, and is switched by the time-up signal output from the timer 24. 2 is switched to the register 22 side.

  Next, the operation of the above embodiment will be described with reference to FIG. It is assumed that a frequency signal having a previously specified frequency is output from the PLL circuit 1. If the frequency channel information is sent from the outside at a certain timing and received by the receiving unit 25 (step S1), among the parameter values corresponding to the specified frequency included in the frequency channel information, the loop filter 4, the parameter value Pk related to the reference oscillating unit 31, and the parameter value Qk related to the frequency divider 35 are read out to the first register 21 and also to the loop filter 4. The second parameter values ak, bk, ck and Pk, Qk are read out to the second register 22.

  Since the reception confirmation signal is output from the reception unit 25, the switching unit 26 is switched to the first register 21 side, and the parameter values Pk and Qk are output to the reference oscillation unit 31 and the frequency divider 35, respectively. The first parameter value is output to the filter 4 (steps S2 and S3). By setting the first parameter value in the loop filter 4, as described above, the PLL circuit 1 locks at a specified frequency at a high speed while maintaining the loop.

  On the other hand, the timer 24 operates in response to the reception confirmation signal from the receiving unit 25, and after a predetermined time (a time until the PLL circuit 1 is locked as described above) has elapsed, a time-up signal is output. The switching unit 26 is switched to the second register 22 side (steps S4 and S5). Although the parameter values are switched at once, Pk and Qk are the same value and do not affect the reference oscillation unit 31 and the frequency divider 35. Since the second parameter value is set for the loop filter 4, the PLL circuit 1 thereafter operates with good phase noise characteristics and low spurious characteristics as described above.

  According to the above-described embodiment, the loop filter 4 that operates by digital processing is used as the loop filter of the PLL circuit 1, and the first parameter is used to lock the PLL circuit 1 at high speed as the parameter value that determines the operating characteristics of the loop filter 4. A parameter value and a second parameter value that provides good phase noise characteristics are prepared. When the frequency is specified, first, the first parameter value is set in the loop filter 4, and after the PLL circuit 1 is locked, the second parameter value is set in the loop filter 4. For this reason, it can switch to the designated frequency at high speed, and can realize a low phase noise characteristic and a low spurious characteristic.

As a timing for switching from the first parameter value to the second parameter value, a lock detection circuit of the PLL circuit 1 may be provided and a lock detection signal may be used. Examples of the lock detection circuit include a circuit that monitors the output of the loop filter 4 and determines that the PLL circuit 1 is locked when it is detected that the output value is continuously within a preset period threshold. Can do. In the above example, the switching unit 26 is switched by the lock detection signal instead of the time-up signal.
The first parameter value and the second parameter value used for the loop filter 4 correspond to each of the designated frequencies instead of being determined for each frequency group (for each frequency band) as in the above embodiment. Or may be made common to all specified frequencies in some systems.
In the above example, only one PLL circuit is used. However, if the range from the upper limit to the lower limit of the specified all frequencies is wide (bandwidth), the specified all frequency bands are divided into a plurality. A system in which a PLL circuit is selected for each divided frequency band may be used.

1 PLL circuit 2 Parameter value output unit 20 Storage unit 21, 22 Register 23 Address output unit 24 Timer 25 Reception unit 26 Switching unit 31 Reference oscillation unit 32 Phase comparison unit 34 Voltage control oscillation unit 35 Frequency divider 4 Loop filters 41, 44 Multiplication unit 42, 45 Addition unit
43 Delay circuit

11 Oscillation circuit unit 12 Communication unit 13 Communication speed control unit

Claims (4)

In an oscillation device that outputs a signal of a frequency designated by a frequency designation signal transmitted from the outside,
Using a loop filter that operates by digital processing and whose operation characteristics are adjusted by parameter values, a PLL circuit including a reference oscillation unit, a phase comparison unit, the loop filter, a voltage controlled oscillator, and a frequency divider,
A storage unit that stores the first parameter value for quickly locking the PLL circuit and the second parameter value for reducing phase noise, the parameter value;
When the frequency designation signal is received, the first parameter value stored in the storage unit is output to the loop filter, and when it is determined that the PLL circuit is locked, the first parameter value is stored in the storage unit. A parameter value setting unit that outputs the second parameter value to the loop filter instead of the first parameter value;
An oscillation device comprising: Each of the first parameter value and the second parameter value is stored in the storage unit in association with a designated frequency or a frequency band including a designated frequency,
When the parameter value setting unit receives the frequency designation signal, the parameter value setting unit outputs a first parameter value corresponding to the designated frequency stored in the storage unit to the loop filter, and the PLL circuit When it is determined that the lock has been established, the second parameter value corresponding to the specified frequency stored in the storage unit is output to the loop filter instead of the first parameter value. The oscillating device according to claim 1. The loop filter includes a multiplication unit that multiplies an input value and a coefficient, a single addition unit and delay circuit unit that are provided in this order after the multiplication unit, and an input value and a coefficient. A multiplication unit, and another addition unit that outputs the output value of the loop filter by adding the output value of the delay circuit unit and the output value of the other multiplication unit,
The one addition unit adds the output value of the one multiplication unit and the output value of the delay circuit unit,
3. The oscillation device according to claim 1, wherein the parameter value of the loop filter is a coefficient corresponding to a coefficient of the one multiplication unit, a coefficient of the other multiplication unit, and a delay time of the delay circuit unit. A first register and a second register for storing a first parameter value and a second parameter value read from the storage unit, respectively, and outputting the stored parameter value to the loop filter;
4. A switching unit that switches a register connected to the loop filter from the first register to the second register when it is determined that the PLL circuit is locked. The oscillation device according to any one of the above.

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