JP2018098768A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving advanced communication by using an amplifier.SOLUTION: A semiconductor device 1 comprises an amplifier 2, a splitter 3, a first output terminal RFOUT1, a second output terminal RFOUT2, output controllers SW1 to SW5, and an SOI substrate. The amplifier amplifies an input signal Sin1. The splitter branches an output signal of the amplifier into a first signal path and a second signal path, and performs impedance conversion between the first and second signal paths. The first output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the first signal path by the splitter. The second output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the second signal path by the splitter. The output controller selectively outputs from the first output terminal the output signal from the amplifier, or outputs from the second output terminal, or outputs from both the first and second output terminals by branching by the splitter.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a semiconductor device.

  Conventionally, a high-frequency low-noise amplifier mounted on a mobile phone terminal or the like has been manufactured by a SiGe (silicon germanium) bipolar process. On the other hand, in recent years, the SiGe bipolar process is being replaced with an SOI (Silicon On Insulator) CMOS process. The reason is that according to the SOICMOS process, a high frequency low noise amplifier can be formed on the same SOI substrate together with a high frequency switch and a complicated control circuit.

  In recent years, high-frequency low-noise amplifiers are compatible with advanced communications such as carrier aggregation. For example, simultaneous reception and selective reception of signals in different frequency bands or reception of different signals in the same frequency band There is a demand for complicated functions such as operating in an operation mode.

  Conventionally, however, there has been no effective proposal for a technique for making a high-frequency low-noise amplifier compatible with advanced communication.

Special table 2015-521010 gazette

  The problem to be solved by the present invention is to provide a semiconductor device capable of realizing advanced communication using an amplifier.

  The semiconductor device according to the present embodiment includes an amplifier, a splitter, a first output terminal, a second output terminal, an output control unit, and an SOI substrate. The amplifier amplifies the input signal. The splitter branches the output signal of the amplifier into a first signal path and a second signal path, and performs impedance conversion of the first and second signal paths. The first output terminal outputs an output signal of the amplifier or a signal obtained by branching the output signal of the amplifier to the first signal path by the splitter. The second output terminal outputs an output signal of the amplifier or a signal obtained by branching the output signal of the amplifier to the second signal path by the splitter. The output control unit switches whether the output signal of the amplifier is output from the first output terminal, from the second output terminal, or branched from the splitter and output from both the first and second output terminals. On the SOI substrate, an amplifier, a splitter, and an output control unit are arranged.

1 is a circuit diagram showing a high-frequency semiconductor device according to a first embodiment. FIG. 3 is a circuit diagram showing a first high frequency LNA in the high frequency semiconductor device according to the first embodiment. It is a figure which shows the truth table of the high frequency semiconductor device by 1st Embodiment. It is a circuit diagram which shows the high frequency semiconductor device by 2nd Embodiment. It is a figure which shows the truth table of the high frequency semiconductor device by 2nd Embodiment. It is a circuit diagram which shows the high frequency semiconductor device by 3rd Embodiment. It is a figure which shows the truth table of the high frequency semiconductor device by 3rd Embodiment. It is a layout figure of the splitter in the high frequency semiconductor device by a 4th embodiment. FIG. 9A to FIG. 9D are graphs showing S parameters of the splitter in the high-frequency semiconductor device according to the fourth embodiment. In the high frequency semiconductor device by a 4th embodiment, it is a graph which shows dependence with respect to the line width of a spiral inductor about the passage loss and length of a splitter. Fig.11 (a) and FIG.11 (b) are figures which show the modification of a switch. It is a circuit diagram which shows the high frequency semiconductor device by 6th Embodiment. It is a circuit diagram which shows a variable capacitor in the high frequency semiconductor device by 6th Embodiment. In the high frequency semiconductor device by a 6th embodiment, it is a figure showing the correspondence of an input signal and a control signal of a variable capacitor. In the high frequency semiconductor device by a 6th embodiment, it is a circuit diagram showing high frequency LNA. In the high-frequency semiconductor device according to the sixth embodiment, it is a diagram showing a correspondence relationship among an operation mode, a bias voltage of a high-frequency LNA, and a control signal of a gain adjustment circuit. It is a graph which shows the small signal characteristic in the single output mode by the low frequency band Band-L in the simulation example of the high frequency semiconductor device by 6th Embodiment. It is a graph which shows the small signal characteristic in the split mode by the low frequency band Band-L in the simulation example of the high frequency semiconductor device by 6th Embodiment. It is a graph which shows the small signal characteristic in the single output mode by the high frequency band Band-H in the simulation example of the high frequency semiconductor device by 6th Embodiment. It is a graph which shows the small signal characteristic in the split mode by the high frequency band Band-H in the simulation example of the high frequency semiconductor device by 6th Embodiment. In the example of a simulation of the high frequency semiconductor device by a 6th embodiment, it is a figure showing a list of typical numerical values in a graph of Drawings 17-20. It is a circuit diagram which shows the splitter by 7th Embodiment. It is a figure which shows a circuit constant in the simulation example of the splitter by 7th Embodiment. It is a graph which shows a frequency characteristic in the simulation example of the splitter by 7th Embodiment. It is a graph which shows a frequency characteristic in the simulation example of the splitter by the comparative example of 7th Embodiment. FIG. 26 is a diagram showing a list of worst values in a band in the graphs of FIGS. 24 and 25 in a splitter simulation example according to the seventh embodiment. It is a circuit diagram which shows the splitter by the 1st modification of 7th Embodiment. It is a circuit diagram which shows the splitter by the 2nd modification of 7th Embodiment. It is a layout figure of the splitter in the high frequency semiconductor device by an 8th embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. In the following embodiments, the characteristic configuration and operation of the semiconductor device will be mainly described. However, the configuration and operation omitted in the following description may exist in the semiconductor device. These omitted configurations and operations are also included in the scope of the present embodiment. In the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same or similar reference numerals, and repeated description thereof is omitted.

(First embodiment)
FIG. 1 is a circuit diagram of a high-frequency semiconductor device 1 according to the first embodiment, which is an example of a semiconductor device. The high-frequency semiconductor device 1 shown in FIG. 1 can be applied to, for example, a mobile phone terminal.

  The high-frequency semiconductor device 1 in FIG. 1 is manufactured by a CMOS process on a common SOI substrate. As shown in FIG. 1, the high-frequency semiconductor device 1 includes an SOI substrate, a first high-frequency LNA (Low Noise Amplifier) 2 that is an example of a first amplifier, a splitter 3, a first output terminal RFout1, and a second output. A terminal RFout2 and first to fifth switches SW1 to SW5, which are examples of an output control unit, are provided.

  The first high-frequency LNA2 amplifies a first high-frequency input signal Sin1 that is an example of a first input signal, and outputs a first high-frequency output signal Sout1 that is an example of an output signal of the first amplifier.

  As shown in FIG. 1, the first high-frequency LNA 2 is disposed on the SOI substrate, one end is connected to the first input terminal RFin 1, and the other end is connected to the first output terminal RFout 1 via the branch node N in the splitter 3. The second output terminal RFout2 is connected.

  FIG. 2 is a circuit diagram showing the first high-frequency LNA 2 in the high-frequency semiconductor device 1 according to the first embodiment. As shown in FIG. 2, the first high frequency LNA 2 is a cascode type high frequency LNA.

  As shown in FIG. 2, the first high-frequency LNA 2 includes a spiral inductor Ls that is an example of a fifth inductor, an nMOSFET 1 that is an example of a first transistor, an nMOSFET 2 that is an example of a second transistor, and an example of a sixth inductor. And an inductor Ld. The nMOSFET is an n-type MOSFET (hereinafter the same). The spiral inductor Ls, nMOSFET1, nMOSFET2, and inductor Ld are connected in series between a ground potential that is an example of a first reference potential and a power supply potential VDD_LNA that is an example of a second reference potential. In addition, the first high-frequency LNA2 includes a plurality of resistors RB1, RB2, and Rd and a plurality of capacitors Cx, Cin, and Cout.

  The gate of the nMOSFET 1 is connected to the first input terminal RFin1 via the capacitor Cx, the input terminal LNAin, and the external inductor Lext. That is, the external inductor Lext and the capacitor Cx are connected in series between the first input terminal RFin1 and the gate of the nMOSFET 1. In FIG. 1, the external inductor Lext is not shown. Further, a bias voltage generation circuit (not shown) is connected to the gate of the nMOSFET 1 via a resistor RB1.

  The nMOSFET 2 is cascode-connected to the nMOSFET 1. The drain of the nMOSFET 2 is connected to the output terminal LNAout of the first high frequency LNA2 through the capacitor Cout. The gate of the nMOSFET 2 is connected to a bias voltage generation circuit (not shown) via the resistor RB2. The gate of the nMOSFET 2 is grounded via a capacitor CB2 that is a ground capacitance.

  The spiral inductor Ls has one end connected to the source of the nMOSFET 1 and the other end connected to the ground potential. In other words, the nMOSFET 1 is a common source FET having inductive source degeneration by the spiral inductor Ls. One end of a capacitor Cin is connected between the spiral inductor Ls and the source of the nMOSFET 1. The other end of the capacitor Cin is connected to the gate of the nMOSFET 1.

  The inductor Ld has one end connected to the drain of the nMOSFET 2 and the other end connected to the power supply potential VDD_LNA. The power supply potential VDD_LNA is generated by a bias voltage generation circuit (not shown). A resistor Rd is connected in parallel to the inductor Ld.

  In the first high frequency LNA2 having the configuration shown in FIG. 2, the nMOSFET 1 is turned on when the bias voltage VB1 is input. The nMOSFET 2 is turned on when the bias voltage VB2 is applied. In the ON state, a drain current due to the power supply potential VDD_LNA flows through nMOSFET 1 and nMOSFET 2. When the first high-frequency input signal Sin1 is input from the first input terminal RFin to the gate of the nMOSFET1 in a state where the drain current flows through the nMOSFET1 and the nMOSFET2, the drain voltage corresponding to the drain voltage of the nMOSFET2 is output from the output terminal LNAout of the first high-frequency LNA2. As a signal, a first high-frequency output signal Sout1 obtained by amplifying the first high-frequency input signal Sin1 is output.

  The first high-frequency input signal Sin1 is a signal belonging to, for example, a frequency band of 1.8 to 2.0 GHz or a frequency band of 2.0 to 2.2 GHz. The first high-frequency input signal Sin1 may include a plurality of high-frequency signals having different frequencies in the same frequency band (for example, 1.8 to 2.0 GHz or 2.0 to 2.2 GHz). A plurality of high-frequency signals having different frequencies in the same frequency band can be individually demodulated by a demodulator (not shown) after passing through the first high-frequency LNA 2 and the splitter 3.

  When the first high-frequency input signal Sin1 is amplified by the first high-frequency LNA2, the external inductor Lext, the capacitor Cin, and the spiral inductor Ls function as input matching elements, and consider gain matching and noise matching of the amplification FET1 and FET2. The desired impedance matching is performed. The capacitor Cx cuts the DC component of the first high frequency input signal Sin1. The inductor Ld and the capacitor Cout function as an output matching circuit that performs impedance matching on the output side. The resistor Rd stabilizes the frequency characteristic of the signal from a steep characteristic to a flat characteristic so that it can cope with a wide band. The resistors RB1 and RB2 prevent the first high-frequency input signal Sin1 from entering the bias voltage generation circuit side.

  The splitter 3 branches the first high-frequency output signal Sout1 that is the output signal of the first high-frequency LNA2 into the first signal path P1 and the second signal path P2, and performs impedance conversion of the first and second signal paths P1 and P2. The first and second signal paths P1 and P2 are isolated from each other.

  The splitter 3 has a plurality of lumped constant elements arranged on the SOI substrate. Specifically, as shown in FIG. 1, the splitter 3 is an example of a first spiral inductor L1a that is an example of a first inductor, a second spiral inductor L2a that is an example of a second inductor, and an example of a third inductor. A third spiral inductor L1b, a fourth spiral inductor L2b, which is an example of a fourth inductor, a first capacitor C1, a second capacitor C2a, a third capacitor C2b, and a resistor R are included.

  The lumped constant elements L1a, L2a, L1b, L2b, C1, C2a, C2b, and R are an input node Nin between the output node Na and the branch node N of the first high-frequency LNA2, and the branch node N and the first output terminal RFout1. To the first output node Nout1 between the first node and the second output node Nout2 between the branch node N and the second output terminal RFout2.

  Specifically, the first capacitor C1 is connected between the input node Nin of the splitter 3 and a ground potential which is an example of a reference potential. The first spiral inductor L1a and the second spiral inductor L2a are connected in series on the first signal path P1, that is, between the branch node N and the first output node Nout1. The third spiral inductor L1b and the fourth spiral inductor L2b are connected in series on the second signal path P2, that is, between the branch node N and the second output node Nout2. The second capacitor C2a has one end connected between the first spiral inductor L1a and the second spiral inductor L2a and the other end connected to a ground potential which is an example of a reference potential. The third capacitor C2b has one end connected between the third spiral inductor L1b and the fourth spiral inductor L2b, and the other end connected to a ground potential which is an example of a reference potential. The resistor R is connected between the first output node Nout1 and the second output node Nout2.

  The first to fourth spiral inductors L1a, L2a, L1b, and L2b are spiral conductive patterns. The first spiral inductor L1a and the third spiral inductor L1b have the same inductance. The second spiral inductor L2a and the fourth spiral inductor L2b have the same inductance. The second capacitor C2a and the third capacitor C2b have the same capacitance. The resistor R has a resistance value that is twice the characteristic impedance of the splitter 3. For example, when the characteristic impedance is 50Ω, the resistance value of the resistor R is 100Ω.

  The splitter 3 having the above configuration branches the first high-frequency output signal Sout1 input to the input node Nin into a first signal path P1 and a second signal path P2 at the branch node N. A signal obtained by branching the first high-frequency output signal Sout1 to the first signal path P1 by the splitter 3 (hereinafter, also referred to as a first high-frequency first branch signal Sout1_d1) and the first high-frequency output signal Sout1 by the splitter 3 to the second signal path P2 (Hereinafter also referred to as the first high-frequency second branched signal Sout1_d2) is a signal obtained by dividing the first high-frequency output signal Sout1 into two. Therefore, the power of the first high-frequency first branch signal Sout1_d1 and the first high-frequency second branch signal Sout1_d2 is attenuated by at least half (that is, 3 dB) with respect to the first high-frequency output signal Sout1.

  The first high-frequency first branch signal Sout1_d1 is output from the first output terminal RFout1 to the first demodulator (not shown) via the first output node Nout1. The first high-frequency second branch signal Sout1_d2 is output from the second output terminal RFout2 to the second demodulator (not shown) via the second output node Nout2. The first high-frequency first branch signal Sout1_d1 and the first high-frequency second branch signal Sout1_d2 are in the same frequency band as the first high-frequency input signal Sin1 (for example, 1.8 to 2.0 GHz or 2.0 to 2.2 GHz). Each of which includes a plurality of high-frequency signals having different frequencies within the frequency band. The first demodulator demodulates a high-frequency signal having a preset first frequency among a plurality of high-frequency signals included in the first high-frequency first branch signal Sout1_d1. The second demodulator demodulates a high-frequency signal having a second frequency different from the preset first frequency among the plurality of high-frequency signals included in the second output node Nout2. In this way, two high-frequency signals having different frequencies within the same frequency band can be received from the first high-frequency first branch signal Sout1_d1 and the first high-frequency second branch signal Sout1_d2 output via the splitter 3. .

  In the splitter 3, the first signal path P1 and the second signal path P2 function as an impedance converter that converts the impedance to 2: 1. Thereby, the impedance when the inside of the splitter 3 is seen from the input node Nin, the impedance when the inside of the splitter 3 is seen from the first output node Nout1, and the impedance when the inside of the splitter 3 is seen from the second output node Nout2 Is a characteristic impedance (for example, 50Ω). That is, desired impedance matching can be realized in the splitter 3. Further, since the splitter 3 includes spiral inductors L1a, L2a, L1b, and L2b that can increase the wiring length in a relatively narrow region, impedance matching can be appropriately performed while having a compact configuration.

  The path from the first output node Nout1 to the second output node Nout2 via the branch node N and the path from the second output node Nout2 to the first output node Nout1 via the branch node N are respectively It functions as a phase shifter that rotates the phase by 180 °. As a result, as the isolation between the first signal path P1 and the second signal path P2, the isolation between the first output node Nout1 and the second output node Nout2 can be reliably performed.

  The first to fifth switches SW1 to SW5 output the first high-frequency output signal Sout1 from the first output terminal RFout1, the second output terminal RFout2, or branch by the splitter 3 according to the switching control. Whether to output from both the first and second output terminals RFout1 and RFout2 is switched. When the first high-frequency output signal Sout1 is branched by the splitter 3, the first high-frequency output signal Sout1 is the first and second outputs in the state of the first high-frequency first branch signal Sout1_d1 and the first high-frequency second branch signal Sout1_d2. Output from terminals RFout1 and RFout2.

  The first switch SW1 has an nMOSFET M1 and a resistor r1. The nMOSFET M1 is connected between the output node Na of the first high frequency LNA2 and the input node Nin of the splitter 3. The resistor r1 is connected to the gate of the nMOSFET M1. The resistor r1 has a high resistance value such as 100 kΩ. The first switch SW1 is ON / OFF controlled by a first control signal Cont1 input to the gate of the nMOSFET M1 via the resistor r1. In addition, illustration is abbreviate | omitted about the production | generation circuit which produces | generates the control signal of nMOSFETM1-M5. The control signal generation circuit is disposed on an SOI substrate, for example. The control signal generation circuit may be provided outside the high-frequency semiconductor device 1.

  The second switch SW2 has an nMOSFET M2 and a resistor r2. The nMOSFET M2 is connected between the first output node Nout1, that is, the first signal path P1 and the first output terminal RFout1. The resistor r2 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M2. The second switch SW2 is ON / OFF controlled by a first control signal Cont1 input to the gate of the nMOSFET M2 via the resistor r2.

  The third switch SW3 includes an nMOSFET M3 and a resistor r3. The nMOSFET M3 is connected between the second output node Nout2, that is, the second signal path P2, and the second output terminal RFout2. The resistor r3 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M3. The third switch SW3 is ON / OFF controlled by the first control signal Cont1 input to the gate of the nMOSFET M3 via the resistor r3.

  The fourth switch SW4 includes an nMOSFET M4 and a resistor r4. The nMOSFET M4 is connected between the output node Na of the first high frequency LNA2 and the first output terminal RFout1. More specifically, the nMOSFET M4 is connected between the output node Na and a node Nb between the nMOSFET M2 and the first output terminal RFout1. The resistor r4 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M4. The fourth switch SW4 is ON / OFF controlled by the second control signal Cont2 input to the gate of the nMOSFET M4 via the resistor r4.

  The fifth switch SW5 includes an nMOSFET M5 and a resistor r5. The nMOSFET M5 is connected between the output node Na of the first high frequency LNA2 and the second output terminal RFout2. More specifically, the nMOSFET M5 is connected between a node Nd between the output node Na and the nMOS transistor M4 and a node Nc between the nMOSFET M3 and the second output terminal RFout2. The resistor r5 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M5. The switch SW5 is on / off controlled by a third control signal Cont3 input to the gate of the nMOSFET M5 via the resistor r5.

  In the example of FIG. 1, nMOSFETs M1 to M5 are arranged one by one, but each of the nMOSFETs M1 to M5 may be connected in series in two or more stages.

  In the first to fifth switches SW1 to SW5 having the above-described configuration, the switches SW1 to SW3 are turned on when the switches SW4 and SW5 are turned off, so that the first high-frequency output signal Sout1 is branched by the splitter 3. The high-frequency first branch signal Sout1_d1 and the first high-frequency second branch signal Sout1_d2 are output from the first and second output terminals RFout1 and RFout2. The switch SW4 is turned on when the switches SW1 to SW3 and SW5 are turned off to output the first high-frequency output signal Sout1 from the first output terminal RFout1. The switch SW5 is turned on when the switches SW1 to SW4 are turned off to output the first high-frequency output signal Sout1 from the second output terminal RFout2.

(action mode)
FIG. 3 is a diagram showing a truth table of the high-frequency semiconductor device 1 according to the first embodiment. The high-frequency semiconductor device 1 according to the first embodiment having the above-described configuration can operate in two operation modes of a single output mode and a split mode, as shown in the truth table of FIG.

  The single output mode is an operation mode in which the first high-frequency output signal Sout1 output from the first high-frequency LNA2 is output from the first output terminal RFout1 or the second output terminal RFout2.

  When the first output terminal RFout1 is activated in the single output mode, as shown in FIG. 3, the first control signal Cont1 is low level (L), the second control signal Cont2 is high level (H), and the third control signal is set. Set Cont3 to low level (L). Thereby, the switches SW1 to SW3 and SW5 are turned off and the switch SW4 is turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 through the signal path a in FIG. 1 via the switch SW4. The first high-frequency output signal Sout1 output from the first output terminal RFout1 is demodulated by a first demodulator (not shown).

  When the second output terminal RFout2 is activated in the single output mode, as shown in FIG. 3, the first control signal Cont1 is set to the low level, the second control signal Cont2 is set to the low level, and the third control signal Cont3 is set to the high level. To do. Thereby, the switches SW1 to SW4 are turned off and the switch SW5 is turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the second output terminal RFout2 through the signal path b of FIG. 1 via the nMOSFET M5. The first high-frequency output signal Sout1 output from the second output terminal RFout2 is demodulated by a second demodulator (not shown).

  The split mode is an operation mode in which the first high-frequency output signal Sout1 output from the first high-frequency LNA2 is branched by the splitter 3 and output from the first output terminal RFout1 and the second output terminal RFout2. In the split mode, as shown in FIG. 3, the first control signal Cont1 is set to a high level, the second control signal Cont2 is set to a low level, and the third control signal Cont3 is set to a low level. As a result, the switches SW1 to SW3 are turned on and the switches SW4 and SW5 are turned off. By such on / off control, the first high-frequency output signal Sout1 output from the first high-frequency LNA2 passes through the signal path c, P1, and P2 of FIG. Output from terminal RFout2. That is, among the first high-frequency output signals Sout1 distributed by the splitter 3, the first high-frequency first branch signal Sout1_d1 is output from the first output terminal RFout1 through the first signal path P1. The first high-frequency second branch signal Sout1_d2 is output from the second output terminal RFout2 through the second signal path P2. The first high-frequency first branch signal Sout1_d1 output from the first output terminal RFout1 is demodulated by a first demodulator (not shown), and the first high-frequency second branch signal Sout1_d2 output from the second output terminal RFout2 is Demodulated by a second demodulator (not shown).

  According to the first embodiment, two types of operation modes of the single output mode and the split mode can be realized for the first high-frequency output signal Sout1 output from the first output terminal RFout1, and therefore, the first high-frequency LNA2 Advanced communication can be realized using.

(Second Embodiment)
Next, a second embodiment using two high frequency low noise amplifiers will be described. FIG. 4 is a circuit diagram showing the high-frequency semiconductor device 1 according to the second embodiment.

  As shown in FIG. 4, the high-frequency semiconductor device 1 of the second embodiment includes a second amplifier in addition to the first high-frequency LNA 2 and the first to fifth switches SW1 to SW5 described in the first embodiment. The second high-frequency LNA 4 as an example and sixth to tenth switches SW6 to SW10 are included.

  The second high frequency LNA 4 amplifies the second high frequency input signal Sin2 which is an example of the second input signal, and outputs a second high frequency output signal Sout2 which is an example of the output signal of the second amplifier.

  As shown in FIG. 4, the second high-frequency LNA 4 is disposed on the SOI substrate, one end is connected to the second input terminal RFin 2, and the other end is connected to the input node Nin of the splitter 3. The basic circuit configuration of the second high frequency LNA 4 is the same as that of the first high frequency LNA 2. The second high frequency LNA 4 outputs a second high frequency output signal Sout2 obtained by amplifying the second high frequency input signal Sin2 input from the second input terminal RFin2.

  The first to tenth switches SW1 to SW10 output the first high-frequency output signal Sout1 from the first output terminal RFout1, the second output terminal RFout2, or are branched by the splitter 3 by the switching control. Switching between output from both the first and second output terminals RFout1 and RFout2 is performed. Further, the first to tenth switches SW1 to SW10 output the second high-frequency output signal Sout2 from the first output terminal RFout1, the second output terminal RFout2, or branch by the splitter 3 by the switching control. Then, the output is switched from both the first and second output terminals RFout1 and RFout2.

  Since the first to fifth switches SW1 to SW5 are the same as those in the first embodiment, detailed description thereof is omitted.

  The ninth switch SW9 includes an nMOSFET M9 and a resistor r9. The nMOSFET M9 is connected between the first high frequency LNA2 and the output node Na of the first high frequency LNA2. The resistor r9 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M9. The ninth switch SW9 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M9 via the resistor r9.

  The tenth switch SW10 includes an nMOSFET M10 and a resistor 10. The nMOSFET M10 is connected between the second high frequency LNA4 and the output node Ne of the second high frequency LNA4. The resistor r10 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M10. The tenth switch SW10 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M10 via the resistor r10.

  The sixth switch SW6 includes an nMOSFET M6 and a resistor r6. The nMOSFET M6 is connected between the output node Ne of the second high frequency LNA4 and the input node Nin of the splitter 3. The resistor r6 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M6. The sixth switch SW6 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M6 via the resistor r6.

  The seventh switch SW7 includes an nMOSFET M7 and a resistor r7. The nMOSFET M7 is connected between the output node Ne of the second high frequency LNA4 and the first output terminal RFout1. More specifically, the nMOSFET M7 is connected between the output node Ne and the node Nb. The resistor r7 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M7. The seventh switch SW7 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M7 via the resistor r7.

  The eighth switch SW8 includes an nMOSFET M8 and a resistor r8. The nMOSFET M8 is connected between the output node Ne of the second high frequency LNA4 and the second output terminal RFout2. More specifically, the nMOSFET M8 is connected between the node Nf between the output node Ne and the nMOS transistor M7 and the node Nc. The resistor r8 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M8. The eighth switch SW8 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M8 via the resistor r8.

  In the first to tenth switches SW1 to SW10 having the above-described configuration, the switches SW1 to SW3 and SW9 are turned on when the switches SWSW4 to SW8 and SW10 are turned off, so that the first high frequency output signal Sout1 is supplied to the splitter 3. Are branched and output from the first and second output terminals RFout1 and RFout2. The switches SW4 and SW9 are turned on at least when the switches SW1 to SW3 and SW5 to SW7 are turned off, so that the first high-frequency output signal Sout1 is output from the first output terminal RFout1. The switches SW5 and SW9 are turned on at least when the switches SW1 to SW4, SW6, and SW8 are turned off to output the first high-frequency output signal Sout1 from the second output terminal RFout2.

  The switches SW2, SW3, SW6, and SW10 are turned on when the switches SW1, SW4, SW5, and SW7 to SW9 are turned off, so that the second high-frequency output signal Sout2 is branched by the splitter 3 and the first and first switches. Output from two output terminals RFout1 and RFout2. The switches SW7 and SW10 are turned on at least when the switches SW1 to SW4, SW6, and SW8 are turned off to output the second high-frequency output signal Sout2 from the first output terminal RFout1. The switches SW8 and SW10 are turned on at least when the switches SW1 to SW3 and SW5 to SW7 are turned off, so that the second high-frequency output signal Sout2 is output from the second output terminal RFout2.

(action mode)
FIG. 5 is a diagram showing a truth table of the high-frequency semiconductor device 1 according to the second embodiment. As shown in the truth table of FIG. 5, the high-frequency semiconductor device 1 of the second embodiment having the above configuration has three operation modes: a single output mode, a split mode, and an LNA1, 2 simultaneous operation mode. It can work.

  The single output mode in the second embodiment is an operation mode in which the high-frequency output signals Sout1 and Sout2 output from one of the first high-frequency LNA2 and the second high-frequency LNA4 are output from the first output terminal RFout1 or the second output terminal RFout2. It is.

  In the single output mode, when the first input terminal RFin1 and the first output terminal RFout1 are activated, a high level control signal is applied to the gates of the nMOSFETs M9 and M4, and the gates of the nMOSFETs M1 to M3, M5 to M8, and M10 are low. Apply level control signal. Thereby, as shown in FIG. 5, the switches SW1 to SW3, SW5 to SW8, and SW10 are turned off, and the switches SW9 and SW4 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 through the signal path a of FIG. 4 via the switches SW9 and SW4.

  In the single output mode, when the first input terminal RFin1 and the second output terminal RFout2 are activated, a high level control signal is applied to the gates of the nMOSFETs M9 and M5, and the gates of the nMOSFETs M1 to M4, M6 to M8, and M10 are low. Apply level control signal. Thereby, as shown in FIG. 5, the switches SW1 to SW4, SW6 to SW8, and SW10 are turned off, and the switches SW9 and SW5 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the second output terminal RFout2 through the signal path b of FIG. 4 via the switches SW9 and SW5.

  In the single output mode, when the second input terminal RFin2 and the first output terminal RFout1 are activated, a high level control signal is applied to the gates of the nMOSFETs M10 and M7, and the low level is applied to the gates of the nMOSFETs M1 to M6, M8, and M9. Apply control signals. As a result, as shown in FIG. 5, the switches SW1 to SW6, SW8, and SW9 are turned off and the switches SW10 and SW7 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the first output terminal RFout1 through the signal path c of FIG. 4 via the switches SW10 and SW7.

  In the single output mode, when the second input terminal RFin2 and the second output terminal RFout2 are activated, a high level control signal is applied to the gates of the nMOSFETs M10 and M8, and a low level control signal is applied to the gates of the nMOSFETs M1 to M7 and M9. Apply. As a result, as shown in FIG. 5, the switches SW1 to SW7 and SW9 are turned off and the switches SW10 and SW8 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the second output terminal RFout2 through the signal path d of FIG. 4 via the switches SW10 and SW8.

  In the split mode in the second embodiment, the high-frequency output signals Sout1 and Sout2 output from one of the first high-frequency LNA2 and the second high-frequency LNA4 are branched by the splitter 3 to be output to the first output terminal RFout1 and the second output. This is an operation mode for outputting from the terminal RFout2.

  In the split mode, when the first input terminal RFin1 is activated, a high level control signal is applied to the gates of the nMOSFETs M9 and M1 to M3, and a low level control signal is applied to the gates of the nMOSFETs M4 to M8 and M10. Thereby, as shown in FIG. 5, the switches SW4 to SW8 and SW10 are turned off, and the switches SW9 and SW1 to SW3 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 and the second output terminal RFout2 through the signal path e of FIG. That is, the first high-frequency output signal Sout1 is divided into two in the splitter 3 into the first high-frequency first branch signal Sout1_d1 and the first high-frequency second branch signal Sout1_d2. The first high-frequency first branch signal Sout1_d1 is output from the first output terminal RFout1, and the first high-frequency second branch signal Sout1_d2 is output from the second output terminal RFout2.

  In the split mode, when the second input terminal RFin2 is activated, a high level control signal is applied to the gates of the nMOSFETs M10, M2, M3, and M6, and the low level is applied to the gates of the nMOSFETs M1, M4, M5, M7, M8, and M9. The control signal is applied. As a result, as shown in FIG. 5, the switches SW1, SW4, SW5, SW7, SW8, and SW9 are turned off, and the switches SW10, SW2, SW3, and SW6 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the first output terminal RFout1 and the second output terminal RFout2 through the signal path f of FIG. That is, the second high-frequency output signal Sout2 includes the second high-frequency output signal Sout2_d1 obtained by branching the second high-frequency output signal Sout2 into the first signal path P1 and the second high-frequency output signal Sout2 in the splitter 3 in the second signal path. Divided into the second high-frequency second branch signal Sout2_d2 branched to P2. The second high-frequency first branch signal Sout2_d1 is output from the first output terminal RFout1, and the second high-frequency second branch signal Sout2_d2 is output from the second output terminal RFout2.

  The LNA 1 and 2 simultaneous operation mode is an operation mode in which both the first high frequency LNA 2 and the second high frequency LNA 4 operate simultaneously. In the LNA1 and 2 simultaneous operation modes, for example, high frequency signals Sin1 and Sin2 belonging to different frequency bands are input to both the first input terminal RFin1 and the second input terminal RFin2. For example, the first high frequency signal Sin1 belonging to 1.8 to 2.0 GHz is input to the first input terminal RFin1, and the second high frequency signal Sin2 belonging to 2.0 to 2.2 GHz is input to the second input terminal RFin2. May be entered.

  In the LNA1, 2 simultaneous operation mode, when the first input terminal RFin1 and the first output terminal RFout1 are associated with each other and the second input terminal RFin2 and the second output terminal RFout2 are associated with each other, the gates of the nMOSFETs M9, M10, M4, and M8 A high level control signal is applied to the gates of nMOSFETs M1 to M3 and M5 to M7. As a result, as shown in FIG. 5, the switches SW1 to SW3 and SW5 to SW7 are turned off, and the switches SW9, SW10, SW4 and SW8 are turned on. With such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 through the signal path a in FIG. 4, and the second high-frequency output signal Sout2 is transmitted through the signal path d in FIG. It is output from the second output terminal RFout2. That is, the single output mode in which the first input terminal RFin1 and the first output terminal RFout1 are activated and the single output mode in which the second input terminal RFin2 and the second output terminal RFout2 are activated are executed simultaneously.

  In the LNA1, 2 simultaneous operation mode, when the first input terminal RFin1 and the second output terminal RFout2 are made to correspond and the second input terminal RFin2 and the first output terminal RFout1 are made to correspond, the gates of the nMOSFETs M9, M10, M5, and M7 A high level control signal is applied to the nMOSFETs M1 to M4, M6, and M8. As a result, as shown in FIG. 5, the switches SW1 to SW4, SW6, and SW8 are turned off, and the switches SW9, SW10, SW5, and SW7 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the second output terminal RFout2 through the signal path b in FIG. 4, and the second high-frequency output signal Sout2 is passed through the signal path c in FIG. It is output from the first output terminal RFout1. That is, the single output mode in which the first input terminal RFin1 and the second output terminal RFout2 are activated and the single output mode in which the second input terminal RFin2 and the first output terminal RFout1 are activated are executed simultaneously.

  According to the second embodiment, since one splitter 3 can be shared between the two high-frequency LNAs 2, 4, more operation modes can be realized with a compact configuration than in the first embodiment.

(Third embodiment)
Next, a third embodiment using three high frequency low noise amplifiers will be described. FIG. 6 is a circuit diagram showing the high-frequency semiconductor device 1 according to the third embodiment. As shown in FIG. 6, the high-frequency semiconductor device 1 of the third embodiment further includes the first high-frequency LNA2, the second high-frequency LNA4, and the first to tenth switches SW1 to SW10 described in the second embodiment. And a third high-frequency LNA 5 that is an example of a third amplifier, an eleventh switch SW11, and a twelfth switch SW12.

  The third high frequency LNA 5 amplifies the third high frequency input signal Sin3, which is an example of a third input signal, and outputs a third high frequency output signal Sout3, which is an example of an output signal of the third amplifier.

  As shown in FIG. 6, the third high frequency LNA 5 is disposed on the SOI substrate, one end is connected to the third input terminal RFin3, and the output node Ng at the other end is connected to the first output terminal RFout1 and the second output terminal RFout2. It is connected. The basic circuit configuration of the third high frequency LNA 5 is the same as that of the first high frequency LNA 2. The third high frequency LNA 5 outputs a third high frequency output signal Sout3 obtained by amplifying the third high frequency input signal Sin3 input from the third input terminal RFin3.

  The first to twelfth switches SW1 to SW12 output the first high-frequency output signal Sout1 from the first output terminal RFout1, the second output terminal RFout2, or branch by the splitter 3 by the switching control. Switching between output from both the first and second output terminals RFout1 and RFout2 is performed. The first to twelfth switches SW1 to SW12 output the second high-frequency output signal Sout2 from the first output terminal RFout1, the second output terminal RFout2, or branch by the splitter 3 according to the switching control. Then, the output is switched from both the first and second output terminals RFout1 and RFout2. Further, the first to twelfth switches SW1 to SW12 switch whether to output the third high-frequency output signal Sout2 from the first output terminal RFout1 or the second output terminal RFout2 by the switching control.

  The eleventh switch SW11 includes an nMOSFET M11 and a resistor r11. The nMOSFET M11 is connected between the output node Ng of the third high frequency LNA5 and the first output terminal RFout1. More specifically, the nMOSFET M11 is connected between the output node Ng and the node Nb. The resistor r11 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M11. The eleventh switch SW11 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M11 via the resistor r11.

  The twelfth switch SW12 includes an nMOSFET M12 and a resistor r12. The nMOSFET M12 is connected between the output node Ng of the third high frequency LNA5 and the second output terminal RFout2. More specifically, the nMOSFET M12 is connected between the output node Ng and the node Nc. The resistor r12 has a high resistance value such as 100 kΩ and is connected to the gate of the nMOSFET M12. The nMOSFET M12 is ON / OFF controlled by a control signal input to the gate of the nMOSFET M12 via the resistor r12.

  In the eleventh and twelfth switches SW11 and SW12 having the above-described configuration, the eleventh switch SW11 is turned on at least when the switches SW1 to SW4, SW6, SW7, and SW12 are turned off, thereby causing the third high-frequency output signal Sout3 to be turned on. Output from the first output terminal RFout1. The twelfth switch SW12 is turned on at least when the switches SW1 to SW3, SW5, SW6, SW8, and SW11 are turned off, thereby outputting the third high-frequency output signal Sout3 from the second output terminal RFout2.

(action mode)
FIG. 7 is a diagram showing a truth table of the high-frequency semiconductor device 1 according to the third embodiment. As shown in the truth table of FIG. 7, the high-frequency semiconductor device 1 according to the third embodiment having the above-described configuration has a single output mode, a split mode, an LNA1, 2 simultaneous operation mode, an LNA1, 3 simultaneous operation. It is possible to operate in five operation modes, that is, a mode and LNA 2 and 3 simultaneous operation modes.

  In the single output mode in the third embodiment, the high-frequency signals Sout1, Sout2, and Sout3 output from any one of the first high-frequency LNA2, the second high-frequency LNA4, and the third high-frequency LNA5 are output to the first output terminal RFout1 or the first output terminal RFout1. This is an operation mode for outputting from the two output terminal RFout2.

  When the first input terminal RFin1 and the first output terminal RFout1 are activated in the single output mode, a high level control signal is applied to the gates of the nMOSFETs M9 and M4, and the gates of the nMOSFETs M1 to M3, M5 to M8, and M10 to M12. A low level control signal is applied to. Thereby, as shown in FIG. 7, SW1-SW3, SW5-SW8, SW10-SW12 are turned off, and nMOSFETs M9, M4 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 through the signal path a of FIG. 6 via the switches SW9 and SW4.

  When the first input terminal RFin1 and the second output terminal RFout2 are activated in the single output mode, a high level control signal is applied to the gates of the nMOSFETs M9 and M5, and the gates of the nMOSFETs M1 to M4, M6 to M8, and M10 to M12. A low level control signal is applied to. Thereby, as shown in FIG. 7, the switches SW1 to SW4, SW6 to SW8, SW10 to SW12 are turned off, and the switches SW9 and SW5 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the second output terminal RFout2 through the signal path b of FIG. 6 via the switches SW9 and SW5.

  When the second input terminal RFin2 and the first output terminal RFout1 are activated in the single output mode, a high level control signal is applied to the gates of the nMOSFETs M10 and M7, and the gates of the nMOSFETs M1 to M6, M8, M9, M11, and M12. A low level control signal is applied to. As a result, as shown in FIG. 7, the switches SW1 to SW6, SW8, SW9, SW11, and SW12 are turned off and the switches SW10 and SW7 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the first output terminal RFout1 through the signal path c of FIG. 6 via the switches SW10 and SW7.

  In the single output mode, when the second input terminal RFin2 and the second output terminal RFout2 are activated, a high-level control signal is applied to the gates of the nMOSFETs M10 and M8, and the gates of the nMOSFETs M1 to M7, M9, M11, and M12 are low. Apply level control signal. As a result, as shown in FIG. 7, the switches SW1 to SW7, SW9, SW11, and SW12 are turned off and the switches SW10 and SW8 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the second output terminal RFout2 through the signal path d in FIG. 6 via the switches SW10 and SW8.

  In the single output mode, when the third input terminal RFin3 and the first output terminal RFout1 are activated, a high level control signal is applied to the gate of the nMOSFET M11, and a low level control signal is applied to the gates of the nMOSFETs M1 to M10 and M12. To do. As a result, as shown in FIG. 7, the switches SW1 to SW10 and SW12 are turned off and the switch SW11 is turned on. By such on / off control, the third high-frequency output signal Sout3 is output from the first output terminal RFout1 through the signal path g of FIG. 6 via the switch SW11.

  In the single output mode, when the third input terminal RFin3 and the second output terminal RFout2 are activated, a high level control signal is applied to the gate of the nMOSFET M12, and a low level control signal is applied to the gates of the nMOSFETs M1 to M11. As a result, as shown in FIG. 7, the switches SWSW1 to SW11 are turned off and the switch SW12 is turned on. By such on / off control, the third high-frequency output signal Sout3 is output from the second output terminal RFout2 through the signal path h of FIG. 6 via the switch SW12.

  In the split mode in the third embodiment, the high-frequency output signals Sout1 and Sout2 output from either the first high-frequency LNA2 or the second high-frequency LNA4 are branched by the splitter 3 as in the second embodiment. This is an operation mode for outputting from the first output terminal RFout1 and the second output terminal RFout2.

  In the split mode, when the first input terminal RFin1 is activated, a high level control signal is applied to the gates of the nMOSFETs M9 and M1 to M3, and a low level control signal is applied to the gates of the nMOSFETs M4 to M8 and M10 to M12. . As a result, as shown in FIG. 7, the switches SW4 to SW8 and SW10 to SW12 are turned off, and the switches SW9 and SW1 to SW3 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 and the second output terminal RFout2 through the signal path e of FIG.

  When the second input terminal RFin2 is an active input in the split mode, a high level control signal is applied to the gates of the nMOSFETs M10, M2, M3, and M6, and the gates of the nMOSFETs M1, M4, M5, M7 to M9, M11, and M12 A low level control signal is applied to. As a result, as shown in FIG. 7, the nMOSFETs M1, M4, M5, M7 to M9, M11, and M12 are turned off, and the nMOSFETs M10, M2, M3, and M6 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the first output terminal RFout1 and the second output terminal RFout2 through the signal path f of FIG.

  In the LNA1, 2 simultaneous operation mode, when the first input terminal RFin1 and the first output terminal RFout1 are associated with each other and the second input terminal RFin2 and the second output terminal RFout2 are associated with each other, the gates of the nMOSFETs M9, M10, M4, and M8 A high level control signal is applied to the gates of nMOSFETs M1 to M3, M5 to M7, M11, and M12. Thereby, as shown in FIG. 7, the switches SW1 to SW3, SW5 to SW7, SW11, and SW12 are turned off, and the switches SW9, SW10, SW4, and SW8 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 through the signal path a in FIG. 6, and the second high-frequency output signal Sout2 is transmitted through the signal path d in FIG. It is output from the second output terminal RFout2.

  In the LNA1, 2 simultaneous operation mode, when the first input terminal RFin1 and the second output terminal RFout2 are made to correspond and the second input terminal RFin2 and the first output terminal RFout1 are made to correspond, the gates of the nMOSFETs M9, M10, M5, and M7 A high level control signal is applied to the nMOSFETs M1 to M4, M6, M8, M11 and M12, and a low level control signal is applied to the gates of the nMOSFETs M1 to M4, M6, M8, M11 and M12. Accordingly, as shown in FIG. 7, the switches SW1 to SW4, SW6, SW8, SW11, and SW12 are turned off, and the switches SW9, SW10, SW5, and SW7 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the second output terminal RFout2 through the signal path b in FIG. 6, and the second high-frequency output signal Sout2 is passed through the signal path c in FIG. It is output from the first output terminal RFout1.

  The LNA1, 3 simultaneous operation mode is an operation mode in which both the first high frequency LNA2 and the third high frequency LNA5 operate simultaneously. Similarly to the LNA1 and 2 simultaneous operation modes, in the LNA1 and 3 simultaneous operation modes, high frequency signals Sin1 and Sin3 belonging to different frequency bands are input to both the first input terminal RFin1 and the third input terminal RFin3. May be.

  In the LNA1, 3 simultaneous operation mode, when the first input terminal RFin1 and the first output terminal RFout1 are associated with each other, and the third input terminal RFin3 and the second output terminal RFout2 are associated with each other, the gates of the nMOSFETs M9, M4, and M12 are high. A level control signal is applied, and a low level control signal is applied to the gates of the nMOSFETs M1 to M3, M5 to M8, M10, and M11. As a result, as shown in FIG. 7, the switches SW1 to SW3, SW5 to SW8, SW10, and SW11 are turned off, and the nMOSFETs SW9, SW4, and SW12 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the first output terminal RFout1 through the signal path a in FIG. 6, and the third high-frequency output signal Sout3 is passed through the signal path h in FIG. It is output from the second output terminal RFout2.

  In the LNA1 and 3 simultaneous operation modes, when the first input terminal RFin1 and the second output terminal RFout2 are associated with each other and the third input terminal RFin3 and the first output terminal RFout1 are associated with each other, the gates of the nMOSFETs M9, M5, and M11 are high. A level control signal is applied, and a low level control signal is applied to the gates of the nMOSFETs M1 to M4, M6 to M8, M10, and M12. Accordingly, as shown in FIG. 7, the switches SW1 to SW4, SW6 to SW8, SW10, and SW12 are turned off, and the switches SW9, SW5, and SW11 are turned on. By such on / off control, the first high-frequency output signal Sout1 is output from the second output terminal RFout2 through the signal path b in FIG. 6, and the third high-frequency output signal Sout3 is passed through the signal path g in FIG. It is output from the first output terminal RFout1.

  The LNA 2 and 3 simultaneous operation mode is an operation mode in which both the second high frequency LNA 4 and the third high frequency LNA 5 operate simultaneously. As in the LNA 1 and 2 simultaneous operation modes, in the LNA 2 and 3 simultaneous operation modes, high-frequency signals Sin 2 and Sin 3 belonging to different frequency bands are input to both the second input terminal RFin 2 and the third input terminal RFin 3. May be.

  In the LNA2 and 3 simultaneous operation modes, when the second input terminal RFin2 and the first output terminal RFout1 are associated with each other and the third input terminal RFin3 and the second output terminal RFout2 are associated with each other, the gates of the nMOSFETs M10, M7, and M12 are high. A level control signal is applied, and a low level control signal is applied to the gates of the nMOSFETs M1 to M6, M8, M9, and M11. Thereby, as shown in FIG. 7, the switches SW1 to SW6, SW8, SW9, and SW11 are turned off, and the switches SW10, SW7, and SW12 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the first output terminal RFout1 through the signal path c of FIG. 6 via the switches SW10 and SW7, and the third high-frequency output signal Sout3 is output from the switch SW12. Is output from the second output terminal RFout2 through the signal path h of FIG.

  In the LNA2 and 3 simultaneous operation modes, when the second input terminal RFin2 and the second output terminal RFout2 are associated with each other and the third input terminal RFin3 and the first output terminal RFout1 are associated with each other, the gates of the nMOSFETs M10, M8, and M11 are high. A level control signal is applied, and a low level control signal is applied to the gates of the nMOSFETs M1 to M7, M9, and M12. Accordingly, as shown in FIG. 7, the switches SWSW1 to SW7, SW9, and SW12 are turned off, and the switches SW10, SW8, and SW11 are turned on. By such on / off control, the second high-frequency output signal Sout2 is output from the second output terminal RFout2 through the signal path d in FIG. 6, and the third high-frequency output signal Sout3 is passed through the signal path g in FIG. It is output from the first output terminal RFout1.

  According to the third embodiment, one splitter 3 can be shared between the two high-frequency LNAs 2 and 4, and the third high-frequency signal can be amplified by the LNA 5 and output from the first or second output terminal. Therefore, more operation modes than the second embodiment can be realized with a compact configuration.

(Fourth embodiment)
Next, a fourth embodiment showing a specific example of the splitter 3 in the first to third embodiments will be described. FIG. 8 is a layout diagram of the splitter 3 in the high-frequency semiconductor device 1 according to the first to third embodiments.

  As shown in FIG. 8, in the splitter 3 of the fourth embodiment, a set of the first spiral inductor L1a and the second spiral inductor L2a so as to have a symmetrical shape in the X direction of FIG. 8 with the input node Nin as the center. And a set of a third spiral inductor L1b and a fourth spiral inductor L2b. The first to fourth spiral inductors L1a, L2a, L1b, and L2b are arranged linearly along the X direction.

  The first spiral inductor L1a has a substantially square outer shape having a side parallel to the X direction and a side parallel to the Y direction when viewed from above, and the timepiece shown in FIG. It is wound around. The first spiral inductor L1a allows a high-frequency output signal (that is, current) of the high-frequency LNA flowing from the input node Nin to flow clockwise.

  The second spiral inductor L2a has a substantially square outer shape having a side parallel to the X direction and a side parallel to the Y direction when seen in a plan view, from the outer peripheral side toward the inner peripheral side. It is wound clockwise. The second spiral inductor L2a allows the high-frequency output signal flowing from the first spiral inductor L1a to flow counterclockwise.

  As described above, since the winding directions of the first spiral inductor L1a and the second spiral inductor L2a are opposite to each other, the coupling coefficient between the first spiral inductor L1a and the second spiral inductor L2a is positive.

  The third spiral inductor L1b is disposed at a position opposite to the first spiral inductor L1a with respect to the input node Nin. The third spiral inductor L1b has a substantially square outer shape having a side parallel to the X direction and a side parallel to the Y direction when seen in a plan view, and is opposite to that shown in FIG. It is wound clockwise. The third spiral inductor L1b flows the high-frequency output signal of the high-frequency LNA flowing from the input node Nin counterclockwise.

  The fourth spiral inductor L2b has a substantially square outer shape having a side parallel to the X direction and a side parallel to the Y direction when seen in a plan view, from the outer peripheral side toward the inner peripheral side. It is wound around. The fourth spiral inductor L2b allows the high-frequency output signal flowing from the third spiral inductor L1b to flow clockwise.

  As described above, since the winding directions of the third spiral inductor L1b and the fourth spiral inductor L2b are opposite to each other, the coupling coefficient between the third spiral inductor L1b and the fourth spiral inductor L2b is positive.

  Further, since the first and second spiral inductors L1a and L2a and the third and fourth spiral inductors L1b and L2b are symmetrical in the X direction with the input node Nin as the center, the first and second spiral inductors L1a, The coupling coefficient of L2a is the same as the coupling coefficient of the third and fourth spiral inductors L1b and L2b. Since the distance between the first spiral inductor L1a and the third spiral inductor L1b is sufficiently large, the coupling coefficient between the first spiral inductor L1a and the third spiral inductor L1b is negligibly small.

  Further, in the splitter 3 of the fourth embodiment, the first capacitor C1, the second capacitor C2a, and the third capacitor C2b are formed with MIM (Metal-Insulator-Metal) capacitance or MOM (Metal-Oxide-Metal) capacitance. be able to.

Next, the S parameter characteristics of the splitter 3 of the fourth embodiment having the above configuration will be described. FIG. 9A shows the splitter 3 when the input node Nin is port 1, the first output node Nout1 is port 2, and the second output node Nout2 is port 3 in the high-frequency semiconductor device 1 according to the fourth embodiment. it is a graph showing the S parameter _{S 21.} FIG. 9 (b), the high-frequency semiconductor device 1 according to the fourth embodiment, a graph showing the S parameter S ₁₁ of the splitter 3. FIG. 9 (c), the high-frequency semiconductor device 1 according to the fourth embodiment, a graph showing the S parameter S ₂₂ of the splitter 3. FIG. 9 (d) in the high-frequency semiconductor device 1 according to the fourth embodiment, a graph showing the S parameter S ₂₃ of the splitter 3.

However, in the splitter 3 corresponding to the S parameter in FIGS. 9A to 9D, the first spiral inductor L1a and the third spiral inductor L1b have the parameters shown below.
Winding number N: 5.25
External side length D: 190 μm
Wiring width W: 6μm
Wiring interval S: 4 μm

In the splitter 3 corresponding to the S parameter in FIGS. 9A to 9D, the second spiral inductor L2a and the fourth spiral inductor L2b have the parameters shown below.
Winding number N: 5.25
External side length D: 175 μm
Wiring width W: 6μm
Wiring interval S: 4 μm

  Further, in the splitter 3 corresponding to the S parameter of FIGS. 9A to 9D, the capacitance of the first capacitor C1 is 0.254 pF, and the capacitances of the second capacitor C2a and the third capacitor C2b are 1. 131 pF. The resistance value of the resistor R is 100Ω.

  9A to 9D, the horizontal axis represents the frequency (GHz), and the vertical axis represents the S parameter size (dB). In the high-frequency semiconductor device 1, the use band is 1.8 GHz to 2.2 GHz.

S _21, the mean input node is S parameter on the Performance of the signal toward the first output node Nout1 from _Nin, the more _{S 21} is large, the loss of a signal traveling from the input node Nin to the first output node Nout1 less To do. As shown in FIG. 9 (a), the worst value of _{S 21} in the used band (1.8~2.2GHz) is -3.7DB. Since the splitter 3 has a configuration in which the high-frequency output signal from the input node Nin is divided into two, that is, equally distributed, it has an attenuation of at least 3 dB in principle. S ₂₁ is that -3.7dB a substantial loss due to the parasitic resistance is 0.7 dB. In general, if the loss is 1 dB or less, it can be said that the characteristic is good. Therefore, S _{21 in} FIG. 9A has a good characteristic in which the loss of the signal from the input node Nin to the first output node Nout1 is sufficiently suppressed. Show.

S ₁₁ is an S parameter related to the reflection characteristic of the signal at the input node Nin, and means that the smaller the S ₁₁ , the smaller the loss due to reflection at the input node Nin. As shown in FIG. 9 (b), the value of _{S 11} in the used band (1.8~2.2GHz) is a -20dB below, _{S 11} in FIG. 9 (b), at the input node Nin It shows good characteristics in which loss due to reflection is sufficiently suppressed.

S ₂₂ is the S parameter relating reflection characteristics of the signal at the first output node _Nout1, as _{S 22} is smaller, it means that losses due to reflection at the first output node Nout1 less. As shown in FIG. 9 (c), the value of _{S 22} in the used band (1.8~2.2GHz) is a -20dB below, _{S 22} in FIG. 9 (c), a first output node Nout1 It shows a good characteristic in which the loss due to reflection is sufficiently suppressed.

S ₂₃ is the S parameter on the Performance of the signal directed from the second output node Nout2 to the first output node _Nout1, as _{S 23} is large, the loss of the signal directed from the second output node Nout2 to the first output node Nout1 It means less. In other _words, as the _{S 23} is large, it means that isolation of the first output node Nout1 and a second output node Nout2 poor. As shown in FIG. 9 (d), the value of _{S 23} in the used band (1.8~2.2GHz) is a -20dB below, _{S 23} in FIG. 9 (d) a first output node Nout1 And the second output node Nout2 shows a good characteristic in which sufficient isolation is ensured.

  Further, the splitter 3 of the fourth embodiment is laid out as shown in FIG. 8 whereas the total sum of inductances when the first and second spiral inductors L1a and L2a are present alone is 10.638 nH. As a result, the inductance from the input node Nin to the first output node Nout1 increased by 12.124 nH, that is, 14%. This is because the mutual inductance of both the first spiral inductor L1a and the second spiral inductor L2a is added to the sum of the self-inductance due to the positive coupling coefficient. Therefore, the inductance necessary for configuring the splitter 3 can be realized with a small layout area. The same applies to the third spiral inductor L1b and the fourth spiral inductor L2b.

  Next, an example of a preferable line width W of the spiral inductors L1a, L2a, L1b, and L2b will be described. FIG. 10 is a graph showing the dependency of the passage loss of the splitter 3 and the length of the splitter 3 on the line width of the spiral inductor in the high-frequency semiconductor device 1 according to the fourth embodiment. More specifically, the solid line graph in FIG. 10 is a graph showing the dependency on the passage loss, and the broken line graph in FIG. 10 is a graph showing the dependency on the length of the splitter 3. The horizontal axis of FIG. 10 is the line width of the spiral inductors L1a, L2a, L1b, and L2b. The vertical axis in FIG. 10 represents the passage loss of the splitter 3 and the length of the splitter 3 in the X direction.

  As shown in FIG. 10, when the line width W of the spiral inductors L1a, L2a, L1b, and L2b is reduced, the length of the splitter 3 is reduced, but the passage loss is increased. As shown in FIG. 10, it can be seen that when the line width W is smaller than 6 μm, the slope of the passage loss increases and the passage loss increases rapidly.

  In view of such characteristics, it is preferable that the line width W of the spiral inductors L1a, L2a, L1b, and L2b is approximately 6 μm. By setting the line width W to 6 μm, it is possible to achieve both the suppression of the layout area and the suppression of the passage loss.

  According to the fourth embodiment, since the spiral inductors L1a, L2a, L1b, and L2b are laid out so that the coupling coefficient is positive, it is possible to ensure the necessary inductance for the splitter 3 while suppressing the size.

(Fifth embodiment)
Next, as a fifth embodiment, examples of preferable line widths of the spiral inductor Ls and the inductor Ld of the first high frequency LNA 2 in the first to third embodiments will be described.

  The line width of the spiral inductor Ls is preferably set to a large value such as 16 μm. Because only 0. This is because the parasitic resistance of the spiral inductor Ls of several Ω causes significant deterioration of the noise figure NF. Note that the value of the spiral inductor Ls is about 1 nH in the case of an LNA for 2 GHz band, and therefore the number of turns of the spiral inductor Ls is relatively small. For this reason, even if the line width is as large as 16 μm, the outer size can be kept relatively small at about 150 μm.

  On the other hand, the line width of the inductor Ld is desirably a small value such as 4 μm. This is because the value of the inductor Ld is about 10 nH in the case of an LNA for the 2 GHz band, and the outer size is increased unless the line width is reduced. By reducing the line width, the parasitic resistance of the inductor Ld is increased and the Q value is lowered. However, if the line width is about 4 μm, the reduction of the Q value is not a problem. This is because, as shown in FIG. 2, a resistor Rd is connected in parallel to the inductor Ld for stabilization. Specifically, if the resistance Rd is increased in anticipation of a decrease in the Q value in the inductor Ld, the combined resistance of the resistance Rd and the parasitic resistance of the inductor Ld can be reduced, so that the inductor Ld and the resistance Rd are connected in parallel. A sufficiently large Q value can be secured as a circuit.

From the above viewpoint, it is desirable that the wiring width of the spiral inductor Ls and the wiring width of the inductor Ld satisfy the following expression.
WLd <W1 <WLs (1)
However, in Formula (1), WLd is the wiring width of the inductor Ld. W1 is the wiring width of each of the spiral inductors L1a, L2a, L1b, and L2b of the splitter 3. WLs is the wiring width of the spiral inductor Ls.

  According to the fifth embodiment, the wiring width of the spiral inductor Ls is made larger than the wiring width of the spiral inductors L1a, L2a, L1b, L2b, and the wiring width of the inductor Ld is set to the wiring width of the spiral inductors L1a, L2a, L1b, L2b. By making it smaller, size, noise, and loss can be suppressed in a well-balanced manner.

(Modification)
Next, modified examples of the switches in the first to third embodiments will be described. FIG. 11A is a diagram illustrating a first modification of the switch. FIG. 11B is a diagram illustrating a second modification of the switch.

  In each of the embodiments described above, the switch SW is composed of an nMOSFET. However, the switch SW is not limited to such a configuration.

  For example, as shown in FIG. 11A, the switch SW may include a diode D having an anode connected to the body of the nMOSFET M and a cathode connected to the gate of the nMOSFET M. The switch SW of FIG. 11A is effective when a negative potential is applied to the gate as a low-level control signal Cont that turns off the nMOSFET M.

  The advantage of applying the negative potential control signal Cont to turn off the nMOSFET M is that Vth for turning on the nMOSFET M can be set near 0 V, so that Vgs−Vth in the on state is increased and the on resistance is reduced. It is to reduce.

  According to the switch SW in FIG. 11A, the diode D is connected between the body and the gate so that the body side is the anode, so that when the negative potential control signal Cont is applied, the hole in the body passes through the diode D to the gate. Therefore, the drain-source breakdown voltage can be improved. Thereby, the off state can be maintained even when the output amplitude of the LNA is large.

  Further, as shown in FIG. 11B, the switch SW may be a T-type switch having the basic configuration of the switch SW in FIG. In the switch SW in FIG. 11B, the drain of the nMOSFET M3 whose source is grounded is connected between the cascode-connected nMOSFET M1 and the nMOSFET M2 constituting the high-frequency signal path. Like each of the nMOSFETs M1 to M3, a diode D is connected between the body and the gate so that the body side is an anode. A control signal Cont / obtained by logically inverting the control signal Cont applied to the gates of the nMOSFETs M1 and M2 is applied to the gate of the nMOSFET M3.

  According to the T-type switch of FIG. 11B, the source of the nMOSFET M01 and the drain of the nMOSFET M02 can be grounded by turning on the nMOSFET M03 while the nMOSFET M1 and the nMOSFET M2 are off. Thereby, the OFF state can be maintained more effectively as compared with the switch SW in FIG.

(Sixth embodiment)
Next, a sixth embodiment in which the second capacitor C2a and the third capacitor C2b are variable capacitors in the high-frequency semiconductor device 1 including the first high-frequency LNA2 and the second high-frequency LNA4 will be described. FIG. 12 is a circuit diagram showing the high-frequency semiconductor device 1 according to the fifth embodiment.

  In the second embodiment shown in FIGS. 4 and 5, in the high-frequency semiconductor device 1 including the first high-frequency LNA2 and the second high-frequency LNA4, the second capacitor C2a and the third capacitor C2b have fixed capacitances. An example is described.

  On the other hand, the second capacitor C2a in the sixth embodiment is an example of a first variable capacitor whose capacitance can be changed. Specifically, one end of the second capacitor C2a is connected between the first spiral inductor L1a and the second spiral inductor L2a, and the other end is connected to a ground potential that is an example of a third reference potential. Have The third capacitor C2b is an example of a second variable capacitor whose capacitance can be changed. Specifically, one end of the third capacitor C2b is connected between the third spiral inductor L1b and the fourth spiral inductor L2b, and the other end is connected to a ground potential that is an example of a fourth reference potential. Have

  FIG. 13 is a circuit diagram showing variable capacitors C2a and C2b in the high-frequency semiconductor device 1 according to the sixth embodiment. More specifically, as shown in FIG. 13, the second capacitor C2a includes two capacitors C2a_1 and C2a_2 connected in parallel between the first signal path P1 and the ground potential (third reference potential). Among the two capacitors C2a_1 and C2a_2, the switch SW13 is connected in series to the capacitor C2a_2 located on the second spiral inductor L2a side. The capacitor C2a_1 located on the first spiral inductor L1a side has a larger capacitance than the capacitor C2a_2 located on the second spiral inductor L2a side to which the switch SW13 is connected.

  The switch SW13 has an nMOSFET M13 and a resistor r13 connected to the gate of the nMOSFET M13. The switch SW13 is ON / OFF controlled by a fourth control signal Cont4 input to the gate of the nMOSFET M13 via the resistor r13. When the switch SW13 is turned on, the second capacitor C2a has a combined capacitance in parallel with the two capacitors C2a_1 and C2a_2. On the other hand, when the switch SW13 is turned off, the second capacitor C2a has a capacitance due to one capacitor C2a_1. Therefore, the capacitance of the second capacitor C2a can be switched according to the on / off control of the switch SW13. In addition, the capacitor which comprises the 2nd capacitor C2a is not limited to two, Three or more may be sufficient.

  As shown in FIG. 13, the third capacitor C2b includes two capacitors C2b_1 and C2b_2 connected in parallel between the second signal path P2 and the ground potential (fourth reference potential), and two capacitors C2b_1. , C2b_2 and a switch SW14 connected in series to a capacitor C2b_2 located on the fourth spiral inductor L2b side. The capacitor C2b_1 located on the third spiral inductor L1b side has a larger capacitance than the capacitor C2b_2 located on the fourth spiral inductor L2b side to which the switch SW14 is connected.

  The capacitor C2b_1 has the same capacitance as the capacitor C2a_1 of the second capacitor C2a. The capacitor C2b_2 has the same capacitance as the capacitor C2a_2 of the second capacitor C2a.

  The switch SW14 has an nMOSFET M14 and a resistor r14 connected to the gate of the nMOSFET M14. The switch SW14 is ON / OFF controlled by a fifth control signal Cont5 input to the gate of the nMOSFET M14 via the resistor r14. When the switch SW14 is turned on, the third capacitor C2b has a combined capacitance in parallel due to the two capacitors C2b_1 and C2b_2. On the other hand, when the switch SW14 is turned off, the third capacitor C2b has a capacitance due to one capacitor C2b_1. Therefore, the capacitance of the third capacitor C2b can be switched according to the on / off control of the switch SW14. In addition, the capacitor which comprises the 3rd capacitor C2b is not limited to two, Three or more may be sufficient.

  Similarly to the second embodiment, the first to tenth switches SW1 to SW10 (output control unit) output the first high-frequency output signal Sout1 from the first output terminal RFout1 or the second output by the switching control. Switching between output from the terminal RFout2 or branching by the splitter 3 and output from both the first and second output terminals RFout1 and RFout2 is performed. Further, the first to tenth switches SW1 to SW10 output the second high-frequency output signal Sout2 from the first output terminal RFout1, the second output terminal RFout2, or branch by the splitter 3 by the switching control. Then, the output is switched from both the first and second output terminals RFout1 and RFout2.

  Also, as shown in FIG. 12, in the sixth embodiment, the first high-frequency input signal Sin1 input to the first high-frequency LNA2 is a low-frequency band Band-L signal and is input to the second high-frequency LNA4. The second high-frequency input signal Sin2 is a signal in the high frequency band Band-H. Accordingly, the first high frequency output signal Sout1 output from the first high frequency LNA2 is a signal in the low frequency band Band-L, and the second high frequency output signal Sout2 output from the second high frequency LNA4 is the high frequency band. This is a Band-H signal.

  The low frequency band Band-L is, for example, 1805 MHz to 2025 MHz. The high frequency band Band-H is, for example, 2110 MHz to 2200 MHz.

  In order to improve the signal characteristics of the splitter 3 for each of the different frequency bands Band-L and Band-H having a certain bandwidth, the switches SW13 and SW14 (output control unit) are connected to the first of the low frequency band Band-L. When the high-frequency output signal Sout1 is branched and output by the splitter 3, and when the second high-frequency output signal Sout2 of the high frequency band Band-H is branched and output by the splitter 3, the capacitances of the variable capacitors C2a and C2b are Switch to a different value. Hereinafter, switching of the capacitance by the variable capacitors C2a and C2b will be specifically described with reference to FIG.

  FIG. 14 is a diagram showing a correspondence relationship between an input signal and a variable capacitor control signal in the high-frequency semiconductor device 1 according to the sixth embodiment. As shown in FIG. 14, when the first high-frequency output signal Sout1 in the low frequency band Band-L is branched and output by the splitter 3, the control signal generation circuit (not shown) generates a high-level fourth control signal at the switch SW13. Cont4: High is input, and the fifth control signal Cont5: High at a high level is input to the switch SW14. That is, in the split mode in the low frequency band Band-L, the capacitances of the second capacitor C2a and the third capacitor C2b are increased by turning on the switches SW13 and SW14.

  On the other hand, as shown in FIG. 14, when the second high-frequency output signal Sout2 in the high frequency band Band-H is branched and output by the splitter 3, the control signal generation circuit sends a low-level fourth control signal to the switch SW13. Cont4: Low is input, and a low-level fifth control signal Cont5: Low is input to the switch SW14. That is, in the split mode using the high frequency band Band-H, the capacitances of the second capacitor C2a and the third capacitor C2b are reduced by turning off the switches SW13 and SW14.

  Thus, in the sixth embodiment, when the low frequency band Band-L is used, the capacitances of the second capacitor C2a and the third capacitor C2b are increased, and when the high frequency band Band-H is used, the second capacitor is increased. The capacitances of C2a and third capacitor C2b are decreased. By changing the capacitances of the second capacitor C2a and the third capacitor C2b in this way, the signal characteristics of the splitter 3 for different frequency bands Band-L and Band-H are improved as shown in the simulation results described later. be able to. Specifically, the S parameters S21, S22, and S23 can be improved over the entire regions of the low frequency band Band-L and the high frequency band Band-H.

  In addition to the above-described configuration, the high-frequency LNAs 2 and 4 in the sixth embodiment further include the amplitude (that is, power) of the output signals Sout1 and Sout2 in the split mode, and the non-split mode (single output mode and LNA1, In order to suppress the difference between the amplitudes of the output signals Sout1 and Sout2 (in the two simultaneous operation mode), the second embodiment has a different configuration. Hereinafter, the configuration of the high-frequency LNAs 2 and 4 different from the second embodiment will be specifically described with reference to FIGS. 15 and 16.

  FIG. 15 is a circuit diagram showing the first high-frequency LNA 2 in the high-frequency semiconductor device 1 according to the sixth embodiment. FIG. 16 is a diagram illustrating a correspondence relationship between an operation mode, bias voltages VB1 and VB2 of the first high frequency LNA2, and a control signal of the gain adjustment circuit 6 described later in the high frequency semiconductor device 1 according to the sixth embodiment. . The second high frequency LNA 4 has a suitable circuit constant different from that of the first high frequency LNA 2 in order to handle the high frequency band Band-H, but its basic configuration is the same as that of the first high frequency LNA 2. Therefore, in the following description, the detailed description of the second high frequency LNA 4 may be omitted, or the configuration of the second high frequency LNA 4 may be described with the configuration of the first high frequency LNA 2.

  As shown in FIG. 16, the bias voltage generation circuit 5 shown in FIG. 15 is inputted to the gate of the nMOSFET 1 in the split mode rather than the value VB1_single of the bias voltage VB1 inputted to the gate of the nMOSFET 1 in the single output mode. The value VB1_split of the bias voltage VB1 is increased. Although not shown, the bias voltage generation circuit 5 has a bias voltage input to the gate of the nMOSFET 1 in the split mode rather than the value of the bias voltage VB1 input to the gate of the nMOSFET 1 in the LNA 1 and 2 simultaneous operation modes. The value VB1_split of VB1 may be increased.

  Here, in the single output mode that does not pass through the splitter 3, the amplitudes of the output signals Sout1 and Sout2 are maintained from the output terminals LNAout of the high frequency LNA2 and 4 to the output terminals RFout1 and RFout2, whereas the split mode is maintained. In this case, the output signals Sout1 and Sout2 are divided by the splitter 3 and the amplitude is reduced (for example, halved).

  If the output signals Sout1 and Sout2 output from the high frequency LNAs 2 and 4 in the split mode are the same as those in the single output mode, the amplitude of the output signals Sout1 and Sout2 after passing through the splitter 3 is It will be greatly reduced than the time of. When the amplitude is greatly reduced, the reception sensitivity at a location far from the base station may be deteriorated in the split mode (that is, carrier aggregation).

  In contrast, according to the sixth embodiment, the value VB1_split of the bias voltage VB1 in the split mode is made larger than the value VB1_single of the bias voltage VB1 in the single output mode. The nMOSFET 1 to which the bias voltage VB1 is input operates in an operation region where the transconductance gm increases and the bias current Idd increases as the bias voltage VB1 increases. For this reason, the bias current Idd in the split mode in which the bias voltage VB1 is large is larger than the bias current Idd in the single output mode in which the bias voltage VB1 is small. By increasing the bias current Idd in the split mode, the output signals Sout1 and Sout2 in the split mode can be made larger than the output signals Sout1 and Sout2 in the single output mode. That is, the driving capability of the high frequency LNAs 2 and 4 in the split mode can be increased as compared with the single output mode. This can suppress the difference between the amplitude of the output signals Sout1 and Sout2 after passing through the splitter 3 in the split mode and the amplitude of the output signals Sout1 and Sout2 in the single output mode. Deterioration of reception sensitivity can be suppressed.

  In addition to the above configuration, in the sixth embodiment, as shown in FIG. 16, the bias voltage generation circuit 5 has a value VB2_single of the bias voltage VB2 input to the gate of the nMOSFET 2 in the single output mode, as shown in FIG. The value VB2_split of the bias voltage VB2 input to the gate of the nMOSFET 2 in the split mode is increased.

  By making VB2_split larger than VB2_single, the drain-source voltage of the nMOSFET 1 can be made constant in the single output mode and the split mode. As a result, the bias point can be prevented from deviating from the ideal state, and output signals Sout1 and Sout2 having desired amplitudes can be obtained.

  In addition to the above configuration, in the sixth embodiment, the high frequency LNAs 2 and 4 further include a gain adjustment circuit 6 shown in FIG. The gain adjustment circuit 6 adjusts the gain of the high frequency LNAs 2 and 4 in the non-split mode to a value smaller than the gain of the high frequency LNAs 2 and 4 in the split mode.

In the example of FIG. 15, the gain adjustment circuit 6 includes a capacitor Ca1, resistors R1 and a switch SW15 connected in series between the node _{N LNA} and the ground potential between the drain and the output terminal LNAout the nMOSFET. The switch SW15 has an nMOSFET 3 and a resistor r15 connected to the gate of the nMOSFET 3. The switch SW15 is ON / OFF controlled by a sixth control signal Cont6 input to the gate of the nMOSFET 3 via the resistor r15. When the switch SW15 is turned on, the gain adjustment circuit 6 is connected to the node N _LNA, and the gains of the high frequency LNAs 2 and 4 are reduced. On the other hand, when the switch SW15 is turned off, the gain adjustment circuit 6 is disconnected from the node N _LNA, and the gains of the high frequency LNAs 2 and 4 are increased.

  As shown in FIG. 16, in the single output mode, the control signal generation circuit inputs the high-level sixth control signal Cont6 to the gate of the nMOSFET 3 and turns on the switch SW15, whereby the high-frequency LNAs 2 and 4 Reduce gain. On the other hand, the control signal generation circuit increases the gain of the high-frequency LNAs 2 and 4 by inputting the low-level sixth control signal Cont6 to the gate of the nMOSFET 3 and turning off the switch SW15 in the split mode.

  Here, as described above, in the split mode, the value of the bias voltage VB1 is increased to increase the drive capability of the high frequency LNAs 2 and 4, so that the output signals Sout1 and Sout2 can be compared with those in the single output mode. Increase the amplitude.

  However, in the split mode, the ideal high-frequency LNAs 2 and 4 are not necessarily expected to have a driving capability, and may have a driving capability lower than the ideal driving capability.

  According to the gain adjustment circuit 6, in anticipation that an ideal driving capability may not be obtained in the split mode, the output signal in the single output mode is reduced by reducing the gain in the single output mode. The amplitudes of Sout1 and Sout2 can be reduced. Thereby, the difference between the amplitudes of the output signals Sout1 and Sout2 in the split mode and the amplitudes of the output signals Sout1 and Sout2 in the single output mode can be more reliably suppressed.

  The gain adjustment circuit 6 may be used to improve the output reflection loss (S22) of the high frequency LNAs 2 and 4 when the output terminal LNAout is the port 2.

  Next, a simulation example of the high-frequency semiconductor device 1 of the sixth embodiment having the above configuration will be described.

  In the simulation, each of the first high-frequency output signal Sout1 in the low frequency band Band-L from the first high-frequency LNA2 and the second high-frequency output signal Sout2 in the high frequency band Band-H from the second high-frequency LNA4. Signal characteristics were measured in two modes: output mode and split mode.

  Specifically, in the single output mode, S21, S11, and S22 were measured with the first input terminal RFin1 as port 1 and the first output terminal RFout1 as port 2. In the split mode, in addition to S21, S11, and S22, S23 was measured using the second output terminal RFout2 as port 3.

  In the simulation, the power supply potential VDD_LNA of the high frequency LNAs 2 and 4 was set to 1.8V.

  In the simulation in the split mode using the first high-frequency output signal Sout1 in the low frequency band Band-L, the capacitances of the second capacitor C2a and the third capacitor C2b are increased by turning on the switches SW13 and SW14. Set. On the other hand, in the simulation in the split mode using the second high-frequency output signal Sout2 in the high frequency band Band-H, the capacitances of the second capacitor C2a and the third capacitor C2b are reduced by turning off the switches SW13 and SW14. Set.

  Further, the value VB1_split of the bias voltage VB1 input to the gate of the nMOSFET 1 in the split mode simulation is made larger than the value VB1_single of the bias voltage VB1 input to the gate of the nMOSFET 1 in the simulation in the single output mode. Further, the value VB2_split of the bias voltage VB2 input to the gate of the nMOSFET 2 in the split mode simulation is made larger than the value VB2_single of the bias voltage VB21 input to the gate of the nMOSFET 2 in the single output mode simulation.

  In the simulation of the single output mode, the gain of the high frequency LNAs 2 and 4 is set to a small value by turning on the switch SW15 of the gain adjusting circuit 6. On the other hand, in the split mode simulation, the gain of the high frequency LNAs 2 and 4 is set to a large value by turning off the switch SW15.

  The other simulation conditions are the same as those in FIGS. 9A to 9D. The simulation results are shown in FIGS.

  FIG. 17 is a graph showing small signal characteristics in the single output mode in the low frequency band Band-L in the simulation example of the high-frequency semiconductor device 1 according to the sixth embodiment. FIG. 18 is a graph showing small signal characteristics in the split mode in the low frequency band Band-L in the simulation example of the high-frequency semiconductor device 1 according to the sixth embodiment. FIG. 19 is a graph showing small signal characteristics in the single output mode in the high frequency band Band-H in the simulation example of the high-frequency semiconductor device 1 according to the sixth embodiment. FIG. 20 is a graph showing small signal characteristics in the split mode in the high frequency band Band-H in the simulation example of the high-frequency semiconductor device 1 according to the sixth embodiment. FIG. 21 is a diagram showing a list of representative numerical values in the graphs of FIGS. 17 to 20 in the simulation example of the high-frequency semiconductor device 1 according to the sixth embodiment.

  As shown in FIG. 17 and FIG. 21, the small signal characteristic in the single output mode by the low frequency band Band-L is that S22 and S11 are smaller than −11 dB in the vicinity of 1915 MHz which is the center frequency of the low frequency band Band-L. It became the minimum value, and S21 became the maximum value larger than 18 dB. Also, in the minimum frequency 1805 MHz and the maximum frequency 2025 MHz in the low frequency band Band-L, S22 was smaller than -10 dB, S11 was smaller than -8 dB, and S21 was larger than 17 dB. The simulation results of FIGS. 17 and 21 show that the gain (S21) is large and the input reflection loss (S11) and the output reflection loss (S22) are sufficiently suppressed in the entire low frequency band Band-L. This is a good result. Further, as shown in FIG. 21, IP1 dB (1 dB compression point) was −16.0 dB, and good results were obtained with respect to large signal characteristics.

  As shown in FIGS. 18 and 21, the small signal characteristic in the split mode by the low frequency band Band-L has a minimum value of S23 smaller than −29 dB in the vicinity of 1915 MHz which is the center frequency of the low frequency band Band-L. , S11 is a minimum value smaller than −18 dB, S22 is smaller than −15 dB, and S21 is larger than 17 dB. Also, in the minimum frequency 1805 MHz and the maximum frequency 2025 MHz in the low frequency band Band-L, S23 was smaller than −20 dB, S11 was −13 dB or less, S22 was smaller than −14 dB, and S21 was larger than 16 dB. The simulation results of FIGS. 18 and 21 show that the gain (S21) is large and the input reflection loss (S11) and the output reflection loss (S22) are sufficiently suppressed in the entire low frequency band Band-L. And it can be said that this is a good result in which the isolation (S23) is sufficiently secured. In addition, as shown in FIG. 21, IP1 dB was −15.5 dB, and good results were obtained for large signal characteristics.

  As shown in FIGS. 19 and 21, the small signal characteristic in the single output mode by the high frequency band Band-H is the minimum value in which S22 is smaller than −15 dB in the vicinity of 2155 MHz which is the center frequency of the high frequency band Band-H. S11 is a minimum value smaller than −8 dB, and S21 is a maximum value larger than 18 dB. Also, in the minimum frequency 2110 MHz and the maximum frequency 2200 MHz of the high frequency band Band-H, S22 was smaller than -13 dB, S11 was smaller than -8 dB, and S21 was larger than 18 dB. The simulation results of FIGS. 19 and 21 show that the gain (S21) is large and the input reflection loss (S11) and the output reflection loss (S22) are sufficiently suppressed in the entire high frequency band Band-H. This is a good result. In addition, as shown in FIG. 21, IP1 dB was −15.4 dB, and good results were obtained for large signal characteristics.

  As shown in FIGS. 20 and 21, the small signal characteristic in the split mode by the high frequency band Band-H has a minimum value of S23 smaller than −30 dB in the vicinity of 2155 MHz which is the center frequency of the high frequency band Band-H. , S11 is a minimum value smaller than −14 dB, S22 is smaller than −13 dB, and S21 is larger than 17 dB. Also, in the minimum frequency 2110 MHz and the maximum frequency 2200 MHz in the high frequency band Band-H, S23 was smaller than −25 dB, S11 was −13 dB or less, S22 was smaller than −13 dB, and S21 was larger than 17 dB. The simulation results of FIGS. 20 and 21 show that the gain (S21) is large and the input reflection loss (S11) and the output reflection loss (S22) are sufficiently suppressed in the entire high frequency band Band-H. And it can be said that this is a good result in which the isolation (S23) is sufficiently secured. In addition, as shown in FIG. 21, IP1 dB was -14.2 dB, and good results were obtained for large signal characteristics.

  According to the sixth embodiment, when the first high-frequency output signal Sout1 of the low frequency band Band-L is output and when the second high-frequency output signal Sout2 of the high frequency band Band-H is output, By switching the capacitances of the variable capacitors C2a and C2b, the signal characteristics in each of the low frequency band Band-L and the high frequency band Band-H can be improved, and the robustness in using a wide band can be improved. .

  Further, according to the sixth embodiment, the bias voltage VB1 in the split mode is made larger than the bias voltage VB1 in the single output mode, thereby splitting the output signals Sout1 and Sout2 in the single output mode. The output signals Sout1 and Sout2 in the mode can be increased. As a result, the difference between the amplitudes of the output signals Sout1 and Sout2 after passing through the splitter 3 in the split mode and the amplitudes of the output signals Sout1 and Sout2 in the single output mode is suppressed, and reception in the split mode is performed. The deterioration of sensitivity can be suppressed.

(Seventh embodiment)
Next, a seventh embodiment for improving signal characteristics over a wide band will be described. FIG. 22 is a circuit diagram showing the splitter 3 according to the seventh embodiment.

  As shown in FIG. 22, the splitter 3 according to the seventh embodiment includes a resistor R (first resistor) connected between the first output node Nout1 and the second output node Nout2 shown in FIG. 1. The resistor R_2, which is an example of the second resistor, and the capacitors C_2a and C2b. The resistor R_2 and the capacitors C_2a and C2b are connected in series between the first output node Nout1 and the l second output node Nout2. More specifically, the capacitor C2_a is connected between the first output node Nout1 and the resistor R_2. The capacitor C2_b is connected between the resistor R_2 and the second output node Nout2. Capacitors C_2a and C2b have the same capacitance. The reason why the capacitor C_2a, the resistor R_2, and the capacitor C2b are connected in series in this order is to maintain symmetry in the layout.

  By providing such a resistor R_2 and capacitors C2_a and C2_b, signal characteristics over a wide band can be improved as shown in the following simulation results. In order to improve signal characteristics over a wide band, the resistance value of the resistor R_2 is preferably smaller than the resistance value of the resistor R. The resistance value of the resistor R is preferably larger than 100Ω.

  In FIG. 22, the capacitor C_1a having one end connected between the first spiral inductor L1a and the second spiral inductor L2a has the same configuration as that of the second capacitor C2a in FIG. The capacitor C_1b having one end connected between the third spiral inductor L1b and the fourth spiral inductor L2b has the same configuration as the third capacitor C2b of FIG.

  Next, a simulation example of the splitter 3 of the seventh embodiment having the above configuration will be described.

  FIG. 23 is a diagram illustrating circuit constants in the simulation example of the splitter 3 according to the seventh embodiment. In the simulation, S21, S11, S22, and S23 were measured for the splitter 3 having the configuration of FIG. 22 in which the circuit constants shown in the “Example” of FIG. 23 were set. In the simulation, S21, S11, S22, and S23 were measured for the splitter 3 similar to the configuration of FIG. 1 in which the circuit constants shown in the “comparative example” of FIG. 23 are set. In the measurement, the port 1 was taken as the input node of the splitter 3 as in the case of FIGS. 9 (a) to 9 (d). The port 2 was taken at the output end of the splitter 3 on the first signal path P1 side. The port 3 was taken at the output end of the splitter 3 on the second signal path P2 side.

  In the simulation, a signal in a frequency band called a so-called high band ranging from 2300 MHz to 2690 MHz was used. In the simulation, the parasitic resistances of the inductors L1a, L1b, L2a, and L2b were set to values obtained by changing the units of the inductors L1a, L1b, L2a, and L2b to Ω. For example, the inductances of the first spiral inductor L1a and the third spiral inductor L1b of the comparative example are 4.65 nH, and the parasitic resistance is 4.65Ω. The simulation results are shown in FIGS.

  FIG. 24 is a graph showing frequency characteristics in the simulation example of the splitter 3 according to the seventh embodiment. FIG. 25 is a graph showing frequency characteristics in a simulation example of the splitter 3 according to the comparative example of the seventh embodiment. FIG. 26 is a table showing a list of worst values in the band in the graphs of FIGS. 24 and 25 in the splitter simulation example according to the seventh embodiment.

  24 and FIG. 26, in the splitter 3 of the seventh embodiment, the worst value (minimum value) of S21 is −3. 3 in the frequency band (2300 MHz to 2690 MHz). The worst value (maximum value) of S11 is smaller than −22 dB, the worst value (maximum value) of S22 is smaller than −24 dB, and the worst value (maximum value) of S23 is smaller than −26 dB. .

  On the other hand, as shown in the “comparative example” of FIGS. 25 and 26, in the splitter 3 of the comparative example, the worst value (minimum value) of S21 is −3.5 dB in the frequency band (2300 MHz to 2690 MHz). The worst value (maximum value) of S11 was larger than −22 dB, the worst value (maximum value) of S22 was smaller than −24 dB, and the worst value (maximum value) of S23 was larger than −26 dB.

  As shown in FIG. 26, in the example, S21 is 0.1 dB better than the comparative example. This is because the value of the inductor is small and the parasitic resistance is small accordingly. Further, in the example, S23 was greatly improved with respect to the comparative example, and 3.8 dB was improved with respect to the comparative example. Moreover, although S22 deteriorated 2.5 dB compared with the comparative example, there is a sufficient margin with respect to the general required value of −20 dB.

  From the above simulation results, the splitter 3 of the seventh embodiment is superior to the splitter 3 of the comparative example in securing gain and isolation when using a wide band (2300 MHz to 2690 MHz), and practically uses reflection loss. It was confirmed that it can be suppressed to the extent that there is no problem.

  According to the seventh embodiment, in the high-frequency semiconductor device 1 including the splitter 3 having a narrow band characteristic in principle, it is possible to improve a wide band signal characteristic.

  Next, a modification of the splitter 3 according to the seventh embodiment will be described. FIG. 27 is a circuit diagram showing a splitter 3 according to a first modification of the seventh embodiment. FIG. 28 is a circuit diagram showing a splitter 3 according to a second modification of the seventh embodiment.

  In the example of FIG. 24, the capacitor C_2a, the resistor R_2, and the capacitor C2_b are sequentially connected in series between the first output node Nout1 and the second output node Nout2 in order to improve the broadband signal characteristics. On the other hand, as shown in FIG. 27, a resistor R_2, a capacitor C_2, and a resistor_R3 may be connected in series between the first output node Nout1 and the second output node Nout2. In this case, it is desirable that the resistors R_2 and R3 have the same resistance value in order to ensure layout symmetry. Also in the example of FIG. 27, an improvement in broadband signal characteristics can be expected. The splitter 3 of the seventh embodiment can also be applied to the high-frequency semiconductor device 1 of the first to sixth embodiments. For example, in order to apply to the sixth embodiment, as shown in FIG. 28, the capacitors C_1a and C_1b may be variable capacitors.

(Eighth embodiment)
Next, as an eighth embodiment, a layout example of the splitter 3 different from that in FIG. 8 will be described. FIG. 29 is a layout diagram of the splitter 3 in the high-frequency semiconductor device 1 according to the eighth embodiment.

  In the example of FIG. 8, all the spiral inductors L1a, L2a, L1b, and L2b are arranged linearly along the X direction. On the other hand, as shown in FIG. 29, the second spiral inductor L2a is arranged in the Y direction with respect to the first spiral inductor L1a, and the fourth spiral inductor L2b is arranged in the Y direction with respect to the third spiral inductor L1b. You may arrange | position in the X direction with respect to 2 spiral inductor L2a.

  Also in the eighth embodiment, since the spiral inductors L1a, L2a, L1b, and L2b are laid out so that the coupling coefficient is positive, it is possible to secure an inductor necessary for the splitter 3 while suppressing the size.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 High frequency semiconductor device, 2 1st high frequency LNA, 3 Splitter, SW1 1st switch, SW2 2nd switch, SW3 3rd switch, SW4 4th switch, SW5 5th switch

Claims (12)

An amplifier for amplifying the input signal;
A splitter for branching the output signal of the amplifier into a first signal path and a second signal path and performing impedance conversion of the first and second signal paths;
A first output terminal for outputting an output signal of the amplifier or a signal obtained by branching the output signal of the amplifier to the first signal path by the splitter;
A second output terminal that outputs an output signal of the amplifier or a signal obtained by branching the output signal of the amplifier to the second signal path by the splitter;
Switching whether the output signal of the amplifier is output from the first output terminal, output from the second output terminal, or branched from the splitter and output from both the first and second output terminals; An output control unit;
An SOI (Silicon On Insulator) substrate on which the amplifier, the splitter, and the output control unit are arranged. The output control unit
A first switch connected between an output node of the amplifier and an input node of the splitter;
A second switch connected between the first signal path and the first output terminal;
A third switch connected between the second signal path and the second output terminal;
A fourth switch connected between the output node of the amplifier and the first output terminal;
A fifth switch connected between the output node of the amplifier and the second output terminal;
The output control unit outputs the output signal of the amplifier from the first output terminal, outputs from the second output terminal, or branches by the splitter by switching control of the first to fifth switches. The semiconductor device according to claim 1, wherein the output is switched from both of the first and second output terminals. The amplifier includes a first amplifier that amplifies a first input signal, and a second amplifier that amplifies a second input signal,
The output control unit outputs the output signal of the first amplifier from the first output terminal, outputs from the second output terminal, or branches by the splitter and outputs from the first and second output terminals. Switching between outputting from both sides, and outputting the output signal of the second amplifier from the first output terminal, outputting from the second output terminal, or branching by the splitter, the first and second The semiconductor device according to claim 1, wherein switching between output from both of the output terminals is performed. The output control unit
A first switch connected between an output node of the first amplifier and an input node of the splitter;
A second switch connected between the first signal path and the first output terminal;
A third switch connected between the second signal path and the second output terminal;
A fourth switch connected between an output node of the first amplifier and the first output terminal;
A fifth switch connected between an output node of the first amplifier and the second output terminal;
A sixth switch connected between an output node of the second amplifier and an input node of the splitter;
A seventh switch connected between an output node of the second amplifier and the first output terminal;
An eighth switch connected between the output node of the second amplifier and the second output terminal;
A ninth switch connected between the first amplifier and an output node of the first amplifier;
A tenth switch connected between the second amplifier and an output node of the second amplifier,
The output control unit outputs the output signal of the first amplifier from the first output terminal, the second output terminal, or the splitter by switching control of the first to tenth switches. Switching between branching and outputting from both the first and second output terminals, and outputting the output signal of the second amplifier from the first output terminal, outputting from the second output terminal, or 4. The semiconductor device according to claim 3, wherein branching by the splitter and switching between output from both the first and second output terminals are performed. 5. The amplifier includes a first amplifier that amplifies a first input signal, a second amplifier that amplifies a second input signal, and a third amplifier that amplifies a third input signal,
The output control unit outputs the output signal of the first amplifier from the first output terminal, outputs from the second output terminal, or branches by the splitter and outputs from the first and second output terminals. Switching between outputting from both sides, and outputting the output signal of the second amplifier from the first output terminal, outputting from the second output terminal, or branching by the splitter, the first and second 2. Switching between whether to output from both output terminals and switching whether to output the output signal of the third amplifier from the first output terminal or from the second output terminal are performed. A semiconductor device according to 1. The output control unit
A first switch connected between an output node of the first amplifier and an input node of the splitter;
A second switch connected between the first signal path and the first output terminal;
A third switch connected between the second signal path and the second output terminal;
A fourth switch connected between an output node of the first amplifier and the first output terminal;
A fifth switch connected between an output node of the first amplifier and the second output terminal;
A sixth switch connected between an output node of the second amplifier and an input node of the splitter;
A seventh switch connected between an output node of the second amplifier and the first output terminal;
An eighth switch connected between the output node of the second amplifier and the second output terminal;
A ninth switch connected between the first amplifier and an output node of the first amplifier;
A tenth switch connected between the second amplifier and an output node of the second amplifier;
An eleventh switch connected between an output node of the third amplifier and the first output terminal;
A twelfth switch connected between an output node of the third amplifier and the second output terminal;
The output control unit outputs the output signal of the first amplifier from the first output terminal, the second output terminal, or the splitter by switching control of the first to twelfth switches. Switching between branching and outputting from both the first and second output terminals, and outputting the output signal of the second amplifier from the first output terminal, outputting from the second output terminal, or Switching between splitting at the splitter and outputting from both the first and second output terminals, and outputting the output signal of the third amplifier from the first output terminal, or outputting from the second output terminal The semiconductor device according to claim 5, wherein switching is performed. The splitter is
A first inductor and a second inductor connected in series on the first signal path;
A third inductor and a fourth inductor connected in series on the second signal path;
The semiconductor device according to claim 1, wherein the first to fourth inductors are spiral conductive patterns arranged on the SOI substrate. The amplifier is
A fifth inductor, a first transistor, a second transistor, and a sixth inductor connected in series between the first reference potential and the second reference voltage;
The input signal is input to the gate of the first transistor,
A bias voltage is input to the gate of the second transistor,
A signal corresponding to the drain voltage of the second transistor is output from the output node of the amplifier;
The wiring width of the fifth inductor is larger than the wiring width of the first to fourth inductors,
The semiconductor device according to claim 7, wherein a wiring width of the sixth inductor is smaller than a wiring width of the first to fourth inductors. The amplifier is
A first amplifier for amplifying a first input signal;
A second amplifier for amplifying the second input signal;
The splitter is
A first variable capacitor having one end connected between the first inductor and the second inductor and the other end connected to a third reference potential;
A second variable capacitor having one end connected between the third inductor and the fourth inductor and the other end connected to a fourth reference potential;
The output control unit
Whether the output signal of the first amplifier is output from the first output terminal, output from the second output terminal, or branched from the splitter and output from both the first and second output terminals Switching and outputting the output signal of the second amplifier from the first output terminal, outputting from the second output terminal, or branching by the splitter and outputting from both the first and second output terminals And switch between
When the output signal of the first amplifier is branched and output by the splitter, and when the output signal of the second amplifier is branched and output by the splitter, the capacitances of the first and second variable capacitors are The semiconductor device according to claim 7, wherein the semiconductor device is switched to a different value. The amplifier is
A first amplifier for amplifying a first input signal;
A second amplifier for amplifying the second input signal;
The splitter is
A first variable capacitor having one end connected between the first inductor and the second inductor and the other end connected to a third reference potential;
A second variable capacitor having one end connected between the third inductor and the fourth inductor and the other end connected to a fourth reference potential;
The output control unit
Whether the output signal of the first amplifier is output from the first output terminal, output from the second output terminal, or branched from the splitter and output from both the first and second output terminals Switching and outputting the output signal of the second amplifier from the first output terminal, outputting from the second output terminal, or branching by the splitter and outputting from both the first and second output terminals And switch between
When the output signal of the first amplifier is branched and output by the splitter, and when the output signal of the second amplifier is branched and output by the splitter, the capacitances of the first and second variable capacitors are Switch to a different value,
A bias voltage is input to the gate of the first transistor,
The value of the bias voltage input to the gate of the first transistor and the value of the bias voltage input to the gate of the second transistor are determined based on the output signal of the first amplifier or the second amplifier. The time when the output signal of the first amplifier or the second amplifier is branched by the splitter and output from both the first and second output terminals is larger than when the signal is output from one of the output terminals. Item 9. The semiconductor device according to Item 8.   The amplifier has a gain when the output signal of the first amplifier or the second amplifier is output from one of the first and second output terminals, and the output signal of the first amplifier or the second amplifier is the splitter. The semiconductor device according to claim 9, further comprising: a gain adjustment circuit that adjusts to a value that is smaller than a gain when the signal is branched and output from both of the first and second output terminals. The splitter is
A first resistor connected between a first output node of the splitter on the first signal path side and a second output node of the splitter on the second signal path side;
The semiconductor device according to claim 7, further comprising: a second resistor and a capacitor connected in series between the first output node and the second output node.

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