JP2018093149A - Light receiving element - Google Patents

Light receiving element Download PDF

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JP2018093149A
JP2018093149A JP2016237858A JP2016237858A JP2018093149A JP 2018093149 A JP2018093149 A JP 2018093149A JP 2016237858 A JP2016237858 A JP 2016237858A JP 2016237858 A JP2016237858 A JP 2016237858A JP 2018093149 A JP2018093149 A JP 2018093149A
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light receiving
receiving element
substrate
lens
semiconductor substrate
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JP6660282B2 (en
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史人 中島
Fumito Nakajima
史人 中島
圭穂 前田
Yoshio Maeda
圭穂 前田
好史 村本
Yoshifumi Muramoto
好史 村本
広明 三条
Hiroaki Sanjo
広明 三条
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Nippon Telegraph and Telephone Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a light receiving element capable of being manufactured at a low cost, which has a structure capable of reducing degradation of optical coupling efficiency and implementation tolerance even when joint area is small, and which has a fast response characteristic, without requiring alignment between a lens and PD when manufacturing the light receiving element to thereby reduce the number of steps and devices.SOLUTION: The light receiving element including a semiconductor substrate which has a photodiode and a lens formed near the photodiode on a first plane. The semiconductor substrate is processed so that a second plane opposite to the first plane reflects a beam of light incident the semiconductor substrate to the inside of the substrate.SELECTED DRAWING: Figure 2

Description

本発明は、光通信用の受光素子の構造に関する。   The present invention relates to a structure of a light receiving element for optical communication.

従来、光通信用受信モジュールにおいては受光素子として、光半導体素子であるフォトダイオード(PD)が使われているが、近年の通信容量の増大に対応してPDには高速な応答特性が求められるようになっている。   Conventionally, a photodiode (PD), which is an optical semiconductor element, is used as a light receiving element in a receiving module for optical communication. However, a high-speed response characteristic is required for the PD in response to an increase in communication capacity in recent years. It is like that.

PDの高速応答に対応するための手段の一つとして、PDの接合面積を縮小して接合容量を低減化することが一般的に行われている。   As one of means for responding to the high-speed response of PD, it is generally performed to reduce the junction capacitance by reducing the junction area of PD.

しかし、接合面積を縮小することはPDとして光を吸収できる面積(受光面積)が縮小することと同義のため、接合面積を縮小することは、信号光との光結合の効率の低下や、受信モジュールとして実装する場合の実装トレランスの低下につながってしまう。   However, reducing the junction area is synonymous with reducing the area (light-receiving area) that can absorb light as a PD, so reducing the junction area can reduce the efficiency of optical coupling with signal light, This leads to a decrease in mounting tolerance when mounted as a module.

この関係を緩和するために、図1の従来例に示すように、PDの裏面にレンズを集積して、裏面から入射する信号光を集光することで、接合面積が小さくても光結合効率の低下や実装トレランスの低下を低減できる構造を持った受光素子が実現されている。(下記非特許文献1参照)
このような従来例の受光素子(PD)の構造は、図1の断面図に示すように、PD基板1の表面側に、n型半導体層2、i型半導体で構成された光吸収層3、p型半導体層4、アノード電極5がこの順で積層されてフォトダイオードが構成されており、光吸収層3の両脇のn型半導体層2上には2つのカソード電極6が設けられている。
In order to alleviate this relationship, as shown in the conventional example of FIG. 1, the optical coupling efficiency can be achieved even if the junction area is small by integrating lenses on the back surface of the PD and condensing the signal light incident from the back surface. Thus, a light receiving element having a structure capable of reducing the deterioration of mounting resistance and mounting tolerance has been realized. (See Non-Patent Document 1 below)
Such a conventional light receiving element (PD) has a structure in which an n-type semiconductor layer 2 and a light absorbing layer 3 made of an i-type semiconductor are formed on the surface side of a PD substrate 1 as shown in the cross-sectional view of FIG. The p-type semiconductor layer 4 and the anode electrode 5 are laminated in this order to constitute a photodiode, and two cathode electrodes 6 are provided on the n-type semiconductor layer 2 on both sides of the light absorption layer 3. Yes.

PD基板1の裏面には、上記フォトダイオードに光軸を合わせて光学部品であるレンズ8がエッチングなどによって形成されており、入射光7は、PD基板1の裏面側から、このレンズ8を通って収束され、フォトダイオードに入射する。PD基板1の裏面には反射防止膜としてAR膜9が積層されて、レンズ8表面も覆っており、入射光のレンズ表面における反射を防いでいる。   On the back surface of the PD substrate 1, a lens 8 that is an optical component is formed by etching or the like with the optical axis aligned with the photodiode, and incident light 7 passes through the lens 8 from the back surface side of the PD substrate 1. Is converged and incident on the photodiode. An AR film 9 is laminated as an antireflection film on the back surface of the PD substrate 1 to cover the surface of the lens 8 and prevent reflection of incident light on the lens surface.

S.R.Cho et al, Enhanced Optical Coupling Performance in an InGaAs Photodiode Integrated With Wet-Etched Microlens,MARCH 2002 IEEE POTONICS TECHNOLOGY LETTERS Vol.14, No.3, p.378-380S.R.Cho et al, Enhanced Optical Coupling Performance in an InGaAs Photodiode Integrated With Wet-Etched Microlens, MARCH 2002 IEEE POTONICS TECHNOLOGY LETTERS Vol.14, No.3, p.378-380

しかしながら、このような従来例の受光素子の製造にあたっては、単に裏面プロセスにおいてレンズ形成という工程が必要となるだけでなく、半導体基板の表面に形成されたPDと裏面に加工されたレンズとの互いの位置合わせが必要となるという課題があった。具体的には、PDにあわせて半導体基板の表面に形成されたマーカなどの位置を読み取った上で、裏面のレンズを構成するパターンの位置を決定する必要がある。   However, in manufacturing such a conventional light receiving element, not only a lens forming process is required in the back surface process, but also the PD formed on the surface of the semiconductor substrate and the lens processed on the back surface are mutually connected. There was a problem that the positioning of was necessary. Specifically, it is necessary to read the position of a marker or the like formed on the front surface of the semiconductor substrate in accordance with the PD, and then determine the position of the pattern constituting the back lens.

このため従来例の受光素子の製造工程では、基板両面のアライメント(位置あわせ)が可能な高価なステッパや、裏面プロセスを行うためのウエハサポートシステムなど、通常のPDの製造工程では必要なかった装置を使用する必要があり、製造コストが増大してしまうという問題があった。   For this reason, in the conventional light receiving element manufacturing process, an expensive stepper capable of aligning both sides of the substrate, a wafer support system for performing the back surface process, and the like, which are not necessary in the normal PD manufacturing process There is a problem that the manufacturing cost increases.

本発明は上記従来の問題に鑑みなされたものであって、本発明の課題は、接合面積が小さくても光結合効率の低下や実装トレランスの低下を低減できる構造を持った受光素子を製造する際に、従来必要であったレンズとPDとのアライメントを不要とすることにより、工程数および使用装置が削減して、低コストに製造可能な高速な応答特性を有する受光素子を提供することにある。   The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to manufacture a light receiving element having a structure capable of reducing a decrease in optical coupling efficiency and a decrease in mounting tolerance even when the junction area is small. At the same time, by eliminating the need for the alignment between the lens and the PD, which has been conventionally required, the number of processes and the apparatus used are reduced, and a light-receiving element having high-speed response characteristics that can be manufactured at low cost is provided. is there.

上記従来の課題を解決するために、一実施形態に記載された発明は、フォトダイオードと、前記フォトダイオードに隣接して形成されたレンズとを第1の面に有する半導体基板を備えた受光素子であって、前記半導体基板は、前記第1の面に対向する第2の面が、当該半導体基板に入射した光を基板内に反射する加工がなされていることを特徴とする受光素子である。   In order to solve the above-described conventional problems, an invention described in an embodiment includes a light receiving element including a photodiode and a semiconductor substrate having a lens formed adjacent to the photodiode on a first surface. The semiconductor substrate is a light-receiving element in which a second surface facing the first surface is processed to reflect light incident on the semiconductor substrate into the substrate. .

従来の受光素子であるPDの断面図である。It is sectional drawing of PD which is the conventional light receiving element. 本発明の実施例1にかかる受光素子であるPDの断面図である。It is sectional drawing of PD which is a light receiving element concerning Example 1 of this invention. 本発明の実施例1にかかる受光素子であるPDの平面図である。It is a top view of PD which is the light receiving element concerning Example 1 of this invention.

以下、本発明の受光素子について、詳細に説明する。   Hereinafter, the light receiving element of the present invention will be described in detail.

本実施形態に記載された受光素子では、半導体基板の表面(第1の面)上にPDを形成し、PDに隣接する半導体基板の表面に半導体レンズを形成し、半導体基板の裏面(第2の面)は基板内に入射した光を基板内に反射する平坦な反射面として、半導体レンズの光軸に斜め方向から入射した光を裏面の反射面で反射させて、PDに収束させる構造としたことを特徴とする。   In the light receiving element described in the present embodiment, the PD is formed on the surface (first surface) of the semiconductor substrate, the semiconductor lens is formed on the surface of the semiconductor substrate adjacent to the PD, and the back surface (second surface) of the semiconductor substrate. Is a flat reflecting surface that reflects the light incident on the substrate into the substrate, and the light incident from the oblique direction on the optical axis of the semiconductor lens is reflected by the reflecting surface on the back surface to converge on the PD. It is characterized by that.

上記構成の受光素子によれば、光結合効率の低下なく高速応答を可能とするために、接合面積が小さくても光結合効率の低下や実装トレランスの低下を低減できる構造を持った受光素子を製造する際に、裏面プロセスにおいて従来必要であったアライメントが不要となり、工程数および使用装置が減るので、高速な応答特性を有する受光素子を低コストで作成可能となる。   According to the light receiving element having the above configuration, in order to enable a high-speed response without a decrease in optical coupling efficiency, a light receiving element having a structure capable of reducing a decrease in optical coupling efficiency and a reduction in mounting tolerance even when the junction area is small. At the time of manufacturing, alignment that has been conventionally required in the back surface process is not required, and the number of processes and the number of devices used are reduced. Therefore, a light receiving element having high-speed response characteristics can be produced at low cost.

(実施例1)
以下、図2および図3を用いて、本発明の受光素子の実施例1を説明する。
Example 1
Hereinafter, Example 1 of the light receiving element of the present invention will be described with reference to FIGS. 2 and 3.

図2は本発明の実施例1にかかる受光素子であるPDの断面図であり、図3はその平面図である。   FIG. 2 is a cross-sectional view of a PD, which is a light receiving element according to Example 1 of the present invention, and FIG. 3 is a plan view thereof.

図2、図3の実施例1では、InP(インジウム燐)系の半導体を用いたPDを例に挙げ、PD基板1については、半絶縁性のInP基板1とする。このPDは、次に示す方法で形成できる。   2 and 3, a PD using an InP (indium phosphorus) based semiconductor is taken as an example, and the PD substrate 1 is a semi-insulating InP substrate 1. This PD can be formed by the following method.

(表面プロセス:PD形成)
まず、高抵抗なInPからなるInP基板1の表面上に、有機金属気相成長(MOVPE)法などのエピタキシャル成長法を利用し、n型InP層2、ノンドープ(i型)InGaAs層(光吸収層)3、p型InGaAs層4を形成する。
(Surface process: PD formation)
First, an n-type InP layer 2, a non-doped (i-type) InGaAs layer (light absorption layer) is formed on the surface of an InP substrate 1 made of high-resistance InP by using an epitaxial growth method such as a metal organic chemical vapor deposition (MOVPE) method. 3) A p-type InGaAs layer 4 is formed.

次に、公知のフォトリソグラフィーおよびエッチング技術により、上述したp型InGaAs層4、ノンドープInGaAs層3,n型InP層2をメサ型に加工し、次いで、n型InP層2およびp型InGaAs層4に、各々オーミック接触する電極6、5を形成してフォトダイオード(PD)とする。   Next, the above-described p-type InGaAs layer 4, non-doped InGaAs layer 3, and n-type InP layer 2 are processed into a mesa shape by a known photolithography and etching technique, and then the n-type InP layer 2 and the p-type InGaAs layer 4 are processed. Then, electrodes 6 and 5 that are in ohmic contact with each other are formed to form a photodiode (PD).

(表面プロセス:レンズ形成)
続いて、InP基板1表面のPDに隣接する横の部分の、エピタキシャル層がすべてエッチングされた領域において、非特許文献1等で公知になっている技術を利用してInP基板1をレンズ形状に加工してレンズ8を形成する。
(Surface process: Lens formation)
Subsequently, the InP substrate 1 is formed into a lens shape by using a technique known in Non-Patent Document 1 or the like in a region where the epitaxial layer is completely etched in a lateral portion adjacent to the PD on the surface of the InP substrate 1. The lens 8 is formed by processing.

レンズ8の表面には、例えばSiO2/TiO2の積層構造からなる反射防止膜(AR膜9) を形成しておく。図3に示すように、InP基板1表面のAR膜9と電極5、6以外の部分(PDおよびレンズを形成した領域以外の部分)は、入射光7を閉じ込めるための反射膜12で覆ってもよい。 On the surface of the lens 8, an antireflection film (AR film 9) made of, for example, a laminated structure of SiO 2 / TiO 2 is formed. As shown in FIG. 3, the portion other than the AR film 9 and the electrodes 5 and 6 on the surface of the InP substrate 1 (the portion other than the region where the PD and the lens are formed) is covered with a reflective film 12 for confining incident light 7. Also good.

(裏面プロセス)
続いて、裏面プロセスに移るが、従来例と異なり本発明ではアライメントが不要であり、通常のプロセス機器を使用可能である。裏面プロセスではまず、PD基板1の裏面を研磨して所望の厚みになるように調整し、裏面の全面にSiO2/TiO2の積層構造からなる全反射膜11をスパッタ等により形成する。
(Back side process)
Subsequently, the process proceeds to the back surface process. Unlike the conventional example, the present invention does not require alignment, and ordinary process equipment can be used. In the back surface process, first, the back surface of the PD substrate 1 is polished and adjusted to have a desired thickness, and a total reflection film 11 having a laminated structure of SiO 2 / TiO 2 is formed on the entire back surface by sputtering or the like.

ここで、全反射膜11は、絶縁膜の上にメタルを形成したものでもよい。   Here, the total reflection film 11 may be formed by forming a metal on an insulating film.

その後、ダイシングによってチッピングされ、表面の半導体レンズ8とPDおよび裏面の全反射膜11が備わった受光部品が完成する。入射光7の閉じ込めをより効果的とするためには、チップ化することにより生じたInP基板1の側面にも全反射膜を設けてもよい。   Thereafter, chipping is performed by dicing, and a light receiving component including the semiconductor lens 8 on the front surface, the PD, and the total reflection film 11 on the back surface is completed. In order to make the confinement of the incident light 7 more effective, a total reflection film may be provided also on the side surface of the InP substrate 1 generated by forming a chip.

このチップに形成されたレンズ8に、図2に示すように、基板面あるいはレンズ8の光軸に対してPDと反対側に傾いた角度で入射光7を入射すると、基板内に入射した光は基板裏面の全反射膜11で全反射した後、PDの吸収層3近傍に収束され、高効率でフォトダイオードに光結合されて光電流が発生する。   As shown in FIG. 2, when the incident light 7 is incident on the lens 8 formed on the chip at an angle inclined to the side opposite to the PD with respect to the optical surface of the substrate surface or the lens 8, the light incident on the substrate After being totally reflected by the total reflection film 11 on the back surface of the substrate, it is converged in the vicinity of the PD absorption layer 3 and is optically coupled to the photodiode with high efficiency to generate a photocurrent.

例えば、InP基板の法線から60度傾けた角度で入射するコリメート光(直径20μm)を用いることを仮定すると、InP基板の厚さが75μmのとき、レンズの中心とPDの中心は約42μm離せばよい。このときレンズの曲率半径が50μmとすると、PDの受光部では直径9.6μmのスポットサイズに集光される。   For example, assuming that collimated light (diameter 20 μm) incident at an angle of 60 ° with respect to the normal line of the InP substrate is used, when the thickness of the InP substrate is 75 μm, the center of the lens and the center of the PD are about 42 μm apart. That's fine. At this time, if the radius of curvature of the lens is 50 μm, the light receiving part of the PD is focused to a spot size of 9.6 μm in diameter.

吸収層で吸収しきれなかった光は、PDの裏面や上面、側面に形成された反射膜11、12で再度反射され、再び吸収層3で吸収されるため、一度しか吸収層を通過しないPD構造よりも受光感度を高めることも可能である。   The light that cannot be absorbed by the absorption layer is reflected again by the reflection films 11 and 12 formed on the back surface, top surface, and side surfaces of the PD, and is absorbed again by the absorption layer 3, so that the PD that passes through the absorption layer only once. It is also possible to increase the light receiving sensitivity rather than the structure.

本実施例の受光素子の構造では、PDとレンズが形成される基板表面にのみパターンニングが施され、裏面は平坦な反射面のみであるため、裏面プロセスでアライメントは不要であり、通常のウエハプロセス装置のみで製造できることから、低コスト化に寄与する。   In the structure of the light receiving element of this embodiment, patterning is performed only on the surface of the substrate on which the PD and the lens are formed, and the back surface is only a flat reflecting surface. Since it can be manufactured with only process equipment, it contributes to cost reduction.

従来の半導体レンズがモノリシック集積されたPDでは、基板表面のPDに合わせて裏面のレンズ位置を決定するため、アライメントが必要となり製造工程が複雑になっていたが、本発明の受光部品であるPDにおいては、同一面にPDと半導体レンズを形成できるため、工程数および使用装置が減るため、製造工程を低コスト化できる。   In the conventional monolithically integrated PD with the semiconductor lens, the position of the lens on the back surface is determined in accordance with the PD on the front surface of the substrate. Therefore, alignment is necessary and the manufacturing process is complicated. Since the PD and the semiconductor lens can be formed on the same surface, the number of processes and the apparatus used are reduced, so that the manufacturing process can be reduced in cost.

以上記載したように、本発明によれば、裏面プロセスが簡素化され、アライメントが不要となり、工程数および使用装置が減るので、高速な応答特性を有する受光素子、受光部品を低コストで作成可能となる。   As described above, according to the present invention, the back surface process is simplified, alignment is not required, the number of processes and the number of devices used are reduced, and light receiving elements and light receiving parts having high-speed response characteristics can be produced at low cost. It becomes.

1 PD基板、半絶縁性のInP基板
2 n型半導体層、n型InP層
3 (i型半導体)光吸収層、InGaAs層
4 p型半導体層、p型InGaAs層
5 アノード電極
6 カソード電極
7 入射光
8 レンズ
9 AR膜
11、12 反射膜
1 PD substrate, semi-insulating InP substrate 2 n-type semiconductor layer, n-type InP layer 3 (i-type semiconductor) light absorption layer, InGaAs layer 4 p-type semiconductor layer, p-type InGaAs layer 5 anode electrode 6 cathode electrode 7 incident Light 8 Lens 9 AR film 11, 12 Reflective film

Claims (4)

フォトダイオードと、前記フォトダイオードに隣接して形成されたレンズとを第1の面に有する半導体基板を備えた受光素子であって、
前記半導体基板は、前記第1の面に対向する第2の面が、当該半導体基板に入射した光を基板内に反射する加工がなされていることを特徴とする受光素子。
A light receiving element including a semiconductor substrate having a photodiode and a lens formed adjacent to the photodiode on a first surface,
The light receiving element, wherein the second surface of the semiconductor substrate facing the first surface is processed to reflect light incident on the semiconductor substrate into the substrate.
半導体基板の前記第2の面に全反射膜が形成されていることを特徴とする、請求項1に記載の受光素子。   The light receiving element according to claim 1, wherein a total reflection film is formed on the second surface of the semiconductor substrate. 前記受光素子の側面が、当該半導体基板に入射した光を基板内に反射する加工がなされていることを特徴とする請求項1または2記載の受光素子。   The light receiving element according to claim 1, wherein a side surface of the light receiving element is processed to reflect light incident on the semiconductor substrate into the substrate. 前記第1の面の、前記フォトダイオードと前記レンズとが形成された部分以外が、当該半導体基板に入射した光を基板内に反射する加工がなされていることを特徴とする請求項2記載の受光素子。   3. The process of reflecting light incident on the semiconductor substrate into the substrate except for a portion of the first surface where the photodiode and the lens are formed. Light receiving element.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136446A (en) * 1991-11-11 1993-06-01 Nikko Kyodo Co Ltd Semiconductor photodetector
US5400419A (en) * 1992-12-03 1995-03-21 Siemens Aktiengesellschaft Bidirectional optical transmission and reception module
JPH08288542A (en) * 1995-04-14 1996-11-01 Ricoh Co Ltd Semiconductor optical element with lens, manufacture thereof and module for parallel light transmission
JP2001015774A (en) * 1999-06-28 2001-01-19 Minolta Co Ltd Optical sensor
JP2011003638A (en) * 2009-06-17 2011-01-06 Opnext Japan Inc Photodetector
US9793424B2 (en) * 2014-08-12 2017-10-17 Samsung Electronics Co., Ltd. Photoelectric conversion device and optical signal receiving unit having photodiode

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136446A (en) * 1991-11-11 1993-06-01 Nikko Kyodo Co Ltd Semiconductor photodetector
US5400419A (en) * 1992-12-03 1995-03-21 Siemens Aktiengesellschaft Bidirectional optical transmission and reception module
JPH08288542A (en) * 1995-04-14 1996-11-01 Ricoh Co Ltd Semiconductor optical element with lens, manufacture thereof and module for parallel light transmission
JP2001015774A (en) * 1999-06-28 2001-01-19 Minolta Co Ltd Optical sensor
JP2011003638A (en) * 2009-06-17 2011-01-06 Opnext Japan Inc Photodetector
US9793424B2 (en) * 2014-08-12 2017-10-17 Samsung Electronics Co., Ltd. Photoelectric conversion device and optical signal receiving unit having photodiode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2021074967A1 (en) * 2019-10-15 2021-04-22
WO2021074967A1 (en) * 2019-10-15 2021-04-22 日本電信電話株式会社 Light-receiving element
JP7280532B2 (en) 2019-10-15 2023-05-24 日本電信電話株式会社 Light receiving element

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