JP2018085358A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method by which a semiconductor device having a fine wiring layer to establish electrical conduction with a high density superior in transmission between chips can be manufactured with good yield at low cost.SOLUTION: A semiconductor device manufacturing method comprises the steps of: (I) forming an insulative material layer on a support body; (II) forming a concave portion in the surface of the insulative material layer; (III) modifying the surface of the insulative material layer including the concave portion in quality; (IV) forming a palladium-adsorbed layer on the quality-modified surface of the insulative material layer including the concave portion; (V) forming, by electroless nickel plating, a nickel layer on the surface of the insulative material layer including the concave portion with the palladium-adsorbed layer formed thereon; (VI) forming a copper layer on the nickel layer by electrolytic copper plating; and (VII) removing the copper layer, the nickel layer and the palladium-adsorbed layer from the surface of the insulative material layer excluding the concave portion, thereby forming a wiring layer including a copper layer formed on the concave portion of the insulative material layer.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device for efficiently manufacturing a semiconductor device that is highly demanded for miniaturization and high density at low cost.

  For the purpose of increasing the density and performance of semiconductor packages, a mounting form in which chips with different performances are mixedly mounted in one package has been proposed, and high-density interconnect technology between chips that is superior in cost has become important. (For example, refer to Patent Document 1).

  A package-on-package that connects by stacking different packages on a package by flip-chip mounting is widely used in smartphones and tablet terminals (see, for example, Non-Patent Document 1 and Non-Patent Document 2). As a form for mounting at higher density, a package technology (organic interposer) using an organic substrate having high-density wiring, a fan-out type package technology (FO-WLP) having a through mold via (TMV), silicon or A package technique using a glass interposer, a package technique using a through silicon via (TSV), a package technique using a chip embedded in a substrate for inter-chip transmission, and the like have been proposed.

  In particular, in the case of organic interposers and FO-WLP, when semiconductor chips are mounted in parallel, a fine wiring layer is required for conducting at high density (see, for example, Patent Document 2).

Special table 2012-529770 gazette US Patent Application Publication No. 2001/0221071

Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

  In order to form the fine wiring layer, steps of seed layer formation, resist formation, electroplating, resist removal, and seed layer removal are usually required by sputtering, and this method has a problem of process cost. Therefore, in order to produce a fine wiring layer at low cost, a lower cost process is strongly desired.

  The present invention has been made in view of the above problems, and is a semiconductor device capable of manufacturing a semiconductor device having a fine wiring layer for conducting at a high density excellent in transmission between chips at a good yield and at a low cost. An object is to provide a manufacturing method.

The method for manufacturing a semiconductor device of the present invention includes a step (I) of forming an insulating material layer on a support, a step (II) of forming a recess on the surface of the insulating material layer, and a recess of the insulating material layer. A surface modifying step (pretreatment step) (III), a palladium adsorbing layer forming step (IV) on the surface including the recessed portion of the modified insulating material layer, and the paradium adsorbing layer were formed. A step (V) of forming a nickel layer by electroless nickel plating on the surface of the insulating material layer including the recess, a step (VI) of forming a copper layer by electrolytic copper plating on the nickel layer, and the insulating material layer Removing the copper layer, the nickel layer, and the paradium adsorbing layer from the surface including the concave portion, thereby forming a wiring layer including the copper layer formed in the concave portion of the insulating material layer (the wiring layer is formed by surface polishing). Craft to expose Provided) and (VIII), the.
Moreover, this invention forms a wiring layer provided with the copper layer formed in the recessed part of the insulating material layer by removing the said copper layer, nickel layer, and palladium adsorption layer from the surface except the recessed part of the said insulating material layer. In the step (VII), the surface of the insulating material layer and the copper layer formed in the recess are flattened when removing the copper layer, nickel layer and palladium adsorption layer from the surface of the insulating material layer excluding the recess. This is a method for manufacturing the semiconductor device.
Further, in the step (I) of forming an insulating material layer on a support, the present invention is a step (II) in which the insulating material layer is formed of a photosensitive resin material and a recess is formed on the surface of the insulating material layer. Then, it is said manufacturing method of the semiconductor device which forms the recessed part by exposing and developing the said photosensitive resin material partially.
In addition, the present invention is the method for manufacturing the semiconductor device, wherein the recess formed on the surface of the insulating material layer has an opening width of at least 0.5 to 20 μm in the width direction.
Furthermore, this invention forms a wiring layer provided with the copper layer formed in the recessed part of the said insulating material layer by removing a copper layer, a nickel layer, and a palladium adsorption layer from the surface except the recessed part of the said insulating material layer. After performing the step (VII), the insulating material layer is formed on the support with respect to the support having the wiring layer including the insulating material layer and the copper layer. At least a step (VII) of forming a wiring layer including a copper layer formed in the recess of the insulating material layer by removing the copper layer, the nickel layer, and the palladium adsorption layer from the surface excluding the recess of the material layer. This is a method of manufacturing a semiconductor device, comprising the step (VIII) of repeating the wiring layer one or more times to make the wiring layer multilayer.

  According to the present invention, it is possible to provide a semiconductor device having a fine wiring layer for conducting at a high density excellent in transmission between chips with good yield and low cost.

(A) It is sectional drawing which shows typically the state which formed the insulating material layer on the support body. (B) It is sectional drawing which shows typically the state which formed the recessed part in the insulating material layer. (C) It is sectional drawing which shows typically the state which formed the palladium-tin colloidal particle adsorption layer by the pretreatment on the surface of the insulating material layer. (D) It is sectional drawing which shows typically the state electroless nickel-plated on the insulating material. (E) It is sectional drawing which shows typically the state electroplated with electroless nickel as a seed layer. (F) It is sectional drawing which shows typically the state which the wiring layer exposed by surface grinding | polishing.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant description is omitted. Further, the positional relationship such as up, down, left and right is based on the positional relationship shown in the drawings unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

  When terms such as “left”, “right”, “front”, “back”, “upper”, “lower”, “upper”, “lower” are used in the description and claims of the present specification, These are intended to be illustrative and do not necessarily mean they are permanently in this relative position. Further, the term “layer” includes a structure formed in a part in addition to a structure formed over the entire surface when observed as a plan view.

  A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. The method for manufacturing a semiconductor device according to the present invention is particularly suitable in a form in which miniaturization and increase in the number of pins are required. In particular, the method for manufacturing a semiconductor device according to the present invention is suitable for a package form that requires an interposer for mounting different types of chips.

  With reference to FIGS. 1A to 2F, a method for manufacturing a semiconductor device according to the present embodiment, particularly a method for manufacturing a wiring board, will be described.

  The method of manufacturing a semiconductor device according to the present embodiment includes a step (I) of forming an insulating material layer on a support, a step (II) of forming a recess on the surface of the insulating material layer, and a recess of the insulating material layer. A step (III) of reforming the surface including the step, a step (IV) of forming a palladium adsorption layer on the surface including the recess of the modified insulating material layer, and an insulating material layer on which the palladium adsorption layer is formed. A step (V) of forming a nickel layer by electroless nickel plating on a surface including a recess, a step (VI) of forming a copper layer by electrolytic copper plating on the nickel layer, and a recess of the insulating material layer are excluded. Forming a wiring layer including a copper layer formed in a recess of the insulating material layer by removing the copper layer, the nickel layer and the palladium adsorption layer from the surface (VII).

  Hereinafter, the step (I) of forming an insulating material layer on a support is referred to as “the step of forming an insulating material layer (I)” and the step of forming a recess on the surface of the insulating material layer (II) is referred to as “forming a recess. Step (II) ”and the step (III) of modifying the surface of the insulating material layer including the recesses into the step of modifying the surface (III) and the surface of the modified insulating material layer including the recesses. The step (IV) of forming the palladium adsorbing layer is the step of forming the palladium adsorbing layer (IV), and the surface of the insulating material layer having the palladium adsorbing layer formed on the surface including the recess is formed by electroless nickel plating. The step (V) of forming is a “step of forming a nickel layer (V)”, and the step of forming a copper layer by electrolytic copper plating on the nickel layer (VI) is a step of forming a copper layer (VI). From the surface of the insulating material layer excluding the recesses, the copper layer, nickel Forming a wiring layer comprising a copper layer formed in the recess of the insulating material layer by removing the layer and the palladium adsorbing layer (VII) is a step of forming a wiring layer (VII); After performing the step (VII) of forming a wiring layer including a copper layer formed in the concave portion of the insulating material layer by removing the copper layer, the nickel layer, and the palladium adsorption layer from the surface excluding the concave portion of From the step (I) of forming the insulating material layer on the support with respect to the support having the wiring layer including the insulating material layer and the copper layer, the copper layer, the nickel layer from the surface excluding the concave portion of the insulating material layer And the step (VII) of forming the wiring layer including the copper layer formed in the recess of the insulating material layer by removing the palladium adsorbing layer is repeated at least once to make the wiring layer a multilayer (V The II), the "step of multilayer wiring layer", sometimes referred to.

<Step (I) of forming an insulating material layer on a support>
First, the step (I) of forming the insulating material layer 2 on the support 1 of the semiconductor device is performed (FIG. 1A). The support 1 is not particularly limited, and is a silicon plate, a glass plate, a SUS plate, a glass cloth-containing substrate, a semiconductor element-containing sealing resin, or the like, and a substrate having high rigidity is preferable.

  The thickness of the support 1 is preferably in the range of 0.2 mm to 2.0 mm. When it is thinner than 0.2 mm, handling becomes difficult, while when it is thicker than 2.0 mm, the material cost tends to increase.

  The support 1 may be a wafer or a panel. Although the size is not particularly limited, a wafer having a diameter of 200 mm, a diameter of 300 mm, or a diameter of 450 mm, or a rectangular panel having a side of 300 to 700 mm is preferably used.

  In the step (I) of forming the insulating material layer 2 on the support 1, it is preferable that the insulating material layer is formed of a photosensitive resin material because a fine recess 3 can be easily formed by a photolithography process. Examples of the photosensitive insulating material used to form the insulating material layer 2 include liquid and film-like materials, but a film-like photosensitive insulating material is preferable from the viewpoint of film thickness flatness and cost. Moreover, it is preferable that the size of the filler (filler) contained in the photosensitive insulating material is an average particle diameter of 500 nm or less or does not contain a filler in that a fine trench structure can be formed.

  The laminating step of the film-like photosensitive insulating material is preferably a low temperature step, and is preferably a photosensitive insulating film made of a photosensitive resin material that can be laminated at 40 ° C to 120 ° C. A photosensitive insulating film with a laminating temperature lower than 40 ° C has a strong tack at normal temperature (about 25 ° C) and tends to deteriorate in handling property, and a photosensitive insulating film with a temperature higher than 120 ° C tends to be warped after lamination. There is.

The insulating material layer 2 preferably has a thermal expansion coefficient of 80 × 10 ⁻⁶ / K or less from the viewpoint of suppressing warpage, and 70 × 10 ⁻⁶ / K or less in terms of obtaining high reliability. More preferably. Moreover, it is preferable that it is 20 * 10 < ^-6 > / K or more at the point from which the stress relaxation property of an insulating material and a high-definition pattern are obtained.

  In order to make the recess 3 formed in the insulating material layer 2 in a subsequent process into a fine trench structure, the thickness of the insulating material layer 2 is preferably 10 μm or less, more preferably 5 μm or less, More preferably, it is 3 μm or less. Moreover, it is preferable that it is 1 micrometer or more from a viewpoint of electrical reliability.

<Step of forming recess (II)>
Next, the step (II) of forming the recesses 3 on the surface of the insulating material layer 2 is performed (FIG. 1B). In the present embodiment, the concave portion 3 refers to a portion that is recessed in the thickness direction of the insulating material layer 2 with respect to the surface of the insulating material layer 2, and the inner walls (side walls, bottom walls, and the like) of the recessed portion. Including. In the step (II) of forming a recess on the surface of the insulating material layer, the insulating material layer 2 is preferably formed of a photosensitive resin material, and the photosensitive resin material is partially exposed and developed to form a recess. The method for forming the recess 3 includes laser ablation, photolithography, imprint, and the like. From the viewpoint of miniaturization and cost, the photosensitive resin material is partially exposed and developed to form the recess. A photolithography process is preferred. Therefore, a film-like photosensitive resin material is most preferably used as the insulating material.

  As an exposure method for the photosensitive resin material, a normal projection exposure method, a contact exposure method, a direct drawing exposure method, or the like can be used. As a development method, an alkaline aqueous solution of sodium carbonate or TMAH (tetramethylammonium hydroxide) is used. It is preferable to use it.

  Further, in the step (II) of forming the recesses on the surface of the insulating material layer, the recesses formed on the surface of the insulating material layer have an opening width of at least 0.5 to 20 μm in the width direction. This is preferable in that a semiconductor device to be realized can be provided, and a semiconductor device having a fine wiring layer can be manufactured with good yield and cost.

  After forming the recess 3, the insulating material may be further heat-cured. The heating temperature is 100 ° C. to 200 ° C., and the heating time is 30 minutes to 3 hours.

<Step of modifying surface (III)>
Next, a step (III) of modifying the surface including the concave portion of the insulating material layer 2 is performed (not shown). In the present embodiment, the reforming means (III) a pretreatment that makes the surface of the insulating material layer 2 more easily adsorbed with palladium-tin colloid particles before the step of forming the palladium adsorption layer. Say. For this reason, the pretreatment in the present embodiment refers to a pretreatment for modifying the surface including the concave portion of the insulating material layer 2 performed before the step of forming the (III) palladium adsorption layer. Such pretreatment for reforming may be simply referred to as “pretreatment”.

As the reforming method, any of the following pretreatment by a wet method and pretreatment by a dry method can be used.
Examples of the pretreatment liquid (modification liquid) used in the pretreatment by the wet method include, for example, a silane cup containing polyether, glycol ether, amine, amide, ureido, triazine, melamine, imidazole, triazole, benzotriazole, etc. in the molecule. What contains at least 1 sort (s) selected from the group which consists of a ring agent is mentioned. The type of the solvent used in these pretreatment liquids is not particularly limited, and can be selected from generally used organic solvents and water, and may be used alone or in combination of two or more. Further, a surfactant may be included for the purpose of improving the wettability of the surface of the insulating material layer 2. Furthermore, as a modification method by a pretreatment with a wet method other than these, a roughening treatment with an acid or an alkali can be mentioned.
Examples of the pretreatment by the dry method include surface modification by plasma treatment, corona treatment, ultraviolet treatment and the like.
In addition, among the modification methods for the surface of the insulating material layer 2 as described above, the surface of the insulating material layer 2 by a pretreatment liquid (modification liquid) containing a silane coupling agent, which is a pretreatment by a wet method. The modification is preferably performed as a pretreatment.

  Examples of the pretreatment method using a wet method include a spray method, a dip method, a spin coating method, and a printing method in which the surface of the insulating material layer 2 is in contact with the pretreatment liquid. preferable.

  In order to increase the reactivity between the components of the pretreatment liquid and the insulating material layer 2, the surface of the insulating material layer 2 may be activated before the pretreatment for the modification. Examples of the activation method include ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, and plasma treatment.

  The pretreatment is preferably performed at 25 ° C to 80 ° C. In order to accelerate the reactivity, 40 ° C to 80 ° C is more preferable, and 60 ° C to 80 ° C is still more preferable.

  The pretreatment is preferably performed in 5 minutes to 30 minutes. In order to accelerate the reactivity, it is more preferably 10 minutes to 30 minutes, and further preferably 15 minutes to 30 minutes.

  After contacting the pretreatment liquid used in the pretreatment, it may be washed with water or an organic solvent in order to remove excess pretreatment liquid.

  After performing the pretreatment, heat treatment may be performed in order to increase the bonding strength between the insulating material layer 2 and the silane coupling agent that is a component of the pretreatment liquid. The heat treatment temperature is preferably 80 ° C. to 200 ° C. In order to accelerate the reactivity, 120 ° C to 200 ° C is more preferable, and heating at 120 ° C to 180 ° C is more preferable. The heat treatment time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and even more preferably 20 minutes to 60 minutes. Further, the pretreatment and the heat treatment may be repeated a plurality of times.

<Process for forming palladium adsorption layer (IV)>
Next, the step (IV) of forming the palladium adsorption layer 4 on the surface including the recessed portion 3 of the modified insulating material layer 2 is performed (FIG. 1C). In the present embodiment, the palladium adsorption layer 4 is formed by adsorbing palladium-tin colloidal particles on the surface of the insulating material layer 2 including the recesses 3 and then activating palladium to act as a catalyst. ) To palladium (0) (metallic palladium), which serves as a catalyst for the electroless plating reaction of electroless nickel plating performed in the subsequent steps. The formation method of this palladium adsorption layer 4 is demonstrated in detail below.

  After the pretreatment, first, palladium-tin colloidal particles are adhered to the surface of the insulating material layer 2. The palladium-tin colloidal particles may be a commercially available colloid solution, and a solution in which palladium-tin colloid is dispersed in water (palladium-tin colloid solution) may be used. The temperature of the palladium-tin colloidal solution immersed for attaching the palladium-tin colloidal particles is 25 ° C. to 80 ° C., and the immersion time for attaching is 1 to 60 minutes. After depositing the palladium-tin colloidal particles, it may be washed with water or an organic solvent in order to remove excess palladium-tin colloidal particles.

  After the palladium-tin colloidal particles are attached, activation is performed to make palladium act as a catalyst, and palladium (II) is reduced to palladium (0) (metallic palladium). The reagent for activating palladium may be a commercially available activator (activation treatment liquid). The temperature of the activator immersed for activating palladium is 25 ° C. to 80 ° C., and the time of immersing for activating is between 1 minute and 60 minutes. After the activation of palladium, it may be washed with water or an organic solvent in order to remove excess activator.

<Step of forming a nickel layer (V)>
Subsequently, a step (V) of forming a nickel layer 5 by electroless nickel plating is performed on the surface including the recess 3 of the insulating material layer 2 on which the palladium adsorption layer 4 is formed (FIG. 1D). This nickel layer 5 serves as a seed layer (feeding layer for electrolytic copper plating) of electrolytic copper plating performed to form the copper layer 6 in the subsequent process.

  As electroless nickel plating, electroless pure nickel plating (purity 99% by mass or more), electroless nickel-phosphorus plating (phosphorus content: 1% by mass to 13% by mass) or electroless nickel-boron plating (boron content) : 0.3 mass% to 1 mass%), etc., from the viewpoint of cost, electroless nickel-phosphorous plating is preferable.

  The electroless nickel plating solution may be a commercially available plating solution. For example, a medium phosphorus type (phosphorus content: 7 mass% to 9 mass%) electroless nickel plating solution (manufactured by Sanmeisha Co., Ltd., trade name "ICP Nicolon GM -SB-M "," ICP Nicolon GMSD "). The electroless nickel plating is performed in an electroless nickel plating solution at 60 ° C to 90 ° C.

  The thickness of the nickel layer 5 formed by electroless nickel plating is preferably 20 nm to 200 nm, more preferably 40 nm to 200 nm, and still more preferably 60 nm to 200 nm.

  After the electroless nickel plating, in order to remove excess plating solution, it may be washed with water or an organic solvent.

  After the electroless nickel plating, in order to increase the adhesion between the nickel layer 5 and the insulating material layer 2, heat curing (annealing: age hardening treatment by heating) may be performed. The thermosetting temperature is preferably heated at 80 ° C to 200 ° C. In order to accelerate the reactivity, 120 ° C to 200 ° C is more preferable, and heating at 120 ° C to 180 ° C is more preferable. The heat curing time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and even more preferably 20 minutes to 60 minutes.

<Step of forming a copper layer (VI)>
Next, a step (VI) of forming a copper layer 6 on the nickel layer 5 by electrolytic copper plating is performed (FIG. 2 (e)). More specifically, a nickel layer 5 formed by electroless nickel plating is used as a seed layer, and a copper layer 6 is formed thereon by electrolytic copper plating (FIG. 1 (d)). In the present embodiment, electrolytic copper plating is used as a method for forming the copper layer 6, but other than this, for example, electroless plating can be selected.

In the present embodiment, the copper layer 6 is filled in the recess 3 on the surface of the insulating material layer 2. In this way, the copper layer 6 is filled in the recess 3 on the surface of the insulating material layer 2, so that the copper layer 6, the nickel layer 5, and the Forming the surface of the insulating material layer 2 and the recess 3 without removing the surface of the insulating material layer 2 simply by removing the palladium adsorbing layer 4 (hereinafter sometimes referred to as “metal layers 6, 5, 4”). It is possible to planarize the copper layer 6 formed. Note that after removing the metal layers 6, 5, and 4, it is possible to planarize the surface of the insulating material layer 2 and the copper layer 6 formed in the recess 3 by further grinding the surface of the insulating material layer 2. is there. In order to fill the copper layer 6 in the recess 3 on the surface of the insulating material layer 2 by electrolytic copper plating, the amount of electrolytic copper plating deposited in the recess 3 (plating thickness) compared to the surface of the insulating material layer 2. It is preferable to use so-called filled plating.
The copper layer 6 may not be filled in the recess 3 on the surface of the insulating material layer 2, and may be formed along the inner wall (bottom wall and side wall) of the recess 3. In this case, not only the metal layers 6, 5, and 4 are removed from the surface of the insulating material layer 2 excluding the concave portion 3, but the surface of the insulating material layer 2 is further shaved to remove the inside of the concave portion 3 (the bottom of the concave portion 3 By exposing the copper layer 6 on the wall), the surface of the insulating material layer 2 and the copper layer 6 formed in the recess 3 can be planarized.

<Process for forming wiring layer (VII)>
Next, by removing the copper layer 6, the nickel layer 5, and the palladium adsorption layer 4 from the surface of the insulating material layer 2 excluding the concave portion 3, a wiring composed of the copper layer 6 formed in the concave portion 3 of the insulating material layer 2. Step (VII) for forming a layer is performed (FIG. 2F). That is, by removing the metal layers 6, 5, 4 on the top (surface) of the insulating material layer 2 (FIG. 2 (f)), the copper layer is formed only on the concave portion 3 on the surface including the concave portion 3 of the insulating material layer 2. 6 (more specifically, the copper layer 6, the nickel layer 5, and the palladium adsorption layer 4) are left, and the copper layer 6 and the like of the recess 3 form a wiring layer.

  When removing the copper layer 6, the nickel layer 5, and the palladium adsorption layer 4 from the surface of the insulating material layer 2 excluding the recess 3, the surface of the insulating material layer 2 and the copper layer 6 formed in the recess 3 are removed. It is preferable to planarize. Further, when removing the metal layers 6, 5, 4 on the upper side of the insulating material layer 2, a part in the thickness direction may be removed from the upper side (surface) side of the insulating material layer 2.

  Examples of a method for removing the metal layers 6, 5, 4 and the insulating material layer 2 above the insulating material layer 2 include a back grinding method, a fly-cut method, and chemical mechanical polishing (CMP). A plurality of removal methods may be used in combination. In the fly-cut method, for example, a grinding device using a diamond tool is used. As a specific example, an automatic surface planer (manufactured by DISCO Corporation, trade name “DAS8930”) compatible with a 300 mm wafer can be used. The removal of the metal layers 6, 5, and 4 by the fly-cut method polishes the entire surface uniformly from the upper side (surface side) of the insulating material layer 2, so that the polished surface becomes flat, and therefore, a flattening process is performed. It can be said that there is.

<Process of multilayer wiring layer (VIII)>
By removing the copper layer 6, the nickel layer 5 and the palladium adsorption layer 4 from the surface of the insulating material layer 2 excluding the concave portion 3, a wiring layer made of the copper layer 6 formed in the concave portion 3 of the insulating material layer 2 is formed. After performing the step (VII), the step (I) of forming the insulating material layer 2 on the support 1 with respect to the support 1 having the wiring layer composed of the insulating material layer 2 and the copper layer 6 is further performed. By removing the copper layer 6, the nickel layer 5 and the palladium adsorption layer 4 from the surface of the insulating material layer 2 excluding the concave portion 3, a wiring layer made of the copper layer 6 formed in the concave portion 3 of the insulating material layer 2 is formed. The process (VII) is repeated at least once until the process (VII) to be formed, and the process (VIII) for forming the wiring layer in multiple layers is performed (not shown).

  The preferred embodiments of the semiconductor device manufacturing member and the semiconductor device manufacturing method using the same have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and does not depart from the gist thereof. You may change suitably in the range.

DESCRIPTION OF SYMBOLS 1 ... Support body, 2 ... Insulating material layer, 3 ... Recessed part, 4 ... Palladium adsorption layer or metal layer, 5 ... Nickel layer or metal layer, 6 ... Copper layer or metal layer

Claims (5)

Forming an insulating material layer on the support (I);
Forming a recess in the surface of the insulating material layer (II);
Modifying the surface of the insulating material layer including the recesses (III);
A step (IV) of forming a palladium adsorption layer on the surface of the modified insulating material layer including the recesses;
A step (V) of forming a nickel layer by electroless nickel plating on the surface including the concave portion of the insulating material layer on which the palladium adsorption layer is formed;
Forming a copper layer on the nickel layer by electrolytic copper plating (VI);
Forming a wiring layer comprising a copper layer formed in the recess of the insulating material layer by removing the copper layer, the nickel layer and the palladium adsorbing layer from the surface of the insulating material layer excluding the recess (VII); ,
A method for manufacturing a semiconductor device comprising:   In the step (VII) of forming a wiring layer including a copper layer formed in the recess of the insulating material layer by removing the copper layer, the nickel layer, and the palladium adsorption layer from the surface excluding the recess of the insulating material layer. The surface of the insulating material layer and the copper layer formed in the recess are flattened when the copper layer, nickel layer and palladium adsorption layer are removed from the surface of the insulating material layer excluding the recess. The manufacturing method of the semiconductor device as described in any one of.   In the step (I) of forming an insulating material layer on a support, the insulating material layer is formed of a photosensitive resin material, and in the step (II) of forming a recess on the surface of the insulating material layer, the photosensitive resin material is formed. The method for manufacturing a semiconductor device according to claim 1, wherein a recess is formed by partially exposing and developing the substrate.   In the step (II) of forming a recess on the surface of the insulating material layer, the recess formed on the surface of the insulating material layer has an opening width of at least 0.5 to 20 μm in the width direction. The manufacturing method of the semiconductor device as described in any one.   Removing a copper layer, a nickel layer, and a palladium adsorption layer from the surface of the insulating material layer excluding the recesses, thereby forming a wiring layer having a copper layer formed in the recesses of the insulating material layer (VII); After the step, the step of forming the insulating material layer on the support (I) is further removed from the support having the wiring layer including the insulating material layer and the copper layer. From the surface, by removing the copper layer, the nickel layer and the palladium adsorbing layer, the step (VII) of forming the wiring layer including the copper layer formed in the concave portion of the insulating material layer is repeated at least once. The manufacturing method of the semiconductor device as described in any one of Claim 1 to 4 which has the process (VIII) of making a layer into a multilayer.

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