JP2018085357A - Storage device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a storage device having a large storage capacity.SOLUTION: A storage device provided with a semiconductor device is constituted on a flexible substrate. The semiconductor device has memory cells and can write data to the memory cells and read data from the memory cells by using a driving circuit and the like. As the method for providing a semiconductor device on a flexible substrate, for example, a method in which a semiconductor device is formed on a substrate having a peeling layer and the semiconductor device is peeled off and transposed on a flexible substrate is given. By providing the semiconductor device on the flexible substrate, the storage device can have, for example, a structure in which the substrate is bent and folded in a bellows shape, a structure in which the substrate is wound in a roll shape, or the like.SELECTED DRAWING: Figure 4

Description

  One embodiment of the present invention relates to a memory device and an electronic device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a processor, a converter, and an encoder. As an example, a decoder, a tuner, an electronic device, a driving method thereof, a manufacturing method thereof, a inspection method thereof, or a system thereof can be given.

  In recent years, electronic components such as a central processing unit (CPU), a storage device, and a sensor have been used in various electronic devices such as personal computers, smartphones, and digital cameras. The electronic components are miniaturized and have low power consumption. Improvements are progressing in various ways.

  In particular, in recent years, the amount of data handled in the electronic devices described above has increased, and a storage device having a large storage capacity has been demanded. Patent Documents 1 and 2 disclose a semiconductor device that can write and read multi-value data. In order to realize a storage device having a large storage capacity, a technique for miniaturizing a circuit included in the storage device is required.

JP 2012-256400 A JP 2014-199707 A

  Multi-level memory cells indicate that one memory cell handles data of three or more values. For example, when one memory cell handles quaternary data, it can handle twice as much data as a binary memory cell, and the effective area of the memory cell can be halved.

  However, in order to multi-value a memory cell, it is necessary to set the number of data (potential that can be held) stored in the memory cell to three or more. That is, unlike the binary value, it is necessary to handle a potential other than the high level potential and the low level potential, and as the types of potentials to be handled increase, the range of the potential of data to be written or read becomes narrower. As the potential range of data becomes narrower, the content of stored data may change even when the potential held in the memory cell slightly fluctuates due to a small defect. Therefore, when a memory cell is multi-valued, it is important that the memory cell has a configuration in which a held potential does not fluctuate even if a small defect occurs.

  In addition, when a memory cell is miniaturized, the breakdown voltage of elements included in the memory cell, such as transistors and capacitors, tends to be low. Therefore, the memory cell is configured so that these elements do not fail due to electrostatic breakdown or the like. There is a need to.

  An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a memory device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device using a memory device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide a memory device with a large data capacity. Another object of one embodiment of the present invention is to provide a highly reliable memory device.

(1)
One embodiment of the present invention includes a first substrate, a first semiconductor device, a second semiconductor device, a first terminal, and a first region, and the first semiconductor device is provided over the first substrate. The first terminal is provided on the first substrate, the first region has a region where the first semiconductor device overlaps the second semiconductor device, and the first terminal is electrically connected to the first semiconductor device. The first substrate has a structure in which the first substrate is bent and folded.

(2)
Alternatively, according to one embodiment of the present invention, in the above (1), the semiconductor device includes a wiring and a bonding layer, the second semiconductor device is provided over the first substrate, and the wiring is provided over the first substrate. Is provided in a bent region of the bent structure, the second semiconductor device is electrically connected to the first semiconductor device through a wiring, and the bonding layer is formed between the first semiconductor device and the second semiconductor device. A memory device is provided between the semiconductor device and the semiconductor device.

(3)
Alternatively, according to one embodiment of the present invention, in the above (1), the first substrate includes a second substrate, a second terminal, a bonding layer, a first wiring, and a second wiring. The first wiring has a function of electrically connecting the first semiconductor device and the second terminal, and the second semiconductor device is provided on the second substrate. The second terminal is provided on the second substrate, the second substrate has a region overlapping with the first substrate through the bonding layer, and the second substrate is bent along the first substrate. The second wiring is provided in a bent region of the second substrate, and the second wiring has a function of electrically connecting the second semiconductor device and the second terminal. This is a storage device.

(4)
Alternatively, according to one embodiment of the present invention, in the method (3), the semiconductor device includes a second region and a third region, the second region includes a region including a first terminal, and the third region The storage device includes an area including two terminals, and each of the second area and the third area is a different area.

(5)
Alternatively, according to one embodiment of the present invention, in (4), the first region has a region overlapping with the second region, and the first region has a region overlapping with the third region. It is a storage device.

(6)
Alternatively, according to one embodiment of the present invention, a first substrate, a second substrate, a first semiconductor device, a second semiconductor device, a first terminal, a second terminal, a bonding layer, and first to third A first semiconductor device is provided on the first substrate, a first terminal is provided on the first substrate, and the first semiconductor device is electrically connected to the first terminal; The second semiconductor device is provided on the second substrate, the second terminal is provided on the second substrate, the second semiconductor device is electrically connected to the second terminal, and the first region is the first region A region including a terminal; a second region including a region including a second terminal; and a third region including a region where the first semiconductor device overlaps with the second semiconductor device through a bonding layer. Each of the first to third areas is a different area.

(7)
Alternatively, according to one embodiment of the present invention, in any one of the above (1) to (6), at least one of the first semiconductor device and the second semiconductor device includes a memory cell, and the memory cell includes the first transistor. And a second transistor and a capacitor, wherein the first terminal of the first transistor is electrically connected to the first terminal of the capacitor, and the gate of the second transistor is the first terminal of the capacitor. The storage device is electrically connected to the storage device.

(8)
Another embodiment of the present invention is the memory device in (7) in which the first transistor includes a metal oxide in a channel formation region.

(9)
Alternatively, according to one embodiment of the present invention, in any one of the above (1) to (8), at least one of the first semiconductor device and the second semiconductor device can perform multi-value data write operation and / or read operation. A storage device having a function of performing an operation.

(10)
Alternatively, one embodiment of the present invention includes a substrate, a semiconductor device, a terminal, and a bonding layer. The semiconductor device is provided over the substrate, and the terminal is over one end portion of the substrate. The memory device is characterized in that the terminal portion is electrically connected to the semiconductor device, the bonding layer is provided below the substrate, and the substrate is wound with the other end portion of the substrate inside. Device.

(11)
Another embodiment of the present invention is the storage device according to (10), including a core, and the core is provided as a shaft of the wound substrate.

(12)
Alternatively, according to one embodiment of the present invention, in the above (10) or (11), the semiconductor device includes a memory cell, and the memory cell includes a first transistor, a second transistor, and a capacitor. The first terminal of the first transistor is electrically connected to the first terminal of the capacitor, and the gate of the second transistor is electrically connected to the first terminal of the capacitor. It is a storage device.

(13)
Another embodiment of the present invention is the memory device in (12) in which the first transistor includes a metal oxide in a channel formation region.

(14)
Alternatively, according to one embodiment of the present invention, in any one of the above (10) to (13), the semiconductor device has a function of performing a multi-value data write operation or a read operation. Device.

(15) Another embodiment of the present invention is a circuit board on which the memory device according to any one of (1) to (14) is mounted.

(16) Alternatively, in the above (15), one embodiment of the present invention includes a driver circuit, and the driver circuit has a function of writing data to the memory device and a function of reading data from the memory device. A circuit board characterized by the above.

(17)
Another embodiment of the present invention is an electronic device including the circuit board according to (15) or (16) and a housing.

  According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a memory device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device using a memory device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a large data capacity can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable memory device can be provided.

The perspective view which shows an example of a memory | storage device. FIG. 14 is a cross-sectional view of an example of a memory device. The perspective view which shows an example of a memory | storage device. FIG. 14 is a cross-sectional view of an example of a memory device. The perspective view which shows an example of a memory | storage device. FIG. 14 is a cross-sectional view of an example of a memory device. The perspective view which shows an example of a memory | storage device. The perspective view which shows an example of a memory | storage device. The perspective view which shows an example of a memory | storage device. FIG. 14 is a cross-sectional view of an example of a memory device. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device. The perspective view which shows the example of mounting of a memory | storage device. The perspective view which shows the example of mounting of a memory | storage device. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device. FIG. 10 is a block diagram illustrating a configuration example of a semiconductor device. The perspective view which shows the example of mounting of a memory | storage device. The circuit diagram which shows the structural example of a memory cell. The circuit diagram which shows the structural example of a memory cell. The circuit diagram which shows the structural example of a memory cell. The schematic diagram of the threshold voltage distribution of a memory cell. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a memory device. The figure explaining the range of atomic ratio of a metal oxide. 4A and 4B are a top view and cross-sectional views illustrating a structural example of a transistor. 4A and 4B are a top view and cross-sectional views illustrating a structural example of a transistor. The perspective view which shows an example of an electronic device.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, in the case where a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide is abbreviated to a metal oxide semiconductor (metal oxide semiconductor). It can be called OS. In the case of describing as an OS FET, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  In this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

(Embodiment 1)
Embodiments of the present invention will be described with reference to FIGS.

<Configuration example 1>
FIG. 1A illustrates the device 100a, the device 100b, and the device 100c. In the device 100a, a semiconductor device 102a including a memory cell is provided over the substrate 101a. Similarly, in the device 100b, the semiconductor device 102b including a memory cell is provided over the substrate 101b, and the device 100c is a semiconductor including a memory cell. A device 102c is provided on the substrate 101c.

  The device 100a includes a terminal 104a and a wiring 105a that electrically connects the terminal 104a and the semiconductor device 102a. Similarly, the device 100b includes a terminal 104b and a wiring 105b that electrically connects the terminal 104b and the semiconductor device 102b. The device 100c includes a terminal 104c and a wiring 105c that electrically connects the terminal 104c and the semiconductor device 102c.

  Each of the substrates 101a, 101b, and 101c has flexibility. As the substrates 101a, 101b, 101c, for example, polyethylene terephthalate resin (PET), polyethylene naphthalate resin (PEN), polyethersulfone resin (PES), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, A polycarbonate resin, a polyamide resin, a polycycloolefin resin, a polystyrene resin, a polyamideimide resin, a polypropylene resin, a polyester resin, a polyhalogenated vinyl resin, an aramid resin, an epoxy resin, or the like can be used. These materials may be mixed or laminated. The same material may be used for the substrate 101a, the substrate 101b, and the substrate 101c, or different materials may be used.

  Here, as shown by the arrows in FIG. 1A, the terminal 104a, the terminal 104b, and the terminal 104c are overlapped in the same direction so that the device 100b is superimposed on the device 100c, and the device 100b is connected to the device 100b. Consider a case where 100a is superimposed. At this time, the sizes of the substrate 101a, the substrate 101b, and the substrate 101c of the device 100a, the device 100b, and the device 100c are different. Specifically, the substrate 101a is smaller than the substrates 101b and 101c, and the substrate 101c is larger than the substrates 101a and 101b. This is because the devices 100a, 100b, and 100c are stacked so that terminals of the devices 100a, 100b, and 100c do not overlap each other as in the storage device 100 illustrated in FIG. In the case where the terminal 104a, the terminal 104b, and the terminal 104c overlap with each other, the terminal 104b or the terminal 104c is electrically connected to a wiring such as an FPC (Flexible Print Circuit) for connecting to an external circuit. Since it becomes difficult, the memory device 100 preferably has a structure in which the terminal 104a, the terminal 104b, and the terminal 104c do not overlap with each other. In addition, the storage device 100 can be electrically connected to the terminal 104a, the terminal 104b, and the terminal 104c by configuring the terminal 104a, the terminal 104b, and the terminal 104c in the same direction. The wiring to be connected can be provided in the same direction. Accordingly, a space for providing a wiring electrically connected to the terminal 104a, the terminal 104b, and the terminal 104c can be reduced.

  As illustrated in FIG. 1B, the storage device 100 with a large storage capacity can be formed by stacking the substrate 101a, the substrate 101b, and the substrate 101c provided with the devices 100a, 100b, and 100c.

  Further, the size of the substrate and the orientation of the terminals of the memory device 100 are not limited to the structure in FIG. For example, as shown in FIG. 1C, three devices 100a may be used so that the devices 100a are overlapped so that the terminals 104a are directed in the same direction and the terminals 104a are exposed. Good. Note that in this configuration example, in FIG. 1B, the sizes of the devices 100a, 100b, and 100c are aligned, and the storage devices are shifted so that the terminals 104a, 104b, and 104c are exposed. This corresponds to a superposed configuration. Further, for example, as shown in FIG. 1D, the apparatus 100a may be overlapped by using three apparatuses 100a so that the terminals 104a are directed in different directions and the terminals 104a are exposed. Good.

  2A and 2B are cross-sectional views taken along one-dot chain line A1 in the memory device 100 illustrated in FIG.

  A memory device 100A illustrated in FIG. 2A includes a bonding layer 106b between the device 100c and the device 100b, and a bonding layer 106a between the device 100b and the device 100a.

  The bonding layer 106a has a function of bonding the devices 100a and 100b, and the bonding layer 106b has a function of bonding the devices 100b and 100c. As the bonding layer 106a or the bonding layer 106b, a photocurable adhesive, a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive can be used. For example, an epoxy resin, an acrylic resin, an imide resin, or the like can be used. Further, a sheet-like adhesive can be used as the bonding layer 106a or the bonding layer 106b. The bonding layer 106a and the bonding layer 106b may be made of the same material or different materials.

  A storage device 100B illustrated in FIG. 2B has a structure in which a substrate 107a and a substrate 107b are added to the storage device 100A in order to increase strength.

  The bonding layer 106a includes a substrate 107a, and the bonding layer 106b includes a substrate 107b. In FIG. 2B, the bonding layer 106a between the substrate 107a and the device 100a is referred to as a bonding layer 106a [1], and the bonding layer 106a between the substrate 107a and the device 100b is referred to as the bonding layer 106a. [2], the bonding layer 106b between the substrate 107b and the device 100b is described as a bonding layer 106b [1], and the bonding layer 106b between the substrate 107b and the device 100c is bonded to the bonding layer 106b [2]. ] Is described.

  Note that the bonding layer 106a [1] and the bonding layer 106a [2] may be formed using different materials instead of the same material. In addition, the bonding layer 106b [1] and the bonding layer 106b [2] may be formed using different materials instead of the same material.

  As the substrate 107a and the substrate 107b, for example, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a plastic substrate, or the like can be used. As other materials, for example, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, or the like can be used. By applying the above material having high thermal conductivity to the substrate 107a and the substrate 107b, the heat dissipation of the device 100a, the device 100b, and the device 100c can be improved. Note that a thermosetting adhesive is used for at least one of the bonding layer 106a [1], the bonding layer 106a [2], the bonding layer 106b [1], and the bonding layer 106b [2], and the substrate 107a and / or In the case where a plastic substrate is used as the substrate 107b, the plastic substrate preferably has heat resistance that can withstand a processing temperature for curing the thermosetting adhesive. Further, the same material may be used for the substrate 107a and the substrate 107b, or different materials may be used.

  In addition, as the substrate 107a and the substrate 107b, a flexible substrate can be used. For example, the same material as any one of the substrate 101a, the substrate 101b, and the substrate 101c can be used.

  Note that the above-described bonding layer 106a (bonding layer 106a [1], bonding layer 106a [2]), bonding layer 106b (bonding layer 106b [1], bonding layer 106b [2]), substrate 107a, and substrate 107b are used. The configuration thus applied can be applied not only to the storage device 100 of FIG. 1B but also to the storage device 100 of FIGS. 1C and 1D.

  Note that one embodiment of the present invention is not limited to this structure example. For example, the storage device 100 illustrated in FIGS. 1B, 1C, and 1D includes a three-layer storage device, but a two-layer storage device or a four-layer or more storage device configuration. It is good.

<Configuration example 2>
Next, FIG. 3 shows a storage device different from the configuration of the storage device 100 shown in FIG.

  A device 110a illustrated in FIG. 3A includes a semiconductor device 102a including a memory cell, a semiconductor device 102b, and a semiconductor device 102c. Each semiconductor device is provided over a substrate 101. The device 110a includes a terminal 104, a wiring 103a that electrically connects the semiconductor device 102a and the semiconductor device 102b, and a wiring 103b that electrically connects the semiconductor device 102b and the semiconductor device 102c.

  The substrate 101 has flexibility. As the substrate 101, the same material as that of the substrate 101a, the substrate 101b, or the substrate 101c described in the above structural example 1 can be used.

  Here, a configuration is considered in which the device 110a illustrated in FIG. 3A is bent in a bellows shape as indicated by an arrow illustrated in FIG. Ultimately, the storage device 110 has a bent configuration as the storage device 110 illustrated in FIG. Note that in this structure example, the memory device 110 illustrated in FIG. 3C is bent and folded so that the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c overlap with each other.

  Note that in the device 110a illustrated in FIG. 3B, components other than the substrate 101 and reference numerals of the components are not illustrated.

  The storage device 110 in FIG. 3C preferably has a structure in which the wiring 103a and / or the wiring 103b is provided in a bent region of the substrate 101. Since the wiring 103a and the wiring 103b do not include circuit elements such as transistors and capacitors, there is no problem in the circuit elements due to stress generated by bending.

  The wiring 103a and the wiring 103b are each preferably a conductive material having spreadability. As the wiring 103a and the wiring 103b, for example, gold, silver, copper, aluminum, iron, zinc, or the like can be used. Moreover, as another material, the alloy containing said material can be used. In the case where the wirings 103a and 103b are formed as thin films, a conductive material other than the above may be used in some cases.

  Next, the shapes of the wiring 103a and the wiring 103b will be described. FIG. 3E1 is a schematic diagram in which the region 103r illustrated in FIG. Note that a region 103r in FIG. 3A illustrates part of the wiring 103a; however, the remaining wiring 103a or the wiring 103b can have a structure similar to that of the wiring 103a in the region 103r.

  In the region 103r in FIG. 3E1, the wiring 103a includes a plurality of elongated rectangular conductors. Further, the structure of the wiring 103a and the wiring 103b in the memory device 110 is not limited to the structure illustrated in FIG. 3E1, and for example, a mesh configuration as illustrated in the wiring 103a in the region 103r illustrated in FIG. It may be. When the wiring 103a and the wiring 103b have the mesh shape illustrated in FIG. 3E2, peeling of the wiring 103a and the wiring 103b due to bending of the memory device 110 can be suppressed.

  As shown in FIG. 3C, the memory device 110 having a large memory capacity can be formed by bending the substrate 101 provided with the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c in a bellows shape and overlapping them. .

  The memory device 110 illustrated in FIG. 3C is stacked in a bellows shape so that the semiconductor device 102a and the terminal 104 face outward, but as illustrated in FIG. 3D, the semiconductor device 102a and A configuration may be adopted in which the terminals 104 are bent in an accordion shape so that the terminals 104 face inward and do not overlap with the bent substrate 101.

  4A and 4B are cross-sectional views taken along one-dot chain line A2 in the memory device 110 illustrated in FIG.

  The storage device 110A illustrated in FIG. 4A has the back surface of the substrate 101 (the surface on which the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c are provided) as a front surface by the substrate 101 being bent and folded. ) Facing each other, and a region facing the surface of the substrate 101. In addition, the memory device 110A includes a bonding layer 106a in a region where the back surface of the substrate 101 faces and a bonding layer 106b in a region where the surface of the substrate 101 faces.

  The bonding layer 106a has a function of bonding the back surfaces of the substrate 101 facing each other, and the bonding layer 106b has a function of bonding the surfaces of the substrate 101 facing each other. As the material of the bonding layer 106a and the bonding layer 106b, the same material as that of the bonding layer 106a and the bonding layer 106b described in Structural Example 1 can be used.

  A storage device 110B illustrated in FIG. 4B has a structure in which a substrate 107a and a substrate 107b are added to the storage device 110A in order to increase strength.

  The bonding layer 106a includes a substrate 107a, and the bonding layer 106b includes a substrate 107b.

  As the materials of the substrate 107a and the substrate 107b, the same materials as those of the substrate 107a and the substrate 107b described in Structure Example 1 can be used, respectively.

  Note that one embodiment of the present invention is not limited to this structure example. For example, the storage device 110 illustrated in FIG. 3C is configured as a three-layer storage device by bending two portions of the substrate 101, but a two-layer storage device by bending one portion of the substrate 101, or A configuration of a storage device having four or more layers may be formed by bending three or more portions of the substrate 101.

<Configuration example 3>
The configuration of the storage device is not limited to the configuration in which the storage device is bent in a bellows shape like the storage device 110. A configuration example of a storage device different from the storage device 110 is shown in FIG.

  The storage device 111 includes a device 111a, a device 111b, and a substrate 107. In the device 111a, the semiconductor device 102a including a memory cell is provided over the substrate 101a. Similarly, in the device 111b, the semiconductor device 102b including a memory cell is provided over the substrate 101b.

  The device 111a includes a terminal 104a and a wiring 103a on each of the sides facing each other. Similarly, the device 111b includes a terminal 104b and a wiring 103b on each of the sides facing each other.

  The wiring 103a functions as a wiring that electrically connects the terminal 104a and the semiconductor device 102a, and the wiring 103b functions as a wiring that electrically connects the terminal 104b and the semiconductor device 102b.

  Each of the substrates 101a and 101b has flexibility. As the substrates 101a and 101b, the same material as that of the substrate 101a, the substrate 101b, or the substrate 101c described in the above structure example 1 can be used.

  Here, as shown by the arrows in FIG. 5A, the devices 111a, 111b, and the substrate 107 are overlapped, and as shown in FIG. 5B, the devices 111a, 111b, Consider a configuration in which the substrate is bonded along the front surface and the back surface of the substrate 107. The final configuration is as shown in FIGS. 5C1 and 5C2.

  5C1 is a perspective view illustrating the surface side of the storage device 111, and FIG. 5C2 is a perspective view illustrating the surface side of the storage device 111. FIG. In the storage device 111, the semiconductor device 102 a and the semiconductor device 102 b are disposed on the front surface side of the storage device 111, and the terminal 104 a and the terminal 104 b are disposed on the back surface side of the storage device 111. In this portion, the wiring 103a and the wiring 103b are positioned.

  Note that in the memory device 111 illustrated in FIG. 5B, components other than the devices 111 a, 111 b, and the substrate 107 and reference numerals of the components are omitted.

  In addition, since the memory device 111 has a structure in which the semiconductor device 102a and the semiconductor device 102b are overlapped with each other, the semiconductor device 102b and its reference are not described in FIG. Similarly, since the memory device 111 has a structure in which the wiring 103a and the wiring 103b are overlapped with each other, the wiring 103b and its reference are not described in FIGS. 5C1 and 5C2.

  As shown in FIGS. 5C1 and 5C2, the storage device 111 having a large storage capacity can be configured by overlapping the devices 111 a and 111 b and bonding them along the substrate 107.

  6A and 6B are cross-sectional views taken along one-dot chain line A3 in the memory device 111 illustrated in FIGS. 5C1 and 5C2.

  A memory device 111A illustrated in FIG. 6A includes a bonding layer 106a between a substrate 101a and a substrate 101b. In addition, the memory device 111B includes a bonding layer 106b between the substrate 101 and the substrate 107.

  The bonding layer 106a has a function of bonding the substrate 101a and the substrate 101b, and the bonding layer 106b has a function of bonding the substrate 101 and the substrate 107. As the material of the bonding layer 106a and the bonding layer 106b, the same material as that of the bonding layer 106a and the bonding layer 106b described in Structural Example 1 can be used.

  As the material of the substrate 107a, the same material as that of the substrate 107a described in Structural Example 1 can be used.

  Note that one embodiment of the present invention may have a structure in which the memory device does not include the substrate 107. A storage device 111B illustrated in FIG. 6B has a structure in which the substrate 107 is removed from the storage device 111A.

  The memory device 111B has two regions where the back surface of the substrate 101b (the surface on which the semiconductor device 102b is provided is the front surface) faces each other when the substrate 101b is bent and folded. The bonding layer 106b [1] is provided in one region, and the bonding layer 106b [2] is provided in the other region.

  The bonding layer 106b [1] and the bonding layer 106b [2] have a function of bonding the back surfaces of the substrates 101b to each other. As the material of the bonding layer 106b [1] and the bonding layer 106b [2], the same material as that of the bonding layer 106b described in Structural Example 1 can be used. In addition, the materials of the bonding layer 106b [1] and the bonding layer 106b [2] may be the same material or different materials.

  One embodiment of the present invention is not limited to the above example. As another aspect of the present invention, an example different from the storage device 111 will be described.

  A memory device 112 illustrated in FIG. 7A1 includes a device 112a, a device 112b, and a substrate 107. As shown by an arrow in FIG. 7A1, the device 112a and the device 112b are attached to each other along the front surface and the back surface of the substrate 107, whereby the device 112a illustrated in FIG. 7A2 can be manufactured. The storage device 112 is different from the storage device 111 in that the wiring 103a of the device 112a and the wiring 103b of the device 112b are bonded to the substrate 107 so as not to overlap each other.

  A storage device 113 illustrated in FIG. 7B1 includes a device 113a, a device 113b, and a substrate 107. As shown by an arrow in FIG. 7B1, the memory device 113 illustrated in FIG. 7B2 can be manufactured by attaching the device 113a and the device 113b along the front surface and the back surface of the substrate 107. . The storage device 113 is different from the storage device 111 in that the device 113a has one terminal 104a and the device 113b has one terminal 104b.

  A storage device 114 illustrated in FIG. 8A includes a device 114a, a device 114b, and a substrate 107. The two terminals 104a and the two wirings 103a included in the device 114a are disposed on the sides adjacent to each other, and similarly, the two terminals 104b and the two wirings 103b included in the device 114b are disposed on the sides adjacent to each other. Has been. As shown by an arrow in FIG. 8A, the memory device 114 illustrated in FIG. 8B can be manufactured by attaching the device 114a and the device 114b along the front surface and the back surface of the substrate 107. . The storage device 114 is different from the storage device 111 in that the two wirings 103a and the two wirings 103b are bonded to the substrate 107 so as not to overlap each other.

  As described above, this configuration example is not limited to the configuration of the storage device 111, and the method of bonding to the substrate 107 or the configuration can be changed as appropriate, such as the storage devices 112 to 114.

<Configuration example 4>
Next, FIG. 9 shows a storage device different from the configuration of the storage device 100 shown in FIG. 1, the storage device 110 shown in FIG. 3C, and the storage device 111 shown in FIG.

  A device 120a illustrated in FIG. 9A1 includes a semiconductor device 102 including a memory cell, and the semiconductor device 102 is provided over a substrate 101. The device 120a includes a terminal 104 and a wiring 105 that electrically connects the terminal 104 and the semiconductor device 102a. Further, the device 120a has a core 108 on a side of the substrate 101 that is paired with a side where the terminal 104 is located.

  Consider a configuration in which the device 120a shown in FIG. 9A1 is wound around the core 108 in a roll shape as shown in FIG. 9A2. With such a configuration, the storage device 120 having a large storage capacity can be configured.

  9A1 and 9B, the semiconductor device 102, the terminal 104, and the wiring 105 are wound around the core 108 so that the semiconductor device 102, the terminal 104, and the wiring 105 face outward. You may wind so that it may become inward.

  Note that the memory device 120 illustrated in FIG. 9A2 may be further wound, and the wiring 105 and the terminal 104 may be wound around the core 108 as in the memory device 120A illustrated in FIG. 9A3. .

  Note that the region 109 of the substrate 101 that starts to be wound around the core 108 preferably has a certain size. When the region 109 is wound around the core 108, the radius of curvature becomes small. In other words, since stress applied to the region 109 is increased, if the region 109 includes a circuit element such as a transistor or a capacitor, a problem may occur in the circuit element. Therefore, it is preferable that no circuit element be provided in the region 109. However, this is not the case when the circuit element is strong against stress.

  FIG. 10 illustrates a part of a cross-sectional view taken along one-dot chain line A4 in the memory device 120 illustrated in FIG. 9A3.

  The storage device 120 has a core 108 at the center thereof. In addition, the bonding layer 106 is provided on the back surface of the substrate 101 (a surface including the semiconductor device 102 is a front surface). When the substrate 101 is wound around the core 108, the storage device 120 is configured to include the bonding layer 106 between the core 108 and the back surface of the region 109 of the substrate 101. In addition, the bonding layer 106 is provided between the surface of the region 109 of the substrate 101 and the back surface of the substrate 101 wound around the surface. In FIG. 10, the substrate 101 is wound around the core 108, and the semiconductor device 102 is illustrated on the surface of the substrate 101 in the second turn. In the second and subsequent rounds, the storage device 120 includes a bonding layer 106 between the front surface of the semiconductor device 102 and the back surface of the substrate 101 wound around the surface by one turn.

  Finally, the storage device 120 is configured such that the wiring 105 and the terminal 104 are positioned on the outermost periphery by winding the substrate 101 around the core 108.

  As the material of the bonding layer 106, the same material as that of the bonding layer 106a and the bonding layer 106b described in Structural Example 1 can be used.

  One embodiment of the present invention is not limited to the above example. As another aspect of the present invention, an example different from the storage device 120 will be described.

  A device 121a illustrated in FIG. 9B1 includes a semiconductor device 102 including memory cells, and the semiconductor device 102 is provided over a substrate 101. The substrate 101 has a convex shape. The device 121 a includes a terminal 104 and a wiring 105 on the side 121 b side of the convex substrate 101, and a core 108 on the side 121 t side of the convex substrate 101. In particular, the device 121 a includes the terminal 104 in the region 121 r of the convex substrate 101.

  The core 108 has two bottom surfaces 108s. The length of the core 108 in the axial direction is shorter than the length of the side 121b of the substrate 101.

  The semiconductor device 102 a is electrically connected to the terminal 104 through a wiring 105.

  Consider a configuration in which the device 121a shown in FIG. 9B1 is wound around the core 108 as in FIG. 9A2. When the substrate 101 is completely wound around the core 108, the region 121r protrudes from the length of the core 108 (see FIG. 9B2). Finally, the region 121r of the substrate 101 is bent toward the bottom surface 108s of the core 108 (see FIG. 9 (B3)).

  In this way, the storage device 121 having a large storage capacity can be configured by winding the device 121a around the core 108 and folding it.

  Further, since the region 121r of the substrate 101 is bent toward the bottom surface 108s of the core 108, a stress stronger than the winding of the substrate 101 may be applied to the bent portion. For this reason, it is preferable that the bent portion is not provided with a circuit element or the like and only has wiring.

  Note that in this structural example, the core 108 is described as a cylinder in FIG. 9, but one embodiment of the present invention is not limited thereto. For example, the core 108 may be an elliptical column or a polygonal column. Further, for example, the storage device 120, the storage device 120 </ b> A, or the storage device 121 may be configured by winding the substrate 101 without having the core 108.

  By applying the memory device of each structure example described in this embodiment, the installation area of the memory device can be reduced even if the area of a circuit included in the memory device is increased. In addition, since the circuit area of the memory device can be increased by applying the memory device of each configuration example of this embodiment, a circuit with reduced parasitic capacitance, an element with high withstand voltage against electrostatic breakdown Etc. can be configured. Thus, a memory device that is resistant to malfunction can be manufactured.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 2)
In this embodiment, the structure of the semiconductor device described in the above embodiment will be described. Note that each configuration example described in this embodiment also includes an example of mounting the storage device described in any of the above embodiments.

<Configuration example 1>
FIG. 11A illustrates an example of a structure of a semiconductor device. The semiconductor device 301 includes a memory cell array MA, a bit line driver circuit BLD, a word line driver circuit WLD, a control logic circuit CLC, and an output circuit OPC. In this configuration example, the bit line driver circuit BLD, the word line driver circuit WLD, the control logic circuit CLC, and the output circuit OPC are collectively referred to as a peripheral circuit or a drive circuit.

  The memory cell array MA includes m (m is an integer of 1 or more) in the column direction, n (n is an integer of 1 or more) in the row direction, and memory cells MC are provided in a matrix. . Note that in FIG. 11A, a memory cell MC located in i row and j column (i is an integer of 1 to m and j is an integer of 1 to n) is defined as a memory cell MC [i, j], the memory cell MC [1,1], the memory cell MC [m, 1], the memory cell MC [1, n], and the memory cells MC other than the memory cell MC [m, n] Description is omitted.

  The memory cell array MA is electrically connected to the bit line driver circuit BLD via one or a plurality of wirings. In addition, the memory cell array MA is electrically connected to the word line driver circuit WLD via one or a plurality of wirings. Note that the number of wirings that electrically connect the memory cell array MA and the bit line driver circuit BLD and the number of wirings that electrically connect the memory cell array MA and the word line driver circuit WLD are the memory included in the memory cell array MA. It is determined by the number of cells MC and the number of wirings electrically connected to one memory cell MC.

  The control logic circuit CLC is electrically connected to the bit line driver circuit BLD. In addition, the control logic circuit CLC is electrically connected to the word line driver circuit WLD. The output circuit OPC is electrically connected to the bit line driver circuit BLD.

  The bit line driver circuit BLD includes a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The function of the column decoder will be described later. The precharge circuit has a function of precharging part or all of the wiring that electrically connects the bit line driver circuit BLD and the memory cell MC. The sense amplifier has a function of amplifying a data signal read from the memory cell MC. Note that the amplified data signal is output to the outside of the semiconductor device 301 as a digital data signal RDATA through the output circuit OPC. The writing circuit has a function of writing the data signal WDATA input from the outside to the memory cell MC.

  The word line driver circuit WLD includes a row decoder, a buffer circuit, and the like. The function of the row decoder will be described later. The buffer circuit has a function of amplifying a selection signal flowing in part or all of the wiring that electrically connects the word line driver circuit WLD and the memory cell MC.

  In addition, a chip enable signal CE, a write enable signal WE, and a read enable signal RE are input to the semiconductor device 301 as input signals from the outside. Specifically, these input signals are input to the control logic circuit CLC. The control logic circuit CLC generates control signals for the row decoder and the column decoder based on these input signals, and transmits them to the row decoder and the column decoder, respectively. The signal processed by the control logic circuit CLC is not limited to this, and another control signal may be input as necessary.

  The row decoder and the column decoder perform a write operation or a read operation on the memory cell MC of the memory cell array MA based on a control signal sent from the control logic circuit CLC and an address signal ADDR inputted from the outside. It has a function to perform. Specifically, the row decoder outputs a signal for selecting a memory cell MC to be written or read based on a control signal sent from the control logic circuit CLC and an address signal ADDR inputted from the outside. It has a function of generating and transmitting to the memory cell array MA. In addition, the column decoder has a function of selecting a memory cell MC based on a control signal sent from the control logic circuit CLC and an address signal ADDR input from the outside. When writing is performed, the data signal WDATA is written into the selected memory cell MC by the writing circuit. When reading is performed, the held data is read from the selected memory cell MC by the precharge circuit and the sense amplifier circuit.

  The semiconductor device 301 is supplied with a reference voltage (GND), a low power supply voltage (VSS), a high power supply voltage (VDD) for peripheral circuits, and a high power supply voltage (VIL) for the memory cell array MC as power supply voltages from the outside. . Note that the above-described external power supply voltage is merely an example, and depending on the configuration of the semiconductor device 301, the type of external power supply voltage may be increased or decreased as appropriate.

  The semiconductor device 301 includes the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c illustrated in FIGS. 1 and 3, the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device illustrated in FIG. 9, respectively. 102 can be provided over the substrate 101.

  Note that the structure of one embodiment of the present invention is not limited to the semiconductor device 301, and a driver circuit may be provided outside the semiconductor device 301 instead of inside the semiconductor device 301. An example of the semiconductor device in that case is illustrated in FIG. The semiconductor device 302 has a configuration in which the semiconductor device 301 is divided into a memory cell array unit 302a (memory cell array MA) and a drive circuit unit 302b.

  This configuration can be applied to the storage device 100, for example. Specifically, the memory cell array portion 302a is provided over the substrate 101 as the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c illustrated in FIG. 1, and the driving circuit portion 302b is provided over an electronic device or the like. Can be provided. Note that in this configuration, the memory device 100 is mounted on the circuit board, and the memory cell array unit 302a and the drive circuit unit 302b are electrically connected by FPC (Flexible Print Circuit), wire bonding, or the like. That's fine.

  FIG. 12A illustrates an example in which the memory device 100 is mounted over a circuit board 302d and the memory cell array portion 302a and the driver circuit portion 302b included in the memory device 100 are electrically connected by an FPC 302c.

  In this manner, by providing the driver circuit portion 302b over the circuit substrate 302d outside the memory device 100, the memory cell array MA having a larger area can be provided over the flexible substrate. Thereby, the storage capacity of the storage device 100 can be increased.

  Further, the configuration divided into the memory cell array unit 302a (memory cell array MA) and the drive circuit unit 302b can be applied to the storage device 111, for example. Specifically, the memory cell array portion 302a is provided as the semiconductor device 102a and the semiconductor device 102b illustrated in FIG. 5 on the substrate 101a and the substrate 101b, respectively, and the circuit board 302d provided with the drive circuit portion 302b in an electronic device or the like. Can be provided above. Note that in this configuration, the storage device 111 may be mounted in a slot provided on the circuit board or the like.

  FIG. 12B1 shows a state in which the memory device 111 is mounted in the slot 302e provided on the circuit board 302d, and FIG. 12B2 shows a state in which the memory device 111 is fitted in the slot 302e. The slot 302e has a terminal 302f for electrical connection with the storage device 111. By inserting the storage device 111 into the slot 302e, the terminal 302f and the terminal 104 of the storage device 111 are electrically connected. Is done. The drive circuit unit 302b may be provided in, for example, the slot 302e or may be provided on the circuit board 302d. In addition, the drive circuit portion 302b may be configured to be electrically connected to the slot 302e via the wiring 302g, for example.

  In this manner, by configuring the drive circuit portion 302b outside the storage device 111, the memory cell array MA having a larger area can be provided over a flexible substrate. Thereby, the storage capacity of the storage device 111 can be increased.

  The configuration divided into the memory cell array portion 302a (memory cell array MA) and the drive circuit portion 302b can be applied to, for example, the storage device 120 or the storage device 120A. Specifically, the memory cell array portion 302a can be provided over the substrate 101 as the semiconductor device 102 illustrated in FIG. 9, and the driver circuit portion 302b can be provided over a circuit substrate included in an electronic device or the like. Note that in this structure, the memory device 120 may be mounted using a fastener, a holder, and the like, and the memory cell array portion 302a and the driver circuit portion 302b may be electrically connected by FPC, wire bonding, or the like.

  FIG. 13A illustrates an example in which the memory device 120 is mounted over the circuit board 302d and the memory cell array portion 302a and the driver circuit portion 302b included in the memory device 100 are electrically connected using an anisotropic conductive material or the like. Is shown. Further, the circuit board 302d includes a fastener 302h, and FIG. 13A illustrates a state in which the storage device 120 is physically fixed to the circuit board 302d by the fastener 302h.

  FIG. 13B shows a state where the storage device 120A is mounted on a holder 302k having a circuit board 302d. The holder 302k has a terminal 302f for electrical connection with the storage device 120A. By fitting the storage device 120A into the holder 302k, the terminal 302f and the terminal 104 of the storage device 120A are electrically connected. Is done. The drive circuit unit 302b may be provided in the holder 302k, for example, or may be provided on the circuit board 302d. For example, the drive circuit portion 302b may be configured to be electrically connected to the slot 302e through the wiring 302g.

<Configuration example 2>
Next, a structural example different from the semiconductor device 301 and the semiconductor device 302 is illustrated in FIG.

  The semiconductor device 303 includes a circuit 303a, a circuit 303b, and a circuit 303c. The circuit 303a has a configuration similar to that of the semiconductor device 301 described in Configuration Example 1 of this embodiment. Note that the circuit 303a includes a word line driver circuit WLD1, and the word line driver circuit WLD1 corresponds to the word line driver circuit WLD in the semiconductor device 301. In addition, the circuit 303a includes a memory cell array MA1, and the memory cell array MA1 corresponds to the memory cell array MA in the semiconductor device 301.

  The circuit 303b includes a word line driver circuit WLD2 and a memory cell array MA2. The circuit 303c includes a word line driver circuit WLD3 and a memory cell array MA3.

  The memory cell array MA1 is electrically connected to the memory cell array MA2 by wiring electrically connected to the bit line driver circuit BLD. In addition, the memory cell array MA2 is electrically connected to the memory cell array MA3 by a wiring electrically connected to the bit line driver circuit BLD.

  The memory cell array MA2 and the memory cell array MA3 are each provided with memory cells MC in a matrix. However, in FIG. 14, the memory cell array MA2 and the memory cell array MA3 show only one row of memory cells.

  Each of the memory cell array MA2 and the memory cell array MA3 has m memory cells in the column direction and n memory cells in the row direction, like the memory cell array MA1. Note that the memory cell arrays MA1 to MA3 do not have to have the same number of memory cells. For example, the memory cell array MA1 has m memory cells in the column direction and n memory cells in the row direction. The cell array MA2 has p memory cells in the column direction (p is an integer greater than or equal to 1 and not m) and n memory cells in the row direction, and the memory cell array MA3 has q memory cells MA3 in the column direction (q is 1 or more). And an integer other than m and p.), It may be configured to have n memory cells in the row direction. In this configuration, the number of memory cells in each row direction of the memory cell array MA2 and the memory cell array MA3 is the same as the number of wirings electrically connected to the bit line driver circuit BLD and the memory cell array MA1. Note that the number of memory cells in each row direction of the memory cell arrays MA1 to MA3 may not necessarily match each other.

  The word line driver circuit WLD1 has a function of selecting a memory cell included in the memory cell array MA1, the word line driver circuit WLD2 has a function of selecting a memory cell included in the memory cell array MA2, and the word line driver circuit WLD3 The memory cell array MA3 has a function of selecting a memory cell. The word line driver circuit WLD1 is electrically connected to the word line driver circuit WLD2 and the word line driver circuit WLD3. In FIG. 14, the word line driver circuit WLD1 to the word line driver circuit WLD3 are combined into a word line driver circuit. Illustrated as WLD. That is, the word line driver circuit WLD has a function of selecting a memory cell included in any of the memory cell arrays MA1 to MA3.

  Note that the semiconductor device 303 having the above-described structure example has the word line driver circuit WLD1 to the word line driver circuit WLD3 in each of the circuit 303a, the circuit 303b, and the circuit 303c, but the word line driver circuit WLD1 to the word line The driver circuit WLD3 may be integrated into the circuit 303a as the word line driver circuit WLD.

  The configuration in that case is shown in FIG. The semiconductor device 304 includes a circuit 304a, a circuit 304b, and a circuit 304c, and the circuit 304a includes a word line driver circuit WLD. In particular, the word line driver circuit WLD has a function of selecting memory cells included in the memory cell arrays MA1 to MA3. Therefore, the circuit 304b and the circuit 304c do not have a word line driver circuit.

  The semiconductor device 303 and the semiconductor device 304 include the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c illustrated in FIGS. 1 and 3, respectively, the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102b illustrated in FIGS. The semiconductor device 102 can be provided over a flexible substrate.

  In particular, the structures of the semiconductor device 303 and the semiconductor device 304 are suitable for manufacturing the memory device 110, for example. In the case of manufacturing the memory device 110 with the structure of the semiconductor device 303, the circuit 303a is the semiconductor device 102a illustrated in FIG. 3A, the circuit 303b is the semiconductor device 102b illustrated in FIG. 3A, and the circuit 303c is illustrated. The semiconductor device 102c is described in 3 (A). Further, the wiring that electrically connects the circuit 303a and the circuit 303b is 103a, and the wiring that electrically connects the circuit 303b and the circuit 303c is 103b, which is provided over the substrate 101. In FIG. The circuit 303a, the circuit 303b, and the circuit 303c may not be provided in the bent region.

  In the case where the memory device 110 is manufactured with the structure of the semiconductor device 304, the circuits 304a, 304b, and 304c are referred to as the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c illustrated in FIG. The wiring for electrically connecting the circuit 303b and the circuit 303b is 103a, and the wiring for electrically connecting the circuit 303b and the circuit 303c is 103b, which is provided over the substrate 101, so that the memory device 110 is configured with the structure of the semiconductor device 303. The same effects as in the case of manufacturing can be obtained.

  That is, depending on the configuration of the semiconductor device 303 and the semiconductor device 304, the circuit 303a, the circuit 303b, and the circuit 303c can be prevented from being affected by stress caused by bending.

  Note that the structure of one embodiment of the present invention is not limited to the semiconductor device 303 and the semiconductor device 304, and a driver circuit (a bit line driver circuit BLD, a word line driver circuit WLD, a control logic circuit CLC, or an output circuit OPC) is included in the semiconductor device. 303 or the semiconductor device 304 may be provided outside the semiconductor device 304. An example of the semiconductor device in that case is shown in FIG. The semiconductor device 305 includes a semiconductor device 303 or a semiconductor device 304, a memory cell array unit 305a (memory cell array MA1), a memory cell array unit 305b (memory cell array MA2), a memory cell array unit 305c (memory cell array MA3), and a drive circuit unit. The configuration is divided into 305p. Note that the memory cell array unit 305a includes wirings that electrically connect the drive circuit unit 305p and the memory cell array unit 305b, and wirings that electrically connect the drive circuit unit 305p and the memory cell array unit 305c.

  For example, when the memory device 110 is manufactured, the memory cell array unit 305a is the semiconductor device 102a illustrated in FIG. 3, the memory cell array unit 305b is the semiconductor device 102b, and the memory cell array unit 305c is the semiconductor device 102c. This is effective when provided on the circuit board 101 and on the circuit board provided in the electronic device or the like. Note that in this structure, the memory device 110 may be mounted on the circuit board, and the memory cell array portion 302a and the driver circuit portion 302b may be electrically connected by FPC, wire bonding, or the like.

  FIG. 17 illustrates an example in which the memory device 110 is mounted over the circuit board 302d and the memory cell array unit 305a and the driver circuit unit 305p included in the memory device 110 are electrically connected by the FPC 305d.

  In this manner, by configuring the drive circuit portion 302b outside the storage device 110, the memory cell array MA having a larger area can be provided over a flexible substrate. Thereby, the storage capacity of the storage device 110 can be increased.

  Here, in the mounting examples shown in FIGS. 12, 13, and 17 described in this embodiment mode, the driver circuit portion 302b is placed on the circuit board 302d side as in the configuration examples in FIGS. The advantage provided will be described.

  18A and 18B described in Embodiment Mode 3 as memory cells included in the memory cell array portion 302a (the memory cell array portion 305a to the memory cell array portion 305c) in the configuration example of FIGS. C), FIG. 19A, FIG. 19B, FIG. 20D, and FIG. 20A, all of the transistors included in these memory cells can be OS transistors described in Embodiment 6. . Since the OS transistor has a very low off-state current, for example, when the OS transistor is used to hold the potential of the memory cell, the frequency of refreshing data held in the memory cell can be reduced.

  On the other hand, a transistor including silicon in a channel formation region (hereinafter referred to as an Si transistor) can be applied to the driver circuit portion 302b (the driver circuit portion 305p) having the above-described configuration example. In particular, the drive circuit portion 302b (drive circuit portion 305p) includes a bit line driver circuit, a word line driver circuit WLD, a control logic circuit CLC, and the like. To improve the performance of these circuits, Si transistors are used. It is known to be good to configure.

  In order to make use of the characteristics of both the OS transistor and the Si transistor, it is desirable that the memory device be formed on the same substrate by both the OS transistor and the Si transistor. However, since the process for forming an OS transistor and the process for forming a high-breakdown-voltage Si transistor used for a driver or the like are different in terms of heat treatment (temperature, time, atmosphere, and the like), the OS transistor is different. It is difficult to construct a high breakdown voltage Si transistor on the same substrate. Therefore, a drive circuit portion 302b (drive circuit portion 305p) constituted only by Si transistors is formed on the circuit substrate 302d side, and a memory cell array portion 302a (memory cell array portion 305a to memory cell array portion 305c) constituted only by OS transistors is formed as a circuit. By adopting a structure mounted on the substrate 302d, a memory device utilizing the characteristics of both the OS transistor and the Si transistor can be realized.

  Note that the plurality of configuration examples described in this embodiment can be combined as appropriate.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, a memory cell included in the memory device described in the above embodiment will be described.

<DRAM memory cell>
FIG. 18A shows a circuit configuration example of a DRAM memory cell. The memory cell 410 includes a transistor M1 and a capacitor C1. Note that the transistor M1 is a dual-gate transistor and includes a front gate (sometimes simply referred to as a gate) and a back gate.

  The first terminal of the transistor M1 is electrically connected to the first terminal of the capacitor C1, the second terminal of the transistor M1 is electrically connected to the wiring BL, and the gate of the transistor M1 is electrically connected to the wiring WL. The back gate of the transistor M1 is electrically connected to the wiring BGL. The second terminal of the capacitor C1 is electrically connected to the wiring CL.

  The wiring BL functions as a bit line, and the wiring WL functions as a word line. The wiring CL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor C1. It is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CL during data writing and data reading.

  The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

  Data writing and reading are performed by applying a high-level potential to the wiring WL, turning on the transistor M1, and electrically connecting the wiring BL and the first terminal of the capacitor C1.

  The memory cell included in the semiconductor device described in the above embodiment is not limited to the memory cell 410. Depending on the situation, the circuit can be discarded, the connection of the circuit can be changed, etc., depending on the situation or if necessary.

  For example, the memory cell included in the semiconductor device described in the above embodiment may have a memory cell structure as illustrated in FIG. The memory cell 420 has a structure in which the back gate of the dual-gate transistor M1 is electrically connected to the wiring WL instead of the wiring BGL. With this configuration, the same potential as that of the gate of the transistor M1 can be applied to the back gate of the transistor M1, and thus the current flowing through the transistor M1 can be increased when the transistor M1 is in a conductive state. it can.

  For example, the memory cell included in the semiconductor device described in any of the above embodiments may be a memory cell including a single-gate transistor, that is, a transistor M1 having no back gate. A circuit configuration example of the memory cell is illustrated in FIG. The memory cell 420 is configured by removing the back gate from the transistor M1 of the memory cell 410. Note that by applying the memory cell 430 to the semiconductor device, the transistor M1 does not have a back gate; therefore, the manufacturing process of the semiconductor device can be shortened compared to the memory cell 410 and the memory cell 420.

<Gain cell type memory cell with two transistors and one capacitor>
FIG. 19A shows a circuit configuration example of a gain cell type memory cell having two transistors and one capacitor. The memory cell 440 includes a transistor M2, a transistor M3, and a capacitor C2. Note that the transistor M2 is a dual-gate transistor and includes a front gate (sometimes simply referred to as a gate) and a back gate.

  The first terminal of the transistor M2 is electrically connected to the first terminal of the capacitor C2, the second terminal of the transistor M2 is electrically connected to the wiring WBL, and the gate of the transistor M2 is electrically connected to the wiring WL. The back gate of the transistor M2 is electrically connected to the wiring BGL. A second terminal of the capacitor C2 is electrically connected to the wiring CL. A first terminal of the transistor M3 is electrically connected to the wiring RBL, a second terminal of the transistor M3 is electrically connected to the wiring SL, and a gate of the transistor M3 is electrically connected to the first terminal of the capacitor C2. It is connected to the.

  The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WL functions as a word line. The wiring CL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor C2. It is preferable to apply a low-level potential (sometimes referred to as a reference potential) to the wiring CL during data writing, during data holding, and during data reading.

  The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

  Data is written by applying a high-level potential to the wiring WL, turning on the transistor M2, and electrically connecting the wiring WBL and the first terminal of the capacitor C2. Specifically, when the transistor M2 is in a conductive state, a potential corresponding to information recorded in the wiring WBL is applied, and the potential is written to the first terminal of the capacitor C2 and the gate of the transistor M3. After that, by applying a low-level potential to the wiring WL and turning off the transistor M2, the potential of the first terminal of the capacitor C2 and the potential of the gate of the transistor M3 are held.

  Data is read by applying a predetermined potential to the wiring SL. Since the current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3, they are connected to the first terminal of the transistor M3. By reading the potential of the connected wiring RBL, the potential held in the first terminal of the capacitor C2 (or the gate of the transistor M3) can be read. That is, information written in the memory cell can be read from the potential held in the first terminal of the capacitor C2 (or the gate of the transistor M3).

  The memory cell included in the semiconductor device described in the above embodiment is not limited to the memory cell 440. Depending on the situation, the circuit can be discarded, the connection of the circuit can be changed, etc., depending on the situation or if necessary.

  For example, the memory cell included in the semiconductor device described in the above embodiment may have a memory cell structure as illustrated in FIG. As in the transistor M1 included in the memory cell 420 in FIG. 18B, the memory cell 450 has a structure in which the back gate of the dual-gate transistor M2 is electrically connected to the wiring WL instead of the wiring BGL. ing. With such a structure, the same potential as that of the gate of the transistor M2 can be applied to the back gate of the transistor M2, so that the current flowing through the transistor M2 can be increased when the transistor M2 is in a conductive state. it can.

  For example, the memory cell included in the semiconductor device described in any of the above embodiments may be a memory cell including a transistor M2 having no back gate. An example of a circuit configuration of the memory cell is shown in FIG. The memory cell 460 has a configuration in which the back gate is removed from the transistor M2 of the memory cell 440. Note that by applying the memory cell 460 to the semiconductor device, the transistor M2 does not have a back gate; thus, the manufacturing process of the semiconductor device can be shortened compared to the memory cell 460 and the memory cell 450.

  For example, the wiring WBL and the wiring RBL may be combined as a single wiring BL. An example of a circuit configuration of the memory cell is shown in FIG. The memory cell 470 has a structure in which the wiring WBL and the wiring RBL of the memory cell 440 are used as one wiring BL and the second terminal of the transistor M2 and the first terminal of the transistor M3 are electrically connected to the wiring BL. It has become. That is, the memory cell 470 has a configuration in which the write bit line and the read bit line operate as one wiring BL.

<Gain cell type memory cell with three transistors and one capacitor>
FIG. 20A shows a gain cell type memory cell having three transistors and one capacitor. The memory cell 480 includes transistors M4 to M6 and a capacitor C3. Note that the transistor M4 is a dual-gate transistor and includes a front gate (sometimes simply referred to as a gate) and a back gate.

  The first terminal of the transistor M4 is electrically connected to the first terminal of the capacitor C3, the second terminal of the transistor M4 is electrically connected to the wiring BL, and the gate of the transistor M4 is electrically connected to the wiring WWL. The back gate of the transistor M4 is electrically connected to the wiring BGL. A second terminal of the capacitor C3 is electrically connected to the first terminal of the transistor M5 and the wiring GND. The second terminal of the transistor M5 is electrically connected to the first terminal of the transistor M6, and the gate of the transistor M5 is electrically connected to the first terminal of the capacitor C3. A second terminal of the transistor M6 is electrically connected to the wiring BL, and a gate of the transistor M6 is electrically connected to the wiring RWL.

  The wiring BL functions as a bit line, the wiring WWL functions as a write word line, and the wiring RWL functions as a read word line.

  The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M4. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M4 can be increased or decreased.

  The wiring GND is a wiring that applies a low level potential.

  Data is written by applying a high-level potential to the wiring WWL, turning on the transistor M4, and electrically connecting the wiring BL and the first terminal of the capacitor C3. Specifically, when the transistor M4 is conductive, a potential corresponding to information recorded in the wiring BL is applied, and the potential is written to the first terminal of the capacitor C3 and the gate of the transistor M5. After that, a low-level potential is applied to the wiring WWL to turn off the transistor M4, whereby the potential of the first terminal of the capacitor C3 and the potential of the gate of the transistor M5 are held.

  Data reading is performed by precharging the wiring BL with a predetermined potential, then bringing the wiring BL into an electrically floating state, and applying a high level potential to the wiring RWL. Since the wiring RWL has a high level potential, the transistor M6 is turned on, and the wiring BL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BL is applied to the second terminal of the transistor M5; however, the transistor depends on the potential held at the first terminal of the capacitor C3 (or the gate of the transistor M5). The potential of the second terminal of M5 and the potential of the wiring BL change. Here, by reading the potential of the wiring BL, the potential held in the first terminal of the capacitor C3 (or the gate of the transistor M5) can be read. That is, information written in the memory cell can be read from the potential held at the first terminal of the capacitor C3 (or the gate of the transistor M5).

  The memory cell included in the semiconductor device described in the above embodiment is not limited to the memory cell 440. Depending on the situation, the circuit can be discarded, the connection of the circuit can be changed, etc., depending on the situation or if necessary. For example, like the transistor M1 of the memory cell 420 illustrated in FIG. 18B and the transistor M2 of the memory cell 450 illustrated in FIG. 19B, the memory cell 480 includes a back gate of the transistor M4 instead of the wiring BGL. Alternatively, a configuration of being electrically connected to the wiring WL may be employed (not shown). With this configuration, the same potential as that of the gate of the transistor M4 can be applied to the back gate of the transistor M4. Therefore, when the transistor M4 is in a conductive state, the current flowing through the transistor M4 can be increased. it can. Further, for example, like the transistor M1 of the memory cell 430 illustrated in FIG. 18C and the transistor M2 of the memory cell 460 illustrated in FIG. 19C, the memory M480 does not have a back gate. It may be a configuration. With such a structure, the manufacturing process of the semiconductor device can be shortened because the transistor M4 does not have a back gate.

<SRAM Memory Cell>
FIG. 20B illustrates an example of an SRAM (Static Random Access Memory). Note that a memory cell 490 illustrated in FIG. 20B is an SRAM memory cell that can be backed up. The memory cell 490 includes transistors M7 to M10, transistors MS1 to MS4, a capacitor C4, and a capacitor C5. Note that the transistors M7 to M10 are dual-gate transistors and each include a front gate (sometimes simply referred to as a gate) and a back gate. Note that the transistors MS1 and MS2 are p-channel transistors, and the transistors MS3 and MS4 are n-channel transistors.

  The first terminal of the transistor M7 is electrically connected to the wiring BL, and the second terminal of the transistor M7 is the first terminal of the transistor MS1, the first terminal of the transistor MS3, the gate of the transistor MS2, and the transistor MS4. The gate is electrically connected to the first terminal of the transistor M10. The gate of the transistor M7 is electrically connected to the wiring WL, and the back gate of the transistor M7 is electrically connected to the wiring BGL1. The first terminal of the transistor M8 is electrically connected to the wiring BLB, and the second terminal of the transistor M8 is the first terminal of the transistor MS2, the first terminal of the transistor MS4, the gate of the transistor MS1, and the transistor MS3. The gate and the first terminal of the transistor M9 are electrically connected. A gate of the transistor M8 is electrically connected to the wiring WL, and a back gate of the transistor M8 is electrically connected to the wiring BGL2.

  A second terminal of the transistor MS1 is electrically connected to the wiring VDD. A second terminal of the transistor MS2 is electrically connected to the wiring VDD. A second terminal of the transistor MS3 is electrically connected to the wiring GND. A second terminal of the transistor MS4 is electrically connected to the wiring GND.

  The second terminal of the transistor M9 is electrically connected to the first terminal of the capacitor C4, the gate of the transistor M9 is electrically connected to the wiring BRL, and the back gate of the transistor M9 is electrically connected to the wiring BGL3. It is connected. The second terminal of the transistor M10 is electrically connected to the first terminal of the capacitor C5, the gate of the transistor M10 is electrically connected to the wiring BRL, and the back gate of the transistor M10 is electrically connected to the wiring BGL4. It is connected.

  A second terminal of the capacitor C4 is electrically connected to the wiring GND, and a second terminal of the capacitor C5 is electrically connected to the wiring GND.

  The wiring BL and the wiring BLB function as bit lines, the wiring WL functions as a word line, and the wiring BRL is a wiring that controls the conduction state and the non-conduction state of the transistors M9 and M10.

  The wirings BGL1 to BGL4 function as wirings for applying potentials to the back gates of the transistors M7 to M10, respectively. By applying an arbitrary potential to the wirings BGL1 to BGL4, the threshold voltages of the transistors M7 to M10 can be increased or decreased, respectively.

  The wiring VDD is a wiring that applies a high level potential, and the wiring GND is a wiring that applies a low level potential.

  Data is written by applying a high level potential to the wiring WL and applying a high level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to information recorded in the wiring BL is applied, and the potential is written on the second terminal side of the transistor M10.

  Incidentally, since the memory cell 490 forms an inverter loop with the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal side of the transistor M8. Since the transistor M8 is in a conductive state, the potential applied to the wiring BL, that is, the inverted signal of the signal input to the wiring BL is output to the wiring BLB. Further, since the transistor M9 and the transistor M10 are conductive, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are the first terminal of the capacitor C5 and the first terminal of the capacitor C4, respectively. Held by one terminal. After that, a low-level potential is applied to the wiring WL and a low-level potential is applied to the wiring BRL so that the transistors M7 to M10 are turned off, so that the first terminal of the capacitor C4 and the capacitor C5 The first terminal is held.

  Data is read by precharging the wiring BL and the wiring BLB to a predetermined potential in advance, then applying a high level potential to the wiring WL and applying a high level potential to the wiring BRL, whereby the first terminal of the capacitor C4. Is refreshed by the inverter loop of the memory cell 490 and output to the wiring BLB. In addition, the potential of the first terminal of the capacitor C5 is refreshed by the inverter loop of the memory cell 490 and output to the wiring BL. In the wiring BL and the wiring BLB, the potential of the first terminal of the capacitor C5 and the potential of the first terminal of the capacitor C4 change from the precharged potential to the potential of the first terminal of the capacitor C4. Can be read out.

  Note that in the channel formation regions of the transistors M1 to M10 described in this embodiment, an oxide semiconductor containing any one of indium, an element M (the element M is aluminum, gallium, yttrium, or tin) and zinc is formed. Can be used. That is, OS transistors can be used as the transistors M1 to M10. In particular, an oxide semiconductor including indium, gallium, and zinc is preferable, and a CAC-OS described in Embodiment 7 is more preferable. An OS transistor using an oxide semiconductor containing indium, gallium, and zinc has a characteristic of extremely low off-state current; therefore, by using an OS transistor as the transistors M1 to M10, the transistors M1 to M10 Leakage current can be made very low. That is, the written data can be held for a long time by the transistors M1 to M10, so that the frequency of refreshing the memory cells can be reduced. Also, the refresh operation of the memory cell can be made unnecessary.

  Note that silicon is preferably used for channel formation regions of the transistors M3, M5, M6, and the transistors MS1 to MS4 described in this embodiment. In particular, the silicon is preferably LTPS (Low Temperature Poly-Silicon) (hereinafter referred to as Si transistor). Since the Si transistor may have higher field effect mobility than the OS transistor, it can be said that the Si transistor is preferably used as the reading transistor or the transistor included in the inverter.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment, multivalued data is stored in the memory cell (DRAM, 2-transistor 1-capacitor gain-cell memory cell, 3-transistor 1-capacitor gain-cell memory cell) described in the previous embodiment. The case of handling will be described. By making it possible to hold not only binary but three or more data states in one memory cell, the memory capacity of the memory cell can be increased.

  FIG. 21 is a schematic diagram showing an example of a threshold voltage distribution of a memory cell that can handle multi-value data.

  FIG. 21 shows, as an example, a case where the memory cell has 8 data states (also referred to as “logic state”). 8 data states are referred to as data states A1-A8 in order from the lowest threshold voltage (referred to as a threshold value in this embodiment). 3-bit data “000”, “001”, “010”, “011”, “100”, “101”, “110”, and “111” are assigned to the data states A1 to A8, respectively. And

  Note that each of the threshold values of the eight data states may have a distribution width due to a difference between the memory cells generated when the manufacturing is completed, a parasitic capacitance of a circuit included in the memory cell, or the like. FIG. 21 illustrates the threshold distribution width of each of the eight data states.

  In the memory device having the memory cell, eight voltages Va1 to Va8 are set to distinguish the eight data states of the memory cell. The voltages Va1-Va8 are threshold value boundary values for identifying adjacent data states, and are also used as read voltages for reading data from the memory cells.

  In the memory cell described in another embodiment, as described above, multi-value data can be handled, so that the storage capacity that can be held by the memory device including the memory cell can be increased.

(Embodiment 5)
In this embodiment, a method for manufacturing a memory device over a flexible substrate described in the above embodiment will be described.

  As for a method for manufacturing a semiconductor device having a memory cell over a flexible substrate, for example, a method in which a circuit element such as a transistor is formed over a flexible substrate, a separation layer (tungsten, And a method in which a semiconductor device is formed over a substrate having polyimide resin, amorphous silicon, or the like, and the semiconductor device is peeled off and transferred to a flexible substrate. In this embodiment, a method for transferring the latter semiconductor device over a flexible substrate will be described.

  22 to 28, semiconductor device devices (device 100a, device 100b, device 100c, device 110a, device 111a, device 111b, device 112a, device 112b, and device 113a provided over a flexible substrate are used. A method for manufacturing the device 113b, the device 120a, and the device 121a) is illustrated.

<Formation of metal oxide layer>
First, the metal oxide layer 20 is formed over the substrate 14 (FIG. 22A).

  The substrate 14 is rigid to the extent that it can be easily transported, and has heat resistance to the temperature required for the manufacturing process. Examples of the material that can be used for the substrate 14 include glass, quartz, ceramic, sapphire, resin, semiconductor, metal, and alloy. Examples of the glass include alkali-free glass, barium borosilicate glass, and alumino borosilicate glass.

  As the metal oxide layer 20, one of titanium, molybdenum, aluminum, tungsten, silicon, indium, zinc, gallium, tantalum, tin, hafnium, yttrium, zirconium, magnesium, lanthanum, cerium, neodymium, bismuth, and niobium. Alternatively, a plurality of layers including a base layer can be used. The underlayer can contain metals, alloys, and compounds thereof (such as metal oxides). The underlayer preferably includes one or more of titanium, molybdenum, aluminum, tungsten, silicon, indium, zinc, gallium, tantalum, and tin.

  In addition, various metal oxides can be used for the metal oxide layer 20. Examples of the metal oxide include titanium oxide (TiOx), molybdenum oxide, aluminum oxide, tungsten oxide, indium tin oxide containing silicon (ITSO), indium zinc oxide, and In—Ga—Zn oxide. .

  Other metal oxides include indium oxide, indium oxide containing titanium, indium oxide containing tungsten, indium tin oxide (ITO), ITO containing titanium, indium zinc oxide containing tungsten, and zinc oxide ( ZnO), ZnO containing gallium, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, tin oxide, bismuth oxide, titanate, tantalate, niobium Examples include acid salts.

  There is no particular limitation on the method of forming the metal oxide layer 20. For example, it can be formed using a sputtering method, a plasma CVD method, a vapor deposition method, a sol-gel method, an electrophoresis method, a spray method, or the like.

  After the metal layer is formed, the metal oxide layer 20 can be formed by introducing oxygen into the metal layer. At this time, only the surface of the metal layer or the entire metal layer is oxidized. In the former case, a laminated structure of the metal layer and the metal oxide layer 20 is formed by introducing oxygen into the metal layer.

  For example, the thickness of the metal oxide layer 20 is preferably 1 nm or more and 200 nm or less, and more preferably 5 nm or more and 100 nm or less. In addition, when forming the metal oxide layer 20 using a metal layer, the thickness of the metal oxide layer 20 finally formed may become thicker than the thickness of the formed metal layer.

<Formation of resin layer 23>
Next, the resin layer 24 is formed over the metal oxide layer 20 (FIG. 22B).

  The resin layer 24 is preferably a material having both thermosetting and photosensitivity. In particular, when a photosensitive material is used, a resin layer having a desired shape (hereinafter, referred to as a resin layer 23) can be formed by a lithography method using light.

  The resin layer 24 is preferably formed using a material containing a polyimide resin or a polyimide resin precursor. The resin layer 24 can be formed using, for example, a material containing a polyimide resin and a solvent, or a material containing a polyamic acid and a solvent. Since polyimide is a material suitably used for a planarizing film or the like, a film forming apparatus and a material can be shared.

  Other resin materials that can be used for forming the resin layer 24 include, for example, acrylic resins, epoxy resins, polyamide resins, polyimide amide resins, siloxane resins, benzocyclobutene resins, phenol resins, and precursors of these resins. Etc.

  The resin layer 24 is preferably formed using a spin coater. By using the spin coating method, a thin film can be uniformly formed on a large substrate.

  The resin layer 24 is preferably formed using a solution having a viscosity of 5 cP or more and less than 500 cP, preferably 5 cP or more and less than 100 cP, more preferably 10 cP or more and 50 cP or less. The lower the viscosity of the solution, the easier the application. In addition, the lower the viscosity of the solution, the more air bubbles can be prevented and the better the film can be formed.

  In addition, examples of the method for forming the resin layer 24 include dip, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coat, roll coat, curtain coat, knife coat, and the like.

  After the resin layer 24 is formed, heat treatment (pre-bake treatment) for removing the solvent is performed, and then exposure is performed using a photomask. Subsequently, unnecessary portions can be removed by performing development processing. Next, the resin layer 23 is formed by performing heat treatment on the resin layer 24 processed into a desired shape (FIG. 22C). FIG. 22C shows an example in which the island-shaped resin layer 23 is formed.

  The shape of the resin layer 23 is not limited to one island shape, and may be a plurality of island shapes, a shape having openings, or the like. Further, an uneven shape may be formed on the surface of the resin layer 23 using an exposure technique using a halftone mask or a gray tone mask, a multiple exposure technique, or the like.

  By forming a mask such as a resist mask or a hard mask on the resin layer 24 or the resin layer 23 and performing etching, the resin layer 23 having a desired shape can be formed. This method is particularly suitable when a non-photosensitive material is used.

  The pre-baking process will be described. The pre-baking temperature can be appropriately determined according to the material used. For example, it can be performed at 50 ° C. or higher and 180 ° C. or lower, 80 ° C. or higher and 150 ° C. or lower, or 90 ° C. or higher and 120 ° C. or lower. Alternatively, the heat treatment may also serve as a prebake treatment, and the solvent contained in the resin layer 24 may be removed by the heat treatment.

  The heat treatment will be described. The heat treatment can be performed, for example, while flowing a gas containing one or more of oxygen, nitrogen, and a rare gas (such as argon) inside the chamber of the heating device. Alternatively, the heat treatment can be performed using a chamber of a heating device, a hot plate, or the like in an air atmosphere.

  When heating is performed in an air atmosphere or a gas containing oxygen, the resin layer 23 may be colored due to oxidation, and the permeability to visible light may be reduced. Therefore, it is preferable to perform heating while flowing nitrogen gas. Thereby, the transparency with respect to the visible light of the resin layer 23 can be improved.

  By the heat treatment, degassing components (for example, hydrogen, water, etc.) in the resin layer 23 can be reduced. In particular, it is preferable to heat at a temperature equal to or higher than the manufacturing temperature of each layer formed on the resin layer 23. Thereby, degassing from the resin layer 23 in the transistor manufacturing process can be significantly suppressed.

  For example, in the case where the transistor manufacturing temperature is up to 350 ° C., the film to be the resin layer 23 is preferably heated at 350 ° C. or higher and 450 ° C. or lower, more preferably 400 ° C. or lower, and even more preferably 375 ° C. or lower. Thereby, degassing from the resin layer 23 in the transistor manufacturing process can be significantly suppressed.

  By extending the treatment time, even in the case where the heating temperature is relatively low, it may be possible to achieve the same peelability as in the case where the heating temperature is higher. Therefore, when the heating temperature cannot be increased due to the configuration of the heating device, it is preferable to increase the treatment time.

  The heat treatment time is preferably, for example, 5 minutes to 24 hours, more preferably 30 minutes to 12 hours, and further preferably 1 hour to 6 hours. Note that the heat treatment time is not limited thereto. For example, when the heat treatment is performed using an RTA (Rapid Thermal Annealing) method, it may be less than 5 minutes.

  As the heating device, various devices such as an electric furnace and a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element can be used. For example, an RTA apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. Since the processing time can be shortened by using an RTA apparatus, it is preferable for mass production. Further, the heat treatment may be performed using an in-line heating apparatus.

  Note that the thickness of the resin layer 23 may change from the thickness of the resin layer 24 due to the heat treatment. For example, when the solvent contained in the resin layer 24 is removed or the curing progresses and the density increases, the volume decreases and the resin layer 23 may become thinner than the resin layer 24 in some cases.

<Formation of insulating layer>
Next, the insulating layer 31 is formed over the resin layer 23 (FIG. 22D). The insulating layer 31 is formed to cover the end portion of the resin layer 23. On the metal oxide layer 20, there is a portion where the resin layer 23 is not provided. Therefore, the insulating layer 31 can be formed in contact with the metal oxide layer 20.

  The insulating layer 31 is formed below the heat resistance temperature of the resin layer 23. It is preferable to form at a temperature lower than the temperature of the heat treatment.

  The insulating layer 31 can be used as a barrier layer that prevents impurities contained in the resin layer 23 from diffusing into transistors and display elements to be formed later. For example, the insulating layer 31 preferably prevents diffusion of moisture or the like contained in the resin layer 23 into the transistor or the display element when the resin layer 23 is heated. Therefore, the insulating layer 31 preferably has a high barrier property.

  As the insulating layer 31, for example, an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, or an aluminum nitride film can be used. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, or the like may be used. Two or more of the above insulating films may be stacked. In particular, it is preferable to form a silicon nitride film on the resin layer 23 and form a silicon oxide film on the silicon nitride film.

  The inorganic insulating film is denser and has a higher barrier property as the deposition temperature is higher, and thus it is preferable to form the inorganic insulating film at a high temperature.

  The substrate temperature during the formation of the insulating layer 31 is preferably room temperature (25 ° C.) or higher and 350 ° C. or lower, more preferably 100 ° C. or higher and 300 ° C. or lower.

<Formation of transistor>
Next, the transistor 40 is formed over the insulating layer 31 (FIG. 22E).

  Note that FIG. 22 illustrates a TGTC (Top Gate Top Contact) transistor as a structure of a transistor included in the memory device. Further, in this manufacturing example, the structure of the transistor is not limited to the TGTC type, and may be applied to another transistor structure.

  Here, a case where a TGTC transistor having a dual gate structure including the metal oxide 44a, the metal oxide 44b, and the metal oxide 44c is manufactured as the transistor 40 is shown. The metal oxide 44 b can function as a semiconductor layer of the transistor 40. The metal oxide 44b functions as an oxide semiconductor.

  In this embodiment, an oxide semiconductor is used as a semiconductor of the transistor. It is preferable to use a semiconductor material with a wider band gap and lower carrier density than silicon because current in an off state of the transistor can be reduced.

  The transistor 40 includes the conductive layer 43a as one of the source electrode and the drain electrode and the conductive layer 43b as the other of the source electrode and the drain electrode. The transistor 40 has a conductive layer 41 as a back gate electrode and a conductive layer 45 as a front gate electrode.

  Further, the transistor 40 includes an insulating layer 33 as a gate insulating film on the back gate electrode side and an insulating layer 34 as a gate insulating film on the front gate electrode side.

  The transistor 40 is formed below the heat resistant temperature of the resin layer 23. The transistor 40 is preferably formed at a temperature lower than the temperature for heat treatment.

  Next, an insulating layer 36 that covers the transistor 40 is formed (FIG. 22E).

  For the method for forming the transistor 40 and the insulating layer 36, the transistor structure 1 of Embodiment 6 is referred to.

<Formation of opening>
Next, an opening is formed in the insulating layer 36, and a conductive layer 46 is formed in the opening (FIG. 23A). The opening can be formed by selectively etching the insulating layer 36. Note that the opening is formed in each of the conductive layer 43a and the conductive layer 43b of the transistor 40.

  The conductive layer 46 can be typically formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.

  After the conductive layer 46 is formed, planarization is performed by etching, CMP (Chemical Mechanical Polishing), or the like. By this treatment, an unnecessary conductive film formed on the insulating layer 36 or the like when the conductive layer 46 is formed can be removed.

  As a material of the conductive layer 46, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used as a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  Note that the structure of the conductive layer 46 is preferably a two-layer structure or a stacked structure of three or more layers, as in the back gate electrode described in Structural Example 1 of the transistor in Embodiment 6. For example, tantalum nitride or the like is formed as a first layer (conductive layer 46a) as a conductor having a barrier property against hydrogen, and tungsten is stacked as a second layer (conductive layer 46b) as a highly conductive material. do it.

<Formation of wiring layer>
Next, a wiring layer is formed. Specifically, an insulating layer 37 is formed over the insulating layer 36, and a conductive layer 47 functioning as a wiring is formed over the insulating layer 36 and the conductive layer 46 (FIG. 23B). Note that the material and the formation method of the insulating layer 37 are referred to for the material and the formation method of the insulating layer 36. Similarly, the material and the formation method of the conductive layer 47 refer to the material and the formation method of the conductive layer 46. In FIG. 23B, the conductive layer 47 has a two-layer structure like the conductive layer 46, but the reference numerals of the first and second layers of the conductive layer 47 are omitted.

  The insulating layer 37 has an opening, and a conductive layer 47 is formed in the opening. The insulating layer 37 has a plurality of openings, and some of the openings are formed to electrically connect the conductive layer 46 and the conductive layer 47. The remaining openings are formed to route the conductive layer 47 as wiring.

<Formation of capacitive element>
Next, a layer including the capacitor 70 is formed over the insulating layer 37 and the conductive layer 47 (FIG. 23C).

  Note that in this manufacturing example, a trench structure is illustrated as the structure of the capacitor included in the memory device; however, the capacitor may have a planar structure.

  The capacitor element 70 includes an insulating layer 38a, an insulating layer 38b, an insulating layer 38c, a conductive layer 48a, and a conductive layer 48b. In particular, the conductive layer 48 a functions as a first electrode of the capacitor 70, and the conductive layer 48 b functions as a second electrode of the capacitor 70.

  The insulating layer 38 a is formed on the insulating layer 37 and the conductive layer 47. As the insulating layer 38a, it is preferable to use a film having a barrier property so that hydrogen and impurities do not diffuse. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, and oxynitride Aluminum, aluminum nitride, or the like may be used.

  In FIG. 23C, the insulating layer 38a has an opening in a region overlapping with the conductive layer 46 and the conductive layer 47 which are electrically connected to the conductive layer 43b. The opening can be formed by selectively etching the insulating layer 36 after the insulating layer 38a is formed.

  A conductive layer 48a is formed in the opening of the insulating layer 38a. As the conductive layer 48a, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, low resistance metal material such as copper or aluminum may be used.

  The conductive layer 48a is formed by sputtering, CVD (including thermal CVD, MOCVD, PECVD, etc.), MBE, ALD, PLD, etc. after the opening of the insulating layer 38a is formed. Can do. After the formation of the conductive layer 48a, the conductive film formed on the conductive layer 48a other than the opening of the insulating layer 38a is removed by an etching process, a CMP method, or the like.

  Thereafter, the insulating layer 38b is formed over the insulating layer 38a and the conductive layer 48a. Examples of the insulating layer 38b include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, and hafnium nitride. May be used, and a stacked layer or a single layer is provided.

  For example, when the insulating layer 38b has a stacked structure, the stacked structure is preferably formed using a high dielectric constant material such as aluminum oxide and a material having high dielectric strength such as silicon oxynitride. With this configuration, the capacitor 70 has a high dielectric constant insulator, so that a sufficient capacitance can be secured. Furthermore, since the insulating layer 38b includes an insulator having a large dielectric strength, the dielectric strength is improved, and electrostatic breakdown of the capacitor 70 can be suppressed.

  After the formation of the insulating layer 38b, a conductive layer 48b is formed on the insulating layer 38b. The conductive layer 48b is formed so as to fill the opening of the insulating layer 38a. The conductive layer 48b can be formed using the same material and method as the conductive layer 48a.

  After the formation of the conductive layer 48b, the other conductive film is removed by an etching process or the like while leaving a region overlapping with the conductive layer 48a through the insulating layer 38b.

  The insulating layer 38c is formed over the insulating layer 38b and the conductive layer 48b. As the insulating layer 38c, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and a stacked layer or a single layer is used. In addition, it is preferable to use silicon nitride (SiNOH) containing oxygen and hydrogen because the amount of hydrogen desorbed by heating can be increased. Alternatively, silicon oxide with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen, nitrous oxide, or the like can be used.

  The insulating layer 38c can be formed using, for example, a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, or a PLD method.

  After the insulating layer 38c is formed, planarization is performed by etching or CMP until the conductive layer 48b is exposed.

<Formation of wiring layer and passivation film>
Next, a wiring layer and a passivation film are formed. Specifically, an insulating layer 39a and a conductive layer 49 functioning as a wiring are formed over the layer including the capacitor 70, and the insulating layer 39a and the conductive layer 49 are functioning as a passivation film. The layer 39b is formed (FIG. 24A).

  The insulating layer 39a has an opening in a region overlapping with the conductive layer 48b. Note that the material and formation method of the insulating layer 37 are referred to for the material and formation method of the insulating layer 39a. The material of the insulating layer 39a may be the same material as the insulating layer 38c.

  The conductive layer 49 is formed in the opening of the insulating layer 39a. For the material and formation method of the conductive layer 49, the material and formation method of the conductive layer 47 are taken into consideration.

  The insulating layer 39b is formed on the insulating layer 39a and the conductive layer 49. The insulating layer 39b is preferably a film having a barrier property so that hydrogen and impurities do not diffuse. Examples of the material of the insulating layer 39b include silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, aluminum oxynitride, Aluminum oxide or the like can be used. In addition, the insulating layer 39b may be a stacked layer formed by selecting a plurality of materials from the above-described materials instead of a single layer.

<Formation of protective layer>
Next, the protective layer 75 is formed over the insulating layer 39b (FIG. 24B). As the protective layer 75, an adhesive layer and a substrate may be used.

  As the adhesive layer, various curable adhesives such as an ultraviolet curable photocurable adhesive, a reactive curable adhesive, a thermosetting adhesive, and an anaerobic adhesive can be used. Further, an adhesive sheet or the like may be used.

  Examples of the substrate include polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES). ) Resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) Resin, ABS resin, cellulose nanofiber, etc. can be used. For the substrate, various materials such as glass, quartz, resin, metal, alloy, and semiconductor having a thickness enough to be flexible may be used.

<Laser irradiation>
Next, the laser beam 55 is irradiated (FIG. 25). For example, in FIG. 25, the laser beam 55 is a linear laser beam scanned from the left side to the right side, and its major axis is perpendicular to the scanning direction and the incident direction (from top to bottom). In the laser device, the stacked body is arranged so that the substrate 14 is on the upper side. The laminated body is irradiated with laser light 55 from above the laminated body (substrate 14).

  The laser beam 55 is preferably applied to the interface between the metal oxide layer 20 and the resin layer 23 or the vicinity thereof through the substrate 14. Further, the laser beam 55 may be irradiated into the metal oxide layer 20 or may be irradiated into the resin layer 23.

  The metal oxide layer 20 absorbs the laser light 55. The resin layer 23 may absorb the laser light 55.

  By the irradiation with the laser beam 55, the adhesion or adhesiveness between the metal oxide layer 20 and the resin layer 23 is lowered. The resin layer 23 may be weakened by the irradiation with the laser beam 55.

  As the laser light 55, light having a wavelength that is at least partially transmitted through the substrate 14 and absorbed by the metal oxide layer 20 is selected and used. The laser light 55 is preferably light in the wavelength region from visible light to ultraviolet light. For example, light having a wavelength of 180 nm to 450 nm, preferably 200 nm to 400 nm, more preferably light having a wavelength of 250 nm to 350 nm can be used. In particular, it is preferable to use an excimer laser having a wavelength of 308 nm because the productivity is excellent. Alternatively, a solid-state UV laser (also referred to as a semiconductor UV laser) such as a UV laser having a wavelength of 355 nm, which is the third harmonic of the Nd: YAG laser, may be used. Since a solid-state laser does not use gas, the running cost can be reduced to about 1/3 compared to an excimer laser, which is preferable. Further, a pulse laser such as a picosecond laser may be used.

  When a linear laser beam is used as the laser beam 55, the laser beam 55 is scanned by relatively moving the substrate 14 and the light source, and the laser beam 55 is irradiated over a region to be peeled off.

<Formation of separation starting point>
Next, a separation starting point is formed in the resin layer 23 (FIGS. 26A, 26B, and 26C). For example, a sharp tool 65 such as a blade is inserted inside the end of the resin layer 23 from the protective layer 75 side, and a cut 64 is made in a frame shape.

  Alternatively, the resin layer 23 may be irradiated with a laser beam in a frame shape.

  As described above, a plurality of storage devices can be formed using one resin layer 23 by multi-cavity. For example, a plurality of storage devices are arranged inside the cut 64 in FIG. Thus, a plurality of storage devices can be separated from the substrate 14 at once.

  Alternatively, a plurality of resin layers 23 may be used to create the resin layers 23 for each storage device. FIG. 7C shows an example in which four resin layers 23 are formed on the substrate 14. Each memory device can be separated from the substrate 14 at different timings by making a cut 64 in a frame shape in each of the four resin layers 23.

  In the method for manufacturing the memory device in this embodiment, a portion in contact with the resin layer 23 and a portion in contact with the insulating layer 31 are provided over the metal oxide layer 20. The adhesiveness (adhesiveness) between the metal oxide layer 20 and the insulating layer 31 is higher than the adhesiveness (adhesiveness) between the metal oxide layer 20 and the resin layer 23. Therefore, it can suppress that the resin layer 23 peels from the metal oxide layer 20 unintentionally. Then, by forming the separation starting point, the metal oxide layer 20 and the resin layer 23 can be separated at a desired timing. Therefore, the separation timing can be controlled and the force required for the separation is small. Accordingly, the yield of the separation process and the manufacturing process of the memory device can be increased.

<Separation process and bonding process>
Next, the metal oxide layer 20 and the resin layer 23 are separated (FIG. 27).

  Then, the substrate 29 is bonded to the exposed resin layer 23 using the adhesive layer 28 (FIG. 28A).

  The substrate 29 can function as a support substrate of the storage device. In particular, the substrate 29 corresponds to the substrate 101, the substrate 101a, the substrate 101b, and the substrate 101c described in Embodiment 1 (the reference numeral of the substrate 101 is illustrated in FIG. 28A). It is preferable to use a film for the substrate 29, and it is particularly preferable to use a resin film. As a result, the storage device can be reduced in weight and thickness. In addition, a storage device using a film substrate is less likely to be damaged than when glass or metal is used. In addition, the flexibility of the storage device can be increased.

  The same material as the adhesive layer that can be used for the protective layer 75 can be applied to the adhesive layer 28. The substrate 29 is formed using the same material as the substrate that can be used for the protective layer 75 or the same material as the substrate that can be used for the substrate 101, the substrate 101a, the substrate 101b, and the substrate 101c described in Embodiment 1. Can do.

  The stack provided above the adhesive layer 28 corresponds to the semiconductor device 102, the semiconductor device 102a, the semiconductor device 102b, and the semiconductor device 102c described in Embodiment 1 (in FIG. The symbols are shown.)

  In particular, when a material capable of removing the protective layer 75 is used as the protective layer 75, a step of removing the protective layer 75 is performed after the adhesive layer 28 and the substrate 29 are bonded together (FIG. 28A). (FIG. 28B). By this step, the terminal portion of the memory device can be easily exposed. In this case, as the protective layer 75, for example, an adhesive having solubility even after curing can be used. When an adhesive that is soluble even after curing is used as the protective layer 75, the protective layer 75 is formed with the adhesive in the step of FIG. 26A, and the adhesive is allowed to be used in the step of FIG. The protective layer 75 may be removed using a material that dissolves.

  In the method for manufacturing the memory device described in this embodiment, the metal oxide layer 20 and the resin layer 23 are stacked and irradiated with light. Thereby, the adhesiveness or adhesiveness of the metal oxide layer 20 and the resin layer 23 can be reduced. Therefore, the substrate 14 and the resin layer 23 can be easily separated. Accordingly, the transistor 40, the capacitor 70, and the like manufactured over the substrate 14 can be separated from the substrate 14 and transferred to the substrate 29.

  In particular, as described above, by forming a plurality of semiconductor devices on one substrate 14, a storage device (device 100a, device 100b, device 100c, device 110a, device 111a, device 111b, device 112a, device 112b) is formed. A plurality of devices 113a, devices 113b, devices 120a, and devices 121a) can be manufactured. This storage device is bent and folded like the structure shown in Embodiment Mode 1, so that the storage capacity is shorter and less expensive than a structure in which semiconductor devices (memory cell array, etc.) are stacked on the same substrate. A large storage device can be manufactured.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 6)
In this embodiment, the structure of the OS transistor used in the above embodiment is described.

<Metal oxide>
First, the metal oxide used for the OS transistor will be described.

  The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one kind or plural kinds selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Next, with reference to FIGS. 29A, 29B, and 29C, a preferable range of the atomic ratio of indium, element M, and zinc included in the metal oxide according to the present invention will be described. . Note that the atomic ratio of oxygen is not described in FIGS. 29A, 29B, and 29C. The terms of the atomic ratio of indium, element M, and zinc of the metal oxide are [In], [M], and [Zn].

  In FIG. 29A, FIG. 29B, and FIG. 29C, a broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line that satisfies (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1-α): line that has an atomic ratio of 2 [In]: [M] : [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): number of atoms of 4 A line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1−α): 5.

  The one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), and [In]: [M]: [Zn] = 2: A line with an atomic ratio of 1: β, [In]: [M]: [Zn] = 1: 1: a line with an atomic ratio of β, [In]: [M]: [Zn] = 1 2: Line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 1 : 4: represents a line having an atomic ratio of β.

  In addition, the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 shown in FIGS. 29 (A), 29 (B), and 29 (C), and the neighborhood values thereof. Metal oxides tend to have a spinel crystal structure.

  In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is a value close to [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure tend to coexist. Further, when the atomic ratio is a value close to [In]: [M]: [Zn] = 1: 0: 0, two phases of a bixbite type crystal structure and a layered crystal structure tend to coexist. When a plurality of phases coexist in a metal oxide, a crystal grain boundary may be formed between different crystal structures.

  A region A illustrated in FIG. 29A illustrates an example of a preferable range of the atomic ratio of indium, the element M, and zinc included in the metal oxide.

  The metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the indium content. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.

  On the other hand, when the content of indium and zinc in the metal oxide is lowered, the carrier mobility is lowered. Therefore, when the atomic ratio is [In]: [M]: [Zn] = 0: 1: 0 and its vicinity (for example, the region C shown in FIG. 29C), the insulating property becomes high. .

  Therefore, the metal oxide of one embodiment of the present invention preferably has an atomic ratio shown in Region A in FIG. 29A, which has a high carrier mobility and a layered structure with few crystal grain boundaries. .

  In particular, in the region B illustrated in FIG. 29B, among the regions A, an excellent metal oxide that easily becomes a CAAC (c-axis aligned crystalline) -OS and has high carrier mobility can be obtained.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

  Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

  CAAC-OS is a metal oxide with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of the metal oxide may be reduced due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide including the CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.

  Note that the region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and the vicinity thereof. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. The region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7, and Includes neighborhood values.

  Note that the properties of metal oxides are not uniquely determined by the atomic ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide film is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. Further, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.

<Transistor structure 1>
30A and 30B are a top view and a cross-sectional view of the transistor 200a. FIG. 30A is a top view, the left diagram in FIG. 30B is a dashed-dotted line X1-X2 shown in FIG. 30A, and the right diagram in FIG. 30B is a dashed-dotted line Y1-Y2. FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

  FIG. 30B illustrates an example in which the transistor 200a is provided over the insulator 214 and the insulator 216.

  The transistor 200a includes a conductor 205 (a conductor 205a and a conductor 205b) and a conductor 260 that function as gate electrodes, an insulator 220, an insulator 222, an insulator 224, and an insulator 250 that function as gate insulators. A metal oxide 230 (metal oxide 230a, metal oxide 230b, and metal oxide 230c), a conductor 240a functioning as one of a source or a drain, and a conductor 240b functioning as the other of a source or a drain And an insulator 241 that protects the conductor 260 and an insulator 280 having excess oxygen (containing oxygen in excess of the stoichiometric composition).

  In the transistor 200a, the conductor 260 may be referred to as a top gate and the conductor 205 may be referred to as a bottom gate. Alternatively, the conductor 260 may be referred to as a first gate and the conductor 205 may be referred to as a second gate.

  The metal oxide 230 includes a metal oxide 230a, a metal oxide 230b on the metal oxide 230a, and a metal oxide 230c on the metal oxide 230b. When the transistor 200a is turned on, a current flows mainly through the metal oxide 230b. The metal oxide 230b functions as a channel formation region. On the other hand, in the metal oxide 230a and the metal oxide 230c, current may flow near the interface with the metal oxide 230b (which may be a mixed region), but the other regions function as insulators. There is a case.

  In the metal oxide 230a and the metal oxide 230c, the energy level at the lower end of the conduction band is closer to the vacuum level than the metal oxide 230b, and the conduction between the metal oxide 230b and the metal oxide 230a is representative. The difference from the energy level at the lower end of the band is preferably from 0.15 eV to 2 eV, more preferably from 0.5 eV to 1 eV. In addition, the difference between the energy level at the lower end of the conduction band between the metal oxide 230b and the metal oxide 230c is preferably 0.15 eV or more and 2 eV or less, and more preferably 0.5 eV or more and 1 eV or less. preferable. That is, the electron affinity of the metal oxide 230b only needs to be higher than the electron affinity of each of the metal oxide 230a and the metal oxide 230c, and specifically, the electron affinity of each of the metal oxide 230a and the metal oxide 230b. And the difference between the electron affinity of each of the metal oxide 230c and the metal oxide 230b is 0.15 eV or more and 2 eV or less, preferably 0.15 eV or more and 2 eV or less, preferably 0.5 eV or more and 1 eV or less. Is preferably 0.5 eV or more and 1 eV or less.

  In the metal oxide 230b, the energy gap is preferably 2 eV or more, and more preferably 2.5 eV or more and 3.0 eV or less. In the metal oxide 230a and the metal oxide 230c, the energy gap is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 2.7 eV or more and 3.5 eV or less. The energy gap between the metal oxide 230a and the metal oxide 230c is preferably larger than the energy gap between the metal oxide 230b. For example, the energy gap between the metal oxide 230a and the metal oxide 230c is greater than or equal to 0.15 eV, or greater than or equal to 0.5 eV, or greater than or equal to 1.0 eV, and less than or equal to 2 eV, or It is preferably 1 eV or less.

  The thicknesses of the metal oxide 230a, the metal oxide 230b, and the metal oxide 230c are 3 nm to 200 nm, preferably 3 nm to 100 nm, and more preferably 3 nm to 60 nm.

  It is preferable to reduce the carrier density of the metal oxide because a negative shift of the threshold voltage of the transistor or an off-state current of the transistor can be reduced. Factors that affect the carrier density of the metal oxide include oxygen deficiency (Vo) in the metal oxide or impurities in the metal oxide. When the number of oxygen vacancies in the metal oxide increases, the density of defect states increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the number of impurities in the metal oxide increases, the density of defect states increases due to the impurities. Therefore, the carrier density of the metal oxide can be controlled by controlling the defect level density in the metal oxide.

The carrier density of the metal oxide 230a and the metal oxide 230c is, for example, less than 8 × 10 ¹⁵ cm ⁻³ , preferably less than 1 × 10 ¹¹ cm ⁻³ , more preferably less than 1 × 10 ¹⁰ cm ⁻³ , What is necessary is just to set it as 1 * 10 < ^-9 > cm < ^-3 > or more.

  On the other hand, for the purpose of improving the on-state current of the transistor or the field effect mobility of the transistor, it is preferable to increase the carrier density of the metal oxide. In order to increase the carrier density of the metal oxide, it is preferable to slightly increase the impurity concentration of the metal oxide or to further reduce the band gap of the metal oxide.

  The carrier density of the metal oxide 230b is preferably higher than that of the metal oxide 230a and the metal oxide 230c.

  It is preferable to reduce the defect state density of the mixed layer formed at the interface between the metal oxide 230a and the metal oxide 230b or at the interface between the metal oxide 230b and the metal oxide 230c. Specifically, the metal oxide 230a and the metal oxide 230b, and the metal oxide 230b and the metal oxide 230c have a common element (main component) in addition to oxygen, so that the density of defect states is low. A layer can be formed. For example, in the case where the metal oxide 230b is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the metal oxide 230a and the metal oxide 230c.

  At this time, the main path of carriers is the metal oxide 230b. Since the defect level density at the interface between the metal oxide 230a and the metal oxide 230b and the interface between the metal oxide 230b and the metal oxide 230c can be reduced, the influence on the carrier conduction due to interface scattering is small. High on-current can be obtained.

  The metal oxide 230a and the metal oxide 230c are preferably formed using a material whose conductivity is sufficiently lower than that of the metal oxide 230b. For example, as the metal oxide 230a and the metal oxide 230c, a metal oxide having an atomic ratio indicated by a region C in which the insulating property is increased in FIG. Note that a region C illustrated in FIG. 29C has [In]: [M]: [Zn] = 0: 1: 0 and its neighboring values, [In]: [M]: [Zn] = 1. 3: 2 and its neighboring values, and [In]: [M]: [Zn] = 1: 3: 4, and the atomic ratios that are neighboring values are shown.

  In particular, when a metal oxide having an atomic ratio represented by the region A illustrated in FIG. 29A is used for the metal oxide 230b, [M] / [In] is included in the metal oxide 230a and the metal oxide 230c. It is preferable to use a metal oxide that is 1 or more, preferably 2 or more. Further, as the metal oxide 230c, it is preferable to use a metal oxide having [M] / ([Zn] + [In]) of 1 or more, which can obtain sufficiently high insulation.

  The conductor 205 includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above-described elements (a titanium nitride film or a nitride film). Molybdenum film, tungsten nitride film) and the like. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  For example, tantalum nitride or the like may be used as the conductor 205a as a conductor having a barrier property against hydrogen, and tungsten having high conductivity may be stacked as the conductor 205b. By using the combination, diffusion of hydrogen to the metal oxide 230 can be suppressed while maintaining conductivity as a wiring. Note that FIG. 30B illustrates a two-layer structure of the conductor 205a and the conductor 205b; however, the present invention is not limited to this structure, and a single layer or a stacked structure including three or more layers may be used.

  The insulator 220 and the insulator 224 are preferably insulators containing oxygen such as a silicon oxide film or a silicon oxynitride film. In particular, an insulator containing excess oxygen is preferably used as the insulator 224. By providing such an insulator containing excess oxygen in contact with the metal oxide included in the transistor 200a, oxygen vacancies in the metal oxide can be compensated. Note that the insulator 222 and the insulator 224 are not necessarily formed using the same material.

The insulator 222 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, An insulator containing Sr) TiO ₃ (BST) or the like is preferably used in a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  Note that the insulator 222 may have a stacked structure of two or more layers. In that case, the present invention is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

  Further, the threshold voltage can be controlled by appropriately adjusting the film thicknesses of the insulator 220, the insulator 222, and the insulator 224. Alternatively, a transistor with low leakage current when not conducting can be provided. It is preferable to reduce the thickness of each of the insulator 220, the insulator 222, and the insulator 224 because threshold voltage control by the conductor 205 is facilitated. For example, the thickness of each of the insulator 220, the insulator 222, and the insulator 224 may be 50 nm or less, more preferably 30 nm or less, more preferably 10 nm or less, and still more preferably 5 nm or less.

  The insulator 250 can be formed using the same material as the insulator 222.

  As the insulator 250, an oxide insulator containing more oxygen than that in the stoichiometric composition is preferably used as in the insulator 224. By providing such an insulator containing excess oxygen in contact with the metal oxide 230, oxygen vacancies in the metal oxide 230 can be reduced.

  The insulator 250 can be formed using an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, and silicon nitride. In the case of using such a material, it functions as a layer that prevents release of oxygen from the metal oxide 230 and entry of impurities such as hydrogen from the outside.

  For the conductors 240a and 240b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used. Further, although a single layer structure is shown in the figure, a stacked structure of two or more layers may be used.

  For example, a titanium film and an aluminum film may be stacked. Also, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film A two-layer structure in which copper films are stacked may be used.

  In addition, a titanium film or a titanium nitride film and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

  The conductor 260 having a function as a gate electrode is, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metal, or an alloy combining the above-described metals. Can be used. Further, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

  For example, the conductor 260 may have a two-layer structure in which a titanium film is stacked over aluminum. Alternatively, a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, or a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film may be employed. .

  Further, there are a titanium film and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon. Alternatively, an alloy film or a nitride film in which one or more metals selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.

  The conductor 260 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal can be used.

  By using a conductive material having a high work function as the conductor 260, the threshold voltage of the transistor 200a can be increased and the cut-off current can be reduced. The work function of the conductor 260 is preferably 4.8 eV or more, more preferably 5.0 eV or more, more preferably 5.2 eV or more, more preferably 5.4 eV or more, more preferably 5.6 eV or more. May be used. Examples of the conductive material having a high work function include molybdenum, molybdenum oxide, Pt, Pt silicide, Ni silicide, indium tin oxide, and nitrogen-added In—Ga—Zn oxide.

  An insulator 241 is provided so as to cover the conductor 260. The insulator 241 can be formed using an insulating film having a barrier property against oxygen or hydrogen, such as aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, or silicon nitride. When formed using such a material, the conductor 260 can be prevented from being oxidized by the heat treatment step. Note that the insulator 241 can be omitted by using a material that is difficult to oxidize for the conductor 260.

  An insulator 280 is provided above the transistor 200a. The insulator 280 preferably contains excess oxygen. In particular, by providing an insulator containing excess oxygen in an interlayer film or the like in the vicinity of the transistor 200a, reliability can be improved by reducing oxygen vacancies in the transistor 200a.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having excess oxygen. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  In addition, the insulator 280 that covers the transistor 200a may function as a planarization film that covers the uneven shape below the transistor 200a.

<Transistor structure 2>
FIG. 31A and FIG. 31B are a top view and a cross-sectional view of the transistor 200b. 31A is a top view, the left diagram in FIG. 31B is a one-dot chain line X1-X2 shown in FIG. 31A, and the right diagram in FIG. 31B is a one-dot chain line Y1-Y2. FIG. Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

  A transistor 200b in FIG. 31 is obtained by etching the central portions of the metal oxides 230a and 230b in the transistor 200a in FIG. 30 (see the left diagram in FIG. 31B).

  The transistor 200a in FIG. 30 has a channel formed in the metal oxide 230b, whereas the transistor 200b in FIG. 31 has a channel formed in the metal oxide 230c. The metal oxide 230c has a lower electron mobility and a wider band gap than the metal oxide 230b. Therefore, the transistor 200b has a smaller on-current than the transistor 200a, but has a smaller off-current. The transistor 200b is suitable for a transistor in which off-state current is more important than on-state current.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 7)
In this embodiment, a metal oxide that can be used for the transistor described in Embodiment 6 will be described. In particular, details of the CAC (cloud-aligned composite) will be described below.

  The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers and the insulating function is a carrier. This function prevents electrons from flowing. By performing the conductive function and the insulating function in a complementary manner, a switching function (function to turn on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

  Further, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving capability, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite. Therefore, the CAC-OS may be referred to as a cloud-aligned composite-OS.

  The CAC-OS is one structure of a material in which elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.

  Note that the metal oxide preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1} or _in X2 _Zn Y2 _{O Z2,} is a configuration in which uniformly distributed in the film (hereinafter, click Also called Udo-like.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is the main component region is a composite metal oxide having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

  The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystal) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

  On the other hand, CAC-OS relates to a material structure of a metal oxide. CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

  Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, and In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component region, in some cases clear boundary can not be observed.

  In place of gallium, aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are selected. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

  The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .

  The CAC-OS is characterized in that no clear peak is observed when it is measured using a θ / 2θ scan by the out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

  In addition, in the CAC-OS, an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in a CAC-OS in an In—Ga—Zn oxide, a region in which GaO _X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2} or _{InO X1,} is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.

On the other hand, areas such as _{GaO X3} is the main _component, as compared to the In _{X2 Zn} Y2 _{O Z2} or _{InO X1} is the main component area, it is highly regions insulating. That is, a region containing GaO _X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _{X3 and the} like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner, resulting in high An on-current (I _on ) and high field effect mobility (μ) can be realized.

  In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimal for various semiconductor devices including a storage device.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 8)
In this embodiment, examples of electronic devices to which the disclosed storage device can be applied will be described.

<Notebook personal computer>
FIG. 32A illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The storage device of one embodiment of the present invention can be provided in a laptop personal computer.

<Smart watch>
FIG. 32B illustrates a smart watch which is a kind of wearable terminal, which includes a housing 5901, a display portion 5902, operation buttons 5903, operation elements 5904, a band 5905, and the like. The storage device of one embodiment of the present invention can be included in a smart watch. Further, a display device to which a function as a position input device is added may be used for the display portion 5902. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. Further, the operation button 5903 can be provided with any one of a power switch for starting a smart watch, a button for operating a smart watch application, a volume adjustment button, a switch for turning on or off the display unit 5902, and the like. In the smart watch illustrated in FIG. 32B, the number of operation buttons 5903 is two, but the number of operation buttons included in the smart watch is not limited thereto. The operation element 5904 functions as a crown for adjusting the time of the smart watch. Further, the operation element 5904 may be used as an input interface for operating the smartwatch application in addition to the time adjustment. Note that the smart watch illustrated in FIG. 32B includes the operation element 5904; however, the present invention is not limited to this and may have a structure without the operation element 5904.

<Video camera>
FIG. 32C illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The storage device of one embodiment of the present invention can be provided in a video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there. The video on the display portion 5803 may be switched in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.

<Mobile phone>
FIG. 32D illustrates a mobile phone having an information terminal function, which includes a housing 5501, a display portion 5502, a microphone 5503, a speaker 5504, and operation buttons 5505. The storage device of one embodiment of the present invention can be provided in a mobile phone. Further, a display device to which a function as a position input device is added may be used for the display portion 5502. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. Further, the operation button 5505 can be provided with any one of a power switch for starting a mobile phone, a button for operating a mobile phone application, a volume adjustment button, a switch for turning on or off the display portion 5502, and the like.

  In the cellular phone illustrated in FIG. 32D, the number of operation buttons 5505 is two, but the number of operation buttons included in the cellular phone is not limited thereto. Although not illustrated, the cellular phone illustrated in FIG. 32D may have a structure including a flashlight or a light-emitting device for illumination.

<Television device>
FIG. 32E is a perspective view illustrating a television device. A television device includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation). Number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, or infrared) Etc. The storage device of one embodiment of the present invention can be included in a television device. The television device can incorporate the display portion 9001 into a large screen, for example, a display portion 9001 with 50 inches or more, or 100 inches or more.

<Moving object>
The display device described above can also be applied to the vicinity of the driver's seat of an automobile that is a moving body.

  For example, FIG. 32 (F) is a diagram illustrating the periphery of a windshield in the interior of an automobile. FIG. 32F illustrates a display panel 5704 attached to a pillar in addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard.

  The display panels 5701 to 5703 can provide various other information such as navigation information, a speedometer and a tachometer, a travel distance, an oil supply amount, a gear state, and an air conditioner setting. In addition, the display items, layout, and the like displayed on the display panel can be changed as appropriate according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

  The display panel 5704 can complement the field of view (dead angle) obstructed by the pillar by projecting an image from the imaging means provided on the vehicle body. That is, by displaying an image from the imaging means provided outside the automobile, the blind spot can be compensated and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity. The display panel 5704 can also be used as a lighting device.

  The storage device according to one embodiment of the present invention can be included in a moving object. The storage device according to one embodiment of the present invention includes, for example, a frame memory that temporarily stores image data used when displaying images on the display panel 5701 to the display panel 5704, and a program that drives a system included in a mobile object. It can be used for a storage device for storing.

  Although not illustrated, the electronic devices illustrated in FIGS. 32A to 32C may have a configuration including a microphone and a speaker. With this configuration, for example, a voice input function can be added to the electronic device described above.

  Although not illustrated, the electronic devices illustrated in FIGS. 32A, 32B, and 32D to 32F may have a camera.

  Although not illustrated, the electronic devices illustrated in FIGS. 32A to 32F include sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, Liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, infrared, etc. May be. In particular, the mobile phone shown in FIG. 32D is provided with a detection device having a sensor that detects a tilt, such as a gyroscope or an acceleration sensor, so that the orientation of the mobile phone (which direction the mobile phone is relative to the vertical direction) The screen display of the display portion 5502 can be automatically switched according to the orientation of the mobile phone.

  Although not illustrated, the electronic device illustrated in FIGS. 32A to 32F may include a device that acquires biological information such as a fingerprint, a vein, an iris, or a voiceprint. By applying this configuration, an electronic device having a biometric authentication function can be realized.

  Alternatively, a flexible substrate may be used as the display portion of the electronic device illustrated in FIGS. Specifically, the display portion may have a structure in which a transistor, a capacitor element, a display element, and the like are provided over a flexible base material. By applying this configuration, it is possible to realize not only a housing having a flat surface as in the electronic devices illustrated in FIGS. 32A to 32F but also a housing having a curved surface. Can do.

(Additional notes regarding the description of this specification etc.)
The description of each component in the above embodiment will be added below.

<Supplementary Note on One Aspect of the Invention described in Embodiment>
The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined with each other as appropriate.

  Note that the content described in one embodiment (may be a part of content) is different from the other content described in the embodiment (may be a part of content) and one or more other implementations. Application, combination, replacement, or the like can be performed on at least one of the contents described in the form (may be part of the contents).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, another drawing (may be a part) described in the embodiment, or one or more different drawings. By combining at least one of the drawings (or a part thereof) described in the embodiment, more drawings can be formed.

<Notes on ordinal numbers>
In this specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It can happen. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.

<Additional notes regarding the description explaining the drawings>
Embodiments are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms, and that the forms and details can be variously changed without departing from the spirit and scope thereof. The Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in the structures of the embodiments of the present invention, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

  In addition, in this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between the components appropriately changes depending on the direction in which each component is drawn. Therefore, the phrase indicating the arrangement is not limited to the description described in the specification, and can be appropriately rephrased depending on the situation.

  Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In the drawings, some components may be omitted from the perspective views and the like for the sake of clarity.

  In the drawings, the same element, an element having a similar function, an element of the same material, or an element formed at the same time may be denoted by the same reference numeral, and repeated description thereof may be omitted. .

<Additional notes on paraphrased descriptions>
In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode. In this specification and the like, two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows, and current can flow through a drain, a channel formation region, and a source.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  In addition, when a transistor described in this specification and the like has two or more gates (this structure is sometimes referred to as a dual gate structure), these gates may be referred to as a first gate and a second gate, , Sometimes called back gate. In particular, the phrase “front gate” can be rephrased as simply the phrase “gate”. Also, the phrase “back gate” can be rephrased simply as the phrase “gate”. Note that a bottom gate refers to a terminal formed before a channel formation region when a transistor is manufactured, and a “top gate” is formed after a channel formation region when a transistor is manufactured. Terminal.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer”. Alternatively, in some cases or depending on circumstances, it is possible to replace with another term without using a phrase such as “film” or “layer”. For example, the term “conductive layer” or “conductive film” may be changed to the term “conductor” in some cases. Alternatively, for example, the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.

  Note that in this specification and the like, terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term “wiring” to the term “signal line”. In addition, for example, the term “wiring” may be changed to a term such as “power supply line”. The reverse is also true, and there are cases where terms such as “signal line” and “power supply line” can be changed to the term “wiring”. A term such as “power line” may be changed to a term such as “signal line”. The reverse is also true, and a term such as “signal line” may be changed to a term such as “power line”. In addition, the term “potential” applied to the wiring may be changed to a term “signal” or the like depending on circumstances or circumstances. The reverse is also true, and a term such as “signal” may be changed to a term “potential”.

<Notes on the definition of words>
Below, the definition of the phrase referred in the said embodiment is demonstrated.

<< About impurities in semiconductor >>
The semiconductor impurity means, for example, a component other than the main component constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When the impurities are included, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

<< About the switch >>
In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

<< About connection >>
In this specification and the like, when X and Y are described as being connected, when X and Y are electrically connected, and when X and Y are functionally connected And the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the figure or text, and includes things other than the connection relation shown in the figure or text.

  X, Y, and the like used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do.

  Note that when X and Y are explicitly described as being electrically connected, when X and Y are electrically connected (that is, another element between X and Y). Or when X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And a case where X and Y are directly connected (that is, a case where another element or another circuit is not connected between X and Y). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

  Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

  For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source of the transistor ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

  In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

<< About parallel and vertical >>
In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

MA memory cell array MA1 memory cell array MA2 memory cell array MA3 memory cell array BLD bit line driver circuit WLD word line driver circuit WLD1 word line driver circuit WLD2 word line driver circuit WLD3 word line driver circuit CLC control logic circuit OPC output circuit MC [1,1] Memory cell MC [m, 1] Memory cell MC [1, n] Memory cell MC [m, n] Memory cell RDATA Data signal WDATA Data signal CE Chip enable signal WE Write enable signal RE Read enable signal ADDR Address signal BL Wiring BLB Wiring WL Wiring BGL Wiring BGL1 Wiring BGL2 Wiring BGL3 Wiring BGL4 Wiring CL Wiring RBL Wiring WBL Wiring RWL Wiring WWL Wiring SL Wiring BR Wiring VDD wiring GND wiring C1 capacitive element C2 capacitive element C3 capacitive element C4 capacitive element C5 capacitive element M1 transistor M2 transistor M3 transistor M4 transistor M5 transistor M6 transistor M7 transistor M8 transistor M9 transistor M10 transistor MS1 transistor MS2 transistor MS3 transistor MS4 transistor 14 substrate 20 metal oxide layer 23 resin layer 24 resin layer 29 substrate 31 insulating layer 33 insulating layer 34 insulating layer 36 insulating layer 37 insulating layer 38a insulating layer 38b insulating layer 38c insulating layer 39a insulating layer 39b insulating layer 40 transistor 41 conductive layer 43a conductive Layer 43b Conductive layer 44a Metal oxide 44b Metal oxide 44c Metal oxide 45 Conductive layer 46 Conductive layer 46a Conductive layer 46b Conductive layer 47 Conductive layer 8a Conductive layer 48b Conductive layer 49 Conductive layer 55 Laser light 64 Cut 65 Device 70 Capacitance element 75 Protective layer 100 Storage device 100A Storage device 100B Storage device 100a Device 100b Device 100c Device 101 Substrate 101a Substrate 101b Substrate 101c Substrate 102 Semiconductor device 102a Semiconductor Device 102b semiconductor device 102c semiconductor device 103a wiring 103b wiring 103r region 104 terminal 104a terminal 104b terminal 104c terminal 105 wiring 105a wiring 105b wiring 105c wiring 106 bonding layer 106a bonding layer 106a [1] bonding layer 106a [2] bonding layer 106b bonding layer 106b [1] bonding layer 106b [2] bonding layer 107 substrate 107a substrate 107b substrate 108 core 108s bottom surface 109 region 110 storage device 110A storage device 110B Storage device 110a Device 111 Storage device 111A Storage device 111B Storage device 111a Device 111b Device 112 Storage device 112a Device 112b Device 113 Storage device 113a Device 113b Device 114 Storage device 114a Device 114b Device 120 Storage device 120A Storage device 120a Device 121 Storage device 121a Device 121b side 121t side 121r region 200a transistor 200b transistor 205 conductor 205a conductor 205b conductor 214 insulator 216 insulator 220 insulator 222 insulator 224 insulator 230 metal oxide 230a metal oxide 230b metal oxide 230c metal oxide Object 240a Conductor 240b Conductor 241 Insulator 250 Insulator 260 Conductor 280 Insulator 301 Semiconductor device 302 Semiconductor device 302a Memory Ruarei section 302b driver circuit portion 302c FPC
302d circuit board 302e slot 302f terminal 302g wiring 302h fastener 302k holder 303 semiconductor device 303a circuit 303b circuit 303c circuit 304 semiconductor device 304a circuit 304b circuit 304c circuit 305 semiconductor device 305a memory cell array unit 305b memory cell array unit 305c memory cell array unit 305d FPC
305p Drive circuit portion 410 Memory cell 420 Memory cell 430 Memory cell 440 Memory cell 450 Memory cell 460 Memory cell 470 Memory cell 480 Memory cell 490 Memory cell 5401 Display unit 5403 Keyboard 5404 Pointing device 5501 Case 5502 Display unit 5503 Microphone 5504 Speaker 5505 Operation button 5701 Display panel 5702 Display panel 5703 Display panel 5704 Display panel 5801 First housing 5802 Second housing 5803 Display unit 5804 Operation key 5805 Lens 5806 Connection unit 5901 Housing 5902 Display unit 5903 Operation button 5904 Operator 5905 Band 9000 Case 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor

Claims (17)

A first substrate, a first semiconductor device, a second semiconductor device, a first terminal, and a first region;
The first semiconductor device is provided on the first substrate,
The first terminal is provided on the first substrate;
The first region has a region where the first semiconductor device overlaps with the second semiconductor device;
The first terminal is electrically connected to the first semiconductor device;
The memory device, wherein the first substrate has a bent structure. In claim 1,
With wiring and bonding layers,
The second semiconductor device is provided on the first substrate;
The wiring is provided on the first substrate;
The wiring is provided at least in a bent region of the bent structure,
The second semiconductor device is electrically connected to the first semiconductor device via the wiring;
The memory device, wherein the bonding layer is provided between the first semiconductor device and the second semiconductor device. In claim 1,
A second substrate, a second terminal, a bonding layer, a first wiring, and a second wiring;
The first wiring is provided at least in a bent region of the first substrate;
The first wiring has a function of electrically connecting the first semiconductor device and the second terminal;
The second semiconductor device is provided on the second substrate,
The second terminal is provided on the second substrate;
The second substrate has a region overlapping with the first substrate through the bonding layer,
The second substrate has a structure that is bent along the first substrate,
The second wiring is provided at least in a bent region of the second substrate;
The memory device, wherein the second wiring has a function of electrically connecting the second semiconductor device and the second terminal. In claim 3,
A second region and a third region;
The second region has a region including the first terminal,
The third region has a region including the second terminal,
Each of the second area and the third area is a different area from each other. In claim 4,
The first region has a region overlapping the second region,
The storage device according to claim 1, wherein the first area has an area overlapping with the third area. A first substrate, a second substrate, a first semiconductor device, a second semiconductor device, a first terminal, a second terminal, a bonding layer, and first to third regions;
The first semiconductor device is provided on the first substrate,
The first terminal is provided on the first substrate;
The first semiconductor device is electrically connected to the first terminal;
The second semiconductor device is provided on the second substrate,
The second terminal is provided on the second substrate;
The second semiconductor device is electrically connected to the second terminal;
The first region has a region including the first terminal,
The second region has a region including the second terminal,
The third region has a region where the first semiconductor device overlaps with the second semiconductor device via the bonding layer;
Each of the first to third areas is a different area from each other. In any one of Claims 1 thru | or 6,
At least one of the first semiconductor device and the second semiconductor device has a memory cell,
The memory cell includes a first transistor, a second transistor, and a capacitor.
A first terminal of the first transistor is electrically connected to a first terminal of the capacitor;
The memory device, wherein the gate of the second transistor is electrically connected to the first terminal of the capacitor. In claim 7,
The memory device, wherein the first transistor includes a metal oxide in a channel formation region. In any one of Claims 1 thru | or 8,
At least one of the first semiconductor device and the second semiconductor device has a function of performing a multi-value data write operation and / or a read operation, respectively. A substrate, a semiconductor device, a terminal, and a bonding layer;
The semiconductor device is provided above the substrate,
The terminal is provided above one end of the substrate,
The terminal portion is electrically connected to the semiconductor device;
The bonding layer is provided below the substrate,
The storage device is characterized in that the substrate is wound with the other end of the substrate as an inner side. In claim 10,
Has a wick,
The storage device according to claim 1, wherein the core is provided as an axis of the wound substrate. In claim 10 or claim 11,
The semiconductor device has a memory cell,
The memory cell includes a first transistor, a second transistor, and a capacitor.
A first terminal of the first transistor is electrically connected to a first terminal of the capacitor;
The memory device, wherein the gate of the second transistor is electrically connected to the first terminal of the capacitor. In claim 12,
The memory device, wherein the first transistor includes a metal oxide in a channel formation region. In any one of Claims 10 thru | or 13,
Each of the semiconductor devices has a function of performing a multi-value data write operation or a read operation.   A circuit board on which the memory device according to any one of claims 1 to 14 is mounted. In claim 15,
Having a drive circuit,
The circuit board having a function of writing data to the storage device and a function of reading data from the storage device.   An electronic device comprising the circuit board according to claim 15 or 16, and a housing.