JP2018098291A - Semiconductor device, and method of operating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of operating a semiconductor device that enables a semiconductor device to hold data for a long period of time.SOLUTION: There is provided the method of operating a semiconductor device which comprises: a first transistor including a first gate, an insulator on the first gate, first and second conductors on the insulator, a first oxide on the insulator and the first and second conductors, and a second gate on the first oxide; a second transistor including a third gate, a second oxide on the third gate, and a fourth gate on the second oxide; and a capacitative element, the first conductor, the third gate, and one electrode of the capacitative element being electrically connected to one another. A first positive potential is applied to the first gate to inject first electric charges to the insulator, and a ground potential is applied to the first gate to hold the first electric charges in the insulator. A second positive potential lower than the first positive potential is applied to the second gate, and a first negative potential is applied to the second conductor, the ground potential is applied to the first and second gates and the second conductor to hold the second electric charge in the capacitative element.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device. One embodiment of the present invention relates to a method for operating a semiconductor device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  Note that in this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A memory device, a display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

  In recent years, transistors using an oxide semiconductor have attracted attention. Patent Document 1 discloses an example in which a transistor having an oxide semiconductor in a channel formation region (hereinafter referred to as an “oxide semiconductor transistor”) is used in a DRAM (Dynamic Random Access Memory). An oxide semiconductor transistor has a very small leakage current in an off state (also referred to as off-state current); thus, a DRAM with a long refresh period and low power consumption can be manufactured.

  Patent Document 2 discloses a non-volatile memory using an oxide semiconductor transistor. Unlike a flash memory, the non-volatile memory has no limit on the number of rewritable times and can easily operate at high speed. It can be realized and has low power consumption.

  Patent Document 2 discloses an example in which a second gate is provided in an oxide semiconductor transistor, the threshold value of the transistor is controlled, and the off-state current of the transistor is reduced.

  Patent Documents 2 and 3 disclose configuration examples of circuits for driving the above-described second gate.

JP2013-168631A JP 2012-069932 A JP 2012-146965 A

  An object of one embodiment of the present invention is to provide a semiconductor device that can hold data for a long period of time and a method for operating the semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device that can reduce power consumption and a method for operating the semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics and a method for operating the semiconductor device. An object of one embodiment of the present invention is to provide a semiconductor device having favorable reliability and a method for operating the semiconductor device. An object of one embodiment of the present invention is to provide a memory device that can hold data for a long period of time and a method for operating the memory device. An object of one embodiment of the present invention is to provide a memory device that can reduce power consumption and a method for operating the memory device. An object of one embodiment of the present invention is to provide a novel semiconductor device and a method for operating the semiconductor device.

  Note that the description of a plurality of tasks does not disturb each other's existence. Note that one embodiment of the present invention does not have to solve all of these problems. Problems other than those listed will be apparent from descriptions of the specification, drawings, claims, and the like, and these problems may also be a problem of one embodiment of the present invention.

  One embodiment of the present invention includes a first gate, an insulator over the first gate, first and second conductors over the insulator, and an insulator over the first and second conductors. A first transistor having a first oxide; a second gate on the first oxide; a third gate; a second oxide on the third gate; A semiconductor device including a second transistor having a fourth gate over an oxide, and a capacitor, the first conductor, a third gate, and one electrode of the capacitor Is electrically connected, and in the region where the second gate and the first conductor overlap, the length of the first gate in the channel width direction is the length of the first conductor in the channel width direction. This is a shorter semiconductor device.

  According to one embodiment of the present invention, in a region where the second gate and the second conductor overlap with each other, the length in the channel width direction of the first gate is in the channel width direction of the second conductor. The semiconductor device may be shorter than the length.

  Another embodiment of the present invention is a semiconductor device in which the threshold voltage of the first transistor may be larger than the threshold voltage of the second transistor.

  Another embodiment of the present invention is a semiconductor in which the insulator includes first to third insulating films, and the first and third insulating films may have an electron affinity smaller than that of the second insulating film. Device.

  Another embodiment of the present invention is a semiconductor device in which the first and third insulating films may have a larger band gap than the second insulating film.

  According to one embodiment of the present invention, the first oxide includes a channel formation region of the first transistor, the second oxide includes a channel formation region of the second transistor, In the semiconductor device, the conductor may have one function of a source and a drain of the first transistor.

  Another embodiment of the present invention is a semiconductor device in which the first conductor and the second gate may not be electrically connected.

  Another embodiment of the present invention is a semiconductor device in which a first conductor and a second gate may be electrically connected.

  Another embodiment of the present invention is a semiconductor device in which the first and second oxides may contain a metal oxide.

  Another embodiment of the present invention is a first gate, an insulator over the first gate, first and second conductors over the insulator, insulator, first and second conductors. A first transistor having a first oxide on the first gate and a second gate on the first oxide; a third gate; a second oxide on the third gate; A second transistor having a fourth gate over the oxide of 2 and a capacitor, and the first conductor, the third gate, and one electrode of the capacitor are In the operating method of the electrically connected semiconductor device, the first transistor applies a first positive potential to the first gate, injects a first charge into the insulator, A ground potential is applied to the gate to hold the first charge in the insulator, a second positive potential smaller than the first positive potential is applied to the second gate, A semiconductor device operating method in which a first negative potential is applied to a conductor, a ground potential is applied to the first and second gates and the second conductor, and a second charge is held in the capacitor. is there.

  Another embodiment of the present invention is a method for operating a semiconductor device, in which a threshold voltage of a first transistor may be higher than a threshold voltage of a second transistor.

  Another embodiment of the present invention is a semiconductor in which the insulator includes first to third insulating films, and the first and third insulating films may have an electron affinity smaller than that of the second insulating film. It is an operation method of the apparatus.

  Another embodiment of the present invention is a method for operating a semiconductor device, in which the first and third insulating films may have a band gap larger than that of the second insulating film.

  According to one embodiment of the present invention, the first oxide includes a channel formation region of the first transistor, the second oxide includes a channel formation region of the second transistor, In the semiconductor device operation method, the conductor may have one function of a source and a drain of the first transistor.

  Another embodiment of the present invention is a method for operating a semiconductor device in which the first conductor and the second gate do not have to be electrically connected to each other.

  Another embodiment of the present invention is a method for operating a semiconductor device in which the first conductor and the second gate may be electrically connected.

  Another embodiment of the present invention is a method for operating a semiconductor device, in which the first and second oxides may include a metal oxide.

  According to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time and a method for operating the semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can reduce power consumption and a method for operating the semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics and a method for operating the semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device having favorable reliability and a method for operating the semiconductor device can be provided. According to one embodiment of the present invention, a memory device that can hold data for a long time and a method for operating the memory device can be provided. According to one embodiment of the present invention, a memory device that can reduce power consumption and a method for operating the memory device can be provided. According to one embodiment of the present invention, a novel semiconductor device and a method for operating the semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

6A and 6B are a circuit diagram illustrating an example of a semiconductor device according to one embodiment of the present invention and a graph illustrating electrical characteristics of a transistor. 6A and 6B are a circuit diagram illustrating an example of a semiconductor device according to one embodiment of the present invention and a graph illustrating electrical characteristics of a transistor. FIG. 10 is a circuit diagram illustrating an operation example of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an operation example of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an operation example of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an operation example of a semiconductor device according to one embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an example of a circuit configuration of a nonvolatile memory according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an example of a circuit configuration of a DRAM according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an example of a circuit configuration of a register according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating an example of a circuit configuration of a display device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views of a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views of a transistor according to one embodiment of the present invention. 3A and 3B each illustrate an energy band structure of a metal oxide. 4A and 4B are a schematic diagram of a transistor and a band diagram of a charge trap layer according to one embodiment of the present invention. 6A and 6B illustrate changes in Vg-Id characteristics and Vth during electron injection into a charge trap layer of a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 10A to 10D are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating a structure example of a CPU according to one embodiment of the present invention. FIG. 14 is a perspective view illustrating an example of an electronic device according to one embodiment of the present invention. FIG. 10 is a perspective view illustrating an example of using an RF tag according to one embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular.

  Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

  In the present specification and the like, ordinal numbers such as “first” and “second” are used for avoiding confusion between components, and are not limited numerically.

  Note that the voltage often indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential.

  Note that the functions of the “source” and “drain” of the transistor may be interchanged when a transistor with a different polarity is used or when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

  Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width refers to, for example, a source and a drain in a region where a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a region where a channel is formed Is the length of the part facing each other. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The transistors described in this specification and the like are enhancement-type (normally-off-type) field effect transistors unless otherwise specified. The transistors described in this specification and the like are n-channel transistors unless otherwise specified. Therefore, the Vth (threshold voltage) is assumed to be larger than 0 V unless otherwise specified. Note that in this specification and the like, Vth is a Vg-Id curve plotted with the gate potential Vg [V] of a transistor as the horizontal axis and the square root Id ^1/2 [A] of the drain current as the vertical axis. It is defined as the gate potential at the intersection of the tangent at the point where the slope is maximum and the straight line of Id ^1/2 = 0 (ie, Vg axis).

  In this specification and the like, a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as the composition, and a silicon nitride oxide film has a nitrogen content as compared to oxygen as a composition. Refers to membranes with a lot of

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, in the case where a metal oxide is used for a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. In the case of describing as an OS FET, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  In this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

  Moreover, in this specification etc., it may describe as CAAC (C-Axis Aligned Crystal) and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material structure.

  In this specification and the like, a CAC-OS or a CAC-metal oxide has a conductive function in part of a material and an insulating function in part of the material, and the whole material is a semiconductor. It has the function of. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is This is a function of preventing electrons (or holes) from flowing. By performing the conductive function and the insulating function in a complementary manner, a switching function (a function for turning on / off) can be given to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, the functions of both can be maximized by separating the functions.

  In this specification and the like, a CAC-OS or a CAC-metal oxide includes a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

  In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in a material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. There is.

  Moreover, CAC-OS or CAC-metal oxide is comprised by the component which has a different band gap. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.

  That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material or a metal matrix composite material.

  In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are directly connected and X and Y are electrically connected. And the case where X and Y are functionally connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. The switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

  In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And when X and Y are directly connected (that is, when X and Y are connected without interposing another element or another circuit), It is disclosed in this specification and the like. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

  In addition, even in the case where independent components are illustrated as being electrically connected to each other in the drawing, one component may have the functions of a plurality of components. is there. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

(Embodiment 1)
In this embodiment, structural examples and operation examples of a semiconductor device according to one embodiment of the present invention will be described.

<Configuration example of semiconductor device>
Hereinafter, a structural example of the semiconductor device according to one embodiment of the present invention will be described in detail with reference to FIGS.

  FIG. 1A is an example of a circuit diagram of a semiconductor device 10 according to one embodiment of the present invention. The semiconductor device 10 includes a first transistor M0, a second transistor M1, and a capacitor C1.

  The first transistor M0 has two gates with an oxide having a channel formation region interposed therebetween. In the transistor M0, one of the two gates functions as a top gate and the other functions as a bottom gate. Hereinafter, the top gate is referred to as a first gate of the transistor M0, and the bottom gate is referred to as a second gate of the transistor M0.

  The second gate of the transistor M0 has a function of controlling Vth of the transistor M0. For example, in the case where the transistor M0 is an n-channel transistor, by applying a potential lower than the source potential to the second gate of the transistor M0, the Vth of the transistor M0 is positively shifted, so that the first gate-source is connected. The off-state current when the voltage (Vgs) is 0 V can be reduced (more normally off can be achieved). On the other hand, by applying a potential higher than the source potential to the second gate of the transistor M0, the Vth of the transistor M0 can be shifted negatively, and an on-current can be allowed to flow when Vgs = 0V (more normally on). be able to.). Note that in this specification, “normally off” refers to a state where the drain current (Id) flowing when the potential (Vg) of the first gate of the transistor is 0 V is smaller than 0 A, "Denotes a state where the drain current (Id) flowing when the potential (Vg) of the first gate of the transistor is 0 V is larger than 0A.

  The second transistor M1 has two gates with an oxide having a channel formation region interposed therebetween. In the transistor M1, one of the two gates functions as a top gate and the other functions as a bottom gate. Hereinafter, the top gate is referred to as a first gate of the transistor M1, and the bottom gate is referred to as a second gate of the transistor M1.

  One of the source and the drain of the transistor M1, the second gate of the transistor M0, and one electrode of the capacitor C1 are electrically connected at a node N1. The first gate of the transistor M1 is electrically connected to the input terminal VG, the other of the source and the drain is electrically connected to the input terminal VD, and the second gate is electrically connected to the input terminal VBG. . Each input terminal can apply different potentials to different connection destinations at different timings. With such a structure, Vth and on current (or off current) of the transistor M1 can be freely controlled.

  For example, by applying a negative potential from the input terminal VBG to the second gate of the transistor M1, the Vg-Id characteristic of the transistor M1 can be positively shifted. Here, Vg is the potential of the first gate of the transistor M1, and Id is the drain current of the transistor M1. In the case where the transistor M1 is an n-channel transistor, when an electric potential of 0 V is applied from the input terminal VGS to the first gate of the transistor M1 in this state, the off-state current of the transistor M1 (here, Vg = Id of the Vg−Id characteristic) In other words, the drain current at 0 V may be reduced as compared with the case where no potential is applied from the input terminal VBG.

  As described above, the semiconductor device 10 according to one embodiment of the present invention includes the second gate of the transistor M0, one of the source and the drain of the transistor M1, and one electrode of the capacitor C1 at the node N1. It has an electrically connected configuration. Note that a constant low potential is applied to the other electrode of the capacitor C1. The low potential may be a ground potential.

  Of the above-described elements included in the semiconductor device 10, the transistor M1, the capacitor C1, and the node N1 form a circuit 100 (see FIG. 1A). Therefore, it can be said that the semiconductor device 10 has a configuration in which the circuit 100 controls the potential applied to the second gate of the transistor M0.

  As described above, the node N1 included in the circuit 100 is electrically connected to one electrode of the capacitor C1. Therefore, a charge (electron) having a magnitude corresponding to the product of the negative potential written in the node N1 and the capacitance value of the capacitor C1 can be held in the capacitor C1.

  For example, it is assumed that the transistor M1 is turned on by applying a predetermined potential from the input terminal VG to the first gate of the transistor M1, and “a certain negative potential” is written to the node N1 from the input terminal VD. When the input terminal VG is fixed at 0 V, the transistor M1 is turned off, and the negative potential written in the node N1 is always applied to the second gate of the transistor M0. As a result, when the transistor M0 is an n-channel transistor, the circuit 100 can continue to maintain the Vg-Id characteristic of the transistor M0 in a positively shifted state (normally off) for an extremely long time. Here, Vg is the potential of the first gate of the transistor M0, and Id is the drain current of the transistor M0.

  Note that the transistor M1 includes an insulator between the oxide having the channel formation region and the second gate. In one embodiment of the present invention, the insulator can have a function of retaining (also referred to as trapping or trapping) charges (electrons) supplied by a potential applied from the input terminal VBG. Therefore, hereinafter, the insulator is referred to as a charge trap layer (details of the mechanism of charge injection / holding into the charge trap layer will be described later). Note that in FIG. 1A, the charge trap layer included in the transistor M1 is indicated by a broken line. For example, by holding charge (electrons) in the charge trap layer, the Vg-Id characteristic of the transistor M1 can be shifted more positively than before charge holding. Here, Vg is the potential of the first gate of the transistor M1, and Id is the drain current of the transistor M1. FIGS. 1B and 1C schematically show this. FIG. 1B is a schematic diagram of the Vg-Id characteristics of the transistor M1 before holding the charge in the charge trap layer (the potential of the second gate is 0 V), and FIG. 1C shows the charge in the charge trap layer. FIG. 10 is a schematic diagram of Vg-Id characteristics of the transistor M1 after holding (the potential of the second gate is 0 V). Accordingly, the off-state current of the transistor M1 can be further reduced as compared with the case where the transistor M1 does not have a charge trap layer, and thus the negative potential written in the node N1 can be held for a longer period. Become. The required plus shift amount varies depending on the application of the semiconductor device 10. In the semiconductor device 10 according to one embodiment of the present invention, the amount of plus shift can be arbitrarily adjusted by changing the magnitude of charges (electrons) held in the charge trap layer of the transistor M1.

  Taking advantage of the operational characteristics of the circuit 100 described above, the semiconductor device 10 according to one embodiment of the present invention can be used, for example, as part of a memory device (details will be described later). For example, when the transistor M0 is used as a transistor included in a DRAM, the semiconductor device 10 includes the circuit 100, thereby realizing a DRAM capable of holding data for an extremely long period of time as compared with the case where the circuit 100 is not included. be able to.

The transistors M0 and M1 are preferably transistors with low off-state current. For example, the off-state current of the transistor M0 and the transistor M1 is preferably 10 ⁻¹⁸ A / μm or less, more preferably 10 ⁻²¹ A / μm or less, and even more preferably 10 ⁻²⁴ A / μm or less. In order to realize such an extremely small off-state current, a metal oxide is preferably used as an oxide having a channel formation region of a transistor.

Note that in this specification, unless otherwise specified, off-state current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state refers to a state where Vgs is lower than Vth for an n-channel transistor and a state where Vgs is higher than Vth for a p-channel transistor unless otherwise specified. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when Vgs is lower than Vth. The off-state current of the transistor may depend on Vgs. Accordingly, the off current of the transistor is less than or equal to ^{10 -21} A, and may say that the value of Vgs of the off current of the transistor is less than ^{10 -21} A are present. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

  In this specification, the off-state current of the transistor may be represented by a current value flowing around the channel width. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a current / length dimension (for example, A / μm).

  In addition, the off-state current of the transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device including the transistor is guaranteed or a temperature at which the semiconductor device including the transistor is used (for example, any one temperature of 5 ° C. to 35 ° C.). May represent off-state current.

  The off-state current of the transistor may depend on the voltage (Vds) between the drain and the source. In this specification, unless otherwise specified, the off-state current has an absolute value of Vds of 0.1 V, 0.8 V, 1.0 V, 1.2 V, 1.8 V, 2.5 V, 3.0 V, and 3. It may represent off-current at 3V, 10V, 12V, 16V, or 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented.

  As described above, in the semiconductor device 10 of one embodiment of the present invention, the Vth of the transistor M0 is controlled by the circuit 100, whereby the off-state current of the transistor M0 (the first gate potential (Vg) is 0 V). The current drain current (Id) is aimed to be kept small. Therefore, the off-state current of the transistor M1 included in the circuit 100 is preferably smaller than the off-state current of the transistor M0. That is, the transistor M1 preferably has a normally-off characteristic than the transistor M0.

  Since the transistor M1 has normally-off characteristics than the transistor M0, it is preferable that the oxides having channel formation regions of the two transistors have different structures (details will be described later separately).

  In addition, since the transistor M1 has normally-off characteristics than the transistor M0, it is preferable that the sizes of the two transistors are different from each other. Specifically, when the channel length of the transistor is L and the channel width is W, the transistor M1 preferably has a smaller W / L than the transistor M0.

  The transistor M1 preferably has a higher withstand voltage than the transistor M0 with respect to the potential applied from the second gate. This is because a high potential may be applied from the input terminal VBG to the second gate when many electrons are injected into the charge trap layer of the transistor M1. There is a possibility that a higher potential is applied to the second gate of the transistor M1 than the first gate of the transistor M1, the first gate of the transistor M0, and the second gate of the transistor M0. Therefore, the structure around the second gate is preferably different between the transistor M0 and the transistor M1 (details will be described later separately).

  Note that the charge trap layer may be included not only in the transistor M1 but also in the transistor M0.

  The transistor M0 and the transistor M1 may be formed on the same plane. Alternatively, a layer including the transistor M1 may be stacked over the layer including the transistor M0. Moreover, the structure laminated | stacked on the contrary may be sufficient.

  Note that the semiconductor device according to one embodiment of the present invention is not limited to the semiconductor device 10 described above. For example, the semiconductor device 20 may include the circuit 200 as illustrated in FIG. In the semiconductor device 20 illustrated in FIG. 2A, the circuit (circuit 100) that controls the potential applied to the second gate of the transistor M0 has the same structure as the circuit (circuit 100) included in the semiconductor device 10 illustrated in FIG. ) Is different.

  Specifically, in the circuit 100, one of the source and drain (the node N1 side) of the transistor M1 constituting the circuit 100 and the first gate are not electrically connected, whereas in the circuit 200, One of the source and drain (node N1 side) of the transistor M1 constituting this and the first gate are electrically connected. The first gate is electrically connected to the input terminal VGS. Therefore, the circuit 200 has a configuration in which the same potential is applied to the first gate and one of the source and the drain.

  As described above, the transistor M1 included in the circuit 200 has a configuration in which one of the source and the drain and the first gate are electrically connected. Therefore, the transistor M1 can be operated as a rectifying element like a diode.

  For example, suppose that the potential from the input terminal VGS and the input terminal VBG is fixed to 0V and an “a certain negative potential” is applied from the input terminal VD to the n-channel transistor M1. In this case, when the absolute value of the negative potential is equal to or higher than Vth of the transistor M1, the transistor M1 is turned on, and the negative potential is written to the node N1 through the transistor M1. After that, when the potential of the input terminal VD is fixed to 0 V, the negative potential is applied to one of the source and drain of the transistor M1 (on the node N1 side) and the first gate, and the other of the source and drain (on the input terminal VD side). ) And a potential of 0 V is applied to the second gate. As a result, the transistor M1 is turned off, and carriers (electrons) do not move from the source side to the drain side and from the drain side to the source side of the transistor M1.

  In this way, by applying a potential of an appropriate magnitude to each input terminal (input terminal VGS, input terminal VD, input terminal VBG) electrically connected to each terminal of the transistor M1, in an appropriate order, The transistor M1 can be operated as a rectifying element capable of moving carriers (electrons) only from the input terminal VD side to the node N1 side. Further, due to the rectifying property of the transistor M1, the negative potential once written to the node N1 can be prevented from leaking to the input terminal VD side through the transistor M1.

  Among the elements constituting the semiconductor device 20, those common to the semiconductor device 10 (input terminal VBG, input terminal VD, charge trap layer, capacitor element C 1, node N 1, transistor M 0, etc.) are described in the semiconductor device 10. You can take into account

  The characteristics required for the transistor M0 and the transistor M1 included in the semiconductor device 20 are the same as those of the semiconductor device 10. The transistor M1 includes a charge trap layer, and by holding charge in the charge trap layer, the Vg-Id characteristic can be positively shifted from that before charge holding (FIGS. 2B and 2C). reference.). Here, Vg is the potential of the first gate of the transistor M1, and Id is the drain current of the transistor M1. The Vg-Id characteristic of the transistor M1 after holding the charge in the charge trap layer is preferably larger than the Vg-Id characteristic of the transistor M0 before the negative potential is written to the node N1.

  Note that for example, in the memory device, the register circuit, the display device, the electronic device, and the like (details will be described later) according to one embodiment of the present invention, the semiconductor device 10 or the semiconductor device 20 may be used. Alternatively, the semiconductor device 10 and the semiconductor device 20 may be used in appropriate combination.

<Operation example of semiconductor device>
Hereinafter, operation examples of the semiconductor device according to one embodiment of the present invention will be described in detail with reference to FIGS.

  First, a specific operation example of the semiconductor device 10 illustrated in FIG. 1A will be described with reference to FIGS. Note that the following description is given assuming that the transistors M0 and M1 are n-channel transistors. In the following, an example in which a potential of −5 V is written to the second gate of the transistor M0 is described; however, the voltage value in this embodiment is an example and is not limited thereto. For example, it is appropriately changed depending on the size of transistor or Vth.

  First, as shown in FIG. 3A, in a state where the potentials of the input terminal VG and the input terminal VD are fixed to 0V (that is, the transistor M1 is in an off state), a potential of 40V is applied to the input terminal VBG. Charge (here, electrons that are negative charges) is injected into the charge trap layer of the transistor M1. By injecting electrons into the charge trap layer of the transistor M1, a negative potential is applied to the second gate of the transistor M1, and the Vth of the transistor M1 can be positively shifted. Thereby, the transistor M1 can have more normally-off characteristics than before the electron injection into the charge trap layer described above. The transistor M1 is described below assuming that Vth is greater than 0V and less than 5V in the Vg-Id characteristics after the plus shift.

  Next, as shown in FIG. 3B, the potentials of the input terminal VG, the input terminal VD, and the input terminal VBG are fixed to 0V. As a result, the transistor M1 is turned off, and electrons injected into the charge trap layer of the transistor M1 are also held in the charge trap layer.

  Next, as illustrated in FIG. 3C, by applying a potential of −5 V to the input terminal VD, the transistor M1 is turned on.

  As a result, as shown in FIG. 4A, a potential of −5 V is written to the node N1 from the input terminal VD through the transistor M1, and the writing potential (−5 V) and the capacitance are written to the capacitor C1. Charges (electrons) having a magnitude corresponding to the product of the capacitance value of the element C1 are held.

  Next, as shown in FIG. 4B, the potential of the input terminal VD is fixed to 0V. At this time, a potential of −5 V is applied to one of the source and drain of the transistor M1 (on the node N1 side), and the potential of the other of the source and drain (on the input terminal VD side), the first gate, and the second gate. Becomes a state of 0V. As a result, the transistor M1 is turned off, and charge (electrons) does not move from the source side to the drain side and from the drain side to the source side of the transistor M1. That is, the potential of −5 V written to the node N1 can be maintained. As described above, the operation of writing the potential of −5 V to the second gate of the transistor M0 is completed. When the potential of −5V is written to the second gate of the transistor M0, the Vth of the transistor M0 is positively shifted, and the off-current of the transistor M0 (the drain current when the first gate potential (Vg) is 0V). (Id)) can be reduced. As described above, once the negative potential is written to the node N1 through the transistor M1, the positive shift of Vth of the transistor M0 can be maintained even if the transistor M0 is turned off thereafter. . Therefore, it can be said that the semiconductor device 10 according to one embodiment of the present invention is a semiconductor device with extremely high power consumption.

  Note that by repeating the series of operations in FIGS. 3C, 4A, and 4B, the potential application to the second gate of the transistor M0 can be performed again and again. Further, by setting the potential applied to the input terminal VD to a value other than −5V, the Vth of the transistor M0 can be controlled to a desired value.

  Next, a specific operation example of the semiconductor device 20 illustrated in FIG. 2A will be described with reference to FIGS. Similar to the operation example of the semiconductor device 10 described above, the transistor M0 and the transistor M1 are n-channel transistors and will be described below. Similarly to the operation example of the semiconductor device 10, an example in which a potential of −5 V is written to the second gate of the transistor M0 is described. As described above, the voltage value in the present embodiment is an example and is not limited thereto. For example, it is appropriately changed depending on the size of transistor or Vth.

  First, as shown in FIG. 5A, in a state where the potentials of the input terminal VGS and the input terminal VD are fixed to 0V (that is, the transistor M1 is off), a potential of 40V is applied to the input terminal VBG. Charge (here, electrons that are negative charges) is injected into the charge trap layer of the transistor M1. By injecting electrons into the charge trap layer of the transistor M1, a negative potential is applied to the second gate of the transistor M1, and the Vth of the transistor M1 can be positively shifted. Thereby, the transistor M1 can have more normally-off characteristics than before the electron injection into the charge trap layer described above. The transistor M1 is described below assuming that Vth is greater than 0V and less than 5V in the Vg-Id characteristics after the plus shift.

  Next, as shown in FIG. 5B, the potentials of the input terminal VGS, the input terminal VD, and the input terminal VBG are fixed to 0V. As a result, the transistor M1 is turned off, and electrons injected into the charge trap layer of the transistor M1 are also held in the charge trap layer.

  Next, as illustrated in FIG. 5C, by applying a potential of −5 V to the input terminal VD, the transistor M1 is turned on.

  As a result, as shown in FIG. 6A, a potential of −5 V is written to the node N1 from the input terminal VD through the transistor M1, and the writing potential (−5 V) and the capacitance are written to the capacitor C1. Charges (electrons) having a magnitude corresponding to the product of the capacitance value of the element C1 are held.

  Next, as shown in FIG. 6B, the potential of the input terminal VD is fixed to 0V. At this time, a potential of −5 V is applied to one of the source and drain of the transistor M1 (on the node N1 side) and the first gate, and the other of the source and drain (on the input terminal VD side) is in a 0 V state. As a result, the transistor M1 is turned off, and carriers (electrons) do not move from the source side to the drain side and from the drain side to the source side of the transistor M1. That is, the potential of −5 V written to the node N1 can be maintained. As described above, the operation of writing the potential of −5 V to the second gate of the transistor M0 is completed. When the potential of −5V is written to the second gate of the transistor M0, the Vth of the transistor M0 is positively shifted, and the off-current of the transistor M0 (the drain current when the first gate potential (Vg) is 0V). (Id)) can be reduced. As described above, once the negative potential is written to the node N1 through the transistor M1, the positive shift of Vth of the transistor M0 can be maintained even if the transistor M0 is turned off thereafter. . Therefore, it can be said that the semiconductor device 20 according to one embodiment of the present invention is a semiconductor device with extremely high power consumption.

  Note that by repeating the series of operations in FIGS. 5C, 6A, and 6B, the potential application to the second gate of the transistor M0 can be performed again and again. Further, by setting the potential applied to the input terminal VD to a value other than −5V, the Vth of the transistor M0 can be controlled to a desired value.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 2)
In this embodiment, application examples of the circuit 100 included in the semiconductor device 10 described in Embodiment 1 will be described with reference to FIGS. Note that the circuit 200 included in the semiconductor device 20 may be used instead of the circuit 100.

<Non-volatile memory>
FIG. 7A illustrates a circuit configuration of the memory cell 110 having a function as a memory element.

  A memory cell 110 in FIG. 7A includes a transistor M0 having a first gate and a second gate, a transistor 112, a capacitor 114, a node FN, a wiring BL, a wiring SL, and a wiring WL. , Wiring RL, and wiring BGL.

  In the memory cell 110 in FIG. 7A, the first gate of the transistor M0 is electrically connected to the wiring WL, and the second gate of the transistor M0 is electrically connected to the wiring BGL. One of the drains is electrically connected to the wiring BL, and the other of the source and the drain of the transistor M0 is electrically connected to the node FN.

  In the memory cell 110 in FIG. 7A, the gate of the transistor 112 is electrically connected to the node FN, one of the source and the drain of the transistor 112 is electrically connected to the wiring BL, and the source or the drain of the transistor 112 The other is electrically connected to the wiring SL.

  In the memory cell 110 in FIG. 7A, one electrode of the capacitor 114 is electrically connected to the wiring RL, and the other electrode of the capacitor 114 is electrically connected to the node FN.

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A / μm or less, more preferably 10 ⁻²¹ A / μm or less, and further preferably 10 ⁻²⁴ A / μm or less. As a transistor with low off-state current, a transistor in which a metal oxide is used for a channel formation region can be given.

  As the transistor 112, a transistor with small variation in Vth is preferably used. Specifically, a transistor using single crystal silicon for a channel formation region can be given.

  The memory cell 110 can write, hold, and read information as follows by utilizing the feature that the charge of the node FN can be held.

  First, writing and holding of information will be described. First, a potential is applied to the wiring WL so that the transistor M0 is turned on. Accordingly, the potential of the wiring BL is supplied to the node FN through the transistor M0. That is, predetermined charge is given to the node FN (writing). Note that here, it is assumed that one of two different electric potential levels (hereinafter, referred to as a Low level and a High level) is applied. After that, application of a potential to the wiring WL is stopped, or application of a potential that does not turn on the transistor M0 is performed, so that the transistor M0 is turned off. As a result, the charge given to the node FN is held (held).

  Here, since the off-state current of the transistor M0 is extremely small, the amount of leakage of the charge given to the node FN through the transistor M0 is extremely small. Therefore, the magnitude of the potential applied to the gate of the transistor 112 hardly varies over a long period.

  Next, reading of information will be described. When an appropriate potential (read potential) is applied to the wiring RL in a state where a predetermined potential (constant potential) is applied to the wiring SL, the potential applied to the gate of the transistor 112 changes due to capacitive coupling with the capacitor 114. The drain current value flowing through the transistor 112 varies. As the drain current value fluctuates, the potential applied to the wiring BL also fluctuates. As illustrated in FIG. 7A, when the transistor 112 is a p-channel transistor, the apparent threshold voltage Vth_H in the case where a high-level charge is applied to the node FN is equal to a low-level charge at the node FN. Is smaller than the apparent threshold voltage Vth_L when. Here, the apparent threshold voltage refers to the potential of the wiring RL necessary for turning on the transistor 112. Therefore, by setting the potential of the wiring RL to a potential V0 (Vth_H <V0 <Vth_L) which is a magnitude between Vth_H and Vth_L, the charge given to the node FN is at a high level or at a low level. It can be determined whether there is.

  For example, in the case where a low-level charge is applied to the node FN, in order to turn on the transistor 112, a potential having a magnitude equal to or lower than Vth_L needs to be applied to the gate of the transistor 112. At this time, when the potential of the wiring RL is set to V0, the potential V0 is also applied to the gate of the transistor 112 due to capacitive coupling with the capacitor 114. Since V0 is lower than Vth_L, the transistor 112 is turned on. Can be. When the transistor 112 is turned on, an on-current flows through the transistor 112, and the potential applied to the wiring BL fluctuates before and after the wiring RL applies the potential V0.

  On the other hand, in the case where a high-level charge is applied to the node FN, in order to turn on the transistor 112, a potential having a magnitude equal to or lower than Vth_H needs to be applied to the gate of the transistor 112. At this time, when the potential of the wiring RL is set to V0, the potential V0 is also applied to the gate of the transistor 112 due to capacitive coupling with the capacitor 114. However, since V0 is higher than Vth_H, the transistor 112 is turned off. Will remain. Since the transistor 112 remains off, the potential applied to the wiring BL hardly fluctuates before and after the wiring RL applies the potential V0.

  As described above, by monitoring the variation in potential applied to the wiring BL, it is possible to determine whether the charge held in the node FN is at a high level or a low level (reading).

  Note that although the case where the transistor 112 is a p-channel transistor has been described above, one embodiment of the present invention is not limited thereto, and the transistor 112 may be an n-channel transistor.

  FIG. 7B illustrates a circuit configuration of the memory device 120 including the memory cells 110 arranged in a matrix and the circuit 100 described in Embodiment 1. The storage device 120 has a function as a nonvolatile memory.

  The storage device 120 includes memory cells 110 arranged in a matrix of m rows and n columns. Here, m and n represent natural numbers. The memory cell 110 arranged in the m-th row is electrically connected to the wiring WL [m] and the wiring RL [m], and the memory cell 110 arranged in the n-th column is connected to the wiring BL [n] and the wiring BL [n]. It is electrically connected to the wiring SL.

  A second gate of the transistor M0 included in each memory cell 110 is electrically connected to the circuit 100 through the wiring BGL. In other words, the circuit 100 has a function of supplying a signal for controlling the second gates of the transistors M0 included in all the memory cells 110.

  The circuit 100 controls the second gate of the transistor M0, so that the transistor M0 can take an appropriate Vth. For example, the transistor M0 can be prevented from being normally on. As a result, the off-state current of the transistor M0 can be reduced, and the potential written in the node FN included in the memory cell 110 can be held for a long time.

  With the above structure of the storage device 120, a storage device capable of holding data for a long time even when the power is turned off can be provided. Accordingly, the frequency of the operation (refresh) of periodically rewriting the charge written in the capacitor 114 can be significantly reduced, so that a memory device with extremely low power consumption can be provided.

<DRAM>
FIG. 8A illustrates a circuit configuration of the memory cell 130 having a function as a memory element.

  A memory cell 130 in FIG. 8A includes a transistor M0 having a first gate and a second gate, a capacitor 131, a wiring BL, a wiring WL, a wiring CL, and a wiring BGL.

  In the memory cell 130 in FIG. 8A, the first gate of the transistor M0 is electrically connected to the wiring WL, and the second gate of the transistor M0 is electrically connected to the wiring BGL. One of the drains is electrically connected to the wiring BL, and the other of the source and the drain of the transistor M0 is electrically connected to one electrode of the capacitor 131. Further, the other electrode of the capacitor 131 is electrically connected to the wiring CL.

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A / μm or less, more preferably 10 ⁻²¹ A / μm or less, and further preferably 10 ⁻²⁴ A / μm or less. As a transistor with low off-state current, a transistor in which a metal oxide is used for a channel formation region can be given.

  The wiring WL has a function of supplying a signal for controlling on / off of the transistor M0, and the wiring BL has a function of writing charge into the capacitor 131 through the transistor M0. The charge written in the capacitor 131 can be held by turning off the transistor M0 after writing the charge in the capacitor 131.

  Since the charge written in the capacitor 131 gradually leaks through the transistor M0, an operation (refresh) for periodically rewriting the charge written in the capacitor 131 is necessary. However, since the off-state current of the transistor M0 according to one embodiment of the present invention is extremely low and the amount of charge leaking from the capacitor 131 is small, the frequency of refreshing can be significantly reduced.

  FIG. 8B illustrates a circuit configuration of the memory device 140 including the memory cells 130 arranged in a matrix and the circuit 100 described in Embodiment 1. The storage device 140 has a function as a DRAM.

  The storage device 140 includes memory cells 130 arranged in a matrix of m rows and n columns. Here, m and n represent natural numbers. Further, the memory cell 130 arranged in the m-th row is electrically connected to the wiring WL [m], and the memory cell 130 arranged in the n-th column is electrically connected to the wiring BL [n]. . In addition, the wiring CL is electrically connected to a terminal VC that applies a constant low potential.

  A second gate of the transistor M0 included in each memory cell 130 is electrically connected to the circuit 100 through the wiring BGL. In other words, the circuit 100 has a function of supplying a signal for controlling the second gates of the transistors M0 included in all the memory cells 130.

  The circuit 100 controls the second gate of the transistor M0, so that the transistor M0 can take an appropriate Vth. For example, the transistor M0 can be prevented from being normally on. As a result, the off-state current of the transistor M0 can be reduced, and the potential written in the capacitor 131 included in the memory cell 130 can be held for a long time.

  With the above structure of the storage device 140, it is possible to provide a storage device that can hold data for a long period of time, has a low refresh frequency, and can operate with low power consumption.

<Register>
FIG. 9 shows a configuration example of the 1-bit register circuit 150.

  The register circuit 150 includes a transistor M0 having a first gate and a second gate, a capacitor 154, a node N5, and a flip-flop circuit 153.

  The flip-flop circuit 153 includes an inverter 151 and an inverter 152. The inverter 151 is connected in parallel and in the opposite direction to the inverter 152, and a node to which the output side of the inverter 151 is connected corresponds to the output terminal OUT of the register circuit 150.

  The second gate of the transistor M0 is electrically connected to the circuit 100, the first gate of the transistor M0 is electrically connected to the input terminal Sig1, and one of the source and the drain of the transistor M0 is the input terminal Sig2. The other of the source and the drain of the transistor M0 is electrically connected to the node N5.

  One electrode of the capacitor 154 is electrically connected to the node N5, and a certain low potential is applied to the other electrode of the capacitor 154. As the low potential, a ground potential may be applied. The node N5 is electrically connected to the flip-flop circuit 153.

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A / μm or less, more preferably 10 ⁻²¹ A / μm or less, and further preferably 10 ⁻²⁴ A / μm or less. As a transistor with low off-state current, a transistor in which a metal oxide is used for a channel formation region can be given.

  The register circuit 150 stores and outputs data in accordance with input signals from the input terminal Sig1 and the input terminal Sig2. For example, when a high level potential is input from the input terminal Sig1 and the input terminal Sig2, the transistor M0 is turned on, and a high level potential is input to the node N5. As a result, the low-level potential inverted by the inverter 151 is output from the output terminal OUT of the register circuit 150, and at the same time, the low-level potential data is stored in the flip-flop circuit 153. On the other hand, when a high-level potential is input from the input terminal Sig1 and a low-level potential is input from the input terminal Sig2, the transistor M0 is turned on, and a low-level potential is input to the node N5. As a result, a high level potential inverted by the inverter 151 is output from the output terminal OUT of the register circuit 150, and at the same time, high level potential data is stored in the flip-flop circuit 153.

  The capacitor 154 has a function of holding the potential written to the node N5.

  As described above, the register circuit 150 writes the potential from the input terminal Sig2 to the node N5 via the transistor M0, and then turns off the transistor M0, so that the node 150 can be turned off even if the supply of the power supply voltage is stopped. The potential written in N5 can be held for a long time. This is because the off-state current of the transistor M0 according to one embodiment of the present invention is extremely small. Therefore, by using the register circuit 150, a memory device that can hold data for a long time even when supply of power supply voltage is stopped can be provided.

  In addition, the circuit 100 has a function of supplying a signal for controlling the second gate of the transistor M0. The circuit 100 controls the second gate of the transistor M0, so that the transistor M0 can take an appropriate Vth. For example, the transistor M0 can be prevented from being normally on. As a result, the off-state current of the transistor M0 can be reduced, and the potential written in the node N5 included in the register circuit 150 can be held for a long time.

  Note that although a simple configuration using two inverter circuits is shown as an example of the flip-flop circuit 153 in this embodiment, the configuration using a clocked inverter capable of clock operation is not limited thereto. Alternatively, a combination of a NAND circuit and an inverter can be used as appropriate. For example, a known flip-flop circuit such as an RS type, a JK type, a D type, or a T type can be used as appropriate.

<Display device>
FIG. 10A illustrates a configuration example of the pixel 170 applicable to the display device. The pixel 170 includes a transistor M0 having a first gate and a second gate, a capacitor 171, a display element 172, a node N 7, a wiring GL, a wiring SL, and a wiring BGL.

  The first gate of the transistor M0 is electrically connected to the wiring GL, the second gate of the transistor M0 is electrically connected to the wiring BGL, and one of the source and the drain of the transistor M0 is electrically connected to the wiring SL. The other of the source and the drain of the transistor M0 is electrically connected to the node N7.

  One electrode of the capacitor 171 is electrically connected to the node N7, and a certain low potential is applied to the other electrode of the capacitor 171.

  Note that the capacitor 171 may be provided as necessary, and the capacitor 171 may be omitted when a capacitance necessary for driving the pixel 170 is obtained by a parasitic capacitance associated with an electrode or a wiring. .

The transistor M0 is preferably a transistor with low off-state current. For example, the off-state current of the transistor M0 is preferably 10 ⁻¹⁸ A / μm or less, more preferably 10 ⁻²¹ A / μm or less, and further preferably 10 ⁻²⁴ A / μm or less. As a transistor with low off-state current, a transistor in which a metal oxide is used for a channel formation region can be given.

  One electrode of the display element 172 is electrically connected to the node N7, and a constant low potential is applied to the other electrode of the display element 172. As the low potential, a ground potential may be applied. As the display element 172, a dielectric element that changes optical characteristics when a potential is applied to electrodes at both ends thereof can be used. For example, a liquid crystal element, an electrophoretic element used in electronic paper or the like, a twist ball element, or the like can be used.

  The wiring GL has a function of supplying a signal for controlling on / off of the transistor M0, and the wiring SL has a function of supplying a potential applied to the display element 172 through the transistor M0.

  Since the off-state current of the transistor M0 according to one embodiment of the present invention is extremely small, the potential written to the node N7 can be held for a long time by turning off the transistor M0. While the potential written to the node N7 is held, the display element 172 can maintain the same display state.

  Since the pixel 170 can hold the potential written to the node N7 for a long time, the optical characteristics of the display element 172 can be kept even if the supply of power supply voltage is stopped. For example, even when a liquid crystal element having no memory property such as a TN (Twisted Nematic) type liquid crystal is used, a state in which a potential is always applied to the element can be maintained. It can be eliminated or the frequency thereof can be extremely reduced.

  FIG. 10B illustrates a circuit configuration of a display device 180 including the pixels 170 arranged in a matrix and the circuit 100 described in Embodiment 1.

  The display device 180 includes pixels 170 arranged in a matrix of m rows and n columns. Here, m and n represent natural numbers. The pixel 170 arranged in the mth row is electrically connected to the wiring GL [m], and the pixel 170 arranged in the nth column is electrically connected to the wiring SL [n].

  A second gate of the transistor M0 included in each pixel 170 is electrically connected to the circuit 100 through the wiring BGL. That is, the circuit 100 has a function of supplying a signal for controlling the second gates of the transistors M0 included in all the pixels 170.

  The circuit 100 controls the second gate of the transistor M0, so that the transistor M0 can take an appropriate Vth. For example, the transistor M0 can be prevented from being normally on. As a result, the off-state current of the transistor M0 can be reduced, and the potential written in the node N7 included in the pixel 170 can be held for a long time.

  Further, the circuit 100 not only controls and holds the Vth of the transistor M0 in the pixel 170 connected thereto to an optimal value, but also changes the Vth temporarily to make it a normally-on transistor. You can also. For example, by temporarily changing m × n transistors M0 connected to the circuit 100 to normally-on type transistors at the same time, the potential stored in each pixel (that is, the display image) is changed to one. It is possible to refresh simultaneously with two signals.

  When the display device 180 has the above structure, a display device that can operate with low power consumption with low rewriting frequency can be provided. Further, a display device including a plurality of pixels that can be easily refreshed can be provided. In addition, a display device that can perform display even when power supply is stopped can be realized.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 3)
In this embodiment, an example of a transistor that can be used as the transistor M0 or the transistor M1 described in Embodiment 1 or 2 will be described.

<Configuration Example 1 of Transistor>
FIG. 11 illustrates an example of a transistor 1000 that can be used as the transistor M0 or the transistor M1 according to one embodiment of the present invention. FIG. 11A is a top view of the transistor 1000. FIG. FIG. 11B is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 11A and is a cross-sectional view in the channel length direction of the transistor 1000. FIG. 11C is a cross-sectional view taken along dashed-dotted line A3-A4 in FIG. 1A and is a cross-sectional view in the channel width direction of the transistor 1000. In the top view of FIG. 11A, some elements are omitted for clarity of illustration.

  The transistor 1000 is provided over the substrate 400, and the insulator 401 is provided between the substrate 400 and the transistor 1000. Further, an insulator 410 and an insulator 420 over the insulator 410 are provided over the transistor 1000.

  The transistor 1000 includes a conductor 310_1 and an insulator 301 over the insulator 401, an insulator 302 over the conductor 310_1 and the insulator 301, an insulator 303 over the insulator 302, and an insulator over the insulator 303. 402, the oxide 406a1 over the insulator 402, the oxide 406b1 over the oxide 406a1, the conductors 416a1 and 416a2 having regions in contact with the top surface of the oxide 406b1, and the barrier film 417a1 over the conductor 416a1 A region in contact with the barrier film 417a2 over the conductor 416a2, the side surface of the conductor 416a1, the side surface of the conductor 416a2, the side surface and top surface of the barrier film 417a1, the side surface and top surface of the barrier film 417a2, and the top surface of the oxide 406b1. The oxide 406c1, the insulator 412a1 over the oxide 406c1, and the oxide 4 Having a conductor 404_1 which has a region overlapping with each other through the upper surface of the oxide 406c1 and insulators 412a1 of 6 b 1, an insulator 418a1 on the conductor 404_1, the. The insulator 301 has an opening, and the conductor 310a1 and the conductor 310b1 are disposed in the opening.

  In FIG. 11B and FIG. 11C, the end portion of the insulator 418a1, the end portion of the insulator 412a2, and the end portion of the oxide 406c1 are flush with each other and are over the barrier film 417a1 in the channel length direction. And on the barrier film 417a2 and on the insulator 402 in one of the channel width directions.

  In the transistor 1000, the conductor 404_1 functions as a first gate electrode. The conductor 404_1 can have a stacked structure of the conductor 404a1 and the conductor 404b1. Further, the conductor 404_1 can have a stacked structure of three or more layers. For example, the conductor 404b1 can be prevented from being oxidized by forming the conductor 404a1 having a function of suppressing permeation of oxygen on the lower layer of the conductor 404b1. Alternatively, for example, the conductor 404_1 preferably includes a metal having oxidation resistance. Alternatively, for example, an oxide conductor may be used. Alternatively, for example, a multilayer structure including a conductive oxide may be used. The insulator 412a1 functions as a first gate insulator.

  The conductors 416a1 and 416a2 function as a source electrode or a drain electrode. The conductors 416a1 and 416a2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, the conductor 416a1 and the conductor 416a2 can be prevented from being oxidized by forming a conductor having a function of suppressing permeation of oxygen in the upper layer. Alternatively, the conductor 416a1 and the conductor 416a2 preferably include a metal having oxidation resistance. Alternatively, an oxide conductor or the like may be used.

  The barrier films 417a1 and 417a2 have a function of suppressing permeation of impurities such as hydrogen and water and oxygen. The barrier film 417a1 is on the conductor 416a1 and prevents oxygen from diffusing into the conductor 416a1. The barrier film 417a2 is on the conductor 416a2 and prevents diffusion of oxygen into the conductor 416a2.

  In the transistor 1000, the oxide 406b1 and the oxide 406c1 each include a channel formation region. Therefore, the transistor 1000 can control the resistance of the oxide 406b1 and the oxide 406c1 with the potential applied to the conductor 404_1. That is, conduction / non-conduction between the conductor 416a1 and the conductor 416a2 (on / off of the transistor 1000) can be controlled by a potential applied to the conductor 404_1.

  As shown in FIG. 11C, the conductor 404_1 having the function of the first gate electrode includes the whole oxide 406b1 and the oxide 406c1 through the insulator 412a1 having the function of the first gate insulator. It is arranged to cover a part of. Accordingly, the whole of the oxide 406b1 and part of the oxide 406c1 can be electrically surrounded by the electric field from the conductor 404_1 functioning as the first gate electrode. A structure of a transistor that electrically surrounds a channel formation region with an electric field from the first gate electrode is referred to as a surrounded channel (s-channel) structure.

  Further, as illustrated in FIG. 11B, the oxide 406b1 and the oxide 406c1 are sandwiched between the conductor 416a1 and the conductor 416a2 which function as a source electrode or a drain electrode, whereby the oxide 406b1 In addition, the area in which the oxide 406c1 is in contact with the source electrode or the drain electrode can be increased. As a result, the contact resistance between the oxides 406b1 and 406c1, and the conductors 416a1 and 416a2 is preferably reduced.

  A metal oxide is preferably used for the oxide 406_1. Note that silicon (including strained silicon), germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used instead of the oxide.

  A transistor using a metal oxide for a channel formation region has extremely small leakage current in an off state. Therefore, a semiconductor device using the transistor can be a semiconductor device with extremely low power consumption. Further, the metal oxide can be formed by a sputtering method or the like. Therefore, it is preferable to use a metal oxide for a transistor included in a highly integrated semiconductor device.

  On the other hand, in a transistor using a metal oxide, its electrical characteristics are likely to vary due to impurities and oxygen vacancies in the metal oxide, and reliability may deteriorate. In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Therefore, a transistor including a metal oxide containing oxygen vacancies is likely to be normally on. For this reason, it is preferable that the oxygen deficiency in a metal oxide is reduced as much as possible.

  The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably included. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. One or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.

  Here, a case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Here, each of In-M-Zn oxides used for the oxide 406b1 and the oxide 406c1 preferably contains more atoms than the element M in In. With such an oxide, the carrier density in the oxide is increased and the mobility of the transistor 1000 is increased. In addition, it is preferable that the oxide be placed on the conductor 404_1 functioning as the first gate electrode because carrier control in the channel formation region of the conductor 404_1 is increased.

  Here, for example, the oxide 406b1 and the oxide 406c1 are preferably the same or in the vicinity of a metal oxide having a composition. Alternatively, for example, the oxide 406b1 and the oxide 406c1 are preferably formed using the same sputtering target member. Alternatively, for example, the oxide 406b1 and the oxide 406c1 are preferably formed using a sputtering target member having substantially the same composition. Alternatively, for example, the oxide 406b1 and the oxide 406c1 are preferably formed under substantially the same process conditions (for example, a film formation temperature and a ratio of oxygen gas).

  Alternatively, for example, the oxide 406b1 and the oxide 406c1 may be formed using sputtering target members having different compositions. For example, the oxide 406b1 and the oxide 406c1 can be made equal to each other by appropriately adjusting process conditions (for example, the film formation temperature and the oxygen gas ratio) of the oxide 406b1 and the oxide 406c1. In some cases, the film can be formed as a metal oxide having a composition in the vicinity. As the oxide 406b1 and the oxide 406c1, it is preferable to use a metal oxide having a similar composition. However, since required thicknesses and functions are different, optimum film formation conditions may be different. Therefore, it is easier to form the oxide 406b1 and the oxide 406c1 using a sputtering target member having a different composition than when a film is formed using a sputtering target member having an equal composition or a nearby composition. In some cases, the compositions of the material 406b1 and the oxide 406c1 can be made close to each other.

  By setting the oxide 406b1 and the oxide 406c1 to have the same composition or in the vicinity thereof, the electron affinity of the oxide 406b1 and the electron affinity of the oxide 406c1 are equal to each other or the difference is reduced. In particular, when not only the composition but also the process conditions are substantially the same, the electron affinity of the oxide 406b1 and the electron affinity of the oxide 406c1 are equal or have a small difference. Therefore, the interface state density between the oxide 406b1 and the oxide 406c1 can be reduced. By reducing the interface state density, reduction in on-state current of the transistor 1000 can be prevented and reliability can be improved. The electron affinity is the energy difference between the vacuum level Evac and the energy value Ec at the bottom of the conduction band. The difference between the Ec of the oxide 406b1 and the Ec of the oxide 406c1 is preferably small, and is set to 0 eV or more and 0.15 eV or less, more preferably 0 eV or more and 0.07 eV.

  As shown in FIG. 13, the electron affinity or Ec can be obtained from the ionization potential Ip, which is the difference between the vacuum level Evac and the energy Ev at the top of the valence band, and the band gap Eg. The ionization potential Ip can be measured using, for example, an ultraviolet photoelectron spectroscopy (UPS) apparatus. The band gap Eg can be measured using, for example, a spectroscopic ellipsometer.

  Further, in the structure of the transistor 1000, processing damage may occur when the source electrode or the drain electrode is formed on the top surface and the side surface of the oxide 406b1. That is, a defect due to processing damage may occur in the vicinity of the interface between the oxide 406b1 and the oxide 406c1.

  However, the oxides 406b1 and 406c1 can be made to have the same Ec by reducing the Ec difference between the oxides 406b1 and 406c1 by using a metal oxide having the same composition or a nearby composition. can do. Thus, the region where the channel of the transistor 1000 is formed is not limited to the vicinity of the interface between the oxide 406b1 and the oxide 406c1, but also the oxide 406c1 and an insulator that functions as a first gate insulator. It can also be provided near the interface with 412a1.

  Thus, even if the vicinity of the interface between the oxide 406b1 and the oxide 406c1 has processing damage, the influence of the processing damage on the electrical characteristics of the transistor 1000 can be reduced. Further, after an oxide to be the oxide 406c1 and an insulator to be the insulator 412a1 functioning as the first gate insulator are stacked, the oxide to be the oxide 406c1 and the insulator 412a1 When the insulator to be processed is processed to form the oxide 406c1 and the insulator 412a1, the vicinity of the interface between the oxide 406c1 and the insulator 412a1 is not affected by damage due to the processing. It can be in the vicinity.

  As described above, the reliability of the transistor 1000 can be improved. Further, the entire oxide 406b1 and part of the oxide 406c1 are surrounded by an electric field from the conductor 404_1 functioning as the first gate electrode of the transistor 1000 (s-channel structure); thus, the channel The controllability of carriers in the formation region is increased, so that the on-state current of the transistor 1000 can be increased and the off-state current can be decreased.

  In addition, the transistor 1000 includes a region in which the conductor 404_1 functioning as a first gate electrode and the conductors 416a1 and 416a2 serving as a source electrode or a drain electrode overlap with each other. 404_1 and a conductor 416a1 and a parasitic capacitance formed by the conductor 404_1 and the conductor 416a2.

  The transistor 1000 includes a barrier film 417a1 in addition to the insulator 412a1 and the oxide 406c1 between the conductor 404_1 and the conductor 416a1. Therefore, the film thickness between the conductor 404_1 and the conductor 416a1 is increased, and the parasitic capacitance between the conductor 404_1 and the conductor 416a1 can be reduced by that amount. Similarly, a barrier film 417a2 is provided between the conductor 404_1 and the conductor 416a2 in addition to the insulator 412a1 and the oxide 406c1, so that the parasitic capacitance between the conductor 404_1 and the conductor 416a2 is increased. Can be reduced. Therefore, the transistor 1000 can reduce an adverse effect (delay or the like) that the parasitic capacitance has on the frequency characteristics.

  In addition, when the transistor 1000 has the above structure, when the transistor 1000 is operated, for example, when a potential difference is generated between the conductor 404_1 and the conductor 416a1 or 416a2, the conductor 404_1 and the conductor Leakage current between 416a1 and the conductor 416a2 can be reduced. This is because the transistor 1000 includes the barrier film 417a1 or the barrier film 417a2, and thus the thickness between the conductor 404_1 and the conductor 416a1 or 416a2 is thick.

  The conductor 310_1 is provided in an opening formed in the insulator 301. A conductor 310a1 is formed in contact with the inner wall of the opening of the insulator 301, and a conductor 310b1 is further formed inside. Here, the heights of the upper surfaces of the conductors 310a1 and 310b1 and the height of the upper surface of the insulator 301 can be approximately the same. The conductor 310_1 functions as a second gate electrode. Alternatively, the conductor 310_1 can be a multilayer film including a conductor having a function of suppressing permeation of oxygen. For example, when the conductor 310a1 is a conductor having a function of suppressing permeation of oxygen, a decrease in conductivity due to oxidation of the conductor 310b1 can be prevented.

  The insulator 302, the insulator 303, and the insulator 402 function as a second gate insulator. Vth of the transistor 1000 can be controlled by a potential applied to the conductor 310_1 functioning as the second gate electrode.

<Configuration Example 2 of Transistor>
The above-described structure of the transistor 1000 can be applied to the transistor M0 or the transistor M1 according to one embodiment of the present invention. The structure of the transistor 1000 may be applied to the transistor M0 or may be applied to the transistor M1. Alternatively, the present invention may be applied to both the transistor M0 and the transistor M1. However, as described in Embodiment 1, the transistor M0 and the transistor M1 have different roles in the semiconductor device 10 or the semiconductor device 20 according to one embodiment of the present invention. Therefore, it is preferable to use a transistor having a structure suitable for each role as the transistor M0 and the transistor M1. In particular, the transistor M1 is required to have characteristics that the transistor M0 does not have, such as Vth larger than that of the transistor M0 and resistance to a potential applied from the second gate when electrons are injected into the charge trap layer. Thus, in the following, a configuration example of the transistor 2000, which is preferably applied mainly to the transistor M1, will be described. Note that the case where the transistor 2000 is formed over the substrate 400 and the insulator 401 in a manner similar to the transistor 1000 described above is described below; however, one embodiment of the present invention is not limited thereto. The transistor 1000 and the transistor 2000 may each be formed in different layers in the same substrate.

  FIG. 12A is a top view of the transistor 2000. FIG. FIG. 12B is a cross-sectional view taken along dashed-dotted line B1-B2 in FIG. 12A and is a cross-sectional view in the channel length direction of the transistor 2000. FIG. 12C is a cross-sectional view taken along dashed-dotted line B3-B4 in FIG. 12A, and is a cross-sectional view in the channel width direction of the transistor 2000. In the top view of FIG. 12A, some elements are omitted for clarity.

  The transistor 2000 is provided over the substrate 400, and the insulator 401 is provided between the substrate 400 and the transistor 2000. Further, an insulator 410 and an insulator 420 over the insulator 410 are provided over the transistor 2000.

  The transistor 2000 includes a conductor 310_2 and an insulator 301 over the insulator 401, an insulator 302 over the conductor 310_2 and the insulator 301, an insulator 303 over the insulator 302, and an insulator over the insulator 303. 402, the oxide 406a2 and the oxide 406a3 over the insulator 402, the oxide 406b2 and the oxide 406b3 over the oxide 406a3, and a conductor 416b1 having a region in contact with the top surface of the oxide 406b2 , A conductor 416b2 having a region in contact with the top surface of the oxide 406b3, a barrier film 417b1 over the conductor 416b1, a barrier film 417b2 over the conductor 416b2, a side surface of the conductor 416b1, a side surface of the conductor 416b2, 406b2 top and side surfaces, oxide 406b3 top and side surfaces, oxide 406a2 A side surface, an oxide 406C2 having a region which is in contact with the side surface of the oxide 406A3, an insulator 412A2 on oxide 406C2, the conductor 404_2 on insulator 412A2, an insulator 418a2 on the conductor 404_2, the. The insulator 301 has an opening, and the conductor 310a2 and the conductor 310b2 are disposed in the opening.

  In the transistor 2000, the conductor 404_2 functions as a first gate electrode. The conductor 404_2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, the conductor 404_2 can be prevented from being oxidized by forming a conductor having a function of suppressing permeation of oxygen as a lower layer. Alternatively, the conductor 404_2 preferably includes a metal having oxidation resistance. Alternatively, an oxide conductor or the like may be used. The insulator 412a2 functions as a first gate insulator.

  The conductors 416b1 and 416b2 function as a source electrode or a drain electrode. The conductors 416b1 and 416b2 can have a stacked structure with a conductor having a function of suppressing permeation of oxygen. For example, the conductor 416b1 and the conductor 416b2 can be prevented from being oxidized by forming a conductor having a function of suppressing permeation of oxygen in the upper layer. Alternatively, the conductor 416b1 and the conductor 416b2 preferably include a metal having oxidation resistance. Alternatively, an oxide conductor or the like may be used.

  The barrier films 417b1 and 417b2 have a function of suppressing permeation of impurities such as hydrogen and oxygen. The barrier film 417b1 is on the conductor 416b1 and prevents oxygen from diffusing into the conductor 416b1. The barrier film 417b2 is on the conductor 416b2 and prevents oxygen from diffusing into the conductor 416b2.

  As shown in FIG. 12B, the transistor 2000 includes a layer including the oxide 406a2, the oxide 406b2, and the conductor 416b1, and a layer including the oxide 406a3, the oxide 406b3, and the conductor 416b2 Is disposed so as to sandwich a region where a part of the upper surface of the oxide film 406c2 is in contact with the oxide 406c2. Here, a layer including the oxide 406a2, the oxide 406b2, and the conductor 416b1, and a layer including the oxide 406a3, the oxide 406b3, and the conductor 416b2 have one side surface and each layer facing each other. The side surfaces that do not face each other, that is, the side surface opposite to one side surface will be referred to as the other side surface.

  The oxide 406c2 includes a region in contact with one side surface of the conductor 416b1 and one side surface of the conductor 416b2. Further, the oxide 406c2 is in contact with part of the top surface of the oxide 406b2 and one side surface, part of the top surface of the oxide 406b3 and one side surface, one side surface of the oxide 406a2, and one side surface of the oxide 406a3. It also has a region. That is, on one side surface, the conductor 416b1 and the conductor 416b2 are recessed from the oxide 406b2 and the oxide 406b3, and have a stepped shape. With such a step shape, the coverage of the oxide 406c2 with respect to the conductor 416b1, the conductor 416b2, the oxide 406b2, the oxide 406b3, the oxide 406a2, and the oxide 406a3 is preferable. . In the other side surface, the oxide 406a2, the oxide 406b2, and the conductor 416b1, and the oxide 406a3, the oxide 406b3, and the conductor 416b2 have shapes that are approximately the same. That is, the other side surface has a flush shape.

  In the transistor 2000, the oxide 406c2 includes a channel formation region. Therefore, the transistor 2000 can control the resistance of the oxide 406c2 by the potential applied to the conductor 404_2. In other words, conduction / non-conduction between the conductor 416b1 and the conductor 416b2 (on / off of the transistor 2000) can be controlled by a potential applied to the conductor 404_2.

  The transistor 2000 includes a channel formation region in the oxide 406c2. On the other hand, as described above, the transistor 1000 includes channel formation regions in two layers of the oxide 406b1 and the oxide 406c1, which are oxides having the same composition or in the vicinity. Here, the oxide 406c1 and the oxide c2 are both formed by processing the oxide 406c (separately described later); therefore, an oxide having a channel formation region of the transistor 2000 (oxide 406c2); It can be said that the oxides having the channel formation region of the transistor 1000 (oxides 406b1 and 406c1) are oxides having substantially the same composition and differ only in film thickness (the transistor 2000 is different in transistor). The thickness of the oxide having a channel formation region is smaller than 1000.) Therefore, the transistor 1000 and the transistor 2000 have different electrical characteristics. Specifically, the transistor 2000 has a larger Vth than the transistor 1000 and can have a low off-state current.

  Since the oxide 406a2 and the oxide 406a3 are both formed by processing the oxide 406a (separately described later), they are metal oxides having the same composition. Similarly, both the oxide 406b2 and the oxide 406b3 are metal oxides having the same composition because they are formed by processing the oxide 406b (separately described later).

  Note that each of the In-M-Zn oxides used for the oxide 406b2, the oxide 406b3, and the oxide 406c2 preferably contains more atoms than the element M in In.

  Here, the oxide affinities of the oxide 406b2 and the oxide 406b3 and the electron affinity of the oxide 406c2 can be obtained by setting the oxides 406b2 and 406b3 and the oxide 406c2 to have the same or close composition. , Equal or smaller difference. Therefore, the interface state density between the oxide 406b2 and the oxide 406c2 and the interface state density between the oxide 406b3 and the oxide 406c2 can be reduced. By reducing the interface state density, the reliability of the transistor 2000 can be improved. The difference between the Ec of the oxide 406b2 and the oxide 406b3 and the Ec of the oxide 406c2 is preferably smaller, and is 0 eV or more and 0.15 eV or less, more preferably 0 eV or more and 0.07 eV or less.

  In the transistor 2000, the conductor 404_2 having a function as a first gate electrode and the conductors 416b1 and 416b2 having a function as a source electrode or a drain electrode have regions overlapping with each other. 404_2 and a conductor 416b1 and a parasitic capacitance formed by the conductor 404_2 and a conductor 416b2.

  The transistor 2000 includes a barrier film 417b1 in addition to the insulator 412a2 and the oxide 406c2 between the conductor 404_2 and the conductor 416b1. Therefore, the film thickness between the conductor 404_2 and the conductor 416b1 is increased, and the parasitic capacitance between the conductor 404_2 and the conductor 416b1 can be reduced accordingly. Similarly, in addition to the insulator 412a2 and the oxide 406c2, the barrier film 417b2 is provided between the conductor 404_2 and the conductor 416b2, so that the parasitic capacitance between the conductor 404_2 and the conductor 416b2 is increased. Can be reduced. Therefore, the transistor 2000 can reduce an adverse effect (delay or the like) that the parasitic capacitance has on the frequency characteristics.

  Further, when the transistor 2000 has the above structure, when the transistor 2000 is operated, for example, when a potential difference is generated between the conductor 404 and the conductor 416a1 or 416a2, the conductor 404 and the conductor Leakage current between 416a1 and the conductor 416a2 can be reduced. This is because the transistor 2000 includes the barrier film 417b1 or the barrier film 417b2, and thus the thickness between the conductor 404_2 and the conductor 416b1 or 416b2 is large.

  In addition, the conductor 310_2 functions as a second gate electrode. The conductor 310a2 functions as a conductive barrier film. The conductor 310a2 can be prevented from being oxidized by being disposed so as to surround the bottom surface and the side surface of the conductor 310b2.

  In addition, the transistor 2000 according to one embodiment of the present invention can inject and hold electrons in the charge trap layer. As illustrated in FIGS. 3A and 5A, In order to perform electron injection, a strong positive potential may be applied from the second gate electrode (conductor 310_2) to the charge trap layer.

  In the transistor 1000, the film configuration between the first gate electrode (conductor 404_1) and the second gate electrode (conductor 310_2) is a cross-sectional view taken along the dashed-dotted line A3-A4 in FIG. The regions where the oxide 406a1, the oxide 406b1, the conductive film 416a1 (conductive film 416a2), and the barrier film 417a1 (conductive film 417a2) are not provided have the smallest thickness (FIG. 11C). reference.). The region includes only the insulator 302, the insulator 303, the insulator 402, the oxide 406c1, and the insulator 412a1 between both gate electrodes. Therefore, for example, when a potential is applied for electron injection to the charge trap layer of the transistor 1000, strong charge concentration occurs in the region, and dielectric breakdown may be induced in the region.

  On the other hand, in the transistor 2000, a film structure between the first gate electrode (conductor 404_2) and the second gate electrode (conductor 310_2) is indicated by a dashed-dotted line in FIG. , The insulator 302, the insulator 303, the insulator 402, the oxide 406c2, the conductor 416b1 functioning as a source or drain electrode, the barrier film 417b1, the insulator 412a2, and the first And a conductor 404_2 having a function as a gate electrode (see FIG. 12C).

  In addition, the transistor 2000 has a conductive function as a second gate electrode in a region where the conductor 404_2 having a function as a first gate electrode overlaps with a conductor 416b1 having a function as a source electrode or a drain electrode. The length of the body 310_2 in the channel width direction is shorter than the length of the conductor 416b1 in the channel width direction. Similarly, in a region where the conductor 404_2 having a function as a first gate electrode and the conductor 416b2 having a function as a source electrode or a drain electrode overlap with each other, the conductor 310_2 having a function as a second gate electrode is formed. The length in the channel width direction is shorter than the length of the conductor 416b2 in the channel width direction (see FIGS. 12A and 12C). Therefore, in the transistor 2000, the conductor 416b1 or the conductor 416b2 is present in a top view (see FIG. 12A) even when a strong potential is applied to the second gate electrode (conductor 310_2). In the region, strong electric field concentration occurs between the first gate electrode (conductor 404_2) and the second gate electrode (conductor 310_2) due to the influence of electric field shielding by the conductor 416b1 or the conductor 416b2. No.

  In the transistor 1000, the entire region of the second gate electrode (conductor 310_1) overlaps with the first gate electrode (conductor 404_1) when viewed from above (see FIG. 11A). In the top view of the transistor 2000, only part of the second gate electrode (conductor 310_2) overlaps with the first gate electrode (conductor 404_2) (see FIG. 12A). Therefore, in the transistor 2000 according to one embodiment of the present invention, when the second gate electrode is provided as in the transistor 1000 illustrated in FIG. With respect to the potential applied from the gate electrode, it can have good dielectric strength breakdown resistance.

  The insulator 302, the insulator 303, and the insulator 402 have a function as a charge trap layer. By applying a desired potential to the conductor 310_2 having a function as the second gate electrode, electrons can be injected into the charge trap layer and held in the charge trap layer (for details, separately (It will be described later.)

  The insulator 302, the insulator 303, and the insulator 402 also function as a second gate insulator. Vth of the transistor 2000 can be controlled by a potential applied to the conductor 310_2 functioning as the second gate electrode.

  Note that as described above, the insulator 302, the insulator 303, and the insulator 402 also function as the second gate insulator or the charge trap layer of the transistor 1000. In this embodiment, since the transistor 1000 and the transistor 2000 are formed over the same layer, the insulator 302, the insulator 303, and the insulator 402 are the second transistors of both the transistor 1000 and the transistor 2000. It can function as a gate insulator or a charge trap layer. In this manner, it is preferable to manufacture transistors having different shapes over the same layer because the number of manufacturing steps for each transistor can be reduced. Details of an example of a method for manufacturing the transistor 1000 and the transistor 2000 over the same layer will be described later.

<Constituent elements of transistor>
Hereinafter, details of each component applicable to the transistor 1000 or the transistor 2000 described above will be described.

〔substrate〕
As the substrate 400, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate including a metal nitride, a substrate including a metal oxide, and the like. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

  Further, a flexible substrate may be used as the substrate 400. Note that as a method for providing a transistor over a flexible substrate, there is a method in which a transistor is manufactured over a non-flexible substrate, and then the transistor is peeled and transferred to the substrate 400 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate 400. Further, the substrate 400 may have elasticity. Further, the substrate 400 may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate 400 has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, and more preferably 15 μm to 300 μm. When the substrate 400 is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate 400 thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate 400 due to a drop or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate 400 which is a flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. The substrate 400, which is a flexible substrate, is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. As the substrate 400 which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less is used. Good. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable for the substrate 400 that is a flexible substrate.

〔Insulator〕
Examples of the insulator include an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, and metal nitride oxide.

  By surrounding the transistor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized. For example, as the insulator 303, the insulator 401, the insulator 418a1 (insulator 418a2), and the insulator 420, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used.

  Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. An insulator containing lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer.

  For example, the insulator 303, the insulator 401, the insulator 418a1 (insulator 418a2), and the insulator 420 include aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, and oxide. A metal oxide such as neodymium, hafnium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like may be used. Note that the insulator 303, the insulator 401, the insulator 418a1 (insulator 418a2), and the insulator 420 preferably include aluminum oxide.

  For example, when the insulator 420 is formed by a sputtering method using plasma containing oxygen, oxygen can be added to the insulator 402 serving as an oxide base layer through the insulator 410. Accordingly, oxygen can be efficiently supplied to the oxide having the channel formation region of the transistor.

  Examples of the insulator 301, the insulator 302, the insulator 402, and the insulator 412a1 (insulator 412a2) include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, An insulator containing germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer. For example, the insulator 301, the insulator 302, the insulator 402, and the insulator 412a1 (insulator 412a2) preferably include silicon oxide, silicon oxynitride, or silicon nitride.

  In particular, the insulator 402 and the insulator 412a1 (insulator 412a2) preferably include an insulator having a high relative dielectric constant. For example, the insulator 402 and the insulator 412a1 (insulator 412a2) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, It is preferable to include oxynitride including silicon and hafnium or nitride including silicon and hafnium. Alternatively, the insulator 402 and the insulator 412a1 (insulator 412a2) preferably have a stacked structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having high thermal stability and high relative dielectric constant can be obtained by combining with an insulator having high relative dielectric constant. For example, in the insulator 402 and the insulator 412a1 (insulator 412a2), aluminum oxide, gallium oxide, or hafnium oxide is in contact with the oxide 406a1 and the oxide 406c1 (oxide 406c2), whereby silicon oxide or oxynitride is formed. Silicon contained in silicon can be prevented from entering the oxide 406a1 and the oxide 406c1 (oxide 406c2). For example, in the insulator 402 and the insulator 412a1 (insulator 412a2), silicon oxide or silicon oxynitride is in contact with the oxide 406a1 and the oxide 406c1 (oxide 406c2), whereby aluminum oxide or gallium oxide is formed. Alternatively, a trap center may be formed at the interface between hafnium oxide and silicon oxide or silicon oxynitride. The trap center may change the Vth of the transistor in the positive direction by capturing electrons in some cases.

  The insulator 410 preferably includes an insulator having a low relative dielectric constant. For example, the insulator 410 includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having a hole Or it is preferable to have resin etc. Alternatively, the insulator 410 is formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having a hole And a laminated structure of resin. Since silicon oxide and silicon oxynitride are thermally stable, a stacked structure having a low thermal stability and a low relative dielectric constant can be obtained by combining with silicon. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

  As the barrier film 417a1 (barrier film 417b1) and the barrier film 417a2 (barrier film 417b2), an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. By the barrier film 417a1 (barrier film 417b1) and the barrier film 417a2 (barrier film 417b2), excess oxygen in the insulator 410 is diffused to the conductor 416a1 (conductor 416b1) and the conductor 416a2 (conductor 416b2). Can be prevented. Accordingly, it is possible to suppress an increase in conductivity due to oxidation of the conductors 416a1 (conductor 416b1) and the conductors 416a2 (conductor 416b2) which function as a source electrode or a drain electrode of the transistor.

  As the barrier film 417a1 (barrier film 417b1) and the barrier film 417a2 (barrier film 417b2), for example, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or oxide A metal oxide such as tantalum, silicon nitride oxide, silicon nitride, or the like may be used.

  By the way, as described in Embodiment 1, the transistor M0 or the transistor M1 of one embodiment of the present invention is a charge that holds charges (electrons) between the oxide having a channel formation region and the second gate. It can have a trap layer. In the case of the transistor 1000 (transistor 2000), the oxide having a channel formation region corresponds to the oxide 406b1 or the oxide 406c1 (oxide 406c2), and the second gate electrode includes the conductor 310a1 (conductor 310a2) and It corresponds to the conductor 310b1 (conductor 310b2). The charge trap layer corresponds to the insulator 302, the insulator 303, or the insulator 402. Hereinafter, a mechanism of charge injection / holding into the charge trap layer will be described.

  FIG. 14A is a simplified schematic diagram of the transistor (the transistor 1000 or the transistor 2000) according to one embodiment of the present invention, leaving only elements necessary for the following description. The reference numerals illustrated in FIG. 14A correspond to the reference numerals of the transistor 2000 illustrated in FIG. Note that FIG. 14A illustrates an example in which the charge trap layer is formed using a three-layer stack of the insulator 302, the insulator 303, and the insulator 402.

  FIG. 14B illustrates an example of a band diagram from point A to point B of the transistor illustrated in FIG. In FIG. 14B, Ec represents the energy at the lower end of the conduction band, and Ev represents the energy at the upper end of the valence band. FIG. 14B is a band diagram in the case where the potential of the conductor 310_2 functioning as the second gate electrode of the transistor is the same as the potential of the source electrode or the drain electrode (both not shown). Show.

  In this example, the electron affinity of the insulator 302 and the insulator 402 is smaller than the electron affinity of the insulator 303. In addition, the band gap of the insulator 302 and the insulator 402 is larger than the band gap of the insulator 303. The charge trap layer (the insulator 302, the insulator 303, and the insulator 402) according to one embodiment of the present invention is formed using silicon oxide or silicon oxynitride for the insulator 302 and the insulator 402, for example. By using aluminum oxide or hafnium oxide, the above band configuration can be obtained.

  The electron trap level 106 exists in the insulator 302 or / and the interface between the insulator 402 and the insulator 303 or / and in the insulator 303. Here, when a positive potential having a desired size is applied to the conductor 310_2 functioning as the second gate electrode of the transistor so that the potential is higher than the potential of the source electrode or the drain electrode, a band illustrated in FIG. The figure is deformed as shown in FIG. That is, the band of the conductor 302 to which a positive potential is applied is lowered and dragged, and the bands of the insulator 302, the insulator 303, the insulator 402, and the oxide 406c2 are distorted.

  Note that at this time, the conductor 404_2 having a function as the first gate electrode of the transistor is preferably the same as the potential of the source electrode or the drain electrode. The electrons 107 existing in the oxide 406c2 tend to move toward the conductor 310 having a higher potential. Then, some of the electrons 107 that have moved from the oxide 406 c 2 toward the conductor 310 are captured by the electron capture level 106.

  Several processes can be considered for the electrons 107 to reach the insulator 303 across the barrier of the insulator 402. The first is due to the tunnel effect. The tunnel effect becomes more prominent as the insulator 402 is thinner. However, in this case, electrons trapped in the electron trap level 106 may be lost again due to the tunnel effect.

  Note that by applying an appropriate potential to the conductor 310_2 functioning as the second gate electrode of the transistor, a tunnel effect (Fowler-Nordheim tunnel effect) can be obtained even when the insulator 402 is relatively thick. Can be expressed. In the case of the Fowler-Nordheim tunnel effect, the electric field applied between the conductor 310_2 and the oxide 406c2 is increased, so that the tunnel current rapidly increases.

  Second, the electrons 107 reach the insulator 303 while hopping trap levels in a band gap such as a defect level in the insulator 402. This is a conduction mechanism called Poole-Frenkel conduction, and it is more likely to be manifested as the absolute temperature is higher and the trap level is shallower.

Third, electrons 107 cross the barrier of the insulator 402 by thermal excitation. The distribution of electrons present in the oxide 406c2 follows a Fermi-Dirac distribution. In general, the proportion of electrons with high energy increases as the temperature increases. For example, assuming that the density of electrons having energy higher by 3 eV from the Fermi level at 300 K (27 ° C.) is 1, 450 × 1 (177 ° C.) is 6 × 10 ¹⁶ , and 600 K (327 ° C.) is 1.5 At × 10 ²⁵ and 750 K (477 ° C.), the value is 1.6 × 10 ³⁰ .

  As described above, the process in which the electrons 107 move toward the conductor 310_2 beyond the barrier of the insulator 402 is generated by the above three processes and a combination thereof. In particular, the second process and the third process are more prominently expressed as the temperature is higher.

  Note that the electrons trapped in the electron trap level 106 are required to be held in the charge trap layer (the insulator 302, the insulator 303, and the insulator 402) and do not flow out. Therefore, it is preferable that the thickness of the insulator 302 and the insulator 402 be a thickness that does not cause the above-described tunnel effect. For example, the physical thickness is preferably greater than 1 nm.

  As described above, the charge trap layer included in the transistor M0 or the transistor M1 of one embodiment of the present invention can inject and hold electrons by application of a desired potential from the second gate.

  FIG. 15 shows data obtained by actually injecting and holding electrons in the charge trap layer and positively shifting Vth for the transistor having the charge trap layer. The transistor used has a channel length (L) of 60 nm and a channel width (W) of 50 nm. When a potential of +44 V is applied from the second gate of the transistor to the charge trap layer at room temperature for 2 seconds, The change in Vth was monitored.

  FIG. 15A shows that 0 sec before the start of electron injection into the charge trap layer is 0.4 sec, 0.8 sec, 1.2 sec, 1.6 sec, and 2.0 sec after the start of electron injection, respectively. The Vg-Id characteristics of the transistor are overwritten. Here, Vg is the potential of the first gate of the transistor, and Id is the drain current of the transistor. Note that the drain potential (Vd) of the transistor was +1.8 V when measuring the Vg-Id characteristics. FIG. 15B is a graph showing the dependency of Vth on the electron injection time into the charge trap layer in each Vg-Id characteristic of the transistor in FIG. The horizontal axis indicates the time for electron injection into the charge trap layer. As shown in FIGS. 15A and 15B, it can be confirmed that as the electron injection time into the charge trap layer is longer, the Vg-Id characteristic of the transistor is shifted more positively. This is because the amount of charge (electrons) injected into the charge trap layer increases as the electron injection time into the charge trap layer increases. Thus, it can be said that the electron injection / holding by the charge trap layer is an effective means for controlling the Vth of the transistor.

〔conductor〕
Conductor 404a1 (conductor 404a2), conductor 404b1 (conductor 404b2), conductor 310a1 (conductor 310a2), conductor 310b1 (conductor 310b2), conductor 416a1 (conductor 416b1), and conductor 416a2 (conductor) The body 416b2) was selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. A material containing one or more metal elements can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

  Further, metal elements and oxygen contained in oxides applicable to the oxides 406a1, 406b1, and 406c1 (oxides 406a2, 406a3, 406b2, oxides 406b3, and oxides 406c2) A conductive material containing may be used. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the oxide 406a1, the oxide 406b1, and the oxide 406c1 (oxide 406a2, oxide 406a3, oxide 406b2, oxide 406b3, and oxide 406c2) is captured. There are cases where it is possible. Alternatively, hydrogen that enters from an external insulator or the like can be captured in some cases.

  A plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

  Note that in the case where an oxide is used for the channel formation region of the transistor, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined is preferably used for the gate electrode. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material can be easily supplied to the channel formation region.

[Oxide]
As the oxide 406a1, the oxide 406b1, and the oxide 406c1 (oxide 406a2, oxide 406a3, oxide 406b2, oxide 406b3, and oxide 406c2), a metal oxide is preferably used. Note that instead of the oxide 406a1, the oxide 406b1, and the oxide 406c1 (the oxide 406a2, the oxide 406a3, the oxide 406b2, the oxide 406b3, and the oxide 406c2), silicon (including strained silicon), germanium, In some cases, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, an organic semiconductor, or the like may be used. The oxide 406a1, the oxide 406b1, and the oxide 406c1 (oxide 406a2, oxide 406a3, oxide 406b2, oxide 406b3, and oxide 406c2) according to one embodiment of the present invention are preferably used below. The metal oxide will be described.

  The metal oxide preferably contains at least indium or zinc. In particular, indium and zinc are preferably included. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the metal oxide is InMZnO containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Examples of other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  By using the metal oxide for a channel formation region of the transistor, a transistor with high field effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, a metal oxide with low carrier density is preferably used. In order to reduce the carrier density of the metal oxide film, the impurity concentration in the metal oxide film may be decreased and the defect level density may be decreased. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high purity intrinsic or substantially high purity intrinsic. For example, the metal oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / What is necessary is just to be cm ³ or more.

  In addition, since a highly purified intrinsic or substantially highly purified intrinsic metal oxide film has a low defect level density, the trap level density may also be low.

  In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in a metal oxide having a high trap state density may have unstable electrical characteristics.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the metal oxide. In order to reduce the impurity concentration in the metal oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

  Here, the influence of each impurity in the metal oxide will be described.

In the metal oxide, when silicon or carbon, which is one of Group 14 elements, is included, a defect level is formed in the metal oxide. Therefore, the concentration of silicon and carbon in the metal oxide and the concentration of silicon and carbon in the vicinity of the interface with the metal oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the metal oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to be normally on. For this reason, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the metal oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is included in the metal oxide, electrons as carriers are generated, the carrier density is increased, and the n-type is easily obtained. As a result, a transistor in which a metal oxide containing nitrogen is used for a channel formation region is likely to be normally on. Accordingly, in the metal oxide, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration in the metal oxide is less than 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS, preferably 5 × 10 ^18. atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, so that oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor in which a metal oxide containing hydrogen is used for a channel formation region is likely to be normally on. For this reason, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. Less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

  By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be imparted.

  Hereinafter, the CAC-OS will be described in detail. The CAC-OS is an example of a function or a material structure that can be included in the metal oxide of the transistor of one embodiment of the present invention.

  The CAC-OS is one structure of a material in which elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as mosaic or patch.

For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). _X1 (X1 is greater real than 0) and.), or indium zinc oxide _{(hereinafter, in X2 Zn Y2 O Z2 (} X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO _X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga _X4 Zn _Y4 O _Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic _{InO X1,} or _in X2 _Zn Y2 _{O Z2} is configured uniformly distributed in the film (hereinafter, cloud Also referred to.) A.

That, CAC-OS includes a region _{GaO X3} is the main _component, In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} there is a region which is a main component, a composite metal oxide having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.

Note that IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O. As a typical example, InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (−1 ≦ x0 ≦ 1, m0 is an arbitrary number) A crystalline compound may be mentioned.

  The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.

  On the other hand, CAC-OS relates to a material structure of a metal oxide. CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.

  Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.

Incidentally, a region _{GaO X3} is the main _component, In _{X2 Zn} Y2 _{O Z2,} or the region _{InO X1} is the main component, it may be difficult to observe a clear boundary.

  Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element as a main component and a nanoparticle mainly including In as a main component. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.

  The CAC-OS can be formed by a sputtering method under a condition that the substrate is not intentionally heated, for example. In the case where the CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during the deposition is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less.

  The CAC-OS is characterized in that no clear peak is observed when measured using a θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.

  In addition, in the CAC-OS, in an electron beam diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam), a ring-shaped high luminance region and a plurality of regions in the ring region are provided. A bright spot is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

In addition, for example, in a CAC-OS in an In—Ga—Zn oxide, GaO _X3 is a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy). It can be confirmed that the region and the region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 are unevenly distributed and mixed.

The CAC-OS has a structure different from that of the IGZO compound in which the metal element is uniformly distributed, and has a property different from that of the IGZO compound. That is, in the CAC-OS, a region in which GaO _X3 or the like is a main component and a region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.

Here, the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component is a region having higher conductivity than a region containing GaO _X3 or the like as a main component. _That, In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is a region which is a main component, by carriers flow, conductive metal oxide is expressed. Therefore, a region mainly composed of In _X2 Zn _Y2 O _Z2 or InO _X1 is distributed in a cloud shape in the metal oxide, so that a transistor using the metal oxide achieves high field-effect mobility. it can.

On the other hand, areas such as _{GaO X3} is the main _component, In _{X2 Zn} Y2 _{O Z2,} or _{InO X1} is compared to region which is a main component, has a high area insulation. That is, a region containing GaO _X3 or the like as a main component is distributed in a metal oxide, so that a transistor using the metal oxide can suppress a leakage current and realize a favorable switching operation.

Therefore, when CAC-OS is used for a semiconductor element such as a transistor, conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 and insulation caused by GaO _X3 or the like act complementarily. Thus, both a high on-current and a low off-current can be realized.

  In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimally used for various semiconductor devices such as a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, and an electronic device.

<Method for Manufacturing Transistor>
An example of a method for manufacturing the transistor 1000 (see FIG. 11) and the transistor 2000 (see FIG. 12) according to one embodiment of the present invention will be described below with reference to FIGS. In the following description, the transistor 1000 is assumed to be the transistor M0 in the semiconductor device 10 shown in FIG. 1 or the semiconductor device 20 shown in FIG. 2, and the transistor 2000 is assumed to be the transistor M1. In the following, an example in which the transistor 1000 and the transistor 2000 are formed over the same layer is described. 16 to 23, (A) in each drawing is a cross-sectional view corresponding to the alternate long and short dash line A1-A2 shown in FIG. 11 (A). Moreover, (B) of each figure is sectional drawing corresponding to the dashed-dotted line A3-A4 shown to FIG. 11 (A). Moreover, (C) of each figure is sectional drawing corresponding to the dashed-dotted line B1-B2 shown to FIG. 12 (A). (D) of each figure is sectional drawing corresponding to the dashed-dotted line B3-B4 shown to FIG. 12 (A).

  First, the substrate 400 is prepared.

  Next, the insulator 401 is formed. The insulator 401 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer. It can be performed using an ALD (Atomic Layer Deposition) method or the like.

  The CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the source gas used.

  In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method that can reduce plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like) included in the semiconductor device may be charged up by receiving electric charge from plasma. At this time, a wiring, an electrode, an element, or the like included in the semiconductor device may be destroyed by the accumulated charge. On the other hand, in the case of a thermal CVD method without using plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. In addition, in the thermal CVD method, plasma damage during film formation does not occur, so that a film with few defects can be obtained.

  The ALD method is also a film forming method that can reduce plasma damage to an object to be processed. In addition, since the ALD method does not cause plasma damage during film formation, a film with few defects can be obtained.

  The CVD method and the ALD method are film forming methods in which a film is formed by reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

  In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of the semiconductor device may be increased.

  The insulator 401 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, an aluminum oxide film may be formed by an ALD method, and the aluminum oxide film may be formed on the aluminum oxide by a sputtering method.

  Next, the insulator 301 is formed over the insulator 401. The insulator 301 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, a recess reaching the insulator 401 is formed in the insulator 301. The groove includes, for example, a hole and an opening. The groove may be formed by wet etching, but dry etching is preferable for fine processing. As the insulator 401, an insulator that functions as an etching stopper film when the insulator 301 is etched to form a groove is preferably selected. For example, in the case where a silicon oxide film is used for the insulator 301 that forms the groove, the insulator 401 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

  In this embodiment, an aluminum oxide film is formed as the insulator 401 by a sputtering method, and an aluminum oxide film is formed over the aluminum oxide by an ALD method. Further, a silicon oxide film is formed as the insulator 301 by a CVD method.

  After the groove is formed, a conductor to be the conductors 310a1 and 310a2 is formed. The conductors to be the conductors 310a1 and 310a2 desirably include a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, or molybdenum tungsten alloy can be used. The conductors to be the conductors 310a1 and 310a2 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, tantalum nitride is formed by a sputtering method as a conductor to be the conductor 310a1 and the conductor 310a2.

  Next, a conductor to be the conductor 310b1 and the conductor 310b2 is formed over the conductor 310a1 and the conductor 310a2. The conductor to be the conductor 310b1 and the conductor 310b2 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, titanium nitride is formed by a CVD method as a conductor to be the conductor 310b1 and the conductor 310b2, and tungsten is formed by a CVD method on the titanium nitride.

  Next, by performing chemical mechanical polishing (CMP), the conductors that become the conductors 310a1 and 310a2 over the insulator 301 and the conductors that become the conductors 310b1 and 310b2 are obtained. Remove. As a result, the conductors 310a1 and 310a2 and the conductors 310b1 and 310b2 remain only in the groove, so that the conductors 310a1 and 310a2 having a flat upper surface are formed. The conductor 310b1 and the conductor 310b2 can be formed.

  Next, the insulator 302 is formed over the insulator 301, the conductor 310a1, the conductor 310a2, the conductor 310b1, and the conductor 310b2. The insulator 302 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 303 is formed over the insulator 302. The insulator 303 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the insulator 402 is formed over the insulator 303. The insulator 402 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, it is preferable to perform a first heat treatment. The first heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. The first heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed in a reduced pressure state. Alternatively, the first heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in a nitrogen or inert gas atmosphere. You may go. By the first heat treatment, impurities such as hydrogen and water contained in the insulator 402 can be removed. Alternatively, in the first heat treatment, plasma treatment containing oxygen may be performed in a reduced pressure state. For the plasma treatment including oxygen, for example, an apparatus having a power source that generates high-density plasma using microwaves is preferably used. Alternatively, a power source for applying RF (Radio Frequency) may be provided on the substrate side. High-density oxygen radicals can be generated by using high-density plasma, and oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 402 by applying RF to the substrate side. Alternatively, plasma treatment containing oxygen may be performed to supplement oxygen that has been desorbed after performing plasma treatment containing an inert gas using this apparatus. Note that the first heat treatment may not be performed.

  The heat treatment can also be performed after the insulator 302 is formed, after the insulator 303 is formed, and after the insulator 402 is formed. Although the first heat treatment condition can be used for the heat treatment, the heat treatment after the formation of the insulator 302 is preferably performed in an atmosphere containing nitrogen.

  In this embodiment, as the first heat treatment, after the insulator 402 is formed, a treatment is performed in a nitrogen atmosphere at a temperature of 400 ° C. for 1 hour, and then, continuously in an oxygen atmosphere at a temperature of 400 ° C. Do time processing.

  Next, an oxide 406 a and an oxide 406 b are formed in order over the insulator 402. Note that the oxide 406a and the oxide 406b are preferably formed successively without being exposed to the air environment. By forming the film in this manner, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide 406a, and the vicinity of the interface between the oxide 406a and the oxide 406b can be kept clean.

  The oxide 406a and the oxide 406b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  For example, in the case where the oxide 406a and the oxide 406b are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased.

  In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 402 when the oxide 406a is formed.

  Note that the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

  Subsequently, an oxide 406b is formed by a sputtering method. At this time, when the film is formed so that the proportion of oxygen contained in the sputtering gas is 1% to 30%, preferably 5% to 20%, an oxygen-deficient oxide is formed. A transistor using an oxygen-deficient oxide can have a relatively high field-effect mobility.

  In the case where an oxygen-deficient oxide is used for the oxide 406b, an oxide containing excess oxygen is preferably used for the oxide 406a. Alternatively, oxygen doping treatment may be performed after the oxide 406b is formed.

  Note that in the case where an oxide is formed by a sputtering method, a film having an atomic ratio that deviates from the atomic ratio of the target may be formed. For example, depending on the substrate temperature during film formation, the atomic ratio of zinc (Zn) in the film may be smaller than the atomic ratio of zinc (Zn) in the target.

  In this embodiment, the oxide 406a is formed by a sputtering method using a target of In: Ga: Zn = 1: 3: 4 [atomic ratio], and the oxide 406b is formed by an sputtering method using an In. : Ga: Zn = 4: 2: 4.1 [atomic ratio] Target is used for film formation.

  Next, second heat treatment may be performed. For the second heat treatment, first heat treatment conditions can be used. By the second heat treatment, impurities such as hydrogen and water in the oxide 406a and the oxide 406b can be removed. In this embodiment mode, after processing for one hour at a temperature of 400 ° C. in a nitrogen atmosphere, the processing is continuously performed for one hour at a temperature of 400 ° C. in an oxygen atmosphere.

  Next, a conductor 416 is formed over the oxide 406b. The conductor 416 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the conductor 416, a conductive oxide such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, or indium oxide containing titanium oxide. , Indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon, or indium gallium zinc oxide containing nitrogen, and aluminum, chromium, copper, Materials containing one or more metal elements selected from silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, etc., or phosphorus Polycrystals containing impurity elements A semiconductor such as silicon, which is typified by silicon, or a silicide such as nickel silicide may be formed.

  The oxide may have a function of absorbing hydrogen in the oxide 406a and the oxide 406b and capturing hydrogen diffused from the outside, so that the electrical characteristics and reliability of the transistor 1000 or the transistor 2000 are improved. There are things to do. Alternatively, even when titanium is used instead of the oxide, the same function may be obtained. In this embodiment, tantalum nitride is formed as the conductor 416.

  Next, an insulator 417 to be a barrier film 417a1, a barrier film 417a2, a barrier film 417b1, and a barrier film 417b2 is formed over the conductor 416. The insulator 417 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is formed as the insulator 417.

  Next, a conductor 411 is formed over the insulator 417. The conductor 411 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tantalum nitride is formed as the conductor 411 (see FIGS. 16A, 16B, 16C, and 16D).

  Next, the conductor 411 and the insulator 417 are processed by a lithography method, so that the conductor 411a, the conductor 411b, the insulator 417a, and the insulator 417b are formed. In the said process, it is preferable that a cross-sectional shape has a taper shape. The taper angle is 30 degrees or more and less than 75 degrees, preferably 30 degrees or more and less than 70 degrees with respect to a plane parallel to the bottom surface of the substrate. By having such a taper angle, the coverage of the film in the subsequent film formation process is improved. Further, it is preferable to use a dry etching method for the processing. Processing by the dry etching method is suitable for fine processing and the above-described tapered processing (see FIGS. 17A, 17B, 17C, and 17D).

  In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developer. Next, the conductor, the semiconductor, the insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, the resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. In addition, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that a mask is not necessary when an electron beam or an ion beam is used. Note that the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after the dry etching process, or performing a dry etching process after the wet etching process.

  As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power source to one of the parallel plate electrodes. Alternatively, a configuration in which a plurality of different high-frequency power supplies are applied to one of the parallel plate electrodes may be employed. Or the structure which applies the high frequency power supply of the same frequency to each parallel plate type | mold electrode may be sufficient. Or the structure which applies the high frequency power source from which a frequency differs to each parallel plate type | mold electrode may be sufficient. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

  Next, a resist 421 is formed by a lithography method. At this time, the resist 421 is disposed so as to cover the regions 406W1 and 406W2 (see FIGS. 18A, 18B, 18C, and 18D).

  Next, using the resist 421 as an etching mask, the conductor 411a, the conductor 411b, the insulator 417a, the insulator 417b, and the conductor 416 are etched, and the conductor 411a1, the conductor 411a2, the conductor 411b1, the conductor 411b2, A barrier film 417a1, a barrier film 417a2, a barrier film 417b1, a barrier film 417b2, a conductor 416_1, a conductor 416_2, and a conductor 416_3 are formed (FIGS. 19A, 19B, 19C, and 19C). FIG. 19D).

  Next, the resist 421 is removed, and the conductor 411a1, the conductor 411a2, the conductor 411b1, the conductor 411b2, the part where the surface of the conductor 416_1 is exposed, the part where the surface of the conductor 416_2 is exposed, and Using the exposed portion of the conductor 416_3 as an etching mask, the oxide 406a and the oxide 406b are etched, and the oxide 406a1, the oxide 406b1, the oxide 406a2, the oxide 406b2, the oxide 406a3, and the oxide 406b3 is formed. In this embodiment mode, tantalum nitride is used for the conductor 411a1, the conductor 411a2, the conductor 411b1, the conductor 411b2, the conductor 416_1, the conductor 416_2, and the conductor 416_3; The oxide 406a and the oxide 406b are preferably processed using etching conditions with a high etching rate. Specifically, when the etching rate of tantalum nitride is 1, the etching rate of the oxide 406a and the oxide 406b is 3 to 50, preferably 5 to 30 (FIG. 20A and FIG. 20). (See B), FIG. 20C, and FIG. 20D.)

  Next, the conductor 411a1, the conductor 411a2, the conductor 411b1, the conductor 411b2, the part where the surface of the conductor 416_1 is exposed, the part where the surface of the conductor 416_2 is exposed (region 406W1), and the conductor A portion where the surface of 416_3 is exposed (region 406W2) is etched, so that the conductor 416a1, the conductor 416a2, the conductor 416b1, and the conductor 416b2 are formed. Further, by etching the portion where the surface of the conductor 416_1 is exposed, a part of the top surface of the oxide 406b1 is exposed and the portion where the surface of the conductor 416_2 is exposed (region 406W1) is etched. Thus, a part of the top surface of the oxide 406b2 is exposed, and a part where the surface of the conductor 416_3 is exposed (region 406W2) is etched, so that a part of the top surface of the oxide 406b3 is exposed ( (See FIG. 21A, FIG. 21B, FIG. 21C, and FIG. 21D.)

  Note that by the dry etching treatment so far, impurities caused by the etching gas are attached or diffused on the surface or inside of the oxide 406a1, the oxide 406b1, the oxide 406a2, the oxide 406b2, the oxide 406a3, the oxide 406b3, and the like. There are things to do. Examples of impurities include fluorine and chlorine.

  Cleaning is performed in order to remove the impurities and the like. As the cleaning method, there are wet cleaning using a cleaning liquid, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

  As the wet cleaning, cleaning may be performed using an aqueous solution obtained by diluting oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning using pure water or carbonated water is performed.

  Next, third heat treatment may be performed. The first heat treatment condition described above can be used as the heat treatment condition. By the heat treatment, the concentration of the impurity can be reduced. Further, the moisture concentration and the hydrogen concentration in the oxide 406a1, the oxide 406b1, the oxide 406a2, the oxide 406b2, the oxide 406a3, and the oxide 406b3 can be reduced. . Note that the third heat treatment may not be performed. In this embodiment, the third heat treatment is not performed.

  Next, an oxide 406c (not shown) to be the oxide 406c1 and the oxide 406c2 is formed. The oxide 406c can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In particular, it is preferable to form a film using a sputtering method. Note that an oxide having the same composition as the oxide 406b is preferably formed as the oxide 406c. When the oxide 406b and the oxide 406c have the same composition, the electron affinity of the oxide 406b and the electron affinity of the oxide 406c are equal to each other, or the difference in electron affinity is reduced. Therefore, the interface state density between the oxide 406b and the oxide 406c can be reduced. By reducing the interface state density, a reduction in on-state current of the transistor 1000 can be prevented.

  For example, in the case where an In-M-Zn oxide is used as the oxide 406c and the oxide 406b, the oxide film 406c and the oxide film 406b are preferably formed so that the atomic ratio of each metal element is approximately the same. Specifically, when a film is formed using a sputtering method, the film may be formed using a target having the same atomic ratio of each metal element. As the sputtering gas, a mixed gas of oxygen and argon is used, and the proportion of oxygen contained in the sputtering gas may be 0% or more, preferably 80% or more, more preferably 100%.

  In this embodiment, in this embodiment, the oxide 406c is contained in the sputtering gas by a sputtering method with a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. The film is formed with an oxygen ratio of 100%.

  When the oxide 406c to be the oxide 406c1 and the oxide 406c2 is formed under the above conditions, excess oxygen can be injected into the oxide 406a1, the oxide 406b1, and the insulator 402, which is preferable.

  Next, an insulator 412 (not shown) to be the insulator 412a1 and the insulator 412a2 is formed over the oxide 406c. The insulator 412 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Here, fourth heat treatment can be performed. The first heat treatment condition can be used for the heat treatment. Through the heat treatment, the moisture concentration and the hydrogen concentration in the insulator 412 can be reduced. Note that the fourth heat treatment may not be performed. In this embodiment, the fourth heat treatment is not performed.

  Next, a film 404a (not shown) to be the conductors 404a1 and 404a2 is formed over the insulator 412. The conductor 404a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Note that an oxide formed using the same conditions as the above-described oxide 404c may be provided under the conductor 404a. By including the oxide, oxygen can be added to the insulator 412. Oxygen added to the insulator 412 becomes excess oxygen and can be diffused into the oxide 406a1, the oxide 406b1, the oxide 406c1, and the oxide 406c2 by heat treatment or the like thereafter.

  Next, a conductor is formed over the oxide by a sputtering method, whereby the electric resistance value of the oxide can be reduced to obtain a conductor. This can be called an OC (Oxide Conductor) electrode. A conductor may be further formed on the conductor on the OC electrode by a sputtering method or the like.

  In this embodiment, titanium nitride is formed by a sputtering method as the conductor to be the conductor 404a.

  Next, a conductor 404b (not shown) to be the conductor 404b1 and the conductor 404b2 is formed over the conductor 404a. The conductor 404b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, tungsten is formed by a sputtering method as the conductor to be the conductor 404b.

  Here, fifth heat treatment can be performed. The first heat treatment condition can be used for the heat treatment. Note that the fifth heat treatment may not be performed. In this embodiment, the fifth heat treatment is not performed.

  Next, the conductor 404a and the conductor 404b are processed by a lithography method, so that the conductor 404a1, the conductor 404b1, the conductor 404a2, and the conductor 404b2 are formed.

  Next, an insulator 418a (not shown) to be the insulator 418a1 and the insulator 418a2 is formed. The insulator 418a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, an aluminum oxide film is formed as the insulator 418a by an ALD method. By using the ALD method, aluminum oxide having a uniform thickness can be formed on the top and side surfaces of the conductors 404b1 and 404b2, so that oxidation of the conductors 404b1 and 404b2 can be prevented. can do.

  Next, the insulator 418a, the insulator 412, and the oxide 406c are processed by a lithography method, so that the insulator 418a1, the insulator 418a2, the insulator 412a1, the insulator 412a2, the oxide 406c1, and the oxide 406c2 are formed ( (See FIG. 22A, FIG. 22B, FIG. 22C, and FIG. 22D.)

  Here, in the transistor 1000, an end portion of the insulator 418a1, an end portion of the insulator 412a1, and an end portion of the oxide 406c1 are flush with each other, and over the barrier film 417a1 and the barrier film 417a2 in the channel length direction. And disposed on the insulator 402 in one of the channel width directions. Similarly, in the transistor 2000, the end portion of the insulator 418a2, the end portion of the insulator 412a2, and the end portion of the oxide 406c2 are flush with each other, and over the barrier film 417b1 and the barrier film 417b2 in the channel length direction. Arranged on the insulator 402 in one of the channel width directions.

  In this manner, it is preferable to process the insulator 418a, the insulator 412, and the oxide 406c at a time because the interface between the insulator 412 and the oxide 406c is hardly damaged. Further, by forming the insulator 418a1 and the insulator 418a2 so as to cover the conductor 404b1 and the conductor 404b2, it is possible to prevent consumption of excess oxygen due to oxidation of the conductor 404b1 and the conductor 404b2. .

  Next, the insulator 410 is formed. The insulator 410 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Alternatively, a spin coating method, a dip method, a droplet discharge method (such as an ink jet method), a printing method (such as screen printing or offset printing), a doctor knife method, a roll coater method, or a curtain coater method can be used.

  The insulator 410 may be formed so that the upper surface has flatness. For example, the insulator 410 may have a flat upper surface immediately after film formation. Alternatively, for example, the insulator 410 may have flatness by removing the insulator and the like from the upper surface so that the insulator 410 is parallel to a reference surface such as the back surface of the substrate after film formation. Such a process is called a flattening process. Examples of the planarization process include a CMP process and a dry etching process. However, the upper surface of the insulator 410 may not have flatness.

  Next, the insulator 420 is formed over the insulator 410. The insulator 420 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIGS. 23A, 23B, 23C, and 23C). (See FIG. 23D.)

  As the insulator 420, oxygen can be added to the insulator 410 by, for example, forming an aluminum oxide film by a sputtering method using oxygen plasma. The added oxygen becomes excess oxygen in the insulator 410. The excess oxygen is added to the oxide 406a1, the oxide 406b1, the oxide 406c1, and the oxide 406c2 by heat treatment or the like, and is added to the oxide 406a1, the oxide 406b1, the oxide 406c1, and the oxidation. The oxygen defect in the object 406c2 can be repaired. Further, the moisture concentration and the hydrogen concentration in the insulator 410 can be reduced.

  The insulator 420 may have a multilayer structure. For example, an aluminum oxide film may be formed by a sputtering method, and the aluminum oxide film may be formed on the aluminum oxide by an ALD method. Alternatively, an aluminum oxide film may be formed by an ALD method, and the aluminum oxide film may be formed on the aluminum oxide by a sputtering method.

  Here, sixth heat treatment can be performed. The first heat treatment condition can be used for the heat treatment. By performing the heat treatment, the moisture concentration and the hydrogen concentration in the insulator 410 can be reduced. In this embodiment, treatment is performed at a temperature of 350 ° C. for 1 hour in an oxygen atmosphere.

  Through the above steps, the transistor 1000 illustrated in FIG. 11 and the transistor 2000 illustrated in FIG. 12 can be manufactured.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 4)
In this embodiment, the transistor described in Embodiment 1 can be used, and a CPU including the memory device described in Embodiment 2 is described.

  FIG. 24 is a block diagram illustrating a configuration example of a CPU using at least part of the transistor described in the above embodiment.

  24 includes an ALU 1191 (ALU: Arithmetic Logic Unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 24 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, a configuration including a CPU or an arithmetic circuit illustrated in FIG. 24 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. The number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, and 64 bits.

  Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

  The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

  In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

  In the CPU illustrated in FIG. 24, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in Embodiment 1 or the memory device described in Embodiment 2 can be used.

  In the CPU illustrated in FIG. 24, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
A semiconductor device according to one embodiment of the present invention can reproduce an image reproducing device including a display device, a personal computer, and a recording medium (typically, a recording medium such as a DVD: Digital Versatile Disc and display the image) It can be used for a device having a display. In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.

  FIG. 25A is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like. The automobile 2980 includes an antenna, a battery, and the like.

  An information terminal 2910 illustrated in FIG. 25B includes a housing 2911 including a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation switch 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. In addition, the information terminal 2910 includes an antenna, a battery, and the like inside the housing 2911. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

  A laptop personal computer 2920 illustrated in FIG. 25C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like. The laptop personal computer 2920 includes an antenna, a battery, and the like inside the housing 2921.

  A video camera 2940 illustrated in FIG. 25D includes a housing 2941, a housing 2942, a display portion 2944, operation switches 2944, a lens 2945, a connection portion 2946, and the like. The operation switch 2944 and the lens 2945 are provided in the housing 2941, and the display portion 2944 is provided in the housing 2942. In addition, the video camera 2940 includes an antenna, a battery, and the like inside the housing 2941. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

  FIG. 25E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. In addition, an antenna, a battery, and the like are provided inside the information terminal 2950 and the housing 2951. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

  FIG. 25F illustrates an example of a wristwatch type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, an operation switch 2965, an input / output terminal 2966, and the like. Further, an antenna, a battery, and the like are provided inside the information terminal 2960 and the housing 2961. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

  The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation switch 2965 can have various functions such as time setting, power on / off operation, wireless communication on / off operation, manner mode execution and cancellation, and power saving mode execution and cancellation. . For example, the function of the operation switch 2965 can be set by an operating system incorporated in the information terminal 2960.

  In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, a hands-free call can be made by communicating with a headset capable of wireless communication. In addition, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. In addition, charging can be performed through the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

  For example, a memory device including the semiconductor device of one embodiment of the present invention can hold control information, a control program, and the like of the above electronic devices for a long period. With the use of the semiconductor device according to one embodiment of the present invention, a highly reliable electronic device can be realized.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 6)
In this embodiment, an example of using an RF tag that can include the semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Applications of RF tags are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 26A), recording media (DVD and video tape) , See FIG. 26B), packaging containers (wrapping paper, bottles, etc., see FIG. 26C), vehicles (bicycles, etc., see FIG. 26D), personal items (鞄And glasses, see FIG. 26E), foods, plants, animals, human body, clothing, daily necessities, medical products including medicines and drugs, or electronic devices (liquid crystal display devices, EL display devices, A television device or a mobile phone) or a tag attached to each item (see FIG. 26F) can be used.

  The RF tag 4000 according to one embodiment of the present invention is fixed to an article by being attached to or embedded in the surface. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 4000 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the product itself after being fixed to the product. In addition, by providing the RF tag 4000 according to one embodiment of the present invention on bills, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided. Counterfeiting can be prevented. In addition, by attaching the RF tag according to one embodiment of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of inspection systems and the like can be improved. Can be planned. Even in the case of vehicles, security against theft can be improved by attaching the RF tag 4000 according to one embodiment of the present invention.

  As described above, by using the RF tag 4000 according to one embodiment of the present invention for each application described in this embodiment, operating power including writing and reading of information can be reduced, so the maximum communication distance is increased. It becomes possible. In addition, even when power is cut off, information can be retained for a very long period of time, and thus can be suitably used for applications where the frequency of writing and reading is low.

  Next, an example of using a display device that can include the semiconductor device of one embodiment of the present invention is described. As an example, the display device includes a pixel. A pixel has a transistor and a display element, for example. Alternatively, the display device includes a driver circuit that drives pixels. The drive circuit includes, for example, a transistor. For example, the transistors described in other embodiments can be used as these transistors.

  For example, in this specification and the like, a display element, a display device that is a device including a display element, a light-emitting element, and a light-emitting device that is a device including a light-emitting element have various forms or have various elements. Can do. A display element, a display device, a light emitting element, or a light emitting device includes, for example, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, Blue LED, etc.), transistor (transistor that emits light in response to current), electron-emitting device, liquid crystal device, electronic ink, electrophoretic device, GLV (grating light valve), PDP (plasma display panel), MEMS (micro electro・ Display element using mechanical system, DMD (digital micromirror device), DMS (digital micro shutter), IMOD (interferometric modulation) element, shutter type MEMS display element, optical interference type MEMS display Child, electrowetting element, a piezoelectric ceramic display, has at least one such display device using a carbon nanotube. In addition to these, a display medium in which contrast, luminance, reflectance, transmittance, and the like are changed by an electric or magnetic action may be included. An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is an FED (Field Emission Display) or a SED type flat display (SED: Surface-Conduction Electron-Emitter Display). As an example of a display device using a liquid crystal element, there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like. An example of a display device using electronic ink or an electrophoretic element is electronic paper. Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced. In addition, when using LED, you may arrange | position graphene or graphite under the electrode and nitride semiconductor of LED. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor such as an n-type GaN semiconductor having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor having a crystal or the like can be provided thereon to form an LED. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor having a crystal. Note that the GaN semiconductor included in the LED may be formed by MOCVD. However, by providing graphene, the GaN semiconductor included in the LED can be formed by a sputtering method.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 20 Semiconductor device 100 Circuit 106 Electron capture level 107 Electron 110 Memory cell 112 Transistor 114 Capacitance element 120 Storage device 130 Memory cell 131 Capacitance element 140 Storage device 150 Register circuit 151 Inverter 152 Inverter 153 Flip-flop circuit 154 Capacitance element 170 Pixel 171 Capacitance element 172 Display element 180 Display device 200 Circuit 301 Insulator 302 Insulator 303 Insulator 310_1 Conductor 310_2 Conductor 310a1 Conductor 310a2 Conductor 310b1 Conductor 310b2 Conductor 400 Substrate 401 Insulator 402 Insulator 404_1 Conductor 404_2 conductor 404a conductor 404a1 conductor 404a2 conductor 404b conductor 404b1 conductor 404b2 conductor 406a oxide 406a1 Oxide 406a2 Oxide 406a3 Oxide 406b Oxide 406b1 Oxide 406b2 Oxide 406b3 Oxide 406c Oxide 406c1 Oxide 406c2 Oxide 406W1 Region 406W2 Region 410 Insulator 411 Conductor 411a Conductor 411b Conductor 411a1 Conductor 411a2 Conductor Body 411b1 conductor 411b2 conductor 412 insulator 412a1 insulator 412a2 insulator 416 conductor 416_1 conductor 416_2 conductor 416_3 conductor 416a1 conductor 416a2 conductor 416b1 conductor 416b2 conductor 417 insulator 417 insulator 417 insulator 417 insulator 417 insulator 417 insulator Barrier film 417a2 barrier film 417b1 barrier film 417b2 barrier film 418a insulator 418a1 insulator 418a2 insulator 420 insulator 421 Str 1000 Transistor 1189 ROM interface 1190 Substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
2000 Transistor 2910 Information terminal 2911 Case 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Operation switch 2916 External connection unit 2917 Microphone 2920 Notebook personal computer 2921 Case 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Case 2942 Case 2943 Display unit 2944 Operation switch 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Case 2952 Display unit 2960 Information terminal 2961 Case 2962 Display unit 2963 Band 2964 Buckle 2965 Operation switch 2966 Input / output terminal 2967 Icon 2980 Car 2981 Car body 2982 Wheel 2983 Dash Board 2984 Light 4000 RF tag

Claims (17)

A first gate;
An insulator on the first gate;
First and second conductors on the insulator;
A first oxide on the insulator, the first and second conductors;
A first transistor having a second gate on the first oxide;
A third gate;
A second oxide on the third gate;
A second transistor having a fourth gate on the second oxide;
A semiconductor device having a capacitive element,
The first conductor, the third gate, and one electrode of the capacitor are electrically connected,
In the region where the second gate and the first conductor overlap, the length of the first gate in the channel width direction is shorter than the length of the first conductor in the channel width direction. A semiconductor device characterized by the above. In claim 1,
In a region where the second gate and the second conductor overlap, the length of the first gate in the channel width direction is shorter than the length of the second conductor in the channel width direction. A semiconductor device characterized by the above. In claim 1 or claim 2,
A semiconductor device, wherein a threshold voltage of the first transistor is larger than a threshold voltage of the second transistor. In any one of Claims 1 thru | or 3,
The insulator has first to third insulating films,
The semiconductor device according to claim 1, wherein the first and third insulating films have an electron affinity smaller than that of the second insulating film. In any one of Claims 1 thru | or 4,
The semiconductor device according to claim 1, wherein the first and third insulating films have a band gap larger than that of the second insulating film. In any one of Claims 1 thru | or 5,
The first oxide has a channel formation region of the first transistor;
The second oxide has a channel formation region of the second transistor;
The semiconductor device, wherein the first conductor has a function of one of a source and a drain of the first transistor. In any one of Claims 1 thru | or 6,
The semiconductor device, wherein the first conductor and the second gate are not electrically connected. In any one of Claims 1 thru | or 7,
The semiconductor device, wherein the first conductor and the second gate are electrically connected. In any one of Claims 1 thru | or 8,
The semiconductor device, wherein the first and second oxides include a metal oxide. A first gate;
An insulator on the first gate;
First and second conductors on the insulator;
A first oxide on the insulator, the first and second conductors;
A first transistor having a second gate on the first oxide;
A third gate;
A second oxide on the third gate;
A second transistor having a fourth gate on the second oxide;
A capacitive element;
An operation method of a semiconductor device in which the first conductor, the third gate, and one electrode of the capacitor are electrically connected,
The first transistor includes:
Applying a first positive potential to the first gate and injecting a first charge into the insulator;
Applying a ground potential to the first gate to hold the first charge in the insulator;
Applying a second positive potential smaller than the first positive potential to the second gate;
Applying a first negative potential to the second conductor;
A method for operating a semiconductor device, wherein a ground potential is applied to the first and second gates and the second conductor to hold a second charge in the capacitor. In claim 10,
The method for operating a semiconductor device, wherein a threshold voltage of the first transistor is larger than a threshold voltage of the second transistor. In claim 10 or claim 11,
The insulator has first to third insulating films,
The method for operating a semiconductor device, wherein the first and third insulating films have an electron affinity smaller than that of the second insulating film. In any one of Claims 10 to 12,
The method of operating a semiconductor device, wherein the first and third insulating films have a band gap larger than that of the second insulating film. In any one of Claims 10 to 13,
The first oxide has a channel formation region of the first transistor;
The second oxide has a channel formation region of the second transistor;
The method of operating a semiconductor device, wherein the first conductor has a function of one of a source and a drain of the first transistor. In any one of Claims 10 to 14,
The method for operating a semiconductor device, wherein the first conductor and the second gate are not electrically connected to each other. In any one of Claims 10 to 15,
The method for operating a semiconductor device, wherein the first conductor and the second gate are electrically connected. In any one of Claims 10 to 16,
The method for operating a semiconductor device, wherein the first oxide and the second oxide include a metal oxide.

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