JP2018207038A - Semiconductor device, storage device, and electronic device - Google Patents

Abstract

To provide a semiconductor device having a large storage capacity.SOLUTION: A semiconductor device comprises first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. An opening is provided as a whole on a structure obtained by sequentially laminating the first insulator, the first conductor, the second insulator, the second conductor, and the third insulator. Further, at the opening, the second conductor is selectively removed by etching processing. Thereafter, the fourth insulator is formed on a lateral face of the opening, and the third conductor is formed in a region from which the second conductor is removed. At the remaining opening, the first semiconductor, the fifth insulator, and the second semiconductor are sequentially formed to manufacture a semiconductor device having a three-dimension structure. In addition, as the first semiconductor, a material containing metal oxide can be applied, and as the second semiconductor, a material containing metal oxide or silicon can be applied.SELECTED DRAWING: Figure 10

Description

  One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, the technical field of one embodiment of the present invention disclosed in this specification more specifically includes a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, an imaging device, a memory device, a processor, an electronic device, As an example, a driving method, a manufacturing method thereof, an inspection method thereof, or a system having at least one of them can be cited.

  In recent years, electronic components such as a central processing unit (CPU), a graphics processing unit, a storage device, and a sensor have been used in various electronic devices such as personal computers, smartphones, and digital cameras. Improvements are progressing in various aspects such as low power consumption.

  In particular, in recent years, the amount of data handled in the electronic devices described above has increased, and a storage device having a large storage capacity has been demanded. Patent Documents 1 and 2 disclose a semiconductor device that can write and read multi-value data. In order to realize a storage device having a large storage capacity, a technique for miniaturizing a circuit included in the storage device is required.

JP 2012-256400 A JP 2014-199707 A

  An object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a memory device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device using a memory device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide a memory device with a large data capacity. Another object of one embodiment of the present invention is to provide a highly reliable memory device.

  Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not disturb the existence of other problems. Other issues are issues not mentioned in this section, which are described in the following description. Problems not mentioned in this item can be derived from descriptions of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the above-described description and other problems. Note that one embodiment of the present invention does not have to solve all of the above listed description and other problems.

(1)
One embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor, and the first conductor is a first conductor. The second insulator is provided on the upper surface of the first insulator, the second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided in the third surface. The fourth insulator includes a side surface of the first insulator, a side surface of the first conductor, a side surface of the second insulator, a second upper surface of the second insulator, The third conductor is connected to a region including the side surface of the second conductor, the second lower surface of the third insulator, and the side surface of the third insulator, and the third conductor is formed with the fourth insulator. In the region overlapping with the side surface of the second conductor, and the first semiconductor is the first insulator in the region where the formation surface of the third conductor and the fourth insulator are formed. An area overlapping with the side surface of A region overlapping with the side surface of the second conductor, a region overlapping with the side surface of the second insulator, and a region overlapping with the side surface of the third insulator; and the fifth insulator is formed of the first semiconductor The second semiconductor is provided on a surface where the fifth insulator is formed.

(2)
Alternatively, one embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, and first to third semiconductors, and the first conductor is a first conductor. The first conductor is provided on the first upper surface of the insulator, the first conductor is provided on the first lower surface of the second insulator, the second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided. Is provided on the first lower surface of the third insulator, and the third semiconductor includes a second upper surface of the first insulator, a side surface of the first conductor, and a second lower surface of the second insulator. And the fourth insulator includes a side surface of the first insulator, a formation surface of the first semiconductor, a side surface of the second insulator, a second upper surface of the second insulator, and a side surface of the second conductor. And a second lower surface of the third insulator and a side surface of the third insulator so as to be continuous with the region, and the third conductor is the first of the regions where the fourth insulator is formed. 2 In the area overlapping the side of the conductor The first semiconductor includes a formation surface of the third conductor, a region overlapping the side surface of the first insulator, and a region overlapping the formation surface of the third semiconductor, in the region where the fourth insulator is formed. , In a region overlapping with the side surface of the second insulator, and in a region overlapping with the third insulator, the fifth insulator is provided on the formation surface of the first semiconductor, and the second semiconductor is A semiconductor device is provided on a surface where an insulator is formed.

(3)
Alternatively, one embodiment of the present invention is a semiconductor device including first to fourth insulators, first to fourth conductors, a first semiconductor, and a second semiconductor, and the first insulator includes: The first conductor has a first upper surface, the second conductor has a first insulator on the first upper surface, the second insulator has a third conductor on the first lower surface, and the second conductor has a second conductor. The conductor is provided on the first lower surface of the second insulator, and the third insulator includes the side surface of the first conductor, the second upper surface of the first conductor, the side surface of the first insulator, and the first insulator. The second upper surface of the insulator, the side surface of the second conductor, the second lower surface of the second insulator, the side surface of the second insulator, the second lower surface of the third conductor, and the side surface of the third conductor The fourth conductor has a region overlapping the side surface of the first insulator and a region overlapping the side surface of the second conductor in the region where the third insulator is formed. And overlaps the side surface of the second insulator The first semiconductor has a formation surface of the fourth conductor, a region where the third insulator is formed, a region overlapping with the first conductor, and a third conductor overlapping The semiconductor device is characterized in that the fourth insulator has a formation surface of the first semiconductor and the second semiconductor has a formation surface of the fourth insulator.

(4)
Alternatively, according to one embodiment of the present invention, in any of the above (1) to (3), the semiconductor device includes a sixth insulator and a fifth conductor, and the sixth insulator is provided on a formation surface of the second semiconductor. The fourth conductor is a semiconductor device having a formation surface of the sixth insulator.

(5)
Alternatively, according to one embodiment of the present invention, in any of (1) to (4), the first semiconductor includes a metal oxide.

(6)
Alternatively, according to one embodiment of the present invention, in any of (1) to (5), the second semiconductor includes a metal oxide.

(7)
Alternatively, according to one embodiment of the present invention, in any of the above (1) to (5), the second semiconductor includes silicon.

(8)
Another embodiment of the present invention is a memory device including the semiconductor device described in any one of (1) to (7) and a peripheral circuit.

(9)
Another embodiment of the present invention is an electronic device including the storage device according to (8) and a housing.

  According to one embodiment of the present invention, a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a memory device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device using a memory device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a memory device with a large data capacity can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable memory device can be provided.

  Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are effects not mentioned in this item described in the following description. Effects not mentioned in this item can be derived from the description of the specification or drawings by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Accordingly, one embodiment of the present invention may not have the above-described effects depending on circumstances.

FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor device. FIG. 10 is a circuit diagram illustrating a configuration example of a semiconductor device. 6 is a flowchart illustrating an operation example of a semiconductor device. 8A and 8B are a top view and a cross-sectional view illustrating a structure example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. 9 is a cross-sectional view illustrating a manufacturing example of a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. FIG. 10 is a cross-sectional view illustrating a semiconductor device. 1 is a block diagram illustrating an example of a storage device. The figure explaining the range of atomic ratio of a metal oxide. The block diagram explaining CPU. The perspective view which shows the example of an electronic device. The perspective view which shows the example of an electronic device.

  In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, in the case where a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide is abbreviated to a metal oxide semiconductor (metal oxide semiconductor). It can be called OS. In the case of describing as an OS FET, it can be said to be a transistor including a metal oxide or an oxide semiconductor.

  In this specification and the like, a transistor including silicon in a channel formation region may be referred to as a Si transistor.

  In this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

(Embodiment 1)
In this embodiment, a circuit configuration, an operation method, and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. In the following description, for example, “[x, y]” means an element in the x-th column and the y-th column, and “[z]” means an element in the z-th row or the z-th column. When there is no need to specify a row or a column, these notations are omitted.

<Circuit configuration example>
First, a circuit configuration of the semiconductor device is described with reference to FIG. FIG. 1A shows a circuit diagram of n (n is an integer of 1 or more) memory cells. That is, the memory cells MC [1] to MC [n], the wirings WWL [1] to WWL [n] for controlling them, the wirings RWL [1] to RWL [n], A wiring WBL and a wiring RBL are included. Note that the wiring WWL functions as a writing word line, the wiring RWL functions as a reading word line, the wiring WBL functions as a writing bit line, and the wiring RBL functions as a reading bit line.

  Each memory cell MC includes a transistor WTr, a transistor RTr, and a capacitor element CS. The transistor RTr illustrated in FIG. 1A is a transistor having a back gate, and the threshold voltage of the transistor RTr can be changed by applying a potential to the back gate. Note that the wiring BGL illustrated in FIG. 1A is electrically connected to the back gate of the transistor RTr included in each of the memory cells MC [1] to MC [n]. In the semiconductor device illustrated in FIG. 1, the wiring BGL is not electrically connected to each of the back gates of the transistors RTr included in the memory cells MC [1] to MC [n]. For example, a configuration may be adopted in which the electric potentials are independently connected to each other to supply different electric potentials.

  The channel formation region of the transistor WTr preferably includes a metal oxide described in Embodiment 3. In particular, in the case of one or a plurality of metal oxides selected from indium, element M (element M, for example, aluminum, gallium, yttrium, tin, and the like) and zinc, the metal oxide functions as a wide gap semiconductor. Therefore, a transistor in which the metal oxide is included in a channel formation region has a characteristic of extremely low off-state current. By applying a transistor having this characteristic as the transistor WTr that retains data, data can be retained in the memory cell MC for a long time. As a result, the number of refreshes of stored data can be reduced, so that power consumption of the semiconductor device can be reduced.

  For the channel formation region of the transistor RTr, a material that can increase the field-effect mobility of the transistor is preferably used. By using such a transistor, the semiconductor device can be operated more quickly. For example, as a material included in the channel formation region of the transistor RTr, a semiconductor material such as a metal oxide or silicon described in Embodiment 3 can be used.

  The transistor WTr functions as a writing transistor, and the transistor RTr functions as a reading transistor. The transistor WTr is switched between an on state and an off state by a potential applied to the wiring WWL. The potential of one electrode of the capacitor CS is controlled by the wiring RWL. The other electrode of the capacitor element CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitor CS can be rephrased as a memory node. The memory node of each memory cell MC is electrically connected to the first terminal of the transistor WTr included in the memory cell MC.

  The second terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr of the adjacent memory cell MC in terms of circuit configuration. Similarly, the first terminal of the transistor RTr is electrically connected in series with the second terminal of the transistor RTr of the adjacent memory cell. A second terminal of the transistor WTr included in the memory cell MC [n] is electrically connected to the wiring WBL, and a second terminal of the transistor RTr included in the memory cell MC [n] is electrically connected to the wiring RBL. Has been. Note that in this embodiment, a connection point between the second terminal of the transistor RTr included in the memory cell MC [n] and the wiring RBL is referred to as a node N1, and the first terminal of the transistor RTr included in the memory cell MC [1]. Is referred to as node N2. Note that a selection transistor may be connected in series with the transistor RTr in order to control a conduction state between the node N1 and the wiring RBL. Similarly, a selection transistor may be connected in series with the transistor RTr in order to control a conduction state between the wiring connected to the node N2 and the node N2.

  Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. One embodiment of the present invention can have a circuit structure in which the semiconductor device illustrated in FIG. 1A is changed as appropriate depending on circumstances or circumstances. For example, as illustrated in FIG. 1B, one embodiment of the present invention may be a semiconductor device in which a back gate is also provided in the transistor WTr if necessary. Note that the semiconductor device illustrated in FIG. 1B includes a transistor WTr included in the memory cells MC [1] to MC [n] in addition to the structure of the semiconductor device illustrated in FIG. The back gate is provided, and the back gate is electrically connected to the wiring BGL. For example, as illustrated in FIG. 1C, one embodiment of the present invention may be a semiconductor device in which a back gate is not provided in the transistor RTr and the transistor WTr.

  By the way, when it is desired to further increase the storage capacity of the semiconductor device shown in FIGS. 1A, 1B, and 1C, the semiconductor devices shown in FIGS. 1A, 1B, and 1C are arranged in a matrix. do it. For example, when the semiconductor devices illustrated in FIG. 1B are arranged side by side in a matrix, the circuit configuration is as illustrated in FIG.

  The semiconductor device illustrated in FIG. 2 includes the semiconductor device illustrated in FIG. 2B arranged in m columns (m is an integer greater than or equal to 1). The wiring RWL and the wiring WWL are arranged in the same row. The memory cell MC is electrically connected so as to be shared. That is, the semiconductor device illustrated in FIG. 2 is a matrix semiconductor device having n rows and m columns, and includes the memory cells MC [1,1] to MC [n, m]. Therefore, the semiconductor device illustrated in FIG. 2 includes the wirings RWL [1] to RWL [n], the wirings WWL [1] to WWL [n], the wirings RBL [1] to RBL [m], the wirings WBL [1] to WBL [m] are electrically connected to each other by wirings BGL [1] to BGL [m]. Specifically, one electrode of the capacitor CS of the memory cell MC [j, i] (j is an integer of 1 to n and i is an integer of 1 to m) is connected to the wiring RWL [ j] and the gate of the transistor WTr of the memory cell MC [j, i] is electrically connected to the wiring WWL [j]. The wiring WBL [i] is electrically connected to the second terminal of the transistor WTr of the memory cell MC [n, i], and the wiring RBL [i] is the second of the transistor RTr of the memory cell MC [n, i]. It is electrically connected to the terminal.

  2 illustrates the memory cell MC [1,1], the memory cell MC [1, i], the memory cell MC [1, m], the memory cell MC [j, 1], and the memory cell MC [j, i]. , Memory cell MC [j, m], memory cell MC [n, 1], memory cell MC [n, i], memory cell MC [n, m], wiring RWL [1], wiring RWL [j], wiring RWL [n], wiring WWL [1], wiring WWL [j], wiring WWL [n], wiring RBL [1], wiring RBL [i], wiring RBL [m], wiring WBL [1], wiring WBL [ i], wiring WBL [m], wiring BGL [1], wiring BGL [i], wiring BGL [m], capacitor element CS, transistor WTr, transistor RTr, node N1, and node N2 are shown. Wiring, elements, symbols, and symbols are omitted.

  FIG. 3 shows the semiconductor device shown in FIG. 2C arranged in m rows (m is an integer of 1 or more). Note that the semiconductor device illustrated in FIG. 3 has a structure in which each transistor included in all the memory cells MC does not include a back gate. Therefore, the semiconductor device illustrated in FIG. 3 does not include the wiring BGL. . Note that the description of the semiconductor device in FIG. 2 is referred to for the semiconductor device in FIG.

<Example of operation>
Next, an example of an operation method of the semiconductor device illustrated in FIGS. 1A to 1C is described. Note that the low-level potential and the high-level potential used in the following description do not mean specific potentials, and the specific potential may be different if the wiring is different. For example, the low level potential and the high level potential applied to the wiring WWL may be different from the low level potential and the high level potential applied to the wiring RWL.

  In this operation method example, the transistor RTr and the transistor WTr are normal in the wiring BGL shown in FIGS. 1A and 1B and the BGW [1] to BGW [n] shown in FIG. It is assumed that a potential within a range of operating in advance is applied in advance. Therefore, the operations of the semiconductor devices illustrated in FIGS. 1A to 1C can be considered in the same manner.

  FIG. 4A is a timing chart showing an operation example of writing data to the semiconductor device, and FIG. 4B is a timing chart showing an operation example of reading data from the semiconductor device. Each of the timing charts in FIGS. 4A and 4B includes a wiring WWL [1], a wiring WWL [2], a wiring WWL [n], a wiring RWL [1], a wiring RWL [2], and a wiring RWL [n. ], Changes in the magnitudes of the potentials of the nodes N1 and N2 are shown. A wiring WBL indicates data supplied to the wiring WBL.

  FIG. 4A illustrates an example in which data D [1] to data D [n] are written in the memory cells MC [1] to MC [n], respectively. Note that the data D [1] to D [n] can be binary or multivalued. Data D [1] to data D [n] are supplied from the wiring WBL. That is, in the circuit configuration of the semiconductor device illustrated in FIGS. 1A to 1C, data is sequentially written from the memory cell MC [1] to the memory cell MC [n].

  On the other hand, when data is written to the memory cell MC [1] after data is written to the memory cell MC [2], the data written to the memory cell MC [2] is once read and moved to another location. If not stored, the data held in the memory cell MC [2] will be lost when the data is written to the memory cell MC [1].

  In the circuit configuration of the semiconductor device illustrated in FIGS. 1A to 1C, when data is written to the memory cell MC [i] (i is an integer of 2 to n), the memory cell MC [1] is written. In order to prevent rewriting of data held in the memory cell MC [i−1], a low-level potential is supplied to the wiring WWL [1] to WWL [i−1] so that the memory cells MC [1] to Each transistor WTr included in the memory cell MC [i−1] is turned off. Accordingly, each data held in the memory cells MC [1] to MC [i-1] can be protected.

  In addition, when data is written to the memory cell MC [i], data is supplied from the wiring WBL. Therefore, a high-level potential is supplied to the wiring WWL [i] to the wiring WWL [n], so that the memory cell MC [i] ] To each transistor WTr included in the memory cell MC [n] are sufficiently turned on. Thereby, data can be held in the memory node of the memory cell MC [i].

  Note that in the case where data is written to the circuit configuration of the semiconductor device illustrated in FIGS. 1A to 1C, the wiring RBL can be controlled independently; therefore, a specific potential is not necessary; be able to. In addition, the potential of the wiring RWL, that is, the node N1, can be a low-level potential. In addition, the potential of the node N2 can be a low level potential.

  Based on the above, an operation example shown in the timing chart of FIG. 4A will be described. At time T10, the potentials of the wirings WWL [1] to WWL [n], the wirings RWL [1] to RWL [n], the wiring WBL, the node N1, and the node N2 are low level potentials. .

  At time T11, a high-level potential is supplied to the wirings WWL [1] to WWL [n]. Accordingly, the transistors WTr included in the memory cells MC [1] to MC [n] are sufficiently turned on. Then, data D [1] is supplied to the wiring WBL. Since the transistors WTr included in the memory cells MC [1] to MC [n] are sufficiently on, the data D [1] reaches the memory node of the memory cell MC [1]. Written.

  At time T12, the low-level potential is supplied to the wiring WWL [1], and the high-level potential is continuously supplied to the wirings WWL [2] to WWL [n]. Accordingly, the transistor WTr included in the memory cell MC [1] is turned off, and the transistors WTr included in the memory cells MC [2] to MC [n] are sufficiently turned on. Then, the data D [2] is supplied to the wiring WBL. Since the transistors WTr included in the memory cells MC [2] to MC [n] are sufficiently on, the data D [2] reaches the memory node of the memory cell MC [2]. Written. Further, since the transistor WTr of the memory cell MC [1] is in an off state, the data D [1] held in the memory cell MC [1] is lost by the write operation from time T12 to time T13. I will not.

  Between time T13 and time T14, the data D [1] write operation to the memory cell MC [1] between time T11 and time T12 and the memory cell MC [between time T12 and time T13 [ 2], the data D [3] to the data D [n− are sequentially transferred to the memory cells MC [3] to MC [n−1], respectively. 1] is written. Specifically, the transistors WTr included in the memory cells MC [1] to MC [j−1] (j is an integer of 3 to n−1) in which data is already written are turned off. The transistors WTr included in the memory cells MC [j] to MC [n] in which no data is written are sufficiently turned on, and the data D [j] is supplied from the wiring WBL, so that the memory cells MC [j] Write to the memory node. When the writing of the data D [j] to the memory cell MC [j] is completed, the transistor WTr included in the memory cell MC [j] is turned off, and the data D [j + 1] is supplied from the wiring WBL. An operation of writing to the memory node of the memory cell MC [j + 1] may be performed. Note that the writing operation when j is n−1 indicates the operation from time T14 to time T15 described below.

  At time T14, the low-level potential is supplied to the wirings WWL [1] to WWL [n−1], and the high-level potential is continuously supplied to the wiring WWL [n]. Accordingly, the transistors WTr included in the memory cells MC [1] to MC [n−1] are turned off, and the respective transistors WTr included in the memory cell MC [n] are sufficiently turned on. Then, data D [n] is supplied to the wiring WBL. Since each transistor WTr included in the memory cell MC [n] is sufficiently on, the data D [n] reaches the memory node of the memory cell MC [n] and is written. Further, since the transistors WTr of the memory cells MC [1] to MC [n−1] are in an off state, they are held in the memory cells MC [1] to MC [n−1], respectively. The data D [1] to D [n−1] that are present are not lost by the write operation from time T14 to time T15.

  Through the above operation, data can be written to the memory cell MC included in any one of the semiconductor devices illustrated in FIGS.

  FIG. 4B illustrates an example in which data D [1] to data D [n] are read from the memory cells MC [1] to MC [n], respectively. Note that at this time, in order to maintain data held in each memory cell MC, the transistor WTr is required to be in an off state. Therefore, in the operation of reading data from the memory cells MC [1] to MC [n], the potentials of the wirings WWL [1] to WWL [n] are low level potentials.

  In the circuit configuration of the semiconductor device illustrated in FIG. 1, when reading data from a specific memory cell MC, the transistor RTr included in another memory cell MC is sufficiently turned on, and then the transistor included in the specific memory cell MC. RTr is operated as a saturation region. That is, the current flowing between the source and drain of the transistor RTr included in the specific memory cell MC is determined according to the source-drain voltage and the data held in the specific memory cell MC.

  For example, consider a case where data held in the memory cell MC [k] (k is an integer of 1 to n) is read. At this time, in order to sufficiently turn on the transistors RTr included in the memory cells MC [1] to MC [n] except the memory cell MC [k], the wiring RWL excluding the wiring RWL [k] is used. A high level potential is supplied to [1] to the wiring RWL [n].

  On the other hand, since the transistor RTr included in the memory cell MC [k] is turned on in accordance with the held data, the data RWL [k] is written when the data is written in the memory cell MC [k]. The potential needs to be the same as that of the wiring RWL [k]. Note that here, the potential of the wiring RWL [k] in the writing operation and the reading operation is considered as a low-level potential.

  For example, a potential of + 3V is applied to the node N1 and 0V is applied to the node N2. Then, the node N2 is floated, and the potential of the subsequent node N2 is measured. When the potentials of the wirings RWL [1] to RWL [n] excluding the wiring RWL [k] are high level potentials, the memory cells MC [1] to MC [n] excluding the memory cell MC [k]. ] Is sufficiently turned on. On the other hand, since the voltage between the first terminal and the second terminal of the transistor RTr included in the memory cell MC [k] is determined by the potential of the gate of the transistor RTr and the potential of the node N1, the potential of the node N2 is determined by the memory cell MC [ k] depending on the data held in the memory node.

  In this way, data held in the memory cell MC [k] can be read.

  Based on the above, an operation example shown in the timing chart of FIG. 4B will be described. At time T20, the potentials of the wirings WWL [1] to WWL [n], the wirings RWL [1] to RWL [n], the wiring WBL, the node N1, and the node N2 are low level potentials. . In particular, the node N2 is in a floating state. Data D [1] to data D [n] are held in the memory nodes of the memory cells MC [1] to MC [n], respectively.

At time T21, the low-level potential is supplied to the wiring RWL [1], and the high-level potential is supplied to the wirings RWL [2] to WWL [n]. Accordingly, the transistors RTr included in the memory cells MC [2] to MC [n] are sufficiently turned on. Then, the transistor RTr of the memory cell MC [1] is turned on according to the data D [1] held in the memory node of the memory cell MC [1]. Further, supplying a potential _{V R} to the wiring RBL. Thus, the potential V _R next to the node N1, the potential at the node N2, the potential of the potential V _R and the node N2 of the node N1 is determined according to the data held in the memory node of the memory cell MC [1]. Here, the potential of the node N2 is V _{D [1]} . Then, by measuring the potential V _{D [1]} of the node N2, the data D [1] held in the memory node of the memory cell MC [1] can be read.

At time T22, the low-level potential is supplied to the wirings RWL [1] to WWL [n]. Further, a low level potential is supplied to the node N2, and then the node N2 enters a floating state. That is, between time T22 and time T23, the potentials of the wirings RWL [1] to WWL [n] and the node N2 are the same as those from the time T20 to the time T21. Incidentally, the wiring RBL continues, it may supply electric potential V _R, or may supply a low-level potential. In this operation example, the wiring RBL, the time T21 after, it is assumed that the potential _{V R} is continuously supplied.

At time T23, the low-level potential is supplied to the wiring RWL [2], and the high-level potential is supplied to the wiring RWL [1] and the wirings RWL [3] to WWL [n]. Accordingly, the transistors RTr included in the memory cell MC [1] and the memory cells MC [3] to MC [n] are sufficiently turned on. Then, the transistor RTr of the memory cell MC [2] is turned on in accordance with the data D [2] held in the memory node of the memory cell MC [2]. The potential _{V R} is subsequently fed to the wiring RBL. Thus, the potential of the node N2, the potential of the potential V _R and the node N2 of the node N1 is determined according to the data held in the memory node of the memory cell MC [2]. Here, the potential of the node N2 is V _{D [2]} . Then, by measuring the potential V _{D [2]} of the node N2, the data D [2] held in the memory node of the memory cell MC [2] can be read.

Between time T24 and time T25, the read operation of data D [1] from the memory cell MC [1] from time T20 to time T22 and the memory cell MC [from time T22 to time T24 [ 2] from data D [3] to data D [n− sequentially from the memory cells MC [3] to MC [n−1], respectively. 1] is read out. Specifically, when data D [j] is read from the memory cell MC [j] (j is an integer of 3 to n−1), the potential of the node N2 is set to a low level potential, and the node N2 is After the floating state, a high level potential is supplied to the wirings RWL [1] to RWL [n] except for the wiring RWL [j], and the memory cells MC [1] to MC [j] except for the memory cell MC [j] are supplied. The transistor RTr included in the memory cell MC [n] is turned on sufficiently, and the transistor RTr included in the memory cell MC [j] is turned on according to the data D [j]. Then, the potential of the node N1 to the V _R, the potential of the node N2, becomes a potential corresponding to the data D [j], by measuring the potential, it is possible to read the data D [j] . Note that after the data D [j] held in the memory cell MC [j] is read, a low-level potential is supplied to the wirings RWL [1] to WWL [n] in preparation for the next reading operation. Then, a low level potential is supplied to the node N2, and then the node N2 is brought into a floating state. When j is n-1, this preparation indicates an operation from time T25 to time T26.

At time T25, the low-level potential is supplied to the wirings RWL [1] to WWL [n]. Further, a low level potential is supplied to the node N2, and then the node N2 enters a floating state. That is, between time T25 and time T26, the potentials of the wirings RWL [1] to WWL [n] and the node N2 are the same as those from the time T20 to the time T21. Incidentally, the wiring RBL continues, it may supply electric potential V _R, or may supply a low-level potential. In this operation example, the wiring RBL, the time T21 after, it is assumed that the potential _{V R} is continuously supplied.

At time T26, a low-level potential is supplied to the wiring RWL [n], and a high-level potential is supplied to the wirings RWL [1] to WWL [n-1]. Accordingly, the transistors RTr included in the memory cells MC [1] to MC [n−1] are sufficiently turned on. Then, the transistor RTr of the memory cell MC [n] is turned on according to the data D [n] held in the memory node of the memory cell MC [n]. The potential _{V R} is subsequently fed to the wiring RBL. Thus, the potential of the node N2, the potential of the potential V _R and the node N2 of the node N1 is determined according to the data held in the memory node of the memory cell MC [n]. Here, the potential of the node N2 is set to V _{D [n]} . Then, by measuring the potential V _{D [n]} of the node N2, the data D [n] held in the memory node of the memory cell MC [n] can be read.

  Through the above operation, data can be read from each memory cell MC in the semiconductor device illustrated in FIGS.

<Example of structure and manufacturing method>
Hereinafter, in order to help understanding of the structure of the semiconductor device of this embodiment, a manufacturing method thereof will be described.

  5A and 5B are schematic views illustrating the semiconductor device illustrated in FIGS. 1A to 1C. 5A is a top view of the semiconductor device, and FIG. 5B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 5A.

  The semiconductor device includes a structure in which a wiring RWL, a wiring WWL, and an insulator (a region where hatching is not illustrated in FIG. 5) are stacked, and an opening is provided in the structure. The conductor PG is formed so as to fill the part. A wiring ER is formed over the conductor PG, and thereby the wiring ER and the wiring RWL or the wiring WWL are electrically connected.

  In addition, an opening that penetrates the wiring RWL and the wiring WWL at once is formed in the structure. In order to provide the memory cell MC in the region AR through which the wiring RWL and the wiring WWL are penetrated, an insulator, a conductor, and a semiconductor are formed in the opening. Note that the conductor functions as the wiring WBL and the wiring RBL, and the semiconductor functions as a channel formation region of the transistor WTr and the transistor RTr. In FIG. 5, a region where an insulator, a conductor, and a semiconductor are formed in the opening is illustrated as a region HL. Note that in the case where a back gate is provided in the transistor included in the memory cell MC, the conductor included in the region HL may function as the wiring BGL for electrically connecting to the back gate.

  That is, in FIG. 5, the semiconductor device illustrated in any one of FIGS. 1A, 1B, and 1C is configured in the region SD1, and the semiconductor device illustrated in FIG. 2 or FIG. 3 is configured in the region SD2. It shows that.

  In the following manufacturing method example 1 and manufacturing method example 2, a method for forming the memory cell MC in the region AR will be described.

<< Production Method Example 1 >>
6 to 10 are cross-sectional views for describing an example of manufacturing the semiconductor device illustrated in FIG. 1A, and particularly show cross-sectional views in the channel length direction of the transistor WTr and the transistor RTr. Further, in the cross-sectional views of FIGS. 6 to 10, some elements are omitted for clarity of illustration.

  As shown in FIG. 6A, the semiconductor device in FIG. 1A includes an insulator 101A disposed above a substrate (not shown), a conductor 131A disposed on the insulator 101A, The insulator 101B disposed on the conductor 131A, the conductor 132A disposed on the insulator 101B, the insulator 101C disposed on the conductor 132A, and the conductor 131B disposed on the insulator 101C And an insulator 101D disposed on the conductor 131B, a conductor 132B disposed on the insulator 101D, and an insulator 101E disposed on the conductor 132B. Hereinafter, a stacked body including the plurality of conductors and the plurality of insulators is referred to as a stacked body 100.

  Note that as the substrate, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a single semiconductor substrate such as silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Further, there are a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Examples of the element provided on the substrate include a capacitor element, a resistor element, a switch element, a light emitting element, and a memory element.

  A flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is formed over a non-flexible substrate, the transistor is peeled off and transferred to a substrate which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor. Note that a sheet, a film, a foil, or the like in which fibers are knitted may be used as the substrate. Further, the substrate may have elasticity. Further, the substrate may have a property of returning to the original shape when bending or pulling is stopped. Or you may have a property which does not return to an original shape. The substrate has a region having a thickness of, for example, 5 μm to 700 μm, preferably 10 μm to 500 μm, more preferably 15 μm to 300 μm. When the substrate is thinned, a semiconductor device including a transistor can be reduced in weight. Further, by making the substrate thin, it may have elasticity even when glass or the like is used, or may have a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device on the substrate due to dropping or the like can be reduced. That is, a durable semiconductor device can be provided.

As the substrate which is a flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. A substrate that is a flexible substrate is preferably as the linear expansion coefficient is lower because deformation due to the environment is suppressed. As the substrate which is a flexible substrate, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a substrate that is a flexible substrate.

  In the manufacturing example described in this embodiment, since heat treatment is included in the process, it is preferable to use a material having high heat resistance and a low thermal expansion coefficient as the substrate.

  The conductor 131A (conductor 131B) functions as the wiring WWL illustrated in FIG. 1A, and the conductor 132A (conductor 132B) functions as the wiring RWL illustrated in FIG.

  Examples of the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, A material containing one or more metal elements selected from magnesium, zirconium, beryllium, indium, ruthenium, or the like can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

  In addition, a conductive material containing oxygen and a metal element contained in a metal oxide that can be used for the semiconductor 151, the semiconductor 152, the semiconductor 153a, and the semiconductor 153b, which will be described later, is used as the conductor, particularly the conductor 131A and the conductor 131B. It may be used. Alternatively, the above-described conductive material containing a metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon were added Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen mixed in from a peripheral insulator or the like may be captured in some cases.

  Further, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen as the conductor, in particular, the conductor 132A and the conductor 132B. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used, and a single layer or a stacked layer may be used.

  A plurality of conductors formed of the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen may be combined. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Alternatively, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed. In addition, when an insulator having an excess oxygen region is used as an insulator in contact with the periphery of the conductor, oxygen may diffuse in a region in contact with the insulator of the conductor. Thus, a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined can be formed. Similarly, when an insulator having an excess nitrogen region is used as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in a region in contact with the insulator of the conductor. Thus, a stacked structure in which a material containing a metal element and a conductive material containing nitrogen are combined can be formed.

  Note that each of the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B may be made of the same material or different materials. That is, materials used for the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B included in the semiconductor device of one embodiment of the present invention can be selected as appropriate and used.

The insulators 101A to 101E are preferably formed using a material in which the concentration of impurities such as water or hydrogen is reduced. For example, the amount of hydrogen desorbed from the insulators 101A to 101E is desorbed in terms of hydrogen molecules in a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)) in the range of 50 ° C. to 500 ° C. The amount is 2 × 10 ¹⁵ molecules / cm ² or less, preferably 1 × 10 ¹⁵ molecules / cm ² or less, more preferably 5 × 10 in terms of the area of any one of the insulators 101A to 101E. It may be ¹⁴ molecules / cm ² or less. The insulators 101A to 101E may be formed using an insulator from which oxygen is released by heating. Accordingly, as described above, the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B can have a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined.

  As the insulators 101A to 101E, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum are used. Insulators can be used in a single layer or stacked layers. For example, a material containing silicon oxide or silicon oxynitride can be used.

  Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates. In this specification, aluminum oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and aluminum nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  In the next step, as shown in FIG. 6B, an opening 191 can be formed in the stacked body 100 shown in FIG. 6A by resist mask formation and etching treatment.

  The resist mask can be formed using a lithography method, a printing method, an inkjet method, or the like as appropriate. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used. In addition, the etching process may be a dry etching method or a wet etching method, or both may be used.

  Then, as illustrated in FIG. 7A, the conductor 132A and the conductor 132B included in the side surface of the opening 191 are removed by using an etching process or the like, so that a recess 192A (a recess 192B) is formed in the side surface. The Here, as the conductor 132A (conductor 132B), a material from which the conductor 132A (conductor 132B) in the stacked body 100 is selectively removed (the insulators 101A to 101E and the conductors) is selectively removed. 131A (material having an etching rate higher than that of the conductor 131B) is applied.

  The recessed portion 192A (recessed portion 192B) is provided with a sacrificial layer in a region where the opening 191 and the recessed portion 192A (recessed portion 192B) are formed in the manufacturing step of the semiconductor device illustrated in FIG. In the manufacturing process of the semiconductor device illustrated in FIG. In some cases, when the opening 191 is formed without providing the sacrificial layer, the recess 192A (the recess 192B) can be formed automatically.

  In the next step, as shown in FIG. 7B, the insulator 102 is formed on the side surface of the opening 191 shown in FIG.

  As the insulator 102, an insulating material having a function of suppressing permeation of oxygen is preferably used. For example, the insulator 102 is preferably formed using silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like. By forming such an insulator 102, it is possible to prevent a decrease in conductivity of the conductor 133 due to oxygen entering through the insulator 102 and oxidizing the conductor 133 described later. .

  In the next step, as shown in FIG. 8A, a conductor 133 is formed on the side surface of the opening 191 shown in FIG. 7B and the formed recess. That is, the conductor 133 is formed on the surface where the insulator 102 is formed.

  As the conductor 133, a material that can be used for the above-described conductor 131A, conductor 131B, conductor 132A, and conductor 132B can be used. In particular, it is preferable to apply a highly conductive material to the conductor 133 among the materials.

  In the next step, as shown in FIG. 8B, the conductor 133 contained in the opening 191 is removed by resist mask formation and etching so that the conductor 133 remains only in the above-described recess. Thereby, the conductor 133a and the conductor 133b are formed. Note that at this time, part of the insulator 102 may be removed as long as the insulators 101A to 101E, the conductor 131A, and the conductor 131B are not exposed to the opening 191.

  Note that the description of FIG. 6B is referred to for the formation of the resist mask and the etching process.

  By the way, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor CS shown in FIG. That is, the capacitor CS is formed in the region 181A (region 181B) illustrated in FIG.

  In the next step, as illustrated in FIG. 9A, the semiconductor 151 is formed over the formation surface of the insulator 102, the conductor 133 a, and the conductor 133 b located on the side surface of the opening 191.

  As the semiconductor 151, a material containing a metal oxide described in Embodiment 3 is preferably used.

  By the way, in the case where the semiconductor 151 includes a metal oxide, the insulator 102 in contact with the semiconductor 151 is formed using an insulating material having a function of suppressing transmission of not only oxygen but also impurities such as water or hydrogen. preferable. By forming such an insulator 102, it is possible to prevent impurities such as water or hydrogen from entering through the insulator 102 and reacting with oxygen contained in the semiconductor 151 to become water. When water is generated in the semiconductor 151, oxygen vacancies may be formed in the semiconductor 151. When an impurity such as hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Therefore, when a region containing a large amount of hydrogen exists in the semiconductor 151, a transistor in which the region is included in the channel formation region is likely to be normally on. In order to prevent this, it is desirable to use an insulating material having a function of suppressing transmission of not only oxygen but also impurities such as water or hydrogen as the insulator 102.

  In the case where the semiconductor 151 includes a metal oxide, the semiconductor 151 may have different conductivity depending on a region where the semiconductor 151 is formed. In FIG. 9A, regions having a surface where the insulator 102 is formed are illustrated as a region 151a and a region 151b in the region where the semiconductor 151 is formed, and the region where the conductor 133a (conductor 133b) is formed is illustrated. The region is illustrated as a region 151c. In particular, the region 151a is a region overlapping with the side surface of the conductor 131A (conductor 131B), and the region 151b is a region overlapping with the side surface of the insulator 101A (insulators 101B to 101E). Since the region 151c is in contact with the conductor 133a (conductor 133b), impurities such as hydrogen or water contained in the conductor 133a may diffuse into the region 151c. As described above, when impurities such as water or hydrogen diffuse in the semiconductor 151, electrons serving as carriers may be generated, and thus the region 151c may have a low resistance. Therefore, the region 151c is a region having higher conductivity than the region 151a and the region 151b.

  The region 151a is a region that serves as a channel formation region of the transistor. Therefore, when the transistor is on, the resistance of the region 151a is reduced, so that the conductivity is higher than that of the region 151b.

  In the next step, as illustrated in FIG. 9B, the insulator 103 and the semiconductor 152 are sequentially formed over the formation surface of the semiconductor 151 located on the side surface of the opening 191.

  As the insulator 103, a material that can be used for the insulator 102 described above can be used. In particular, when the semiconductor 151 includes a metal oxide, the insulator 102 is preferably an insulating material having a function of suppressing transmission of not only oxygen but also impurities such as water or hydrogen.

  By the way, in the region 182A (region 182B) illustrated in FIG. 9B, the transistor WTr illustrated in FIG. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, and each of the two regions 151b of the semiconductor 151 functions as a source electrode and a drain electrode of the transistor WTr. The conductor 132A functions as the gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, the transistor WTr forms an OS transistor.

  As the semiconductor 152, a material containing a metal oxide described in Embodiment 3 can be used as in the semiconductor 151. As an alternative to the semiconductor 152, a semiconductor material such as silicon can be used.

  In the next step, as shown in FIG. 10A, the insulator 104 is formed on the formation surface of the semiconductor 152, and the conductor 134 is formed so that the remaining opening 191 is filled.

  As the insulator 104, a material that can be used for the insulator 102 and the insulator 103 described above can be used.

  As the conductor 134, a material that can be used for the conductor 131A, the conductor 131B, the conductor 132A, the conductor 132B, the conductor 133a, and the conductor 133b described above can be used.

  Incidentally, in the region 183A (region 183B) illustrated in FIG. 10A, the transistor RTr illustrated in FIG. Specifically, in the region 183A (region 183B), the region 151c, the two regions 151b, and the conductor 133a (conductor 133b) of the semiconductor 151 function as a gate electrode of the transistor RTr, and the semiconductor 152 is a channel of the transistor RTr. The conductor 134 functions as a formation region, and the conductor 134 functions as a back gate electrode of the transistor RTr. In particular, when a material containing a metal oxide is used for the semiconductor 152, the transistor RTr forms an OS transistor.

  By performing the steps from FIG. 6A to FIG. 10A, the semiconductor device illustrated in FIG. 1A can be manufactured.

  One embodiment of the present invention is not limited to the structure example of the semiconductor device illustrated in FIG. One embodiment of the present invention can have a structure in which the semiconductor device illustrated in FIG. 10A is changed as appropriate depending on circumstances or circumstances.

  For example, as described above, one embodiment of the present invention can be a semiconductor device in which the back gate is not provided in the transistor WTr and the transistor RTr as illustrated in FIG. In the case of manufacturing the semiconductor device illustrated in FIG. 1C, the process illustrated in FIG. 10B may be performed instead of the process illustrated in FIG. 10A in the process of manufacturing FIG. FIG. 10B illustrates a process in which the insulator 105 is formed so as to fill the opening 191 instead of the conductor 134 in FIG. Note that the insulator 105 can be formed using a material that can be used as the insulator 104, for example.

  For example, in one embodiment of the present invention, the structure of the gate electrode of the transistor WTr may be changed from the structure illustrated in FIG. 10A in order to improve the switching characteristics of the transistor WTr. 11A, 11B, and 12A and 12B illustrate an example of a method for manufacturing the semiconductor device. FIG. 11A shows a process in which the conductor 131A (conductor 131B) on the side surface of the opening 191 is removed in FIG. 6B to form the recess 193A (recess 193B). Here, as the conductor 131A (conductor 131B), a material from which the conductor 131A (conductor 131B) is selectively removed in the stacked body 100 (conductor 132A (conductor 132B), insulator) 101A to a material having a higher etching rate than the insulator 101E) is used.

  The recessed portion 193A (recessed portion 193B) is provided with a sacrificial layer in a region where the opening 191 and the recessed portion 193A (recessed portion 193B) are formed in the step of manufacturing the semiconductor device illustrated in FIG. In the manufacturing process of the semiconductor device illustrated in FIG. In some cases, when the opening 191 is formed without providing the sacrificial layer, the recess 193A (the recess 193B) can be formed automatically.

  In the next step, as shown in FIG. 11B, the semiconductor 153 is formed on the side surface of the opening 191 and the recess 193A (recess 193B) shown in FIG.

  As the semiconductor 153, a material containing a metal oxide described in Embodiment 3 is used.

  In the next step, as shown in FIG. 12A, the semiconductor 153 included in the opening 191 is removed by resist mask formation and etching so that the semiconductor 153 remains only in the above-described recess 193A (recess 193B). The At the same time as or after this process, an etching process is performed to remove the conductor 132A (conductor 132B) to form a recess 192A (recess 192B).

  Next, as in the step of FIG. 8B, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). In the case where a material containing a metal oxide is used as the semiconductor 153 (semiconductor 153b), the semiconductor 153a (semiconductor 153b) is in contact with the insulator 102, so that impurities such as hydrogen and water contained in the insulator 102 are contained in the semiconductor. It diffuses into 153a (semiconductor 153b). The semiconductor 153a (semiconductor 153b) is in contact with the conductor 133a (conductor 133b), so that impurities such as hydrogen and water contained in the conductor 133a (conductor 133b) are diffused into the semiconductor 153a (semiconductor 153b). That is, the semiconductor 153a (semiconductor 153b) has a role of collecting impurities such as hydrogen and water. Accordingly, the resistance of the semiconductor 153a (semiconductor 153b) is reduced, and the semiconductor 153a (semiconductor 153b) can function as the gate electrode of the transistor WTr. After that, by performing steps similar to those in FIGS. 9A to 10A, the semiconductor device illustrated in FIG. 12B can be formed.

  For example, according to one embodiment of the present invention, the electrical resistance between the first terminal or the second terminal of the transistor WTr illustrated in FIG. 1A and the gate of the transistor RTr can be reduced. The structure of the gate electrode of the transistor RTr may be changed from the structure illustrated in FIG. 13A and 13B illustrate an example of a method for manufacturing the semiconductor device. In FIG. 13A, not only the conductor 132A (conductor 132B) included in the side surface of the opening 191 in FIG. 7A but also the insulators 101A to 101E are removed, and the recesses are formed. The process of forming 194B (concave part 194A, concave part 194C) is shown. Here, as the conductor 132A (conductor 132B) and the insulators 101A to 101E, the conductor 132A (conductor 132B) and the insulators 101A to 101E in the stacked body 100 are selectively removed. Such a material (a material having an etching rate higher than that of the conductor 131A (conductor 131B)) is applied.

  The recessed portion 194B (the recessed portion 194A and the recessed portion 194C) is a sacrificial layer in a region where the opening 191 and the recessed portion 194B (the recessed portion 194A and the recessed portion 194C) are formed in the step of manufacturing the semiconductor device illustrated in FIG. May be formed in a lump with the opening 191 in the manufacturing process of the semiconductor device illustrated in FIG. In some cases, when the opening 191 is formed without providing the sacrificial layer, the concave portion 194B (the concave portion 194A and the concave portion 194C) can be automatically formed.

  In FIG. 13A, the conductor 132A (conductor 132B) is formed in the recess 194B (recess 194A, recess 194C) rather than the insulator 101B and insulator 101C (insulator 101A, insulator 101D, insulator 101E). However, the insulator 101B and the insulator 101C (insulator 101A, insulator 101D, insulator 101E) may be removed more than the conductor 132A (conductor 132B). . The insulator 101B, the insulator 101C (the insulator 101A, the insulator 101D, and the insulator 101E) and the conductor 132A (the conductor 132B) may be formed at the same depth.

  FIG. 13B illustrates an example of a structure of a semiconductor device through the process of FIG. After the step of FIG. 13A, the conductor 133 is formed so as to fill the recess 194B (the recess 194A and the recess 194C), and the gate electrode of the transistor RTr is formed. FIG. 13A illustrates a conductor 133a, a conductor 133b, and a conductor 133c that function as gate electrodes of the transistor RTr. After that, by performing the same steps from FIG. 9A to FIG. 10A, the semiconductor device shown in FIG. 13B can be formed. This semiconductor device has a structure in which the contact area between the semiconductor 151 and the conductor 133a (conductor 133b) is larger than that of the semiconductor device illustrated in FIG. In the case where a material including a metal oxide is applied to the semiconductor 151, the semiconductor device illustrated in FIG. 13B does not include the region 151b illustrated in FIG. 10A; therefore, the first terminal or the second terminal of the transistor WTr The electrical resistance between the transistor RTr and the gate of the transistor RTr can be reduced.

<< Production Method Example 2 >>
Here, an example of a structure different from that of Manufacturing Method Example 1 as the semiconductor device of this embodiment is described with reference to FIGS.

  FIGS. 14 to 16 are cross-sectional views for describing an example of manufacturing the semiconductor device illustrated in FIG. 1A, as in FIGS. 6 to 10. In particular, FIGS. A cross-sectional view is shown. Further, in the cross-sectional views of FIGS. 14 to 16, as in FIGS. 6 to 10, some elements are omitted for clarity of illustration.

  For the first step, the description of FIGS. 6A to 7B described in Manufacturing Method Example 1 is referred to.

  The process shown in FIG. 14A is a continuation of the process shown in FIG. In FIG. 14A, the semiconductor 151 is formed on the side surface of the opening 191 and the formed recess shown in FIG. That is, the semiconductor 151 is formed on the surface where the insulator 102 is formed.

  As the semiconductor 151, the semiconductor described in Embodiment 3 is preferably used.

  In the next step, as shown in FIG. 14B, a conductor 133 is formed on the side surface of the opening 191 shown in FIG.

  For the conductor 133, the description of the conductor 133 described in Manufacturing Method Example 1 is referred to.

  In the next step, as shown in FIG. 15A, the conductor 133 contained in the opening 191 is removed by resist mask formation and etching so that the conductor 133 remains only in the above-described recess. Thereby, the conductor 133a and the conductor 133b are formed. Note that at this time, part of the semiconductor 151 may be removed as long as the insulator 102 is not exposed to the opening 191.

  Note that the description of FIG. 6B is referred to for the formation of the resist mask and the etching process.

  By the way, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor CS shown in FIG. That is, the capacitor CS is formed in the region 181A (region 181B) illustrated in FIG.

  For the semiconductor 151, the description of the semiconductor 151 described in Manufacturing Method Example 1 is referred to. In the case where the semiconductor 151 includes a metal oxide, the semiconductor 151 can be divided into a region 151a, a region 151b, and a region 151c. For the region 151a, the region 151b, and the region 151c, the description of the region 151a, the region 151b, and the region 151c described in Manufacturing Method Example 1 is referred to.

  In the next step, as shown in FIG. 15B, the insulator 103 is formed on the formation surfaces of the conductor 133a, the conductor 133b, and the semiconductor 151 located on the side surface of the opening 191. A semiconductor 152 is formed on the formation surface of the body 103.

  For the insulator 103, the description of the insulator 103 described in Manufacturing Method Example 1 is referred to.

  For the semiconductor 152, the description of the semiconductor 152 described in manufacturing method example 1 is referred to.

  By the way, in the region 182A (region 182B) illustrated in FIG. 15B, the transistor WTr illustrated in FIG. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, and each of the two regions 151b of the semiconductor 151 functions as a source electrode and a drain electrode of the transistor WTr. The conductor 132A functions as the gate electrode of the transistor WTr. In particular, when a material containing a metal oxide is used as the semiconductor 151, the transistor WTr forms an OS transistor.

  In the next step, as shown in FIG. 16A, the insulator 104 is formed on the formation surface of the semiconductor 152, and the conductor 134 is formed so that the remaining opening 191 is filled.

  For the insulator 104, the description of the insulator 104 described in Manufacturing Method Example 1 is referred to.

  For the conductor 134, the description of the conductor 134 described in Manufacturing Method Example 1 is referred to.

  By the way, in the region 183A (region 183B) illustrated in FIG. 16A, the transistor RTr illustrated in FIG. Specifically, in the region 183A (region 183B), the region 151c, the two regions 151b, and the conductor 133a (conductor 133b) of the semiconductor 151 function as a gate electrode of the transistor RTr, and the semiconductor 152 is a channel of the transistor RTr. The conductor 134 functions as a formation region, and the conductor 134 functions as a back gate electrode of the transistor RTr. In particular, when a material containing a metal oxide is used for the semiconductor 152, the transistor RTr forms an OS transistor.

  By performing the steps from FIGS. 6A to 7B and FIGS. 14A to 16A, the semiconductor device illustrated in FIG. 1A can be manufactured.

  One embodiment of the present invention is not limited to the structure example of the semiconductor device illustrated in FIG. One embodiment of the present invention can have a structure in which the semiconductor device illustrated in FIG. 16A is changed as appropriate depending on circumstances or circumstances.

  For example, as described above, one embodiment of the present invention can be a semiconductor device in which the back gate is not provided in the transistor WTr and the transistor RTr as illustrated in FIG. In the case of manufacturing the semiconductor device illustrated in FIG. 1C, the process illustrated in FIG. 16B may be performed instead of the process illustrated in FIG. 16A in the process of manufacturing FIG. FIG. 16B illustrates a process in which the insulator 105 is formed so as to fill the opening 191 instead of the conductor 134 in FIG. Note that the insulator 105 can be formed using a material that can be used as the insulator 104, for example.

  For example, in one embodiment of the present invention, the structure of the gate electrode of the transistor WTr may be changed from the structure illustrated in FIG. 16A in order to improve the switching characteristics of the transistor WTr. FIG. 17 shows a configuration example of the semiconductor device. When the semiconductor device illustrated in FIG. 17 is manufactured, the semiconductor 153a (semiconductor 153b) is formed so that the recess 193A (recess 193B) is filled as in the structure example illustrated in FIG. . Next, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). After that, by performing the same steps as those in FIGS. 14A to 16A, the semiconductor device illustrated in FIG. 17 can be formed. Note that the description of FIGS. 11A and 11B and FIGS. 12A and 12B described in the manufacturing method example 1 is referred to for the effect of the configuration in FIG.

  For example, according to one embodiment of the present invention, the electrical resistance between the first terminal or the second terminal of the transistor WTr illustrated in FIG. 1A and the gate of the transistor RTr can be reduced. The structure of the gate electrode of the transistor RTr may be changed from the structure illustrated in FIG. FIG. 18 shows a configuration example of the semiconductor device. When the semiconductor device illustrated in FIG. 18 is manufactured, the configuration example illustrated in FIG. 13A described in Manufacturing Method Example 1 is manufactured. After that, by performing the same steps as those in FIGS. 14A to 16A, the semiconductor device illustrated in FIG. 18 can be formed. Note that the description of FIG. 13B described in the manufacturing method example 1 is referred to for the effect of configuring FIG.

  By the manufacturing method example 1 or the manufacturing method example 2 described above, a semiconductor device capable of holding a large amount of data can be manufactured.

  Here, FIG. 19 illustrates a structure in which the cross-sectional view of the semiconductor device illustrated in FIG. 10A (the circuit configuration in FIG. 1A) is applied to the region SD2 of the semiconductor device illustrated in FIG. Note that the region SD1 corresponds to the memory cell MC. As shown in FIGS. 19A and 19B, an opening is collectively provided for the stacked body of the conductor RWL and the conductor WWL, the insulator, and the manufacturing method example 1 or the manufacturing method example 2 described above. By manufacturing as described, the circuit configuration in FIG. 1A can be realized.

<Connection example with peripheral circuit>
In the semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2, peripheral circuits of the memory cell array such as a reading circuit and a precharge circuit may be formed in a lower layer. In that case, a Si transistor is formed over a silicon substrate or the like to form the peripheral circuit, and then the semiconductor device of one embodiment of the present invention is formed over the peripheral circuit in Manufacturing Method Example 1 or Manufacturing Method Example 2. What is necessary is just to form. FIG. 20A is a cross-sectional view in which the peripheral circuit is formed using a planar Si transistor and the semiconductor device of one embodiment of the present invention is formed thereover. FIG. 21A is a cross-sectional view in which the peripheral circuit is formed using a FIN Si transistor and the semiconductor device of one embodiment of the present invention is formed thereover. Note that the semiconductor device illustrated in FIGS. 20A and 20B has the structure illustrated in FIG. 10A as an example.

  In FIG. 20A and FIG. 21A, the Si transistor forming the peripheral circuit is formed over the substrate 1700. The element isolation layer 1701 is formed between a plurality of Si transistors. A conductor 1712 is formed as the source and drain of the Si transistor. The conductor 1730 extends in the channel width direction and is connected to another Si transistor or the conductor 1712 (not shown).

  As the substrate 1700, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

  Further, as the substrate 1700, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, a bonded film, paper containing a fibrous material, a base film, or the like may be used. Alternatively, a semiconductor element may be formed using a certain substrate, and then the semiconductor element may be transferred to another substrate. 20A and 21A illustrate an example in which a single crystal silicon wafer is used for the substrate 1700 as an example.

  Here, details of the Si transistor will be described. The planar Si transistor shown in FIG. 20A shows a cross-sectional view in the channel length direction, and the planar Si transistor shown in FIG. 20B shows a cross-sectional view in the channel width direction. The Si transistor includes a channel formation region 1793 provided in a well 1792, a low-concentration impurity region 1794 and a high-concentration impurity region 1795 (also collectively referred to as an impurity region), and a conductive layer provided in contact with the impurity region. Region 1796, a gate insulating film 1797 provided over the channel formation region 1793, a gate electrode 1790 provided on the gate insulating film 1797, a sidewall insulating layer 1798 provided on a side surface of the gate electrode 1790, sidewall insulation Layer 1799. Note that a metal silicide or the like may be used for the conductive region 1796.

  21A shows a cross-sectional view in the channel length direction, and the FIN-type Si transistor shown in FIG. 21B shows a cross-sectional view in the channel width direction. In the Si transistor illustrated in FIGS. 21A and 21B, a channel formation region 1793 has a convex shape, and a gate insulating film 1797 and a gate electrode 1790 are provided along a side surface and an upper surface thereof. In this embodiment mode, a case where a part of the semiconductor substrate is processed to form a convex portion is shown; however, a semiconductor layer having a convex shape may be formed by processing an SOI substrate. In addition, the code | symbol shown to FIG. 21 (A) and (B) is the same as the code | symbol shown to FIG. 20 (A) and (B).

  Note that an insulator, a conductor, a semiconductor, and the like disclosed in this specification and the like can be formed by a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. Examples of the PVD method include a sputtering method, a resistance heating vapor deposition method, an electron beam vapor deposition method, and a PLD (Pulsed Laser Deposition) method. Examples of the CVD method include formation using a plasma CVD method and a thermal CVD method. In particular, examples of the thermal CVD method include a MOCVD (Metal Organic Chemical Deposition) method and an ALD (Atomic Layer Deposition) method.

  The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.

  In the thermal CVD method, film formation may be performed by sending a source gas and an oxidant into the chamber at the same time, making the inside of the chamber under atmospheric pressure or reduced pressure, reacting in the vicinity of the substrate or on the substrate and depositing on the substrate. .

  Further, in the ALD method, film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases. For example, each switching valve (also referred to as a high-speed valve) is switched to supply two or more types of source gases to the chamber in order, so that a plurality of types of source gases are not mixed with the first source gas at the same time or thereafter. An active gas (such as argon or nitrogen) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first thin layer, reacts with a second source gas introduced later, and the second thin layer is formed on the first thin layer. To form a thin film. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

A thermal CVD method such as an MOCVD method or an ALD method can form various films such as a metal film, a semiconductor film, and an inorganic insulating film disclosed in the embodiments described so far. For example, In—Ga—Zn In the case where the —O film is formed, trimethylindium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), and dimethylzinc (Zn (CH ₃ ) ₂ ) are used. The invention is not limited to these combinations, triethyl gallium instead of trimethylgallium _{(Ga (C 2 H 5)} 3) can also be used, diethylzinc in place of dimethylzinc _{(Zn (C 2 H 5)} 2) Can also be used.

For example, when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf [N (CH ₃ ) ₂ ]) ₄ ) gas of hafnium amide) is used, and ozone (O ₃ ) is used as an oxidizing agent. Other materials include tetrakis (ethylmethylamide) hafnium.

For example, when an aluminum oxide film is formed by a film forming apparatus using ALD, a raw material gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA, Al (CH ₃ ) ₃ )) containing a solvent and an aluminum precursor compound. And two kinds of gases of H ₂ O are used as the oxidizing agent. Other materials include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. React with things.

For example, in the case where a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by repeatedly introducing WF ₆ gas and B ₂ H ₆ gas successively, and then WF ₆ gas and H _2. A tungsten film is formed by successively introducing gases. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film such as an In—Ga—Zn—O film is formed by a film formation apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced, and In -O layer is formed, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are repeatedly introduced sequentially to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are successively introduced repeatedly. To form a ZnO layer. Note that the order of these layers is not limited to this example. Alternatively, a mixed oxide layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

  Note that the structure examples of the semiconductor devices described in this embodiment can be combined with each other as appropriate.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 2)
In this embodiment, a memory device including the semiconductor device described in the above embodiment is described.

  FIG. 22 shows an example of the configuration of the storage device. The memory device 2600 includes a peripheral circuit 2601 and a memory cell array 2610. The peripheral circuit 2601 includes a row decoder 2621, a word line driver circuit 2622, a bit line driver circuit 2630, an output circuit 2640, and a control logic circuit 2660.

  The semiconductor device illustrated in FIG. 1A, FIG. 1B, or FIG. 1C described in Embodiment 1 can be applied to the memory cell array 2610.

  The bit line driver circuit 2630 includes a column decoder 2631, a precharge circuit 2632, a sense amplifier 2633, and a write circuit 2634. The precharge circuit 2632 has a function of precharging the node N1 (not illustrated in FIG. 22) of the wiring RBL described in Embodiment 1 to a predetermined potential. The sense amplifier 2633 has a function of acquiring the read potential of the node N2 as a data signal and amplifying the data signal. The amplified data signal is output to the outside of the storage device 2600 through the output circuit 2640 as a digital data signal RDATA.

  In addition, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 2601, and a high power supply voltage (VIL) for the memory cell array 2610 are supplied from the outside to the memory device 2600.

  In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 2600 from the outside. The address signal ADDR is input to the row decoder 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit 2634.

  The control logic circuit 2660 processes input signals (CE, WE, RE) from the outside, and generates control signals for the row decoder 2621 and the column decoder 2631. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 2660 is not limited to this, and another control signal may be input as necessary.

  Note that the above-described circuits or signals can be appropriately discarded as necessary.

  In addition, by using a transistor including a p-channel Si transistor and an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in an embodiment later in a channel formation region, the transistor 2600 is used. A small storage device 2600 can be provided. In addition, a storage device 2600 that can reduce power consumption can be provided. In addition, a storage device 2600 that can improve the operation speed can be provided. In particular, manufacturing costs can be kept low by using only p-channel Si transistors.

  Note that the configuration example of the present embodiment is not limited to the configuration of FIG. For example, the configuration may be changed as appropriate, such as providing a part of the peripheral circuit 2601, for example, the precharge circuit 2632 or / and the sense amplifier 2633 below the memory cell array 2610.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, the metal oxide included in the channel formation region of the OS transistor used in the above embodiment is described.

  The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, or the like may be included.

  Here, a case where the metal oxide is an In-M-Zn oxide containing indium, the element M, and zinc is considered. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  Next, a preferable range of the atomic ratio of indium, element M, and zinc included in the metal oxide according to the present invention will be described with reference to FIGS. 23 (A), 23 (B), and 23 (C). . Note that FIG. 23A, FIG. 23B, and FIG. 23C do not describe the atomic ratio of oxygen. The terms of the atomic ratio of indium, element M, and zinc of the metal oxide are [In], [M], and [Zn].

  In FIG. 23A, FIG. 23B, and FIG. 23C, a broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line that satisfies (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1-α): line that has an atomic ratio of 2 [In]: [M] : [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): number of atoms of 4 A line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1−α): 5.

  The one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 5: 1: β (β ≧ 0), and [In]: [M]: [Zn] = 2: A line with an atomic ratio of 1: β, [In]: [M]: [Zn] = 1: 1: a line with an atomic ratio of β, [In]: [M]: [Zn] = 1 2: Line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 1 : 4: represents a line having an atomic ratio of β.

  In addition, the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 shown in FIGS. 23 (A), 23 (B), and 23 (C), and the neighborhood values thereof. Metal oxides tend to have a spinel crystal structure.

  In addition, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic ratio is a value close to [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure tend to coexist. Further, when the atomic ratio is a value close to [In]: [M]: [Zn] = 1: 0: 0, two phases of a bixbite type crystal structure and a layered crystal structure tend to coexist. When a plurality of phases coexist in a metal oxide, a crystal grain boundary may be formed between different crystal structures.

  A region A illustrated in FIG. 23A illustrates an example of a preferable range of the atomic ratio of indium, element M, and zinc included in the metal oxide.

  The metal oxide can increase the carrier mobility (electron mobility) of the metal oxide by increasing the indium content. Therefore, a metal oxide having a high indium content has higher carrier mobility than a metal oxide having a low indium content.

  On the other hand, when the content of indium and zinc in the metal oxide is lowered, the carrier mobility is lowered. Therefore, when the atomic ratio is [In]: [M]: [Zn] = 0: 1: 0 and its vicinity (for example, the region C shown in FIG. 23C), the insulating property becomes high. .

  Therefore, the metal oxide of one embodiment of the present invention preferably has an atomic ratio shown in a region A in FIG. 23A which has a high carrier mobility and a layered structure with few crystal grain boundaries. .

  In particular, in the region B illustrated in FIG. 23B, among the regions A, an excellent metal oxide that easily becomes a CAAC (c-axis aligned crystalline) -OS and has high carrier mobility can be obtained.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in the ab plane direction and have a strain. Note that the strain refers to a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned in a region where a plurality of nanocrystals are connected.

  Nanocrystals are based on hexagons, but are not limited to regular hexagons and may be non-regular hexagons. In addition, there may be a lattice arrangement such as a pentagon and a heptagon in the distortion. Note that in the CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. This is probably because of this.

  CAAC-OS is a metal oxide with high crystallinity. On the other hand, since CAAC-OS cannot confirm a clear crystal grain boundary, it can be said that a decrease in electron mobility due to the crystal grain boundary hardly occurs. In addition, since the crystallinity of the metal oxide may be reduced due to entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxide including the CAAC-OS are stable. Therefore, a metal oxide including a CAAC-OS is resistant to heat and has high reliability.

  Note that the region B includes [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and the vicinity thereof. The neighborhood value includes, for example, [In]: [M]: [Zn] = 5: 3: 4. The region B includes [In]: [M]: [Zn] = 5: 1: 6 and its neighboring values, and [In]: [M]: [Zn] = 5: 1: 7, and Includes neighborhood values.

  Note that the properties of metal oxides are not uniquely determined by the atomic ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide film is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. Further, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Therefore, the illustrated region is a region that exhibits an atomic ratio in which the metal oxide tends to have specific characteristics, and the boundaries of the regions A to C are not strict.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment, a CPU that can include the semiconductor device of the above embodiment is described.

FIG. 24 is a block diagram illustrating a configuration example of a CPU that partially uses the semiconductor device described in Embodiment 1.

  24 includes an ALU 1191 (ALU: arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 24 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 24 may be a single core, and a plurality of the cores may be included and each core may operate in parallel, that is, a configuration like a GPU. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

  Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

  The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

  In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

  In the CPU illustrated in FIG. 24, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the transistor described in the above embodiment can be used.

  In the CPU illustrated in FIG. 24, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 5)
The present invention can be applied to various removable storage devices such as a memory card (for example, an SD card), a USB (Universal Serial Bus) memory, and an SSD (Solid State Drive) that can include the storage device of the above embodiment. In this embodiment, several configuration examples of the removable storage device will be described with reference to FIGS.

  FIG. 25A is a schematic diagram of a USB memory. The USB memory 5100 includes a housing 5101, a cap 5102, a USB connector 5103, and a substrate 5104. The substrate 5104 is housed in the housing 5101. The substrate 5104 is provided with a memory device and a circuit for driving the memory device. For example, a memory chip 5105 and a controller chip 5106 are attached to the substrate 5104. The memory chip 5105 incorporates the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, the column decoder 2631, and the like described in Embodiment 3. Specifically, the controller chip 5106 incorporates a processor, a work memory, an ECC circuit, and the like. Note that the circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances or in some cases. For example, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, and the column decoder 2631 may be incorporated in the controller chip 5106 instead of the memory chip 5105. The USB connector 5103 functions as an interface for connecting to an external device.

  FIG. 25B is a schematic diagram of the appearance of the SD card, and FIG. 25C is a schematic diagram of the internal structure of the SD card. The SD card 5110 includes a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. The substrate 5113 is provided with a memory device and a circuit for driving the memory device. For example, a memory chip 5114 and a controller chip 5115 are attached to the substrate 5113. The memory chip 5114 incorporates the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, the column decoder 2631, and the like described in Embodiment 3. The controller chip 5115 incorporates a processor, work memory, ECC circuit, and the like. Note that the circuit configurations of the memory chip 5114 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate according to circumstances or in some cases. For example, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, and the column decoder 2631 may be incorporated in the controller chip 5115 instead of the memory chip 5114.

  By providing the memory chip 5114 on the back side of the substrate 5113, the capacity of the SD card 5110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 5113. Accordingly, wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the memory chip 5114.

  FIG. 25D is a schematic diagram of the external appearance of the SSD, and FIG. 25E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a substrate 5153. The connector 5152 functions as an interface for connecting to an external device. The substrate 5153 is housed in the housing 5151. The substrate 5153 is provided with a memory device and a circuit for driving the memory device. For example, a memory chip 5154, a memory chip 5155, and a controller chip 5156 are attached to the substrate 5153. The memory chip 5154 incorporates the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, the column decoder 2631, and the like described in Embodiment 3. By providing the memory chip 5154 on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. A work memory is incorporated in the memory chip 5155. For example, a DRAM chip may be used as the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. Note that the circuit configurations of the memory chip 5154, the memory chip 5155, and the controller chip 5115 are not limited to the above description, and the circuit configurations may be changed as appropriate depending on the situation or in some cases. . For example, the controller chip 5156 may be provided with a memory that functions as a work memory.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 6)
In this embodiment, examples of electronic devices to which the memory device of the above embodiments can be applied will be described.

<Notebook personal computer>
FIG. 26A illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The storage device of one embodiment of the present invention can be provided in a laptop personal computer.

<Smart watch>
FIG. 26B illustrates a smart watch which is a kind of wearable terminal, which includes a housing 5901, a display portion 5902, operation buttons 5903, operation elements 5904, a band 5905, and the like. The storage device of one embodiment of the present invention can be included in a smart watch. Further, a display device to which a function as a position input device is added may be used for the display portion 5902. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. Further, the operation button 5903 can be provided with any one of a power switch for starting a smart watch, a button for operating a smart watch application, a volume adjustment button, a switch for turning on or off the display unit 5902, and the like. In the smart watch illustrated in FIG. 26B, the number of operation buttons 5903 is two, but the number of operation buttons included in the smart watch is not limited thereto. The operation element 5904 functions as a crown for adjusting the time of the smart watch. Further, the operation element 5904 may be used as an input interface for operating the smartwatch application in addition to the time adjustment. Note that the smart watch illustrated in FIG. 26B includes the operation element 5904; however, the present invention is not limited to this and may have a structure without the operation element 5904.

<Video camera>
FIG. 26C illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The storage device of one embodiment of the present invention can be provided in a video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there. The video on the display portion 5803 may be switched in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.

<Mobile phone>
FIG. 26D illustrates a mobile phone having an information terminal function, which includes a housing 5501, a display portion 5502, a microphone 5503, a speaker 5504, and operation buttons 5505. The storage device of one embodiment of the present invention can be provided in a mobile phone. Further, a display device to which a function as a position input device is added may be used for the display portion 5502. The function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device. Further, the operation button 5505 can be provided with any one of a power switch for starting a mobile phone, a button for operating a mobile phone application, a volume adjustment button, a switch for turning on or off the display portion 5502, and the like.

  In the mobile phone illustrated in FIG. 26D, the number of operation buttons 5505 is two, but the number of operation buttons included in the mobile phone is not limited thereto. Although not illustrated, the cellular phone illustrated in FIG. 26D may have a structure including a light-emitting device for flashlight or illumination.

<Television device>
FIG. 26E is a perspective view illustrating a television device. A television device includes a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, velocity, acceleration, angular velocity, rotation). Number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, or infrared) Etc. The storage device of one embodiment of the present invention can be included in a television device. The television device can incorporate a display portion 9001 having a large screen, for example, 50 inches or more, or 100 inches or more.

<Moving object>
The display device described above can also be applied to the vicinity of the driver's seat of an automobile that is a moving body.

  For example, FIG. 26F is a diagram illustrating the periphery of a windshield in a car interior. FIG. 26F illustrates a display panel 5704 attached to a pillar in addition to the display panel 5701, the display panel 5702, and the display panel 5703 attached to the dashboard.

  The display panels 5701 to 5703 can provide various other information such as navigation information, a speedometer and a tachometer, a travel distance, an oil supply amount, a gear state, and an air conditioner setting. In addition, the display items, layout, and the like displayed on the display panel can be changed as appropriate according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

  The display panel 5704 can complement the field of view (dead angle) obstructed by the pillar by projecting an image from the imaging means provided on the vehicle body. That is, by displaying an image from the imaging means provided outside the automobile, the blind spot can be compensated and safety can be improved. Also, by displaying a video that complements the invisible part, it is possible to confirm the safety more naturally and without a sense of incongruity. The display panel 5704 can also be used as a lighting device.

  The storage device according to one embodiment of the present invention can be included in a moving object. The storage device according to one embodiment of the present invention includes, for example, a frame memory that temporarily stores image data used when displaying images on the display panel 5701 to the display panel 5704, and a program that drives a system included in a mobile object. It can be used for a storage device for storing.

  Although not illustrated, the electronic devices illustrated in FIGS. 26A to 26C, E, and F may include a microphone and a speaker. With this configuration, for example, a voice input function can be added to the electronic device described above.

  Although not illustrated, the electronic devices illustrated in FIGS. 26A, 26B, and 26D to 26F may have a camera.

  Although not illustrated, the electronic devices illustrated in FIGS. 26A to 26F include sensors (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, Liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, infrared, etc. May be. In particular, the mobile phone shown in FIG. 26D is provided with a detection device having a sensor that detects a tilt, such as a gyroscope or an acceleration sensor, so that the orientation of the mobile phone (which direction the mobile phone is relative to the vertical direction) The screen display of the display portion 5502 can be automatically switched according to the orientation of the mobile phone.

  Although not illustrated, the electronic device illustrated in FIGS. 26A to 26F may include a device that acquires biological information such as a fingerprint, a vein, an iris, or a voiceprint. By applying this configuration, an electronic device having a biometric authentication function can be realized.

  Alternatively, a flexible base material may be used as the display portion of the electronic device illustrated in FIGS. Specifically, the display portion may have a structure in which a transistor, a capacitor element, a display element, and the like are provided over a flexible base material. By applying this configuration, not only a housing having a flat surface as in the electronic devices shown in FIGS. 26A to 26F but also an electronic device having a housing having a curved surface is realized. Can do.

  Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Additional notes regarding the description of this specification etc.)
The description of each component in the above embodiment will be added below.

<Supplementary Note on One Aspect of the Invention described in Embodiment>
The structure described in each embodiment can be combined with the structure described in any of the other embodiments as appropriate, for one embodiment of the present invention. In the case where a plurality of structure examples are given in one embodiment, any of the structure examples can be combined with each other as appropriate.

  Note that the content described in one embodiment (may be a part of content) is different from the other content described in the embodiment (may be a part of content) and one or more other implementations. Application, combination, replacement, or the like can be performed on at least one of the contents described in the form (may be part of the contents).

  Note that the contents described in the embodiments are the contents described using various drawings or the contents described in the specification in each embodiment.

  Note that a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, another drawing (may be a part) described in the embodiment, or one or more different drawings. By combining at least one of the drawings (or a part thereof) described in the embodiment, more drawings can be formed.

<Notes on ordinal numbers>
In this specification and the like, the ordinal numbers “first”, “second”, and “third” are given to avoid confusion between components. Therefore, the number of components is not limited. Further, the order of the components is not limited. Further, for example, a component referred to as “first” in one embodiment of the present specification or the like is a component referred to as “second” in another embodiment or in the claims. It is also possible. In addition, for example, the constituent elements referred to as “first” in one embodiment of the present specification and the like may be omitted in other embodiments or in the claims.

<Additional notes regarding the description explaining the drawings>
Embodiments are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms, and that the forms and details can be variously changed without departing from the spirit and scope thereof. The Therefore, the present invention should not be construed as being limited to the description of the embodiments. Note that in the structures of the embodiments of the present invention, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

  In addition, in this specification and the like, terms indicating arrangement such as “above” and “below” are used for convenience in describing the positional relationship between components with reference to the drawings. The positional relationship between the components appropriately changes depending on the direction in which each component is drawn. Therefore, the phrase indicating the arrangement is not limited to the description described in the specification, and can be appropriately rephrased depending on the situation.

  Further, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below, and is in direct contact with each other. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

  In the drawings, the size, the layer thickness, or the region is shown in an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are schematically shown for the sake of clarity, and are not limited to the shapes or values shown in the drawings. For example, variation in signal, voltage, or current due to noise, variation in signal, voltage, or current due to timing shift can be included.

  In the drawings, some components may be omitted from the perspective views and the like for the sake of clarity.

  In the drawings, the same element, an element having a similar function, an element of the same material, or an element formed at the same time may be denoted by the same reference numeral, and repeated description thereof may be omitted. .

<Additional notes on paraphrased descriptions>
In this specification and the like, when describing a connection relation of a transistor, one of a source and a drain is referred to as “one of a source and a drain” (or a first electrode or a first terminal), and the source and the drain The other is referred to as “the other of the source and the drain” (or the second electrode or the second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of the transistor can be appropriately rephrased depending on the situation, such as a source (drain) terminal or a source (drain) electrode. In this specification and the like, two terminals other than the gate may be referred to as a first terminal and a second terminal, or may be referred to as a third terminal and a fourth terminal. Note that in this specification and the like, a channel formation region refers to a region where a channel is formed by applying a potential to a gate, and current can flow between a source and a drain by forming this region. it can.

  In addition, the functions of the source and drain may be switched when transistors having different polarities are employed or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.

  In addition, when a transistor described in this specification and the like has two or more gates (this structure is sometimes referred to as a dual gate structure), these gates may be referred to as a first gate and a second gate, , Sometimes called back gate. In particular, the phrase “front gate” can be rephrased as simply the phrase “gate”. Also, the phrase “back gate” can be rephrased simply as the phrase “gate”. Note that a bottom gate refers to a terminal formed before a channel formation region when a transistor is manufactured, and a “top gate” is formed after a channel formation region when a transistor is manufactured. Terminal.

  Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

  In this specification and the like, voltage and potential can be described as appropriate. The voltage is a potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), the voltage can be rephrased as a potential. The ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

  Note that in this specification and the like, terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer”. Alternatively, in some cases or depending on circumstances, it is possible to replace with another term without using a phrase such as “film” or “layer”. For example, the term “conductive layer” or “conductive film” may be changed to the term “conductor” in some cases. Alternatively, for example, the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.

  Note that in this specification and the like, terms such as “wiring”, “signal line”, and “power supply line” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term “wiring” to the term “signal line”. In addition, for example, the term “wiring” may be changed to a term such as “power supply line”. The reverse is also true, and there are cases where terms such as “signal line” and “power supply line” can be changed to the term “wiring”. A term such as “power line” may be changed to a term such as “signal line”. The reverse is also true, and a term such as “signal line” may be changed to a term such as “power line”. In addition, the term “potential” applied to the wiring may be changed to a term “signal” or the like depending on circumstances or circumstances. The reverse is also true, and a term such as “signal” may be changed to a term “potential”.

<Notes on the definition of words>
Below, the definition of the phrase referred in the said embodiment is demonstrated.

<< About impurities in semiconductor >>
The semiconductor impurity means, for example, other than the main component constituting the semiconductor layer. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When the impurities are included, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

<< About the switch >>
In this specification and the like, a switch refers to a switch that is in a conductive state (on state) or a non-conductive state (off state) and has a function of controlling whether or not to pass current. Alternatively, the switch refers to a switch having a function of selecting and switching a current flow path.

  As an example, an electrical switch or a mechanical switch can be used. That is, the switch is not limited to a specific one as long as it can control the current.

  Examples of electrical switches include transistors (for example, bipolar transistors, MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes. , Diode-connected transistors, etc.), or a logic circuit combining these.

  Note that in the case where a transistor is used as the switch, the “conducting state” of the transistor means a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically short-circuited. In addition, the “non-conducting state” of a transistor refers to a state where the source electrode and the drain electrode of the transistor can be regarded as being electrically disconnected. Note that when a transistor is operated as a simple switch, the polarity (conductivity type) of the transistor is not particularly limited.

  An example of a mechanical switch is a switch using MEMS (micro electro mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

<< About connection >>
In this specification and the like, when X and Y are described as being connected, when X and Y are electrically connected, and when X and Y are functionally connected And the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the figure or text, and includes things other than the connection relation shown in the figure or text.

  X, Y, and the like used here are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

  As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current.

  As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do.

  Note that when X and Y are explicitly described as being electrically connected, when X and Y are electrically connected (that is, another element between X and Y). Or when X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And a case where X and Y are directly connected (that is, a case where another element or another circuit is not connected between X and Y). That is, when it is explicitly described that it is electrically connected, it is the same as when it is explicitly only described that it is connected.

  Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.

  For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal, etc.) of the transistor is electrically connected to X, the drain (or the second terminal, etc.) of the transistor is electrically connected to Y, and X, the source of the transistor ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

  In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

<< About parallel and vertical >>
In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

MC [1] Memory cell MC [2] Memory cell MC [n] Memory cell MC [1, 1] Memory cell MC [j, 1] Memory cell MC [n, 1] Memory cell MC [1, i] Memory cell MC [j, i] Memory cell MC [n, i] Memory cell MC [1, m] Memory cell MC [j, m] Memory cell MC [n, m] Memory cell WWL [1] Wiring WWL [2] Wiring WWL [j] Wiring WWL [n] Wiring RWL [1] Wiring RWL [2] Wiring RWL [j] Wiring RWL [n] Wiring WBL Wiring WBL [1] Wiring WBL [i] Wiring WBL [m] Wiring RBL Wiring RBL [1] Wiring RBL [i] Wiring RBL [m] Wiring BGL Wiring BGL [1] Wiring BGL [i] Wiring BGL [m] Wiring WTr Transistor RTr Transistor CS Capacitance element N1 Node N2 Node Node PG Conductor WWL Wiring RWL Wiring ER Wiring HL Region AR Region SD1 Region SD2 Region 100 Laminate 101A Insulator 101B Insulator 101C Insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductor 133 Conductor 133a Conductor 133b Conductor 133c Conductor 134 Conductor 151 Semiconductor 151a Region 151b Region 151c Region 152 Semiconductor 153 Semiconductor 153a Semiconductor 153b Semiconductor 181A Region 181B Region 182A Region 18 183A region 183B region 191 opening 192A recess 192B recess 193A recess 193B recess 194A recess 194B recess 194C recess 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1189 ROM interface 1190 Substrate 1700 Substrate 1701 Element isolation layer 1712 Conductor 1730 Conductor 1790 Gate electrode 1792 Well 1793 Channel formation region 1794 Low concentration impurity region 1795 High concentration impurity region 1796 Conductive region 1797 Gate insulating film 1798 Side wall insulating layer 1799 Side wall Insulating layer 2600 Memory device 2601 Peripheral circuit 2610 Memory cell array 2621 Row decoder 2622 Word line driver circuit 2630 Bit line driver circuit 2631 Column decoder 2632 Precharge circuit 2633 Sense amplifier 2634 Write circuit 2640 Output circuit 2660 Control logic circuit 5100 USB memory 5101 Housing 5102 Cap 5103 USB connector 5104 Board 5105 Memory chip 5106 controller chip 5110 SD card 5111 housing 5112 connector 5113 substrate 5114 memory chips 5115 controller chip 5150 SSD
5151 Housing 5152 Connector 5153 Board 5154 Memory chip 5155 Memory chip 5156 Controller chip 5401 Housing 5402 Display unit 5403 Keyboard 5404 Pointing device 5501 Housing 5502 Display unit 5503 Microphone 5504 Speaker 5505 Operation buttons 5701 Display panel 5702 Display panel 5703 Display panel 5704 Display panel 5801 First housing 5802 Second housing 5803 Display unit 5804 Operation key 5805 Lens 5806 Connection unit 5901 Housing 5902 Display unit 5903 Operation button 5904 Operator 5905 Band 9000 Housing 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection Terminal 9007 sensor

Claims (9)

A semiconductor device having first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor;
The first conductor has an upper surface of the first insulator,
The second insulator has an upper surface of the first conductor,
The second conductor has a first upper surface of the second insulator;
The second conductor has a first lower surface of the third insulator,
The fourth insulator includes a side surface of the first insulator, a side surface of the first conductor, a side surface of the second insulator, a second upper surface of the second insulator, and the second conductor. A side surface of the third insulator, a second lower surface of the third insulator, and a side surface of the third insulator.
The third conductor has a region overlapping the side surface of the second conductor in a region where the fourth insulator is formed,
The first semiconductor is
A formation surface of the third conductor;
Of the region where the fourth insulator is formed, a region overlapping with the side surface of the first insulator, a region overlapping with the side surface of the second conductor, and a side surface of the second insulator are overlapped. A region and a region overlapping with a side surface of the third insulator,
The fifth insulator has a formation surface of the first semiconductor,
The semiconductor device, wherein the second semiconductor is provided on a formation surface of the fifth insulator. A semiconductor device having first to fifth insulators, first to third conductors, and first to third semiconductors;
The first conductor has a first upper surface of the first insulator;
The first conductor has a first lower surface of the second insulator;
The second conductor has a first upper surface of the second insulator;
The second conductor has a first lower surface of the third insulator,
The third semiconductor has a region including a second upper surface of the first insulator, a side surface of the first conductor, and a second lower surface of the second insulator;
The fourth insulator includes a side surface of the first insulator, a formation surface of the first semiconductor, a side surface of the second insulator, a second upper surface of the second insulator, and the second conductor. A side surface of the third insulator, a second lower surface of the third insulator, and a side surface of the third insulator.
The third conductor has a region overlapping the side surface of the second conductor in a region where the fourth insulator is formed,
The first semiconductor is
A formation surface of the third conductor;
Of the region where the fourth insulator is formed, a region overlapping with the side surface of the first insulator, a region overlapping with the formation surface of the third semiconductor, and a side surface of the second insulator are overlapped. A region and a region overlapping with the third insulator,
The fifth insulator has a formation surface of the first semiconductor,
The semiconductor device, wherein the second semiconductor is provided on a formation surface of the fifth insulator. A semiconductor device having a first to a fourth insulator, a first to a fourth conductor, a first semiconductor, and a second semiconductor;
The first insulator has a first upper surface of the first conductor;
The second conductor has a first upper surface of the first insulator;
The second insulator has a first lower surface of the third conductor;
The second conductor has a first lower surface of the second insulator,
The third insulator includes a side surface of the first conductor, a second upper surface of the first conductor, a side surface of the first insulator, a second upper surface of the first insulator, and the second insulator. A side surface of the conductor, a second lower surface of the second insulator, a side surface of the second insulator, a second lower surface of the third conductor, and a side surface of the third conductor. Have
The fourth conductor includes a region that overlaps a side surface of the first insulator, a region that overlaps a side surface of the second conductor, and a second region of the region where the third insulator is formed. A region overlapping the side surface of the insulator,
The first semiconductor is
A formation surface of the fourth conductor;
Of the region where the third insulator is formed, the region overlaps with the first conductor and the region overlaps with the third conductor.
The fourth insulator has a formation surface of the first semiconductor,
The semiconductor device, wherein the second semiconductor has a formation surface of the fourth insulator. In claims 1 to 3,
A sixth insulator and a fifth conductor;
The sixth insulator has a formation surface of the second semiconductor,
The semiconductor device, wherein the fourth conductor is provided on a formation surface of the sixth insulator. In Claims 1 to 4,
The semiconductor device, wherein the first semiconductor includes a metal oxide. In claims 1 to 5,
The semiconductor device, wherein the second semiconductor includes a metal oxide. In claims 1 to 5,
The semiconductor device, wherein the second semiconductor includes silicon.   A memory device comprising the semiconductor device according to claim 1 and a peripheral circuit.   An electronic apparatus comprising the storage device according to claim 8 and a housing.