JP2023093611A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device having a large storage capacity.SOLUTION: A semiconductor device includes first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor. An opening is provided collectively for a structure in which the first insulator, the first conductor, the second insulator, the second conductor and the third insulator are stacked in the order. Further, the second conductor is selectively removed by etching in the opening. Then, the fourth insulator is formed on a side face of the opening, and the third conductor is formed in a region where the second conductor is removed. The first semiconductor, the fifth insulator and the second semiconductor are formed in order in the remaining opening to form a semiconductor device having a three-dimensional structure. A material containing a metal oxide may be applied for the first semiconductor, and a material containing a metal oxide or silicon may be applied for the second semiconductor.SELECTED DRAWING: Figure 10

Description

One embodiment of the present invention relates to semiconductor devices, memory devices, and electronic devices.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention is
Process, Machine, Manufacture, or Composition of Matter
It is about. Therefore, the technical fields of one embodiment of the present invention disclosed in this specification more specifically include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices,
Storage devices, processors, electronic devices, methods for driving them, methods for manufacturing them, methods for testing them, or systems having at least one of them can be given as examples.

In recent years, electronic components such as central processing units (CPUs), graphics processing units, storage devices, and sensors have been used in various electronic devices such as personal computers, smartphones, and digital cameras. Improvements are progressing in various aspects such as low power consumption.

In particular, in recent years, the amount of data handled by the electronic devices described above has been increasing, and a storage device with a large storage capacity has been demanded. Patent Documents 1 and 2 disclose a semiconductor device capable of writing and reading multilevel data. In addition, in order to realize a memory device having a large memory capacity, a technique for miniaturizing circuits included in the memory device is required.

JP 2012-256400 A JP 2014-199707 A

An object of one embodiment of the present invention is to provide a novel semiconductor device. Alternatively, an object of one embodiment of the present invention is to provide a memory device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device using a memory device including a novel semiconductor device. Another object of one embodiment of the present invention is to provide a storage device with a large data capacity. Alternatively, an object of one embodiment of the present invention is to provide a highly reliable storage device.

Note that the problem of one embodiment of the present invention is not limited to the problems listed above. The issues listed above do not preclude the existence of other issues. Still other issues are issues not mentioned in this section, which will be described in the following description. Problems not mentioned in this section can be derived from the descriptions in the specification, drawings, or the like by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention is to solve at least one of the above-described problems and other problems. Note that one embodiment of the present invention does not necessarily solve all of the above-listed descriptions and other problems.

(1)
One embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, a first semiconductor, and a second semiconductor; A second
The insulator is provided on the upper surface of the first conductor, the second conductor is provided on the first upper surface of the second insulator, and the second conductor is provided on the upper surface of the second insulator.
The conductor is provided on the first lower surface of the third insulator, and the fourth insulator includes side surfaces of the first insulator, side surfaces of the first conductor, side surfaces of the second insulator, and the second insulator. the second upper surface of the second conductor, the side surface of the second conductor, and the third
It is connected to a region including the second lower surface of the insulator and the side surface of the third insulator, and the third conductor is the second conductor in the region in which the fourth insulator is formed. It has in the area overlapping with the side surface,
The first semiconductor includes a surface on which the third conductor is formed, a region overlapping with the side surface of the first insulator in a region where the fourth insulator is formed, and a region overlapping with the side surface of the second conductor. , a region overlapping with the side surface of the second insulator and a region overlapping with the side surface of the third insulator, the fifth insulator having the formation surface of the first semiconductor, the second semiconductor having: It is a semiconductor device characterized by having it on the formation surface of a 5th insulator.

(2)
Alternatively, one embodiment of the present invention is a semiconductor device including first to fifth insulators, first to third conductors, and first to third semiconductors, wherein the first conductor is the first conductor. on the first top surface of the insulator,
A first conductor is provided on the first lower surface of the second insulator, a second conductor is provided on the first upper surface of the second insulator, and a second conductor is provided on the first lower surface of the third insulator. a third semiconductor in a region including a second upper surface of the first insulator, side surfaces of the first conductor, and a second lower surface of the second insulator;
A side surface of the first insulator, a formation surface of the first semiconductor, a side surface of the second insulator, a second upper surface of the second insulator, a side surface of the second conductor, and a second lower surface of the third insulator. and the side surface of the third insulator, and the third conductor is located in the area overlapping the side surface of the second conductor in the area where the fourth insulator is formed. and the first semiconductor includes a surface on which the third conductor is formed, a region overlapping the side surface of the first insulator in a region where the fourth insulator is formed, and a surface on which the third semiconductor is formed. a region overlapping with the side surface of the second insulator; a region overlapping with the third insulator; the fifth insulator having the formation surface of the first semiconductor; , and a fifth insulator formation surface.

(3)
Alternatively, one embodiment of the present invention is a semiconductor device including first to fourth insulators, first to fourth conductors, a first semiconductor, and a second semiconductor, wherein the first insulator comprises: The first conductor has a first upper surface, the second conductor has a first upper surface of the first insulator, the second insulator has a first lower surface of the third conductor, and the second The conductor is provided on the first lower surface of the second insulator, and the third insulator includes the side surface of the first conductor, the second upper surface of the first conductor, the side surface of the first insulator, and the first insulator. A second upper surface of the insulator, a side surface of the second conductor, a second lower surface of the second insulator, a side surface of the second insulator, a second lower surface of the third conductor, and a side surface of the third conductor. and the fourth conductor has a region overlapping with the side surface of the first insulator and a region overlapping with the side surface of the second conductor in the region where the third insulator is formed. and a region that overlaps with the side surface of the second insulator, the first semiconductor includes a surface on which the fourth conductor is formed, and
In the region where the third insulator is formed, it has a region overlapping with the first conductor and a region overlapping with the third conductor, and the fourth insulator is on the formation surface of the first semiconductor and the second semiconductor has a fourth
The semiconductor device is characterized in that it is provided on a formation surface of an insulator.

(4)
Alternatively, according to one embodiment of the present invention, in any of the above (1) to (3), the sixth insulator and the fifth conductor are provided, and the sixth insulator is provided on the formation surface of the second semiconductor. , the fourth conductor is provided on the formation surface of the sixth insulator.

(5)
Alternatively, one embodiment of the present invention is the semiconductor device in any of (1) to (4) above, in which the first semiconductor includes a metal oxide.

(6)
Alternatively, one embodiment of the present invention is the semiconductor device in any of (1) to (5) above, in which the second semiconductor includes a metal oxide.

(7)
Alternatively, one embodiment of the present invention is the semiconductor device in any of (1) to (5) above, in which the second semiconductor contains silicon.

(8)
Alternatively, one embodiment of the present invention is a memory device including any of the semiconductor devices described in (1) to (7) and a peripheral circuit.

(9)
Alternatively, one embodiment of the present invention is an electronic device including the storage device described in (8) and a housing.

One embodiment of the present invention can provide a novel semiconductor device. Alternatively, according to one embodiment of the present invention, a memory device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, an electronic device using a memory device including a novel semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a storage device with a large data capacity can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable storage device can be provided.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Still other effects are effects not mentioned in this section that will be described in the following description. Effects not mentioned in this item can be derived from the descriptions in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Accordingly, one aspect of the present invention may not have the effects listed above depending on the case.

FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device; FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device; FIG. 2 is a circuit diagram showing a configuration example of a semiconductor device; 4 is a flowchart showing an operation example of a semiconductor device; 1A and 1B are a top view and a cross-sectional view for explaining a configuration example of a semiconductor device; FIG. 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; 5A to 5C are cross-sectional views for explaining an example of manufacturing a semiconductor device; FIG. 3 is a cross-sectional view for explaining a semiconductor device; FIG. 3 is a cross-sectional view for explaining a semiconductor device; FIG. 3 is a cross-sectional view for explaining a semiconductor device; 4 is a block diagram showing an example of a storage device; FIG. The figure explaining the range of the atomic ratio of a metal oxide. FIG. 3 is a block diagram for explaining a CPU; 1 is a perspective view showing an example of an electronic device; FIG. 1 is a perspective view showing an example of an electronic device; FIG.

In this specification and the like, a metal oxide is a metal oxide in broad terms. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as oxide semiconductors or simply OSs).
etc. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, when a metal oxide can constitute a channel formation region of a transistor having at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide is called a metal oxide semiconductor (metal oxide semiconductor).
icon), which can be abbreviated as OS. In the case of describing an OS FET, it can also be referred to as a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, a transistor including silicon in a channel formation region is referred to as Si.
It may be described as a transistor.

In addition, in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide (metal ox
ide) in some cases. In addition, a metal oxide containing nitrogen is a metal oxynitride (me
tal oxynitride).

(Embodiment 1)
In this embodiment, a circuit configuration, an operation method, and a manufacturing method of a semiconductor device according to one embodiment of the disclosed invention will be described. In the description below, for example, "[x, y]" means an element in the x-th column and y-th column, and "[z]" means an element in the z-th row or z-th column.
These notations are omitted when there is no particular need to specify a row or column.

<Example of circuit configuration>
First, the circuit configuration of a semiconductor device is described with reference to FIG. Figure 1 (A
) shows a circuit diagram of n (n is an integer equal to or greater than 1) memory cells. That is, the memory cells MC[1] to MC[n], the wirings WWL[1] to WWL[n], and the wirings RWL[1] to RWL[n] for controlling them.
], a wiring WBL, and a wiring RBL. Note that the wiring WWL functions as a write word line, the wiring RWL functions as a read word line, the wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line.

Each memory cell MC includes a transistor WTr, a transistor RTr, a capacitive element C
S. The transistor RTr illustrated in FIG. 1A has a back gate, and application of a potential to the back gate can change the threshold voltage of the transistor RTr. Note that the wiring BGL illustrated in FIG. 1A is electrically connected to the back gates of the transistors RTr included in the memory cells MC[1] to MC[n]. In the semiconductor device illustrated in FIG. 1, the wiring BGL is not electrically connected to the back gates of the transistors RTr included in the memory cells MC[1] to MC[n]. may be electrically connected to each other independently to supply potentials different from each other.

A channel formation region of the transistor WTr preferably contains the metal oxide described in Embodiment 3. In particular, in the case of a metal oxide selected from one or more of indium, element M (element M is, for example, aluminum, gallium, yttrium, tin, etc.), and zinc, the metal oxide functions as a wide-gap semiconductor. Therefore, a transistor including the metal oxide in a channel formation region has very low off-state current. By using a transistor having this characteristic as the transistor WTr that holds data, data can be held in the memory cell MC for a long time. Accordingly, since the number of refreshes of held data can be reduced, power consumption of the semiconductor device can be reduced.

Further, for a channel formation region of the transistor RTr, a material with which the field-effect mobility of the transistor is high is preferably used. By using such a transistor,
A semiconductor device can operate faster. For example, as a material included in the channel formation region of the transistor RTr, a semiconductor material such as a metal oxide or silicon described in Embodiment 3 can be used.

The transistor WTr functions as a write transistor, and the transistor RTr functions as a read transistor. Switching between the on state and the off state of the transistor WTr is performed by the potential applied to the wiring WWL. The potential of one electrode of the capacitor CS is controlled by the wiring RWL. The other electrode of the capacitor CS is electrically connected to the gate of the transistor RTr. The other electrode of the capacitive element CS can be called a memory node. A memory node of each memory cell MC is electrically connected to a first terminal of a transistor WTr included in the memory cell MC.

In terms of circuit configuration, the second terminal of the transistor WTr is electrically connected in series with the first terminal of the transistor WTr of the adjacent memory cell MC. Similarly, the first terminal of transistor RTr is in series with the second terminal of transistor RTr of an adjacent memory cell,
electrically connected. Then, the second transistor WTr included in the memory cell MC[n]
The terminal is electrically connected to the wiring WBL and the transistor R included in the memory cell MC[n].
A second terminal of Tr is electrically connected to the wiring RBL. Note that in this embodiment, a connection point between the second terminal of the transistor RTr included in the memory cell MC[n] and the wiring RBL is referred to as a node N1, and the first terminal of the transistor RTr included in the memory cell MC[1] is referred to as a node N1. is called node N2. Note that in order to control the conduction state between the node N1 and the wiring RBL,
A selection transistor may be connected in series with the transistor RTr. Similarly, node N
2 and the node N2, the transistor R
A selection transistor may be connected in series with Tr.

Note that one embodiment of the present invention is not limited to the semiconductor device illustrated in FIG. One embodiment of the present invention can have a circuit structure in which the semiconductor device illustrated in FIG. 1A is changed as appropriate, depending on circumstances or as needed. For example, as illustrated in FIG. 1B, one embodiment of the present invention may be a semiconductor device in which the transistor WTr is also provided with a back gate if necessary. Note that in addition to the configuration of the semiconductor device illustrated in FIG. 1A, the semiconductor device illustrated in FIG. 1B has transistors WTr included in the memory cells MC[1] to MC[n]. , and each of the back gates is electrically connected to the wiring BGL. Further, for example, as illustrated in FIG. 1C, one embodiment of the present invention may be a semiconductor device in which the transistor RTr and the transistor WTr are not provided with back gates.

1A, 1B, and 1C, the semiconductor devices shown in FIGS. 1A, 1B, and 1C are arranged in a matrix. do it. For example, when the semiconductor devices illustrated in FIG. 1B are arranged in a matrix, the circuit configuration is illustrated in FIG.

In the semiconductor device shown in FIG. 2, the semiconductor devices shown in FIG. 2B are arranged in m columns (where m is an integer of 1 or more) with one column, and the wiring RWL and the wiring WWL are arranged in the same row. are electrically connected so as to be shared with other memory cells MC. That is, the semiconductor device illustrated in FIG. 2 is a matrix semiconductor device with n rows and m columns, and includes memory cells MC[1,1] to MC[n,m]. Therefore, the semiconductor device shown in FIG.
[1] to wiring RWL[n], wiring WWL[1] to wiring WWL[n], and wiring RBL
[1] to wiring RBL[m], wiring WBL[1] to WBL[m], wiring BGL[1]
] to wiring BGL[m]. Specifically, memory cell MC[j, i] (j is an integer of 1 to n and i is an integer of 1 to m).
One electrode of the capacitive element CS of is electrically connected to the wiring RWL[j], and the memory cell MC
A gate of the transistor WTr in [j, i] is electrically connected to the wiring WWL[j]. The wiring WBL[i] is electrically connected to the second terminal of the transistor WTr of the memory cell MC[n, i], and the wiring RBL[i] is connected to the transistor RT of the memory cell MC[n, i].
is electrically connected to the second terminal of r.

2, memory cell MC[1,1], memory cell MC[1,i], memory cell M
C[1,m], memory cell MC[j,1], memory cell MC[j,i], memory cell MC
[j,m], memory cell MC[n,1], memory cell MC[n,i], memory cell MC[
n, m], wiring RWL[1], wiring RWL[j], wiring RWL[n], wiring WWL[1]
, wiring WWL[j], wiring WWL[n], wiring RBL[1], wiring RBL[i], wiring R
BL[m], wiring WBL[1], wiring WBL[i], wiring WBL[m], wiring BGL[1
], the wiring BGL[i], the wiring BGL[m], the capacitor CS, the transistor WTr, the transistor RTr, the node N1, and the node N2 are illustrated, and other wirings, elements, symbols, and symbols are omitted. there is

Further, the semiconductor device shown in FIG. 2C is taken as one column, and m columns (m is an integer of 1 or more) are arranged.
The side-by-side arrangement is shown in FIG. Note that the semiconductor device shown in FIG. 3 has a configuration in which back gates are not provided in the transistors of all the memory cells MC.
Therefore, the semiconductor device shown in FIG. 3 does not have the wiring BGL. Note that for the semiconductor device in FIG. 3, the description of the semiconductor device in FIG. 2 is referred to.

<Example of operation method>
Next, an example of an operation method of the semiconductor device illustrated in FIGS. 1A to 1C is described. Note that low-level potential and high-level potential used in the following description do not mean specific potentials, and specific potentials may differ depending on wiring. For example, wiring WW
The low-level potential and high-level potential applied to L may be potentials different from the low-level potential and high-level potential applied to the wiring RWL.

In addition, in this operation method example, the wiring BGL illustrated in FIGS. 1A and 1B and BGW[1] to BGW[n] illustrated in FIG. It is assumed that a potential within the operating range is applied in advance. Therefore, in Fig. 1 (
The operations of the semiconductor devices shown in A) to (C) can be considered in the same way.

FIG. 4A is a timing chart showing an operation example of writing data to a semiconductor device, and FIG. 4B is a timing chart showing an operation example of reading data from the semiconductor device. Timing charts in FIGS. 4A and 4B show the wiring WWL[1], the wiring WWL[2], the wiring WWL[n], the wiring RWL[1], the wiring RWL[2], and the wiring RWL.
[n], node N1, and node N2. Also, the wiring W
BL indicates data supplied to the wiring WBL.

FIG. 4A shows data D[1] to data D[n] each stored in memory cell MC[1].
to memory cell MC[n]. Note that data D[1] to data D[n] can be binary or multivalued. Then, data D[1] to data D
[n] is supplied from the wiring WBL. That is, in the circuit configurations of the semiconductor devices illustrated in FIGS. 1A to 1C, data is written sequentially from the memory cell MC[1] to the memory cell MC[n].

Conversely, if an attempt is made to write data to memory cell MC[1] after data has been written to memory cell MC[2], the data written to memory cell MC[2] is first read and stored in another location. Otherwise, the data held in memory cell MC[2] will be lost at the stage of writing data to memory cell MC[1].

In the circuit configuration of the semiconductor device shown in FIGS. 1A to 1C, the memory cell MC[i] (
i is an integer of 2 or more and n or less. ), in order to prevent the data held in the memory cells MC[1] to MC[i−1] from being rewritten, the wiring WWL
[1] to the wiring WWL[i−1] are supplied with a low-level potential to turn off the transistors WTr included in the memory cells MC[1] to MC[i−1]. Thus, each data held in the memory cells MC[1] to MC[i−1] can be protected.

Further, when data is written to the memory cell MC[i], the data is supplied from the wiring WBL. ] to the respective transistors WTr included in the memory cells MC[n] are sufficiently turned on. Thereby, data can be held in the memory node of the memory cell MC[i].

Note that in the case of writing data to the circuit structures of the semiconductor devices illustrated in FIGS. 1A to 1C, the wiring RBL can be controlled independently; therefore, the wiring RBL need not have a specific potential; be able to. Further, the potential of the wiring RWL, that is, the node N1 can be a low-level potential. In addition, the potential of node N2 can also be a low level potential.

Based on the above description, an operation example shown in the timing chart of FIG. 4A will be described. At time T10, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wirings WBL, the nodes N1, and N2 are low-level potentials. .

At time T11, a high-level potential is supplied to the wirings WWL[1] to WWL[n]. Accordingly, the transistors WTr included in the memory cells MC[1] to MC[n] are sufficiently turned on. Data D[
1] is supplied. Since the transistors WTr included in the memory cells MC[1] to MC[n] are sufficiently on, the data D[1] does not reach the memory node of the memory cell MC[1]. written as

At time T12, the wiring WWL[1] is supplied with a low-level potential, and the wiring WWL[1]
2] to the wiring WWL[n] are continuously supplied with the high-level potential. As a result, the transistor WTr included in the memory cell MC[1] is turned off, and the memory cell MC[2] is turned off.
] to the transistors WTr included in the memory cells MC[n] are sufficiently turned on. Data D[2] is supplied to the wiring WBL. Since the transistors WTr included in the memory cells MC[2] to MC[n] are sufficiently on, the data D[2] does not reach the memory node of the memory cell MC[2]. written as Further, since the transistor WTr of the memory cell MC[1] is in an off state, the data D[1] held in the memory cell MC[1] is lost by the write operation from time T12 to time T13. can't break

Between time T13 and time T14, data D[1] is written to memory cell MC[1] between time T11 and time T12, and memory cell MC[1] is written between time T12 and time T13. 2] as well as each of the write operations of data D[2] to
Data D[3] to D[n−1] are sequentially written to the memory cells MC[3] to MC[n−1], respectively. Specifically, the transistors WTr included in the memory cells MC[1] to MC[j−1] (where j is an integer greater than or equal to 3 and less than or equal to n−1) to which data has already been written are turned off; Memory cell MC to which no data is written
The transistors WTr included in the memory cells MC[j] to MC[n] are sufficiently turned on, and the data D[j] is supplied from the wiring WBL and written to the memory node of the memory cell MC[j]. Then, when the writing of the data D[j] to the memory cell MC[j] is completed, the transistor WTr included in the memory cell MC[j] is turned off, and the data D[j+1] is supplied from the wiring WBL. An operation of writing to the memory node of the memory cell MC[j+1] may be performed. Note that the write operation when j is n−1 is the time T14 described below.
to time T15.

At time T14, the wirings WWL[1] to WWL[n−1] are supplied with a low-level potential, and the wiring WWL[n] is continuously supplied with a high-level potential. Accordingly, the transistors WTr included in the memory cells MC[1] to MC[n−1] are turned off, and the transistors WTr included in the memory cell MC[n] are sufficiently turned on. Data D[n] is supplied to the wiring WBL. Memory cell MC
Since each transistor WTr included in [n] is sufficiently on, the data D[n] reaches the memory node of the memory cell MC[n] and is written. In addition, since the transistors WTr of the memory cells MC[1] to MC[n−1] are in the off state, the transistors WTr of the memory cells MC[1] to MC[n−1] are held in the respective memory cells MC[1] to MC[n−1]. Data D[1] to Data D[n-1] are stored in the data from time T14 to time T15.
not lost by write operations up to

By the above operation, in any one of the semiconductor devices shown in FIGS.
Data can be written to the memory cell MC included in the semiconductor device.

FIG. 4B shows data D[1] to data D[n] each stored in memory cell MC[1].
to an example of reading from the memory cell MC[n]. Note that at this time, the transistor WTr is required to be in an off state in order to maintain the data held in each memory cell MC. Therefore, in the operation of reading data from the memory cells MC[1] to MC[n], the potentials of the wirings WWL[1] to WWL[n] are low.

In the circuit configuration of the semiconductor device shown in FIG. 1, when reading data from a specific memory cell MC, the transistor RTr of the other memory cell MC is sufficiently turned on, and then the transistor of the specific memory cell MC is read. RTr is operated as a saturation region. That is, the current flowing between the source and drain of the transistor RTr included in the specific memory cell MC is determined according to the source-drain voltage and the data held in the specific memory cell MC.

For example, consider the case of reading data held in a memory cell MC[k] (k is an integer equal to or greater than 1 and equal to or less than n). At this time, memory cells M other than memory cell MC[k]
In order to sufficiently turn on the transistors RTr included in the memory cells C[1] to MC[n], the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are supplied with a high-level potential. supplied.

On the other hand, the transistor RTr included in the memory cell MC[k] is turned on according to the held data. The potential must be the same as that of the wiring RWL[k]. Note that here, the potential of the wiring RWL[k] during the writing operation and the reading operation is considered to be a low-level potential.

For example, a potential of +3V is applied to the node N1 and a potential of 0V is applied to the node N2. and node N2
is set to float, and the potential of the node N2 is measured after that. When the potentials of the wirings RWL[1] to RWL[n] excluding the wiring RWL[k] are set to a high level potential, the memory cells MC[1] to MC[n] excluding the memory cell MC[k] ] is sufficiently turned on. On the other hand, the voltage between the first terminal and the second terminal of the transistor RTr included in the memory cell MC[k] is determined by the potential of the gate of the transistor RTr and the potential of the node N1. k] memory nodes.

Thus, the data held in the memory cell MC[k] can be read.

Based on the above description, an operation example shown in the timing chart of FIG. 4B will be described. At time T20, the potentials of the wirings WWL[1] to WWL[n], the wirings RWL[1] to RWL[n], the wirings WBL, the nodes N1, and N2 are low-level potentials. . In particular, node N2 is in a floating state. It is assumed that data D[1] to data D[n] are held in the memory nodes of the memory cells MC[1] to MC[n], respectively.

At time T21, the wiring RWL[1] is supplied with a low-level potential, and the wiring RWL[1] is supplied with a low-level potential.
2] to the wiring WWL[n] are supplied with a high-level potential. As a result, the memory cell M
Each transistor RTr included in memory cells C[2] to MC[n] is sufficiently turned on. The transistor RTr of memory cell MC[1] is connected to memory cell MC[1].
1] is turned on according to the data D[1] held in the memory node D[1]. In addition, the potential _VR is supplied to the wiring RBL. As a result, the potential of the node N1 becomes V _R and the potential of the node N
2 depends on the potential _VR of the node N1 and the potential of the node N2 depends on the data held in the memory node of the memory cell MC[1]. Here, the potential of the node N2 is V _D[1
] . Then, by measuring the potential _VD[1] of the node N2, the memory cell M
Data D[1] held in the memory node of C[1] can be read.

At time T22, a low-level potential is supplied to the wirings RWL[1] to WWL[n]. A low-level potential is supplied to the node N2, after which the node N2 becomes floating. That is, from time T22 to time T23, the wiring RW
The potentials of L[1] to the wiring WWL[n] and the node N2 change from time T20 to time T
The situation will be the same as before 21. Note that the wiring RBL may continue to be supplied with the potential _VR or may be supplied with a low-level potential. In this operation example, the wiring RBL is
21 onward, the potential V _R continues to be supplied.

At time T23, the wiring RWL[2] is supplied with a low-level potential, and the wiring RWL[2] is supplied with a low-level potential.
1] and the wirings RWL[3] to WWL[n] are supplied with a high-level potential. Accordingly, the transistors RTr included in the memory cell MC[1], memory cell MC[3] to memory cell MC[n] are sufficiently turned on. and memory cell MC[2]
transistor RTr is turned on according to data D[2] held in the memory node of memory cell MC[2]. Further, the potential _VR is still supplied to the wiring RBL. Thus, the potential of the node N2 is determined by the potential _VR of the node N1 and the potential of the node N2 is determined by the data held in the memory node of the memory cell MC[2]. Here, the potential of the node N2 is _VD[2] . By measuring the potential VD _[2] of the node N2, the data D[2] held in the memory node of the memory cell MC[2] can be read.

Between time T24 and time T25, data D[1] is read from memory cell MC[1] between time T20 and time T22, and memory cell MC[1] is read between time T22 and time T24. 2], and data D[2] is sequentially read from each of the memory cells MC[3] to MC[n-1].
3] to data D[n−1] are read. Specifically, when data D[j] is read from memory cell MC[j] (where j is an integer of 3 or more and n−1 or less), the potential of node N2 is set to a low level potential, and node N2 is set to a low level potential. After the floating state, the wiring RWL
A high-level potential is supplied to the wirings RWL[1] to RWL[n] excluding the memory cell [j], and the memory cells MC[1] to MC[n] excluding the memory cell MC[j] have The transistor RTr is sufficiently turned on, and the transistor RT included in the memory cell MC[j] is turned on.
r is turned on according to data D[j]. Next, by setting the potential of the node N1 to _VR , the potential of the node N2 becomes a potential corresponding to the data D[j]. By measuring this potential, the data D[j] can be read. . Note that after the data D[j] held in the memory cell MC[j] has been read, the wiring RWL is read as preparation for the next read operation.
A low-level potential is supplied to the wirings [1] to WWL[n], the node N2 is supplied with the low-level potential, and then the node N2 is brought into a floating state. Note that when j is n-1, this preparation refers to the operation from time T25 to time T26.

At time T25, a low-level potential is supplied to the wirings RWL[1] to WWL[n]. A low-level potential is supplied to the node N2, after which the node N2 becomes floating. That is, from time T25 to time T26, the wiring RW
The potentials of L[1] to the wiring WWL[n] and the node N2 change from time T20 to time T
The situation will be the same as before 21. Note that the wiring RBL may continue to be supplied with the potential _VR or may be supplied with a low-level potential. In this operation example, the wiring RBL is
21 onward, the potential V _R continues to be supplied.

At time T26, the wiring RWL[n] is supplied with a low-level potential, and the wiring RWL[n]
1] to the wiring WWL[n−1] are supplied with a high-level potential. As a result, the transistors RTr included in the memory cells MC[1] to MC[n−1] are sufficiently turned on. Then, the transistor RTr of the memory cell MC[n] is turned on according to the data D[n] held in the memory node of the memory cell MC[n].
Further, the potential _VR is still supplied to the wiring RBL. Thus, the potential of the node N2 is determined by the potential _VR of the node N1 and the potential of the node N2 is determined by the data held in the memory node of the memory cell MC[n]. Here, the potential of the node N2 is _VD[n] . Then, by measuring the potential _VD[n] of the node N2, the memory cell MC[n
] can be read out.

Through the above operation, data can be read from each memory cell MC of the semiconductor devices illustrated in FIGS.

<Structure example and manufacturing method example>
In order to help understanding of the structure of the semiconductor device of this embodiment mode, a manufacturing method thereof will be described below.

5A and 5B are schematic diagrams showing the semiconductor device shown in FIGS. 1A to 1C. FIG. 5A shows a top view of the semiconductor device, and FIG. 5B shows a cross-sectional view corresponding to the dashed-dotted line A1-A2 in FIG. 5A.

The semiconductor device has a structure in which a wiring RWL, a wiring WWL, and an insulator (regions not shown hatched in FIG. 5) are stacked, and an opening is provided in the structure. A conductor PG is formed so as to fill the portion. A wiring ER is formed over the conductor PG, whereby the wiring ER is electrically connected to the wiring RWL or the wiring WWL.

In addition, an opening is formed in the structure so as to collectively penetrate the wiring RWL and the wiring WWL. An insulator, a conductor, and a semiconductor are formed in the opening in order to provide the memory cell MC in the region AR through which the wiring RWL and the wiring WWL penetrate. Note that the conductor functions as the wiring WBL and the wiring RBL, and the semiconductor functions as channel formation regions of the transistor WTr and the transistor RTr. In Figure 5,
A region in which an insulator, a conductor, and a semiconductor are formed in the opening is shown as a region HL. Note that when the transistor included in the memory cell MC is provided with a back gate, the conductor included in the region HL may also function as the wiring BGL electrically connected to the back gate.

That is, in FIG. 5, the semiconductor device shown in any one of FIGS.
D1 indicates that the semiconductor device shown in FIG. 2 or 3 is configured in the region SD2.

In the following manufacturing method example 1 and manufacturing method example 2, a method for forming the memory cell MC in the region AR will be described.

<<Manufacturing method example 1>>
6 to 10 are cross-sectional views for describing an example of manufacturing the semiconductor device illustrated in FIG. 1A, and particularly cross-sectional views of the transistor WTr and the transistor RTr in the channel length direction. Also, in the cross-sectional views of FIGS. 6 to 10, some elements are omitted for clarity of illustration.

As shown in FIG. 6A, the semiconductor device in FIG. 1A includes an insulator 101A over a substrate (not shown), a conductor 131A over the insulator 101A, Insulator 101B arranged on conductor 131A and conductor 132 arranged on insulator 101B
A, an insulator 101C placed on the conductor 132A, a conductor 131B placed on the insulator 101C, an insulator 101D placed on the conductor 131B, and an insulator 101D placed on the insulator 101D. It has a conductor 132B and an insulator 101E over the conductor 132B. In addition, hereinafter, a laminated body having a plurality of conductors and a plurality of insulators will be referred to as a laminated body 1.
It is described as 00.

Note that an insulator substrate, a semiconductor substrate, or a conductor substrate may be used as the substrate, for example. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates. again,
Examples of semiconductor substrates include single semiconductor substrates such as silicon and germanium, and compound semiconductor substrates such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, a semiconductor substrate having an insulator region inside the semiconductor substrate described above, such as an SOI (Silicon On Insulator).
) substrates, etc. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.

Also, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is also a method in which after manufacturing a transistor over a non-flexible substrate, the transistor is peeled off and transferred to a substrate that is a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. A sheet, film, foil, or the like in which fibers are woven may be used as the substrate. Also, the substrate may have stretchability.
The substrate may also have the property of returning to its original shape when bending or pulling is ceased.
Alternatively, it may have the property of not returning to its original shape. The substrate is, for example, 5 μm or more and 700 μm
m or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less
It has a region with a thickness of μm or less. By thinning the substrate, the weight of a semiconductor device having a transistor can be reduced. In addition, by making the substrate thin, even when glass or the like is used, it may have stretchability, or may have the property of returning to its original shape when bending or pulling is stopped. Therefore, it is possible to mitigate the impact applied to the semiconductor device on the substrate due to dropping or the like. That is, a durable semiconductor device can be provided.

As the flexible substrate, for example, metals, alloys, resins, glass, or fibers thereof can be used. The substrate, which is a flexible substrate, preferably has a lower coefficient of linear expansion because deformation due to the environment is suppressed. As the flexible substrate, for example, a material having a coefficient of linear expansion of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. . Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. In particular, aramid has a low coefficient of linear expansion, so it is suitable as a flexible substrate.

In the manufacturing example described in this embodiment, heat treatment is included in the process; therefore, a material with high heat resistance and a low coefficient of thermal expansion is preferably used for the substrate.

The conductor 131A (conductor 131B) functions as the wiring WWL illustrated in FIG. 1A, and the conductor 132A (conductor 132B) functions as the wiring RWL illustrated in FIG.

Examples of the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, A material containing one or more metal elements selected from magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Further, as the conductors, particularly the conductors 131A and 131B, the semiconductor 1 described later
51, the semiconductor 152, the semiconductor 153a, and the conductive material containing oxygen and a metal element contained in a metal oxide that can be applied to the semiconductor 153a and the semiconductor 153b. Alternatively, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen entering from a surrounding insulator or the like.

Further, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen for the conductors, particularly the conductors 132A and 132B. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or stacked layers may be used.

Alternatively, a plurality of conductors formed using any of the above materials may be stacked and used. For example, a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used. Alternatively, a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined. Alternatively, a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined. Further, when an insulator having an excess oxygen region is used as an insulator which is in contact with the periphery of the conductor, oxygen may diffuse in a region of the conductor which is in contact with the insulator. Thereby, it is possible to form a layered structure in which a material containing a metal element and a conductive material containing oxygen are combined. Also, similarly,
By applying an insulator having an excess nitrogen region as an insulator in contact with the periphery of the conductor, nitrogen may diffuse in a region of the conductor in contact with the insulator. Thereby, it is possible to form a laminated structure in which a material containing a metal element and a conductive material containing nitrogen are combined.

Note that the conductor 131A, the conductor 131B, the conductor 132A, and the conductor 132B may be made of the same material or may be made of different materials. That is, the conductor 131A, the conductor 131B, and the conductor 132A included in the semiconductor device of one embodiment of the present invention
, and the conductor 132B can be appropriately selected and used.

The insulators 101A to 101E are preferably made of water or a material with a reduced concentration of impurities such as hydrogen. For example, the amount of desorption of hydrogen from the insulators 101A to 101E can be determined by thermal desorption spectroscopy (TDS).
Electroscopy)), in the range of 50° C. to 500° C., the desorption amount in terms of hydrogen molecules is 2×10 ¹⁵ molecules/cm in terms of the area of any one of the insulators 101A to 101E. ² or less, preferably 1×10 ¹⁵ moles
It may be ules/cm ² or less, more preferably 5×10 ¹⁴ molecules/cm ² or less. Alternatively, the insulators 101A to 101E may be formed using an insulator from which oxygen is released by heating. Thereby, as described above, the conductor 131A, the conductor 1
31B, the conductor 132A, and the conductor 132B can have a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined.

The insulators 101A to 101E are, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Insulators including can be used in single layers or in stacks. Alternatively, for example, a material containing silicon oxide or silicon oxynitride can be used.

In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon oxynitride refers to a material whose composition contains more nitrogen than oxygen. indicates In this specification, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum oxynitride refers to a material whose composition contains more nitrogen than oxygen. indicates

In the next step, as shown in FIG. 6B, an opening 191 can be formed in the stacked body 100 shown in FIG. 6A by resist mask formation, etching treatment, and the like.

A resist mask can be formed using a lithography method, a printing method, an inkjet method, or the like as appropriate. Since a photomask is not used when the resist mask is formed by an inkjet method, the manufacturing cost can be reduced. In addition, the etching process may be dry etching, wet etching, or both.

Then, as shown in FIG. 7A, the conductors 132A and 132B on the side surfaces of the opening 191 are removed by etching treatment or the like, and recesses 192A (recesses 192B) are formed in the side surfaces. be. Here, as the conductor 132A (conductor 132B), a material (insulators 101A to 101E and conductor 131A (a material having a higher etching rate than the conductor 131B) is applied.

Further, the recess 192A (recess 192B) is formed by providing a sacrificial layer in a region where the opening 191 and the recess 192A (recess 192B) are formed in the manufacturing process of the semiconductor device shown in FIG. It may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in (B).
Also, when the opening 191 is formed without providing a sacrificial layer, the recess 192A (the recess 192A) is automatically formed.
2B) can also be formed.

In the next step, as shown in FIG. 7B, the insulator 102 is formed on the side surface of the opening 191 shown in FIG. 7A and the recesses described above.

As the insulator 102, an insulating material having a function of suppressing permeation of oxygen is preferably used. For example, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like is preferably used as the insulator 102 . By forming the insulator 102 in such a manner, it is possible to prevent the conductivity of the conductor 133 from decreasing due to oxygen entering through the insulator 102 and oxidation of the conductor 133, which will be described later. .

In the next step, as shown in FIG. 8A, a conductor 133 is formed on the side surface of the opening 191 shown in FIG. 7B and the formed concave portion. That is, the conductor 133 is formed on the surface where the insulator 102 is formed.

As the conductor 133, a material that can be used for the conductors 131A, 131B, 132A, and 132B described above can be used. Among these materials, it is particularly preferable to use a material with high conductivity for the conductor 133 .

In the next step, as shown in FIG. 8B, the conductor 1 included in the opening 191 is removed by forming a resist mask and etching so as to leave the conductor 133 only in the recess.
33 are removed. Thus, conductors 133a and 133b are formed. Note that at this time, the insulators 101A to 101E, the conductor 131A, and the conductor 131B
A portion of the insulator 102 may be removed as long as it is not exposed in the opening 191 .

Note that the description of FIG. 6B is referred to for the formation of the resist mask and the etching treatment.

Incidentally, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor CS illustrated in FIG. That is, the capacitive element CS is formed in the region 181A (region 181B) shown in FIG. 8B.

In the next step, as shown in FIG.
2. A semiconductor 151 is formed on the formation surfaces of the conductors 133a and 133b.

As the semiconductor 151, a material containing a metal oxide, which is described in Embodiment 3, is preferably used.

By the way, in the case where the semiconductor 151 contains a metal oxide, the insulator 102 in contact with the semiconductor 151 can be formed using an insulating material which has a function of suppressing permeation of impurities such as water or hydrogen as well as oxygen. preferable. By forming such an insulator 102, the insulator 1
Impurities such as water or hydrogen can be prevented from entering through the film 02 and reacting with oxygen contained in the semiconductor 151 to become water. When water is generated in the semiconductor 151, the semiconductor 151
Oxygen vacancies may form within When impurities such as hydrogen enter the oxygen vacancies, electrons serving as carriers may be generated. Therefore, when a region containing a large amount of hydrogen exists in the semiconductor 151, a transistor whose channel formation region includes the region is likely to have normally-on characteristics. In order to prevent this, it is desirable to use an insulating material that has a function of suppressing penetration of not only oxygen but also impurities such as water or hydrogen as the insulator 102 .

In the case where the semiconductor 151 contains a metal oxide, the semiconductor 151 may have different conductivity depending on the region where it is formed. In FIG. 9A, of the regions where the semiconductor 151 is formed, regions on the surface where the insulator 102 is formed are shown as regions 151a and 151b.
A region 151c is shown as a region on the surface where the conductor 133a (the conductor 133b) is formed. In particular, the region 151a is a region overlapping with the side surface of the conductor 131A (conductor 131B), and the region 151b is a region overlapping with the side surface of the insulator 101A (insulators 101B to 101E). Since the region 151c is in contact with the conductor 133a (the conductor 133b), impurities such as hydrogen or water contained in the conductor 133a might diffuse into the region 151c. As described above, when an impurity such as water or hydrogen is diffused into the semiconductor 151, electrons serving as carriers may be generated, so the resistance of the region 151c may be reduced. Therefore, the region 151c has higher conductivity than the regions 151a and 151b.

The region 151a is a region to be a channel formation region of a transistor. Therefore, when the transistor is on, the resistance of the region 151a is lowered, and the conductivity is higher than that of the region 151b.

In the next step, as shown in FIG. 9B, the semiconductor 15 positioned on the side of the opening 191 is removed.
An insulator 103 and a semiconductor 152 are formed in this order on the formation surface of 1 .

As the insulator 103, any material that can be used for the insulator 102 can be used. In particular, when the semiconductor 151 contains a metal oxide, the insulator 102 is preferably an insulating material that has a function of suppressing permeation of not only oxygen but also impurities such as water or hydrogen.

Incidentally, the transistor WTr illustrated in FIG. 1A is formed in the region 182A (region 182B) illustrated in FIG. 9B. Specifically, in the region 182A (region 182B), the region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, and the two regions 151b of the semiconductor 151 function as a source electrode and a drain electrode of the transistor WTr, respectively. , the conductor 132A functions as the gate electrode of the transistor WTr. In particular, when a material containing metal oxide is used as the semiconductor 151, the transistor WTr is an OS transistor.

As the semiconductor 152, the material containing the metal oxide described in Embodiment 3 can be used, similarly to the semiconductor 151. Also, as an alternative to the semiconductor 152, a semiconductor material such as silicon can be used.

In the next step, as shown in FIG. 10A, the insulator 104 is formed on the surface where the semiconductor 152 is formed, and the conductor 134 is formed so as to fill the remaining opening 191 .

As the insulator 104, a material that can be used for the insulators 102 and 103 can be used.

As the conductor 134, the above conductor 131A, conductor 131B, conductor 132A,
A material that can be applied to the conductor 132B, the conductor 133a, and the conductor 133b can be used.

Incidentally, the transistor RTr illustrated in FIG. 1A is formed in the region 183A (region 183B) illustrated in FIG. 10A. Specifically, region 183A (region 183B)
, the region 151c, the two regions 151b, and the conductor 133a (the conductor 133b) of the semiconductor 151 function as the gate electrode of the transistor RTr, the semiconductor 152 functions as the channel formation region of the transistor RTr, and the conductor 134 functions as the transistor. It functions as a back gate electrode of RTr. In particular, when a material containing metal oxide is used as the semiconductor 152, the transistor RTr constitutes an OS transistor.

By performing the steps from FIG. 6A to FIG. 10A, the semiconductor device illustrated in FIG. 1A can be manufactured.

One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. One embodiment of the present invention can have a structure in which the semiconductor device illustrated in FIG. 10A is changed as appropriate depending on circumstances or as needed.

For example, as described above, one embodiment of the present invention includes a transistor W as illustrated in FIG.
A semiconductor device in which the Tr and the transistor RTr are not provided with a back gate can also be used. In the case of manufacturing the semiconductor device illustrated in FIG. 1C, the step illustrated in FIG. 10B may be performed instead of the step illustrated in FIG. 10A in the manufacturing process of FIG. Figure 10 (B
) shows a step of forming an insulator 105 so as to fill the opening 191 instead of the conductor 134 in FIG. 10A. For the insulator 105, for example, a material that can be used as the insulator 104 can be used.

Further, for example, in one embodiment of the present invention, the structure of the gate electrode of the transistor WTr may be changed from the structure illustrated in FIG. 10A in order to improve switching characteristics of the transistor WTr. 11A, 11B, 12A, and 12B show an example of a method for manufacturing the semiconductor device. 11A shows a step of removing the conductor 131A (conductor 131B) on the side surface of the opening 191 in FIG. 6B to form a recess 193A (recess 193B). Here, as the conductor 131A (conductor 131B),
A material (a material having a higher etching rate than the conductor 132A (conductor 132B) and the insulators 101A to 101E) from which the conductor 131A (conductor 131B) is selectively removed in the stacked body 100 is used. shall be applied.

Further, the concave portion 193A (the concave portion 193B) is formed by providing a sacrificial layer in a region where the opening portion 191 and the concave portion 193A (the concave portion 193B) are formed in the manufacturing process of the semiconductor device shown in FIG. It may be formed together with the opening 191 in the manufacturing process of the semiconductor device shown in 6B. Also, when the opening 191 is formed without providing a sacrificial layer, the recess 193A (recess 1
93B) can be formed.

In the next step, as shown in FIG. 11(B), the side surface of the opening 191 shown in FIG. 11(A),
And the semiconductor 153 is deposited on the concave portion 193A (the concave portion 193B).

As the semiconductor 153, the material containing the metal oxide described in Embodiment 3 is used.

In the next step, as shown in FIG. 12A, the semiconductor 153 included in the opening 191 is removed by forming a resist mask and etching so that the semiconductor 153 remains only in the recess 193A (recess 193B). be. Simultaneously with or after this treatment, an etching treatment is performed to remove the conductor 132A (conductor 132B) to form a recess 192A (recess 192B).

Next, similarly to the step of FIG. 8B, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). Semiconductor 153 (semiconductor 153b)
as the semiconductor 153a (semiconductor 153b
) is in contact with the insulator 102, impurities such as hydrogen and water contained in the insulator 102 are diffused into the semiconductor 153a (semiconductor 153b). In addition, when the semiconductor 153a (semiconductor 153b) is in contact with the conductor 133a (conductor 133b), the conductor 133a (conductor 133b)
Impurities such as hydrogen and water contained in the silicon diffuse into the semiconductor 153a (semiconductor 153b). That is, the semiconductor 153a (semiconductor 153b) has a role of collecting impurities such as hydrogen and water. As a result, the resistance of the semiconductor 153a (semiconductor 153b) is reduced, and the transistor WT
It can function as a gate electrode for r. After that, the semiconductor device shown in FIG. 12B can be formed by performing the same steps as in FIGS. 9A to 10A.

Further, for example, in one embodiment of the present invention, the first terminal of the transistor WTr illustrated in FIG.
Alternatively, the structure of the gate electrode of the transistor RTr may be changed from that shown in FIG. 10A in order to reduce the electrical resistance between the second terminal and the gate of the transistor RTr. 13A and 13B show an example of a method for manufacturing the semiconductor device. Figure 1
In 3A, not only the conductor 132A (conductor 132B) on the side surface of the opening 191 in FIG. (Recess 194A, recess 194C) is shown. Here, as the conductor 132A (conductor 132B) and the insulators 101A to 101E, the conductor 132A (conductor 132B) and the insulators 101A to 101E in the stack 100 are selectively removed. (a material with a higher etching rate than the conductor 131A (conductor 131B)) is applied.

Further, the recess 194B (recess 194A, recess 194C) is formed by a sacrificial layer in a region where the opening 191 and recess 194B (recess 194A, recess 194C) are formed in the manufacturing process of the semiconductor device shown in FIG. is provided, and in the manufacturing process of the semiconductor device shown in FIG.
91 may be formed together. Further, when the opening 191 is formed without providing a sacrificial layer, the recess 194B (recess 194A, recess 194C) may be automatically formed in some cases.

In addition, in FIG. 13A, in the recess 194B (recess 194A, recess 194C), the conductor 132A (the conductor 132B) is higher than the insulator 101B and the insulator 101C (the insulator 101A, the insulator 101D, and the insulator 101E). ) is removed to a greater extent, but the conductor 13
Insulator 101B and insulator 101C (insulator 101A, insulator 101D and insulator 101E) may be removed more than 2A (conductor 132B). Also, the insulator 101B
, insulator 101C (insulator 101A, insulator 101D, insulator 101E), and conductor 13
2A (conductor 132B) may be formed to have the same depth.

FIG. 13B shows a configuration example of a semiconductor device through the process of FIG. 13A. After the step of FIG. 13A, the conductor 133 is formed so as to fill the recess 194B (the recess 194A and the recess 194C) to form the gate electrode of the transistor RTr. Figure 1
3A illustrates a conductor 133a, a conductor 133b, and a conductor 133c that function as gate electrodes of the transistor RTr. After that, the semiconductor device shown in FIG. 13B can be formed by performing the same steps from FIGS. 9A to 10A. This semiconductor device has a semiconductor 151 and a conductor 13 more than the semiconductor device shown in FIG.
The contact area with 3a (conductor 133b) is increased. When a material containing a metal oxide is used for the semiconductor 151, the semiconductor device shown in FIG.
1 does not exist, electrical resistance between the first terminal or the second terminal of the transistor WTr and the gate of the transistor RTr can be reduced.

<<Production method example 2>>
Here, as a semiconductor device of this embodiment, an example of a structure different from that of Manufacturing Method Example 1 is described with reference to FIGS.

Similar to FIGS. 6 to 10, FIGS. 14A to 16B are cross-sectional views for explaining an example of manufacturing the semiconductor device illustrated in FIG. Fig. 3 shows a cross-sectional view; 6 to 1 in cross-sectional views of FIGS.
0, some elements are omitted for clarity of illustration.

For the first steps, the description of FIGS. 6A to 7B described in Manufacturing Method Example 1 is taken into consideration.

The process shown in FIG. 14A is a continuation of the process shown in FIG. 7B. Figure 14
In (A), a semiconductor 151 is formed on the side surface of the opening 191 shown in FIG. 7B and on the formed concave portion. That is, the semiconductor 151 is formed on the surface where the insulator 102 is formed.

As the semiconductor 151, the semiconductor described in Embodiment 3 is preferably used.

In the next step, as shown in FIG. 14(B), the side surface of the opening 191 shown in FIG. 14(A),
And the conductor 133 is deposited in the formed concave portion.

For the conductor 133, the description of the conductor 133 in Manufacturing Method Example 1 is referred to.

In the next step, as shown in FIG. 15A, the conductor 133 included in the opening 191 is removed by forming a resist mask and etching so that the conductor 133 remains only in the recess. Thus, conductors 133a and 133b are formed. Note that at this time, part of the semiconductor 151 may be removed as long as the insulator 102 is not exposed in the opening 191 .

Note that the description of FIG. 6B is referred to for the formation of the resist mask and the etching treatment.

Incidentally, the conductor 133a (conductor 133b) functions as the other electrode of the capacitor CS illustrated in FIG. That is, the capacitive element CS is formed in the region 181A (region 181B) shown in FIG. 15A.

For the semiconductor 151, the description of the semiconductor 151 in Manufacturing Method Example 1 is referred to. Further, when the semiconductor 151 contains a metal oxide, the semiconductor 151 can be divided into regions 151a, 151b, and 151c. Region 151a, Region 151b, Region 1
For 51c, the regions 151a, 151b, and 151c described in Manufacturing Method Example 1
Consider the description of.

In the next step, as shown in FIG. 15B, the conductor 1 positioned on the side surface of the opening 191
The insulator 103 is formed over the formation surface of the conductor 33 a , the conductor 133 b , and the semiconductor 151 , and then the semiconductor 152 is formed over the formation surface of the insulator 103 .

For the insulator 103, the description of the insulator 103 in Manufacturing Method Example 1 is referred to.

For the semiconductor 152, the description of the semiconductor 152 described in Manufacturing Method Example 1 is referred to.

Incidentally, the transistor WTr illustrated in FIG. 1A is formed in the region 182A (region 182B) illustrated in FIG. 15B. Specifically, region 182A (region 182B)
, a region 151a of the semiconductor 151 functions as a channel formation region of the transistor WTr, two regions 151b of the semiconductor 151 function as a source electrode and a drain electrode of the transistor WTr, and a conductor 132A functions as a gate electrode of the transistor WTr. Function. In particular, when a material containing metal oxide is used as the semiconductor 151, the transistor WTr is an OS transistor.

In the next step, as shown in FIG. 16A, the insulator 104 is formed on the surface where the semiconductor 152 is formed, and the conductor 134 is formed so as to fill the remaining opening 191 .

For the insulator 104, the description of the insulator 104 in Manufacturing Method Example 1 is referred to.

For the conductor 134, the description of the conductor 134 in Manufacturing Method Example 1 is referred to.

Incidentally, the transistor RTr illustrated in FIG. 1A is formed in the region 183A (region 183B) illustrated in FIG. 16A. Specifically, region 183A (region 183B)
, the region 151c, the two regions 151b, and the conductor 133a (the conductor 133b) of the semiconductor 151 function as the gate electrode of the transistor RTr, the semiconductor 152 functions as the channel formation region of the transistor RTr, and the conductor 134 functions as the transistor. It functions as a back gate electrode of RTr. In particular, when a material containing metal oxide is used as the semiconductor 152, the transistor RTr constitutes an OS transistor.

By performing the steps of FIGS. 6A to 7B and FIGS. 14A to 16A, the semiconductor device illustrated in FIG. 1A can be manufactured.

One embodiment of the present invention is not limited to the structural example of the semiconductor device illustrated in FIG. One embodiment of the present invention can have a structure in which the semiconductor device illustrated in FIG. 16A is changed as appropriate depending on circumstances or as needed.

For example, as described above, one embodiment of the present invention includes a transistor W as illustrated in FIG.
A semiconductor device in which the Tr and the transistor RTr are not provided with a back gate can also be used. In the case of manufacturing the semiconductor device shown in FIG. 1C, the process shown in FIG. 16B may be performed instead of the process shown in FIG. 16A in the process of manufacturing FIG. FIG. 16(B)
Then, instead of the conductor 134 in FIG. 16A, a step of forming an insulator 105 so as to fill the opening 191 is shown. For the insulator 105, for example, a material that can be used as the insulator 104 can be used.

Further, for example, in one embodiment of the present invention, the structure of the gate electrode of the transistor WTr may be changed from the structure illustrated in FIG. 16A in order to improve switching characteristics of the transistor WTr. FIG. 17 shows a configuration example of the semiconductor device. When fabricating the semiconductor device shown in FIG.
A semiconductor 153a (semiconductor 153b) is formed to fill 3A (recess 193B). Next, the insulator 102 is formed on the side surface of the opening 191 so as to cover the semiconductor 153a (semiconductor 153b). After that, the semiconductor device shown in FIG. 17 can be formed by performing steps similar to those of FIGS. 14A to 16A. 11A, 11B, 12A, and 12B described in the manufacturing method example 1.
The description of B) is taken into consideration.

Further, for example, in one embodiment of the present invention, the first terminal of the transistor WTr illustrated in FIG.
Alternatively, the structure of the gate electrode of the transistor RTr may be changed from that shown in FIG. 16A in order to reduce the electrical resistance between the second terminal and the gate of the transistor RTr. FIG. 18 shows a configuration example of the semiconductor device. In the case of manufacturing the semiconductor device illustrated in FIG. 18, the structural example illustrated in FIG. After that,
14A to 16A, the semiconductor device shown in FIG. 18 can be formed. Note that the description of FIG. 13B described in Manufacturing Method Example 1 will be referred to for the effect of the structure shown in FIG.

By manufacturing method example 1 or manufacturing method example 2 described above, a semiconductor device capable of holding a large amount of data can be manufactured.

Here, FIG. 19 shows a structure in which the cross-sectional view of the semiconductor device shown in FIG. 10A (the circuit configuration of FIG. 1A) is applied to the region SD2 of the semiconductor device shown in FIG. 5B. Note that the region SD1 corresponds to the memory cell MC. As shown in FIG. 19, openings are collectively provided in the stacked structure of the conductors and insulators, which are the wiring RWL and the wiring WWL, and the manufacturing method example 1 described above is performed.
Alternatively, by manufacturing as described in Manufacturing Method Example 2, the circuit structure in FIG. 1A can be realized.

<Connection example with peripheral circuit>
In the semiconductor device shown in Manufacturing Method Example 1 or Manufacturing Method Example 2, a peripheral circuit of a memory cell array such as a reading circuit and a precharge circuit may be formed in a lower layer. In this case, the peripheral circuit is formed by forming a Si transistor over a silicon substrate or the like, and then the semiconductor device of one embodiment of the present invention is formed over the peripheral circuit by Manufacturing Method Example 1 or Manufacturing Method Example 2. should be formed. FIG. 20A is a cross-sectional view in which a peripheral circuit is formed using a planar Si transistor and a semiconductor device of one embodiment of the present invention is formed thereover. FIG. 21A is a cross-sectional view in which a peripheral circuit is formed using a FIN Si transistor and a semiconductor device of one embodiment of the present invention is formed thereover. Note that the structure of FIG. 10A is applied to the semiconductor devices illustrated in FIGS. 20A and 20B as an example.

In FIGS. 20A and 21A, Si transistors forming a peripheral circuit are formed on a substrate 1700. In FIG. A device isolation layer 1701 is formed between a plurality of Si transistors. A conductor 1712 is formed as the source and drain of the Si transistor.
The conductor 1730 extends in the channel width direction and is connected to another Si transistor or the conductor 1712 (not shown).

As the substrate 1700, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, an SOI substrate, or the like can be used.

Alternatively, as the substrate 1700, for example, a glass substrate, a quartz substrate, a plastic substrate, a metal substrate, a flexible substrate, an adhesive film, paper containing a fibrous material, a base film, or the like may be used. Alternatively, a semiconductor element may be formed using a substrate and then transferred to another substrate. In FIGS. 20A and 21A, as an example, the substrate 170
0 shows an example using a single crystal silicon wafer.

Details of the Si transistor will now be described. The planar Si transistor shown in FIG. 20A shows a cross-sectional view in the channel length direction, and the planar Si transistor shown in FIG. 20B shows a cross-sectional view in the channel width direction. The Si transistor includes a channel forming region 1793 provided in a well 1792, a low-concentration impurity region 1794 and a high-concentration impurity region 1795 (collectively referred to as impurity regions), and a conductive region provided in contact with the impurity regions. a gate insulating film 1797 provided over a channel forming region 1793; a gate electrode 1790 provided over the gate insulating film 1797;
Sidewall insulating layers 1798 and 1799 are provided on the side surfaces of the gate electrode 1790 . Note that metal silicide or the like may be used for the conductive region 1796 .

The FIN Si transistor shown in FIG. 21A is a cross-sectional view in the channel length direction, and the FIN Si transistor shown in FIG. 21B is a cross-sectional view in the channel width direction. The Si transistor shown in FIGS. 21A and 21B has a channel formation region 1793
has a convex shape, and a gate insulating film 1797 and a gate electrode 179 are formed along its side and top surfaces.
0 is provided. In this embodiment mode, the case where a part of a semiconductor substrate is processed to form a convex portion is described; however, a semiconductor layer having a convex shape may be formed by processing an SOI substrate. note that,
The symbols shown in FIGS. 21A and 21B are the same as the symbols shown in FIGS. 20A and 20B.

Insulators, conductors, semiconductors, etc. disclosed in this specification etc. are PVD (Phis
Cal Vapor Deposition) method, CVD (Chemical Vapor Deposition) method
r Deposition) method. PVD methods include, for example, a sputtering method, a resistance heating vapor deposition method, an electron beam vapor deposition method, and a PLD (Pulsed La
(ser Deposition) method and the like. As the CVD method, a plasma CVD method, a thermal CVD method, and the like are used. In particular, as a thermal CVD method, for example, MOCVD (Metal Organic Chemical Vapor Depth
position) method and ALD (Atomic Layer Deposition) method.

The thermal CVD method is a film forming method that does not use plasma, so it has the advantage of not generating defects due to plasma damage.

In the thermal CVD method, a source gas and an oxidizing agent are sent into a chamber at the same time, the inside of the chamber is made to be under atmospheric pressure or reduced pressure, and a film is formed by reacting near or on the substrate and depositing it on the substrate. .

Further, in the ALD method, the inside of the chamber is set to atmospheric pressure or reduced pressure, raw material gases for reaction are sequentially introduced into the chamber, and film formation may be performed by repeating the order of gas introduction. For example, by switching the switching valves (also called high-speed valves), two or more source gases are sequentially supplied to the chamber, and the first source gas is supplied simultaneously with or after the first source gas so as not to mix the two or more source gases. Introduce an active gas (argon, nitrogen, etc.),
A second source gas is introduced. When the inert gas is introduced at the same time, the inert gas serves as a carrier gas, and the inert gas may be introduced at the same time as the introduction of the second raw material gas. Alternatively, instead of introducing the inert gas, the second source gas may be introduced after the first source gas is exhausted by evacuation. The first source gas adsorbs on the surface of the substrate to form a first thin layer, which reacts with the second source gas introduced later to form a second thin layer on the first thin layer. is laminated to form a thin film. A thin film with excellent step coverage can be formed by repeating this gas introduction sequence several times until a desired thickness is obtained. Since the thickness of the thin film can be adjusted by the number of times the gas introduction order is repeated, precise film thickness adjustment is possible, and this method is suitable for fabricating fine FETs.

Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above.
Trimethylindium (In(CH ₃ ) ₃ ), trimethylgallium (Ga(CH ₃ ) ₃ ), and dimethylzinc (Zn(CH ₃ ) ₂ ) are used for forming an a-Zn-O film. Moreover, it is not limited to these combinations, triethylgallium (Ga(C ₂ H ₅ ) ₃ ) can be used instead of trimethylgallium, and diethylzinc (
Zn( _{C2H5 )2 )} can also be used.

For example, when a hafnium oxide film is formed by a film forming apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, tetrakisdimethylamide hafnium (TDMAH, Hf[N(CH ₃ ) ₂ ] ₄ ) Hafnium amides such as
and ozone (O ₃ ) as an oxidizing agent. again,
Other materials include tetrakis(ethylmethylamido)hafnium.

For example, when forming an aluminum oxide film with a film forming apparatus using ALD, a liquid containing a solvent and an aluminum precursor compound (trimethylaluminum (TMA, Al(C
Two types of gases are used: a source gas obtained by vaporizing H ₃ ) ₃ ), etc.) and H ₂ O as an oxidizing agent. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, when a silicon oxide film is formed by a film forming apparatus using ALD, hexachlorodisilane is adsorbed on the film formation surface, and radicals of oxidizing gas (O ₂ , dinitrogen monoxide) are supplied and adsorbed. react with things.

For example, when forming a tungsten film with a film forming apparatus using ALD, WF ₆
gas and B ₂ H ₆ gas are sequentially and repeatedly introduced to form an initial tungsten film, and then WF
₆ gas and _H2 gas are successively and repeatedly introduced to form a tungsten film. _SiH4 gas may be used instead of _B2H6 gas _.

For example, an oxide semiconductor film such as In—Ga—Zn—
When forming an O film, In(CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an In film.
—O layer is formed, and then Ga(CH ₃ ) ₃ gas and O ₃ gas are successively and repeatedly introduced to form Ga
An O layer is formed, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are sequentially and repeatedly introduced to form a Zn layer.
Form an O layer. Note that the order of these layers is not limited to this example. In addition, a mixed oxide layer such as an In--Ga--O layer, an In--Zn--O layer, or a Ga--Zn--O layer may be formed using these gases. Although H ₂ O gas obtained by bubbling water with an inert gas such as Ar may be used instead of O ₃ gas, it is preferable to use O ₃ gas that does not contain H. Also, In
In(C ₂ H ₅ ) ₃ gas may be used instead of (CH ₃ ) ₃ gas. Also, Ga(CH
₃ ) Ga(C ₂ H ₅ ) ₃ gas may be used instead of ₃ gas. Also, Zn( _CH3 ) ₂
Gas may be used.

Note that the structural examples of the semiconductor devices described in this embodiment can be combined as appropriate.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 2)
In this embodiment, a memory device including the semiconductor device described in the above embodiment will be described.

FIG. 22 shows an example of the configuration of a storage device. A memory device 2600 has a peripheral circuit 2601 and a memory cell array 2610 . The peripheral circuit 2601 has a row decoder 2621 , a word line driver circuit 2622 , a bit line driver circuit 2630 , an output circuit 2640 and a control logic circuit 2660 .

The semiconductor device illustrated in FIGS. 1A, 1B, or 1C described in Embodiment 1 can be applied to the memory cell array 2610. FIG.

The bit line driver circuit 2630 includes a column decoder 2631 and a precharge circuit 263.
2, a sense amplifier 2633 and a write circuit 2634 . precharge circuit 26
32 has a function of precharging the node N1 (not shown in FIG. 22) of the wiring RBL described in the first embodiment to a predetermined potential. The sense amplifier 2633 has a function of acquiring the read potential of the node N2 as a data signal and amplifying the data signal.
The amplified data signal is output via output circuit 2640 to digital data signal RDATA.
, and is output to the outside of the storage device 2600 .

In addition, the storage device 2600 is supplied with a low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 2601, and a high power supply voltage (VI) for the memory cell array 2610.
L) is supplied.

In addition, the storage device 2600 stores control signals (CE, WE, RE), an address signal ADDR
, the data signal WDATA is input from the outside. The address signal ADDR is input to the row decoder 2621 and the column decoder 2631, and the data signal WDATA is input to the write circuit 2634.

The control logic circuit 2660 processes external input signals (CE, WE, RE) to generate control signals for the row decoder 2621 and column decoder 2631 . CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 2660 is not limited to this, and other control signals may be input as necessary.

It should be noted that each circuit or each signal described above can be appropriately discarded as needed.

In addition, a p-channel Si transistor and a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in an embodiment described below in a channel formation region are used and applied to the memory device 2600. , a compact storage device 2600 can be provided. Further, the memory device 2600 capable of reducing power consumption can be provided. In addition, the storage device 2600 whose operation speed can be improved can be provided. In particular, manufacturing costs can be kept low by using only p-channel Si transistors.

Note that the configuration example of this embodiment is not limited to the configuration in FIG. 22 . For example, peripheral circuit 26
01, for example, the precharge circuit 2632 and/or the sense amplifier 2633 may be provided in the lower layer of the memory cell array 2610 .

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 3)
In this embodiment, the metal oxide contained in the channel formation region of the OS transistor used in the above embodiment will be described.

The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. Also, in addition to them, aluminum, gallium,
It preferably contains yttrium, tin, or the like. In addition, boron, silicon,
One or more selected from titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Consider here the case where the metal oxide is an In--M--Zn oxide with indium, the element M and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above elements may be combined.

Next, with reference to FIGS. 23(A), 23(B), and 23(C), a preferred range of atomic number ratios of indium, element M, and zinc in the metal oxide according to the present invention will be described. . Note that the atomic number ratio of oxygen is not shown in FIGS. 23A, 23B, and 23C. Further, the terms of the atomic ratios of indium, the element M, and zinc contained in the metal oxide are represented by [In], [M], and [Zn], respectively.

In FIGS. 23(A), 23(B), and 23(C), dashed lines indicate [In]:[M
]: [Zn] = (1 + α): (1-α): A line with an atomic ratio of 1 (-1 ≤ α ≤ 1),
[In]: [M]: [Zn] = (1 + α): (1-α): a line with an atomic ratio of 2, [
In]:[M]:[Zn]=(1+α):(1−α): lines with an atomic number ratio of 3, [I
n]:[M]:[Zn]=(1+α):(1−α):4 lines and [In]:[M]:[Zn]=(1+α):(1− α): Represents a line with an atomic number ratio of 5.

In addition, the dashed-dotted line is a line with an atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0), [In]:[M]:[Zn]=2: A line with an atomic ratio of 1:β, [In
]: [M]: [Zn] = 1: 1: line with an atomic ratio of β, [In]: [M]: [Zn
]=1:2:β atomic ratio, [In]:[M]:[Zn]=1:3:β atomic ratio, and [In]:[M]:[ Zn]=1:4:β line.

23(A), 23(B), and 23(C), [In]:[M]:
A metal oxide having an atomic ratio of [Zn]=0:2:1 or a value close thereto tends to have a spinel crystal structure.

In addition, multiple phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is close to [In]:[M]:[Zn]=0:2:1, two phases, a spinel crystal structure and a layered crystal structure, tend to coexist. Also, the atomic ratio is [In]:
When [M]:[Zn] is close to 1:0:0, two phases of a bixbite crystal structure and a layered crystal structure tend to coexist. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

A region A shown in FIG. 23A shows an example of a preferable range of the atomic ratio of indium, element M, and zinc in the metal oxide.

By increasing the indium content of the metal oxide, the carrier mobility of the metal oxide (
electron mobility) can be increased. Therefore, a metal oxide with a high indium content has higher carrier mobility than a metal oxide with a low indium content.

On the other hand, lower contents of indium and zinc in the metal oxide result in lower carrier mobility. Therefore, when the atomic number ratio is [In]:[M]:[Zn]=0:1:0 and its neighboring values (for example, region C shown in FIG. 23C), the insulating property is high. .

Therefore, the metal oxide of one embodiment of the present invention preferably has an atomic ratio shown in region A in FIG. 23A, which tends to have a layered structure with high carrier mobility and few crystal grain boundaries. .

In particular, in region B shown in FIG. 23B, even in region A, CAAC (c-axis a
ligned crystalline)-OS, and an excellent metal oxide having high carrier mobility can be obtained.

CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. Also, the distortion may have a lattice arrangement of pentagons, heptagons, and the like. In CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It is considered to be for

CAAC-OS is a highly crystalline metal oxide. On the other hand, since a clear grain boundary cannot be confirmed in CAAC-OS, it can be said that the decrease in electron mobility caused by the grain boundary is unlikely to occur. In addition, since the crystallinity of a metal oxide may be deteriorated due to contamination with impurities, generation of defects, or the like, CAAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, metal oxides with CAAC-OS have stable physical properties.
Therefore, a metal oxide containing CAAC-OS is heat resistant and highly reliable.

Note that region B includes [In]:[M]:[Zn]=4:2:3 to 4.1 and their neighboring values. Neighborhood values include, for example, [In]:[M]:[Zn]=5:3:4. Also, region B has [In]:[M]:[Zn]=5:1:6 and its neighboring values, and [In]:[M]:[Zn]=5:1:7 and its Contains neighborhood values.

The properties of metal oxides are not uniquely determined by the atomic number ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide is deposited using a sputtering apparatus, a film having an atomic ratio deviating from the atomic ratio of the target is formed. Also, depending on the substrate temperature during film formation, more than [Zn] of the target,
[Zn] of the film may become small. Thus, the illustrated regions are regions exhibiting atomic ratios where metal oxides tend to have particular properties, and the boundaries of regions A through C are not strict.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 4)
In this embodiment, a CPU which can include the semiconductor device of any of the above embodiments will be described.

FIG. 24 is a block diagram showing a configuration of an example of a CPU partially using the semiconductor device described in Embodiment 1. FIG.

The CPU shown in FIG. 24 has an ALU 1191 (ALU: Arithme
ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I/F), rewritable ROM 1199, and ROM interface 1189 (ROM I/F). A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190 . ROM 1199 and ROM interface 1189 are
It may be provided in another chip. Of course, the CPU shown in FIG. 24 is merely an example of a simplified configuration, and actual CPUs have a wide variety of configurations depending on their uses. For example, a configuration including a CPU or an arithmetic circuit shown in FIG. 24 may be used as one core, a plurality of such cores may be included, and the cores may operate in parallel, that is, a configuration like a GPU. The number of bits that the CPU can handle in the internal arithmetic circuit and data bus is, for example, 8 bits, 16 bits, and 16 bits.
bits, 32 bits, 64 bits, and so on.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193 , decoded, and input to the ALU controller 1192 , interrupt controller 1194 , register controller 1197 and timing controller 1195 .

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on decoded instructions. Specifically, ALU controller 1192 generates signals for controlling the operation of ALU 1191 . Further, the interrupt controller 1194 judges and processes interrupt requests from external input/output devices and peripheral circuits based on their priority and mask status during program execution by the CPU. A register controller 1197 generates an address for the register 1196 and reads or writes the register 1196 according to the state of the CPU.

Also, the timing controller 1195 includes the ALU 1191 and the ALU controller 11
92, generates signals that control the timing of the operation of instruction decoder 1193, interrupt controller 1194, and register controller 1197; For example, the timing controller 1195 has an internal clock generator that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits described above.

In the CPU shown in FIG. 24, the register 1196 is provided with memory cells. As the memory cell of the register 1196, the transistor described in any of the above embodiments can be used.

In the CPU shown in FIG. 24, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191 . That is, register 1
196, whether to hold data by a flip-flop or by a capacitor is selected. When data holding by the flip-flop is selected, power supply voltage is supplied to the memory cells in the register 1196 . When data retention in the capacitor is selected, data is rewritten in the capacitor, and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 5)
A memory card (for example, an SD card) that can include the storage device of the above embodiment
, USB (Universal Serial Bus) memory, SSD (Solid
It can be applied to various removable storage devices such as State Drive. In this embodiment, several configuration examples of the removable storage device will be described with reference to FIG.

FIG. 25A is a schematic diagram of a USB memory. The USB memory 5100 has a housing 5101
, a cap 5102 , a USB connector 5103 and a substrate 5104 . substrate 5104
are accommodated in the housing 5101 . A substrate 5104 is provided with a memory device and a circuit for driving the memory device. For example, a memory chip 5105 and a controller chip 5106 are attached to the substrate 5104 . The memory chip 5105 includes the memory cell array 2610, word line driver circuit 2622, and row decoder 26 described in the third embodiment.
21, a sense amplifier 2633, a precharge circuit 2632, a column decoder 2631 and the like are incorporated. The controller chip 5106 specifically incorporates a processor, work memory, ECC circuit, and the like. Note that the circuit configurations of the memory chip 5105 and the controller chip 5106 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation or circumstances. For example, word line driver circuit 2622,
The row decoder 2621, the sense amplifier 2633, the precharge circuit 2632, and the column decoder 2631 may be incorporated in the controller chip 5106 instead of the memory chip 5105. FIG. A USB connector 5103 functions as an interface for connecting with an external device.

FIG. 25B is a schematic diagram of the appearance of the SD card, and FIG. 25C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111 , a connector 5112 and a substrate 5113 . A connector 5112 functions as an interface for connecting with an external device. A substrate 5113 is housed in a housing 5111 . A substrate 5113 is provided with a memory device and a circuit for driving the memory device. For example, a memory chip 5114 and a controller chip 5115 are attached to the substrate 5113 . memory chip 511
4 includes the memory cell array 2610 and the word line driver circuit 26 described in the third embodiment.
22, a row decoder 2621, a sense amplifier 2633, a precharge circuit 2632, a column decoder 2631 and the like are incorporated. The controller chip 5115 incorporates a processor, work memory, ECC circuit, and the like. Note that the circuit configurations of the memory chip 5114 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation or circumstances. For example, word line driver circuit 2622, row decoder 2621, sense amplifier 2633, precharge circuit 263
2. The column decoder 2631 is installed in the controller chip 511 instead of the memory chip 5114.
5 may be incorporated.

By providing a memory chip 5114 also on the back side of the substrate 5113, the SD card 5110
capacity can be increased. Alternatively, a wireless chip having a wireless communication function may be provided over the substrate 5113 . As a result, wireless communication can be performed between the external device and the SD card 5110, and data can be read from and written to the memory chip 5114. FIG.

FIG. 25D is a schematic diagram of the appearance of the SSD, and FIG. 25E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151 , a connector 5152 and a substrate 5153 . A connector 5152 functions as an interface for connecting with an external device.
A substrate 5153 is housed in a housing 5151 . A substrate 5153 is provided with a memory device and a circuit for driving the memory device. For example, the substrate 5153 has a memory chip 5154
, a memory chip 5155 and a controller chip 5156 are attached. The memory chip 5154 includes the memory cell array 2610, the word line driver circuit 2622, the row decoder 2621, the sense amplifier 2633, the precharge circuit 26 described in the third embodiment.
32, a column decoder 2631 and the like are incorporated. By providing a memory chip 5154 also on the back side of the substrate 5153, the capacity of the SSD 5150 can be increased. The memory chip 5155 incorporates a work memory. For example, the memory chip 5155 may be a DRAM chip. The controller chip 5156 includes a processor, E
CC circuit etc. are incorporated. Note that the memory chip 5154 and the memory chip 515
5 and the controller chip 5115 are not limited to the above description, and the circuit configurations may be changed as appropriate depending on the situation or circumstances. For example, the controller chip 5156 may also be provided with a memory functioning as a work memory.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Embodiment 6)
In this embodiment, examples of electronic devices to which the memory device of the above embodiment can be applied will be described.

<Laptop Personal Computer>
FIG. 26A shows a notebook personal computer including a housing 5401 and a display portion 540.
2. It has a keyboard 5403, a pointing device 5404, and the like. A storage device of one embodiment of the present invention can be provided in a notebook personal computer.

<smart watch>
FIG. 26B shows a smart watch, which is a type of wearable terminal, and has a housing 5901.
, a display portion 5902, an operation button 5903, an operator 5904, a band 5905, and the like. A storage device of one embodiment of the present invention can be provided in a smartwatch. Further, a display device having a function as a position input device may be used as the display portion 5902 . A function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, also called a photosensor, in a pixel portion of the display device. In addition, the operation button 5903 can include any one of a power switch for starting the smart watch, a button for operating an application of the smart watch, a volume adjustment button, a switch for turning on/off the display portion 5902, and the like. In addition, although the smart watch shown in FIG. 26B has two operation buttons 5903, the number of operation buttons included in the smart watch is not limited to this. Also, the operator 5904 functions as a crown for setting the time of the smartwatch. In addition to adjusting the time, the operator 5904 may be used as an input interface for operating smartwatch applications. In the smart watch shown in FIG. 26(B), the operator 590
4, the configuration is not limited to this, and a configuration without the operator 5904 may be employed.

<Video camera>
FIG. 26C shows a video camera including a first housing 5801, a second housing 5802, and a display portion 5.
803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. A storage device of one embodiment of the present invention can be provided in a video camera. Operation key 5804 and lens 58
05 is provided in the first housing 5801 and the display portion 5803 is provided in the second housing 5802 . The first housing 5801 and the second housing 5802 are connected by a connecting portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connecting portion 5806. be. The image on the display unit 5803 may be switched according to the angle between the first housing 5801 and the second housing 5802 on the connection unit 5806 .

<mobile phone>
FIG. 26D shows a mobile phone having an information terminal function, which includes a housing 5501 and a display portion 55.
02, a microphone 5503, a speaker 5504, and operation buttons 5505. A storage device of one embodiment of the present invention can be provided in a mobile phone. Further, a display device having a function as a position input device may be used as the display unit 5502 . A function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, also called a photosensor, in a pixel portion of the display device. In addition, the operation button 5505 can include any of a power switch for activating the mobile phone, a button for operating an application of the mobile phone, a volume adjustment button, a switch for turning on/off the display portion 5502, and the like.

Although the mobile phone shown in FIG. 26D has two operation buttons 5505, the number of operation buttons of the mobile phone is not limited to this. In addition, although not shown, the mobile phone shown in FIG. 26D may have a structure including a flashlight or a light-emitting device for illumination.

<Television equipment>
FIG. 26E is a perspective view showing a television device. The television set includes a housing 9
000, display unit 9001, speaker 9003, operation key 9005 (including power switch or operation switch), connection terminal 9006, sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, number of revolutions, distance, light, liquid , magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared). A storage device of one embodiment of the present invention can be provided in a television device. Television equipment has a large screen, eg, 50 inches or more, or 100
It is possible to incorporate a display 9001 of an inch or more.

<Moving body>
The display device described above can also be applied around the driver's seat of an automobile, which is a mobile object.

For example, FIG. 26F is a diagram showing the vicinity of the windshield in the interior of an automobile.
In FIG. 26F, the display panel 5701 attached to the dashboard and the display panel 5
702, a display panel 5703 as well as a display panel 5704 attached to a pillar are shown.

Display panels 5701 through 5703 can provide navigation information, speedometer and tachometer, mileage, fuel level, gear status, air conditioning settings, and a variety of other information. In addition, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

The display panel 5704 can complement the field of view (blind spot) blocked by the pillars by displaying an image from an imaging means provided on the vehicle body. That is, by displaying an image from an imaging means provided outside the automobile, blind spots can be compensated for and safety can be enhanced. In addition, by projecting an image that supplements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

A storage device of one embodiment of the present invention can be provided in a mobile object. A storage device of one embodiment of the present invention is, for example, a frame memory that temporarily stores image data, which is used when images are displayed on the display panels 5701 to 5704, and a program that drives a system of a mobile object. can be used as a storage device for storing

Further, although not shown, the electronic devices shown in FIGS. With this configuration, for example, the electronic device described above can be provided with a voice input function.

Although not shown, the electronic devices shown in FIGS. 26A, 26B, and 26D to 26F may have a camera.

Although not shown, the electronic devices shown in FIGS. 26A to 26F have sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, fluid, magnetism, temperature,
chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, infrared rays, etc.). In particular, by providing the mobile phone shown in FIG. 26(D) with a detection device having a sensor such as a gyro or an acceleration sensor that detects the inclination, the orientation of the mobile phone (which orientation of the mobile phone with respect to the vertical direction) can be detected. ), and the screen display on the display unit 5502 can be automatically switched according to the orientation of the mobile phone.

Also, although not shown, the electronic device shown in FIGS.
The configuration may include a device for acquiring biometric information such as iris or voiceprint. By applying this configuration, an electronic device having a biometric authentication function can be realized.

Further, a flexible base material may be used for the display portion of the electronic device shown in FIGS. Specifically, the display portion may have a structure in which a transistor, a capacitor, a display element, and the like are provided over a flexible base material. By applying this configuration,
An electronic device having a curved surface can be realized in addition to a housing having a flat surface as in the electronic devices shown in FIGS.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

(Additional remarks regarding descriptions in this specification, etc.)
A description of each configuration in the above embodiment will be added below.

<Additional Remarks Regarding One Mode of the Present Invention Described in the Embodiment>
The structure described in each embodiment can be combined with any structure described in another embodiment as appropriate to be one embodiment of the present invention. Moreover, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

It should be noted that the content (or part of the content) described in one embodiment may be combined with another content (or part of the content) described in that embodiment, or one or a plurality of other implementations. can be applied, combined, or replaced with at least one of the contents described in the form of (may be part of the contents).

In addition, the content described in the embodiment means the content described using various drawings or the content described using sentences described in the specification in each embodiment.

It should be noted that the figure (may be part of) described in one embodiment refers to another part of that figure, another figure (may be part) described in that embodiment, and one or more other More drawings can be formed by combining at least one of the drawings (or part of them) described in the embodiments.

<Notes on ordinal numbers>
In this specification and the like, the ordinal numbers "first", "second", and "third" are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Also, the order of the components is not limited. Also, for example, the component referred to as "first" in one embodiment of this specification etc. is the component referred to as "second" in another embodiment or the scope of claims It is possible. Further, for example, the component referred to as "first" in one of the embodiments of this specification etc. may be omitted in other embodiments or the scope of claims.

<Supplementary remarks regarding the description explaining the drawings>
Embodiments are described with reference to the drawings. However, those skilled in the art will readily appreciate that the embodiments can be embodied in many different forms and that various changes in form and detail can be made without departing from the spirit and scope thereof. be. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In addition, in the configuration of the invention of the embodiment, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted.

In this specification and the like, terms such as “above” and “below” are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. The positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, the words and phrases indicating the arrangement are not limited to the descriptions described in the specification, and can be appropriately rephrased according to the situation.

In addition, the terms "upper" and "lower" do not limit the positional relationship of the components to being directly above or directly below and in direct contact with each other. For example, the expression “electrode B on insulating layer A” does not require that electrode B be formed on insulating layer A in direct contact with another configuration between insulating layer A and electrode B. Do not exclude those containing elements.

Also, in the drawings, sizes, layer thicknesses, and regions are shown as arbitrary sizes for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values shown in the drawings. For example, variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing shift can be included.

Also, in the drawings, in perspective views and the like, descriptions of some components may be omitted in order to ensure clarity of the drawings.

In addition, in the drawings, the same reference numerals may be given to the same elements, elements having similar functions, elements made of the same material, or elements formed at the same time, and repeated description thereof may be omitted. .

<Supplementary notes on rephrasable descriptions>
In this specification and the like, when describing the connection relationship of a transistor, one of a source and a drain is referred to as “one of the source or the drain” (or the first electrode or the first terminal). The other is described as "the other of source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of a transistor can be appropriately changed to a source (drain) terminal, a source (drain) electrode, or the like, depending on the situation. In addition, in this specification and the like, two terminals other than the gate are referred to as the first terminal and the second terminal.
It may be called a terminal, or may be called a third terminal or a fourth terminal. In addition, in this specification etc.,
A channel formation region refers to a region in which a channel is formed by applying a potential to the gate, and the formation of this region allows current to flow between the source and the drain.

Also, the functions of the source and drain may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, the terms "source" and "drain" can be used interchangeably in this specification and the like.

Further, when a transistor described in this specification and the like has two or more gates (this structure is sometimes referred to as a dual gate structure), these gates are sometimes referred to as a first gate and a second gate, or a front gate , is sometimes called a back gate. In particular, the term "front gate" is interchangeable with simply the term "gate."again,"
The phrase "back gate" is interchangeable with the phrase simply "gate." Note that a bottom gate is a terminal formed before a channel formation region is formed when a transistor is manufactured, and a “top gate” is a terminal formed after a channel formation region is formed when a transistor is manufactured. It refers to a terminal that

In addition, the terms “electrode” and “wiring” in this specification and the like do not functionally limit these constituent elements. For example, an "electrode" may be used as part of a "wiring" and vice versa. Furthermore, the terms "electrode" and "wiring" are used to refer to multiple "electrodes" and "
It also includes the case where "wiring" is integrally formed.

In this specification and the like, voltage and potential can be interchanged as appropriate. A voltage is a potential difference from a reference potential. For example, if the reference potential is a ground potential, the voltage can be translated into a potential. Ground potential is not always 0V
does not necessarily mean Note that the potential is relative, and depending on the reference potential,
In some cases, the potential applied to wiring or the like is changed.

Note that in this specification and the like, terms such as “film” and “layer” can be interchanged depending on the case or situation. For example, it may be possible to change the term "conductive layer" to the term "conductive film." Or, for example, it may be possible to change the term "insulating film" to the term "insulating layer". Alternatively, as the case may be, or depending on the circumstances, the terms "film", "layer", etc. can be omitted and replaced with other terms. For example, it may be possible to change the term "conductive layer" or "conductive film" to the term "conductor." Alternatively, for example, the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.

Note that in this specification and the like, terms such as “wiring”, “signal line”, and “power line” can be interchanged depending on the case or situation. For example, it may be possible to change the term "wiring" to the term "signal line". Also, for example,
It may be possible to change the term "wiring" to a term such as "power line". In addition, vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring". It may be possible to change terms such as "power line" to terms such as "signal line". Also, vice versa, terms such as "signal line" may be changed to terms such as "power line". In addition, the term "potential" applied to the wiring can be changed to the term "signal" or the like in some cases or depending on the situation. And vice versa, terms such as "signal" may be changed to the term "potential".

<Supplementary notes on definitions of terms>
Definitions of terms referred to in the above embodiments will be described below.

<<Semiconductor Impurities>>
An impurity of a semiconductor means, for example, a substance other than the main component that constitutes a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. When impurities are contained, for example, DOS (Density of States) is formed in the semiconductor, carrier mobility is lowered, crystallinity is lowered, and the like may occur. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, and elements other than the main component. transition metals, etc.
In particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed due to entry of impurities such as hydrogen. When the semiconductor is a silicon layer, the impurities that change the characteristics of the semiconductor include, for example, group 1 elements excluding oxygen and hydrogen, group 2 elements, and
There are Group 3 elements, Group 15 elements, and the like.

<<About the switch>>
In this specification and the like, a switch has a function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not current flows. Alternatively, a switch has a function of selecting and switching a path through which current flows.

As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control current.

Examples of electrical switches include transistors (e.g., bipolar transistors,
MOS transistors, etc.), diodes (for example, PN diodes, PIN diodes,
Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), or logic circuits combining these.

When a transistor is used as a switch, the "conducting state" of the transistor means:
A state in which the source and drain electrodes of a transistor can be considered to be electrically short-circuited. A “non-conducting state” of a transistor means a state in which a source electrode and a drain electrode of the transistor can be considered to be electrically cut off. Note that the polarity (conductivity type) of the transistor is not particularly limited when the transistor is operated as a simple switch.

An example of a mechanical switch is a switch using MEMS (micro-electro-mechanical system) technology, such as a digital micromirror device (DMD). The switch has an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction by moving the electrode.

<<About connection>>
In this specification and the like, when it is described that X and Y are connected, it means that X and Y are electrically connected and that X and Y are functionally connected. and where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the diagram or text, and includes connections other than the connection relationship shown in the diagram or text.

It is assumed that X, Y, etc. used here are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

An example of the case where X and Y are electrically connected is an element that enables electrical connection between X and Y (for example, switch, transistor, capacitive element, inductor, resistive element, diode, display elements, light emitting elements, loads, etc.) can be connected between X and Y. Note that the switch has a function of being controlled to be turned on and off. In other words, the switch has the function of being in a conducting state (on state) or a non-conducting state (off state) and controlling whether or not to allow current to flow.

As an example of the case where X and Y are functionally connected, a circuit that enables functional connection between X and Y (eg, a logic circuit (inverter, NAND circuit, NOR circuit, etc.), a signal conversion Circuits (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (
Power supply circuit (booster circuit, step-down circuit, etc.), level shifter circuit that changes the potential level of the signal, etc.), voltage source, current source, switching circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier) circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, storage circuit, control circuit, etc.) can be connected between X and Y. As an example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected. do.

It should be noted that when explicitly describing that X and Y are electrically connected, it means that X and Y are electrically connected (that is, another element or connected across another circuit), and when X and Y are functionally connected (that is, functionally connected across another circuit between X and Y). and the case where X and Y are directly connected (that is, the case where X and Y are connected without another element or another circuit between them). In other words, the explicit description of "electrically connected" is the same as the explicit description of "connected".

Note that, for example, the source (or the first terminal, etc.) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal, etc.) of the transistor is
When electrically connected to Y through (or not through) Z2, or when the source (or first terminal, etc.) of a transistor is directly connected to part of Z1 and another part of Z1 One part is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to one part of Z2, and another part of Z2 is directly connected to Y. If so, it can be expressed as follows.

For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected together, and X, the source (or first terminal, etc.) of the transistor terminal, etc.), the drain of the transistor (or the second terminal, etc.), and are electrically connected in the order of Y.". Or "the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X is the source of the transistor ( or the first terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are electrically connected in this order. or "X is electrically connected to Y through the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor; terminal, etc.), the drain of the transistor (or the second terminal, etc.)
, Y are provided in this connection order”. Using expressions similar to these examples, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor can be distinguished by defining the order of connections in the circuit configuration. Alternatively, the technical scope can be determined. In addition, these expression methods are examples, and are not limited to these expression methods. where X, Y, Z1, Z2 are objects (e.g., devices,
element, circuit, wiring, electrode, terminal, conductive film, layer, etc.).

Even if the circuit diagram shows independent components electrically connected to each other, if one component has the functions of multiple components There is also For example, when a part of the wiring also functions as an electrode, one conductive film has both the function of the wiring and the function of the electrode. Therefore, the term "electrically connected" in this specification includes cases where one conductive film functions as a plurality of constituent elements.

<<Regarding Parallel and Perpendicular>>
As used herein, the term “parallel” refers to a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, the case of −5° or more and 5° or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30° or more and 30° or less.
"Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Also, "substantially vertical" means
A state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

MC[1] memory cell MC[2] memory cell MC[n] memory cell MC[1,1] memory cell MC[j,1] memory cell MC[n,1] memory cell MC[1,i] memory cell MC[j,i] memory cell MC[n,i] memory cell MC[1,m] memory cell MC[j,m] memory cell MC[n,m] memory cell WWL[1] wiring WWL[2] wiring WWL[j] Wiring WWL[n] Wiring RWL[1] Wiring RWL[2] Wiring RWL[j] Wiring RWL[n] Wiring WBL Wiring WBL[1] Wiring WBL[i] Wiring WBL[m] Wiring RBL Wiring RBL [1] Wiring RBL[i] Wiring RBL[m] Wiring BGL Wiring BGL[1] Wiring BGL[i] Wiring BGL[m] Wiring WTr Transistor RTr Transistor CS Capacitive element N1 Node N2 Node PG Conductor WWL Wiring RWL Wiring ER Wiring HL Region AR Region SD1 Region SD2 Region 100 Laminate 101A Insulator 101B Insulator 101C Insulator 101D Insulator 101E Insulator 102 Insulator 103 Insulator 104 Insulator 105 Insulator 131A Conductor 131B Conductor 132A Conductor 132B Conductive Body 133 Conductor 133a Conductor 133b Conductor 133c Conductor 134 Conductor 151 Semiconductor 151a Region 151b Region 151c Region 152 Semiconductor 153 Semiconductor 153a Semiconductor 153b Semiconductor 181A Region 181B Region 182A Region 182B Region 183A Region 183B Region 191 Opening 192A recess 192B Recess 193A Recess 193B Recess 194A Recess 194B Recess 194C Recess 1191 ALU
1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM
1189 ROM interface 1190 substrate 1700 substrate 1701 element isolation layer 1712 conductor 1730 conductor 1790 gate electrode 1792 well 1793 channel forming region 1794 low concentration impurity region 1795 high concentration impurity region 1796 conductive region 1797 gate insulating film 1798 sidewall insulating layer 1799 sidewall Insulating layer 2600 Storage device 2601 Peripheral circuit 2610 Memory cell array 2621 Row decoder 2622 Word line driver circuit 2630 Bit line driver circuit 2631 Column decoder 2632 Precharge circuit 2633 Sense amplifier 2634 Write circuit 2640 Output circuit 2660 Control logic circuit 5100 USB memory 5101 Case 5102 Cap 5103 USB connector 5104 Board 5105 Memory chip 5106 Controller chip 5110 SD card 5111 Case 5112 Connector 5113 Board 5114 Memory chip 5115 Controller chip 5150 SSD
5151 housing 5152 connector 5153 substrate 5154 memory chip 5155 memory chip 5156 controller chip 5401 housing 5402 display unit 5403 keyboard 5404 pointing device 5501 housing 5502 display unit 5503 microphone 5504 speaker 5505 operation button 5701 display panel 5702 display panel 5703 display panel 5 704 Display panel 5801 First housing 5802 Second housing 5803 Display unit 5804 Operation keys 5805 Lens 5806 Connection unit 5901 Housing 5902 Display unit 5903 Operation buttons 5904 Operators 5905 Band 9000 Housing 9001 Display unit 9003 Speaker 9005 Operation keys 9006 Connection Terminal 9007 Sensor

Claims (1)

a first conductor functioning as a gate electrode of the first transistor;
a first oxide semiconductor having a region surrounding the first conductor with a first insulator interposed therebetween;
a second oxide semiconductor having a region surrounding the first oxide semiconductor with a second insulator;
a semiconductor layer having a region surrounding the second oxide semiconductor via a third insulator;
a second conductor having a region surrounding the semiconductor layer and functioning as a gate electrode of a second transistor;
The semiconductor layer has a region in contact with the second conductor,
the first transistor is positioned above or below the second transistor;
the first oxide semiconductor has a first region functioning as a channel of the first transistor;
A semiconductor device in which the second oxide semiconductor has a second region functioning as a channel of the second transistor.

Images