JP2018082025A - Semiconductor device, power conversion apparatus and manufacturing method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve suppression of a voltage-withstanding from fluctuating due to a changing electric field distribution in a termination region.SOLUTION: The semiconductor device includes: an active region 2 formed on a silicon carbide substrate 101; and a termination region 3 formed around the active region 2. The termination region 3 includes: a drift layer 102 formed on the silicon carbide substrate 101 and having a step-off part 200 on the surface; and a dielectric layer 107 formed to cover the step-off part 200 on the surface of the drift layer 102.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, a power conversion device, and manufacture of the semiconductor device.

  In recent years, power semiconductor devices (SiC power semiconductor devices) using SiC (silicon carbide) having excellent physical property values have begun to be mounted on inverters and the like of power sections such as railways. The SiC power semiconductor device includes an active region in which a current flows when a forward voltage is applied, and a termination region that relaxes an electric field that does not flow in a forward voltage but is concentrated on a chip termination portion when a reverse voltage is applied. Is done. A dielectric layer is formed on the termination region. An SiC power semiconductor device having such a configuration is disclosed in Patent Document 1, for example.

JP, 2014-160036, A

J. et al. Appl. Phys. 119, 154506 (2016)

  However, in the SiC power semiconductor device of Patent Document 1, a dielectric layer (resin layer) is directly formed on a termination region having a flat surface. With such a configuration, a positive charge storage layer is formed at the interface between the dielectric layer and the termination region. The formation of this positive charge storage layer is closely related to the manufacturing process of the SiC power semiconductor device. That is, in the manufacturing process of the SiC power semiconductor device, an oxidation step generally exists before the dielectric layer forming step. In this oxidation step, a positive charge storage layer is formed. Then, due to the presence of the positive charge accumulation layer, the electric field distribution changes in the termination region and the breakdown voltage varies (see Non-Patent Document 1). Patent Document 1 does not mention the fluctuation of the electric field distribution in the termination region caused by the presence of the positive charge storage layer.

  An object of the present invention is to provide a semiconductor device, a power conversion device, and a method of manufacturing a semiconductor device that can suppress an electric field distribution from changing and a withstand voltage fluctuation in a termination region.

  A semiconductor device according to an aspect of the present invention includes an active region formed on a silicon carbide substrate, and a termination region formed around the active region, and the termination region is formed on the silicon carbide substrate. A drift layer formed and having a stepped portion on a surface thereof, and a dielectric layer formed on the surface of the drift layer so as to cover the stepped portion.

  A power conversion device according to one embodiment of the present invention includes the semiconductor device according to the above embodiment.

  A method for manufacturing a semiconductor device according to an aspect of the present invention is a method for manufacturing a semiconductor device having a termination region around an active region, wherein a drift layer is formed on the silicon carbide substrate in the termination region. A step of forming, an oxidation step of oxidizing the surface of the drift layer, an etching step of forming a step by etching the surface of the drift layer, and covering the step formed by the etching And a dielectric layer forming step of forming the dielectric layer as described above.

  According to the present invention, it can be suppressed that the electric field distribution changes and the breakdown voltage fluctuates in the termination region.

1 is a plan view of a semiconductor device according to Embodiment 1. FIG. 3 is a cross-sectional view taken along line X-X ′ of the semiconductor device according to the first embodiment. FIG. FIG. 6 is a cross-sectional view taken along line XX ′ of another semiconductor device according to the first embodiment. This is a reverse current-reverse voltage characteristic before and after applying a reverse voltage for a long time at a high temperature of a general semiconductor device. 2 is a reverse current-reverse voltage characteristic before and after applying a reverse voltage for a long time at a high temperature in the semiconductor device of Embodiment 1. FIG. This is a capacitance-reverse voltage characteristic before and after applying a reverse voltage of a general semiconductor device for a long time. It is a capacitance-reverse voltage characteristic before and after applying the reverse voltage of the semiconductor device of Embodiment 1 for a long time. It is a figure which shows the simulation result of the internal state of a termination area | region when changing the quantity of positive charge. It is an ion implantation profile of a semiconductor device. 3 is a flowchart showing a method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ showing the manufacturing process of the semiconductor device according to the first embodiment. FIG. 10 is a flowchart showing another method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ of the semiconductor device according to the second embodiment. FIG. 6 is a cross-sectional view taken along line X-X ′ of another semiconductor device according to the second embodiment. 5 is a flowchart illustrating a method for manufacturing a semiconductor device according to a second embodiment. FIG. 6 is a circuit diagram of a three-phase motor driving inverter according to a third embodiment. FIG. 6 is a schematic circuit diagram of a converter and an inverter that constitute a railway vehicle according to a fourth embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  Until now, Si (silicon) has been the mainstream material for power semiconductor devices, but in recent years, SiC (silicon carbide) having excellent physical properties has begun to be adopted. Since a power semiconductor device using SiC has a dielectric breakdown strength about 10 times that of Si, the width of the depletion layer that expands to the epitaxial layer side when a reverse voltage is applied to the power semiconductor device is about 1/10. The thickness can be reduced. Therefore, the on-resistance of the element can be reduced at the same breakdown voltage as compared with a power converter using Si. Moreover, since SiC has a thermal conductivity three times that of Si, it is suitable for operation in a high temperature environment.

  The power semiconductor device includes an active region in which a current flows when a forward voltage is applied, and a termination region for relaxing an electric field concentrated on a chip termination portion when a reverse voltage is applied. Since no current flows in the termination region, it is desirable to make the termination area per chip as small as possible from the viewpoint of cost. As described above, SiC has a depletion layer width that spreads to the epitaxial layer side as compared with Si, which is about 1/10. Therefore, theoretically, the termination width can be designed to be narrow. However, the present situation is that the termination width cannot be designed to be sufficiently narrow for the following reasons. When a reverse voltage is applied to a SiC power semiconductor device at a high temperature for a long time, a phenomenon that the voltage fluctuates occurs. When the charge in the termination region fluctuates in accordance with the change in the depletion layer capacitance that spreads to the termination region when applied in the reverse direction, the electric field distribution changes, and as a result, the voltage fluctuates. Therefore, it is necessary to design a termination structure that can obtain a desired withstand voltage even if the amount of charge increases, and the termination width is widened.

The charge fluctuation width in the termination region of the SiC power semiconductor device is 0 to 2e10 ¹³ cm ⁻² . If a desired withstand voltage characteristic is obtained in this range, the termination area increases, and the number of chips that can be obtained from one wafer decreases. For SiC, which has a high wafer cost, the number of chips per wafer is a major cause of cost increase. In order to solve this problem, it is necessary to suppress the charge fluctuation in the termination region or to provide a structure in which the electric field distribution does not change even if the charge fluctuation occurs. That is, there is a need for a structure that suppresses charge fluctuations that occur in the termination region before and after applying a reverse voltage at a high temperature for a long time, or that is less susceptible to charge fluctuations, and a manufacturing method thereof. In consideration of such a viewpoint, the embodiment of the present invention provides an SiC power semiconductor device and a method for manufacturing the same, in which the electric field distribution changes and the withstand voltage fluctuates in the termination region.

Embodiment 1

  Hereinafter, the structure of the semiconductor chip 1 which is the semiconductor device (SiC power semiconductor device) according to the first embodiment will be described with reference to FIGS. As shown in FIG. 1, the semiconductor device of Embodiment 1 has an active region 2 and a termination region (termination region) 3. In FIG. 1, the electrodes formed on the active region 2 and the passivation film formed on the termination region 3 are omitted.

  FIG. 2 is a cross-sectional view taken along line XX ′ shown in FIG. As shown in FIG. 2, the semiconductor device according to the first embodiment includes a SiC substrate 101 that is a semiconductor substrate made of SiC. SiC substrate 101 contains an n-type impurity (for example, N (nitrogen)) at a high concentration. A back electrode 108 is formed on the back surface of SiC substrate 101, that is, the second main surface. The back electrode 108 is, for example, a back electrode made of a laminated film in which a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film are formed in order from the bottom of the SiC substrate 101 downward. Back electrode 108 and SiC substrate 101 are in ohmic contact.

  An n-type drift layer 102 made of SiC having an n-type impurity concentration lower than that of the SiC substrate 101 is formed on the upper surface of the n-type SiC substrate 101 made of SiC, that is, on the first main surface. The drift layer 102 contains an n-type impurity (for example, N (nitrogen) or P (phosphorus)) at a relatively low concentration. The thicknesses of the n-type SiC substrate 101 and the n-type drift layer 102 are determined by a desired breakdown voltage. For example, the thickness of the drift layer 102 in the 3.3 kV breakdown voltage specification semiconductor device is 25 to 35 μm.

  A p-type impurity region 103 for forming the termination region 3 is formed on a part of the surface of the epitaxial layer including the drift layer 102. The p-type impurity region 103 contains a p-type impurity (for example, Al (aluminum) or B (boron)). The first p-type impurity region 103a and the second p-type impurity region 103b have different concentrations. Preferably, the impurity concentration of first p-type impurity region 103a is higher than the impurity concentration of second p-type impurity region 103b.

  The termination region 3 shown in FIG. 2 includes two regions (a first p-type impurity region 103a and a second p-type impurity region 103b) having different concentrations, but may be formed of three or more regions. Moreover, the termination area | region 3 which consists of a some discrete p-type area | region 109 (109a-109d) may be sufficient as shown in FIG.

  A surface electrode 106 is formed on the surface of the drift layer 102 in the active region 2. The end portion of the surface electrode 106 is on the p-type impurity region 103a. The surface electrode 106 is composed of, for example, a laminated film in which a Ti (titanium) film, a TiN film, and an Al film are formed in order from the upper surface of the drift layer 102 upward.

  In the termination region 3, a dielectric layer 107 is formed thereon with the surface of the drift layer 102 being scraped. As a result, the drift layer 102 has a structure having a predetermined stepped portion 200 on the surface. Specifically, the stepped portion 200 is formed with respect to the p-type impurity region 103 (see FIG. 12). Accordingly, the dielectric layer 107 formed on the surface of the drift layer 102 also has a predetermined stepped portion 210. Here, the dielectric layer 107 is, for example, a resin film or silicon oxide. Since the drift layer 102 and the dielectric layer 107 have such stepped portions 200 and 210, the surface height of a part of the termination region 3 is lower than the surface height of the active region 2.

  FIG. 4A shows reverse current-voltage characteristics before and after applying a reverse voltage for a long time at a high temperature to a sample in which the dielectric layer 107 is formed without cutting the surface of the drift layer 102. On the other hand, FIG. 4B shows reverse current-voltage characteristics before and after applying a reverse voltage for a long time at a high temperature to a sample in which the surface of the drift layer 102 is cut and the dielectric layer 107 is formed. . In the figure, the initial stage shows the characteristics before applying the reverse voltage, and the applied characteristics show the characteristics after applying the reverse voltage. In FIG. 4A, it changes with the initial withstand voltage 10 and the withstand voltage 11 after application, but there was almost no change in FIG. 4B.

  FIG. 5A shows reverse capacitance-voltage characteristics before and after applying a reverse voltage for a long time at a high temperature to a sample in which the dielectric layer 107 is formed without cutting the surface of the drift layer 102. On the other hand, FIG. 5B shows reverse capacitance-voltage characteristics before and after applying a reverse voltage for a long time at a high temperature to a sample in which the surface of the drift layer 102 is cut and the dielectric layer 107 is formed. . In the figure, the initial stage shows the characteristics before applying the reverse voltage, and the applied characteristics show the characteristics after applying the reverse voltage. In FIG. 5A, the capacitance fluctuation 12 and the capacitance fluctuation 13 are generated in the initial stage and after voltage application, but in FIG.

  FIG. 6 shows a simulation result of a change in the internal state of the termination region 3 due to a difference in charge amount. Comparing the state where the positive charge 14 is small and the state where the positive charge 14 is large, at the time of 500V, the depletion layer end 15 advances to the active region side with a large amount of positive charge. The depletion layer end 15 does not change when the positive charge is small, but at 3000 V, the depletion layer end 15 advances toward the active region again with a large positive charge. When the amount of the positive charge 14 increases, the depletion layer end 15 easily expands toward the active region, and the difference between the depletion layer expansions appears in the characteristics as the capacitance variation 12 and the capacitance variation 13 shown in FIG. 5A. That is, if there is no difference in capacitance before and after the reverse voltage is applied for a long time at a high temperature, there is no charge fluctuation in the termination region 3. In FIG. 5B, since the capacitance does not fluctuate in the initial stage and after the voltage application, the charge fluctuation does not occur, and the structure in which the surface of the drift layer 102 is cut and the dielectric layer 107 is formed is effective in suppressing the charge fluctuation. It can be said.

  In the process of the SiC power semiconductor, there are a sacrificial oxidation step in which silicon oxide is formed on the SiC surface by thermal oxidation to remove the impurity layer on the surface, and a step of forming a gate insulating film in the switching element. At this time, a C (carbon) segregation layer is formed on the SiC surface, and this segregation layer functions as a charge storage layer. Therefore, in the structure in which the dielectric layer 107 is formed without removing the surface of the drift layer 102, charge fluctuation occurs. It can be said that.

  The effect of scraping the surface of the drift layer 102 also appears in the ion implantation profile. FIG. 7 shows an ion implantation profile for forming the p-type impurity region 103. In the box profile in which the concentration is constant up to a certain depth, the ion implantation concentration near the surface of the drift layer 102 becomes low (17). When the ion implantation concentration in the vicinity of the surface of the drift layer 102 is low, the depletion layer spreading difference due to the charge fluctuation increases, and the fluctuation of the electric field distribution increases. As a result, the withstand voltage fluctuation is likely to occur. By scraping the surface of the drift layer 102, a region having a high ion implantation concentration becomes the drift layer resurface. In the ion implantation profile, the region having the highest impurity concentration corresponds to the bottom surface of the stepped portion 200 (see FIG. 2). As a result, a depletion layer expansion difference due to charge fluctuation is less likely to occur. For this reason, even if the charge storage layer cannot be removed and charge fluctuations occur, the influence can be minimized.

  Next, with reference to FIGS. 8 to 14, a method for manufacturing the semiconductor device according to the first embodiment will be described.

  First, as shown in FIG. 9, a substrate preparation step is performed (S121). Specifically, an n-type SiC substrate 101 made of 4H—SiC doped with an n-type impurity (for example, N (nitrogen)) is prepared. Subsequently, an epitaxial layer including an n-type drift layer 102 made of SiC (silicon carbide) is formed on the main surface of the SiC substrate 101 using an epitaxial growth method.

  Next, as shown in FIG. 10, an ion implantation step is performed (S122). Specifically, the p-type semiconductor region 103 is formed by ion-implanting p-type impurities (for example, Al (aluminum) or B (boron)) into the upper surface of the drift layer 102. As a mask at the time of ion implantation, for example, a silicon oxide film or a photoresist film formed by using a plasma CVD (Chemical Vapor Deposition) method is used.

  Next, as shown in FIG. 11, an impurity activation step is performed (S123). Specifically, after removing the silicon oxide film and depositing a carbon film 104 as a cap material for impurity activation annealing, impurity activation annealing is performed. The impurity activation annealing temperature is, for example, 1550 to 1800 ° C.

  Next, an oxidation step is performed (S124). Specifically, after removing the carbon film 104 of the cap material by oxygen plasma ashing or the like, an oxide film is formed on the surface of the epitaxial layer by a thermal oxidation method or the like in order to obtain a clean surface, and this oxide film is removed. To do. In the case of the switching element, thereafter, an oxidation process for forming a gate oxide film and a gate insulating film are formed. In this oxidation step (S124), a charge storage layer is formed on the surface of the epitaxial layer.

  Next, as shown in FIG. 12, a silicon carbide etching step is performed (S125). Specifically, the surface of the drift layer 102 in the termination region 3 (the surface of the p-type semiconductor region 103) is shaved by sputter etching. As a result, silicon carbide etching region 105 is formed as stepped portion 200 shown in FIG. By this silicon carbide etching, the charge storage layer formed in the oxidation step (S124) is removed. At this time, the surface of the drift layer 102 may be shaved by dry etching.

  Next, as shown in FIG. 13, a surface electrode forming step is performed (S126). Specifically, the surface electrode 106 is formed on the surface of the p-type semiconductor region 103a. For example, a Ti (titanium) film, a TiN film, and an Al film are formed in this order from the upper surface of the drift layer 102 by sputtering or the like.

  Next, as shown in FIG. 14, next, a step of forming a dielectric layer is performed (S127). Specifically, dielectric layer 107 is formed so as to cover silicon carbide etching region 105 formed by silicon carbide etching (S125) and surface electrode 106 formed by surface electrode formation (S126). Here, as the dielectric layer 107, for example, resin or silicon oxide is used.

  Next, a back electrode forming step (S128) is performed. Specifically, as shown in FIG. 2, back electrode 108 is formed on the second main surface of SiC substrate 101. Thereby, the semiconductor device shown in FIG. 2 is completed. Here, the back electrode 108 is, for example, a back electrode made of a laminated film in which a Ti (titanium) film, a Ni (nickel) film, and an Au (gold) film are formed in order from the bottom surface of the SiC substrate 101 downward. .

  Here, a method for manufacturing a semiconductor device different from the method for manufacturing the semiconductor device shown in FIG. 8 will be described with reference to FIG. The difference between the step of FIG. 8 and the step of FIG. 15 is that the order of the surface electrode forming step and the silicon carbide etching step is interchanged. The effect of the first embodiment can be obtained by performing silicon carbide etching after the oxidation step (S124) and before forming the dielectric layer 107. For this reason, even if the steps are switched as shown in FIG. 15, the same effects as those of the first embodiment can be obtained.

Embodiment 2

  A semiconductor device according to the second embodiment will be described with reference to FIGS. As shown in FIG. 16, the second embodiment is different from the first embodiment (see FIG. 2) in that an insulating film 110 is formed between the dielectric layer 107 and the p-type semiconductor region 103 whose surface has been cut. The point is that the end portion of the surface electrode 106 rides on the insulating film 110. By adopting the configuration shown in FIG. 16, the distance from the surface of the drift layer 102 to the end portion of the surface electrode 106 is increased, so that the breakdown when the electric field is concentrated on the end portion of the surface electrode 106 is less likely to occur. As shown in FIG. 16, the insulating film 110 may not be formed on the entire termination region 3. That is, as shown in FIG. 17, the insulating film 110 may be formed in a part of the termination region 3. Since the configuration of other semiconductor devices is almost the same as the configuration of the semiconductor device according to the first embodiment (see FIG. 2), the description thereof is omitted.

  Next, with reference to FIG. 18, the manufacturing method of the semiconductor device concerning Embodiment 2 is explained. The semiconductor device manufacturing method according to the second embodiment is different from the semiconductor device manufacturing method according to the first embodiment (see FIG. 8) in that an insulating film formation step (S136) is performed after the silicon carbide etching step (S135). ). Since other semiconductor device manufacturing methods are substantially the same as those of the semiconductor device manufacturing method according to the first embodiment (see FIG. 8), description thereof is omitted.

Embodiment 3

  With reference to FIG. 19, the power converter device which concerns on Embodiment 3 is demonstrated. The semiconductor device described in Embodiment 1 or Embodiment 2 can be used for automobiles such as hybrid cars and electric cars, for example. That is, it can be used for a power conversion device such as a motor drive inverter. FIG. 19 shows a circuit diagram of a three-phase motor driving inverter using the semiconductor device of the first embodiment or the second embodiment.

  As illustrated in FIG. 19, the three-phase motor system according to the third embodiment includes a motor 601, an inverter module 602 that is a power module, and a control circuit 603. The inverter module 602 and the control circuit 603 constitute a power conversion device. The motor 601 is driven by three-phase voltages having different phases.

  The inverter module 602 includes the switching element 604 having the termination region 3 described in the first or second embodiment and the diode 605 having the termination region 3 described in the first or second embodiment.

  The inverter module 602 has terminals 606 to 612. In the inverter module 602, in each single phase of the three phases, the switching element 604 and the diode 605 functioning as a free-wheeling diode are connected between the power supply potential (Vd) and the input potential of the motor 601 via the terminals 607 to 610. Are connected in antiparallel, and the switching element 604 and the diode 605 are also connected in antiparallel via the terminals 607 to 610 between the input potential of the motor 601 and the ground potential (GND).

  As described above, the switching element 604 and the diode 605 having the termination region 3 described in the first or second embodiment are connected in antiparallel for each single phase connected to the motor 601. Therefore, the inverter module 602 is provided with a total of 12 chips in three phases. Although a part of the wiring is not shown, a control circuit 603 is connected to the gate electrode of each chip via terminals 612 to 613, and the MOSFET of each chip is controlled by the control circuit 603. The In the three-phase motor system of the third embodiment, the motor 601 is rotated by controlling the current flowing through the MOSFET of each chip of the inverter module 602 by the control circuit 603.

  By using the semiconductor device having the termination region 3 according to the first embodiment or the second embodiment, it is possible to provide a power module and a power conversion device whose withstand voltage characteristics do not change.

  Note that the semiconductor device having the termination region 3 described in Embodiment 1 or Embodiment 2 can be used not only for the above-described inverter but also for a converter described later.

Embodiment 4

  With reference to FIG. 20, the power converter device which concerns on Embodiment 4 is demonstrated. The semiconductor device having the termination region 3 according to the first embodiment or the second embodiment can be used for a power conversion circuit such as an AC-DC-AC converter including a converter and an inverter used in a railway vehicle. Below, the rail vehicle of Embodiment 4 is demonstrated with reference to FIG.

  FIG. 20 is a schematic circuit diagram of a converter and an inverter constituting the railway vehicle of the fourth embodiment. In FIG. 20, circuits constituting the converter module 706 and the inverter module 702 are shown in a simplified manner. The inverter module 702 has a structure similar to that of the inverter module 602 shown in FIG. In FIG. 20, a power conversion circuit including a converter module 706 and an inverter module 702 is shown without illustration of the structure of the railway vehicle.

  As shown in FIG. 20, power is supplied to the railway vehicle of the fourth embodiment from, for example, an overhead line 711 that supplies a voltage of 25 kV via a pantograph 710 provided in the railway vehicle. As a result, the current flowing through the overhead line 711 passes through the transformer 708 in the railway vehicle, and then flows to the track 712 via the wheels 709 of the railway vehicle. The railway vehicle includes a transformer 708, a converter module 706, a capacitor 707, an inverter module 702, and a motor 701. Here, the motor 701 is a three-phase motor.

  When the voltage is applied to the transformer 708, the voltage is stepped down to 1.5 kV via the transformer 708, and the voltage is converted from alternating current to direct current in the converter module 706 connected to the transformer 708 in the railway vehicle. This voltage is converted from direct current to alternating current in the inverter module 702 via the capacitor 707 to drive the motor 701. The configurations of the switching element 704 and the diode 705 in the converter module 706 and the inverter module 702 are the same as the switching element 604 and the diode 605 of the third embodiment shown in FIG.

  As the switching element 704 and the diode 705 used in the converter module 706 and the inverter module 702, a semiconductor device having the termination region 3 according to the first embodiment or the second embodiment is used. Thereby, like Embodiment 3, the alternating current-direct current-alternating current converter whose withstand voltage characteristic does not change can be provided.

  According to the embodiment, it is possible to provide an SiC power semiconductor device in which charge fluctuation in the termination region is suppressed. In addition, it is possible to provide a SiC power semiconductor device in which the withstand voltage characteristic is unlikely to change even if the charge fluctuates.

DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Active region 3 Termination region 101 SiC substrate 102 Drift layer 103 P-type impurity region 104 Carbon film 105 Silicon carbide etching region 106 Surface electrode 107 Dielectric layer 108 Back surface electrode 109 Discrete p-type region 110 Insulating film

Claims (12)

An active region formed on the silicon carbide substrate, and a termination region formed around the active region,
The termination region is
A drift layer formed on the silicon carbide substrate and having a stepped portion on the surface;
A dielectric layer formed on the surface of the drift layer so as to cover the stepped portion;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the drift layer has the same conductivity type as the silicon carbide substrate and has a lower impurity concentration than the silicon carbide substrate. An impurity region is formed on the upper surface of the drift layer,
The semiconductor device according to claim 1, wherein the step portion is formed with respect to the impurity region.   The semiconductor device according to claim 3, wherein the impurity region has a conductivity type different from that of the drift layer.   5. The semiconductor device according to claim 4, wherein the impurity region includes at least a first impurity region and a second impurity region having an impurity concentration different from that of the first impurity region.   The semiconductor device according to claim 1, wherein the step portion is provided to remove a charge storage layer formed on a surface of the drift layer. The impurity region has a predetermined impurity concentration profile;
4. The semiconductor device according to claim 3, wherein in the impurity concentration profile, a region having the highest impurity concentration corresponds to a bottom surface of the step portion.   The semiconductor device according to claim 3, wherein an insulating film is formed between the impurity region and the dielectric layer.   The semiconductor device according to claim 1, wherein a surface height of a part of the termination region is lower than a surface height of the active region.   A power conversion device comprising the semiconductor device according to claim 1. A method of manufacturing a semiconductor device having a termination region around an active region,
In the termination region,
A drift layer forming step of forming a drift layer on the silicon carbide substrate;
An oxidation step of oxidizing the surface of the drift layer;
An etching step of forming a stepped portion by etching the surface of the drift layer;
A dielectric layer forming step of forming a dielectric layer so as to cover the stepped portion formed by the etching;
A method for manufacturing a semiconductor device, comprising:   The etching is performed after the oxidation process and before the dielectric layer formation process so that the charge storage layer formed in the oxidation process is removed. Semiconductor device manufacturing method.

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