JP2018074209A - Imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging apparatus which reduces current consumption of a counter without being influenced by signal levels that are acquired in the past and without performing useless processing.SOLUTION: An imaging apparatus comprises a pixel array part and a column processing circuit. An A/D conversion part includes: a comparator which compares an analog signal with a gradient reference voltage and of which the output is inverted in the timing that the analog signal crosses the reference voltage; and a counter including a first count function which performs a count operation until from generation timing of the reference voltage to the timing that the output of the comparator is inverted, synchronously with a clock of a fixed period, and a second count function which performs a count operation after the timing that the output of the comparator is inverted. A system control part that controls the entire imaging apparatus inhibits either the first count function or the second count function in accordance with an imaging mode.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a solid-state imaging device, a driving method for the solid-state imaging device, and an electronic apparatus.

  In an imaging device that converts light into an electrical signal and outputs an image signal, such as a digital still camera, in a solid-state imaging device used as an image capturing unit (photoelectric conversion unit), an increase in the number of pixels and a high frame in recent years Along with the increase in rate, technologies for realizing high-speed reading and technologies for reducing power consumption have become essential technologies.

  A MOS (including CMOS) type image sensor, which is one of solid-state imaging devices, takes advantage of the characteristics that can be manufactured in the same process as a CMOS integrated circuit, converts electric charges into electric signals for each pixel, and reads out electric signals from the pixels. Can be read out in parallel for each column. On the other hand, although high speed can be realized by performing parallel processing for each column, there is concern about an increase in current consumption due to local concentration of current consumed by the circuit during parallel processing.

  Conventionally, as a readout circuit for reading out signals from a plurality of pixels arranged in a matrix in parallel for each column, a configuration in which pixel signals are subjected to analog-digital conversion (hereinafter referred to as “A / D conversion”) for each column Things are known. This A / D conversion is roughly performed as follows.

  First, the analog electric signal read out to the vertical signal line is compared with a reference voltage (a linearly changing slope waveform with a certain slope) by a comparator arranged for each column, and at the same time, for each column as in the comparator. The counting operation is started in synchronization with a clock with a fixed period by the arranged counter. Thereafter, the counting operation of the counter is stopped when the analog electrical signal and the reference voltage cross each other and the output of the comparator is inverted. The final count value of the counter becomes a digital signal corresponding to the magnitude of the analog electric signal.

  Some conventional solid-state imaging devices have reduced current consumption due to local concentration of current consumed by a circuit when parallel processing is performed (see Patent Document 1). In Patent Document 1, when the signal level is relatively low, the counter is operated until the comparator output is inverted. On the other hand, when the signal level is relatively high, the counter is operated after the comparator output is inverted. Thus, the current consumption is reduced by shortening the operation period of the counter.

JP 2009-206709 A

  In the method of Patent Document 1, the operation period of the counter is determined on the assumption that the signal level of the image one frame before and the signal level of the frame acquired from now on are almost the same. Alternatively, the operation period of the counter is determined on the assumption that the signal level of the previous row and the signal level of the row to be acquired are almost the same.

  However, in practice, there is a problem that the signal level of an image acquired in the past is not always the same as the signal level of an image acquired in the future. In some cases, it is known in advance that the image becomes dark in the imaging mode of the camera, such as high ISO sensitivity shooting. As described above, there is another problem that wasteful processing is performed while the signal level is known to be low in advance.

  In view of the above-described problems, the present invention allows the system control unit to select the counter operation period according to the imaging mode, so that it does not depend on the signal level acquired in the past and does not perform wasteful processing. The purpose is to reduce the current.

To achieve the above purpose. The present invention
A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A column processing circuit having an A / D conversion unit that converts an analog signal output from the unit pixel into a digital signal in units of pixel columns of the pixel array unit;
The A / D converter compares the analog signal with an inclined reference voltage,
A comparator whose output is inverted at the timing when the analog signal and the reference voltage cross each other;
A first counting function that performs a counting operation from a timing at which the reference voltage is generated to a timing at which the output of the comparator is inverted in synchronization with a clock having a fixed period;
A counter having a second counting function for performing a counting operation after the timing at which the output of the comparator is inverted;
A system control unit that controls the entire imaging apparatus,
The system control unit prohibits either the first count function or the second count function according to an imaging mode.

  According to the present invention, the system control unit prohibits either the first count function or the second count function according to the imaging mode, so that it does not depend on the signal level acquired in the past and is useless. It is possible to provide an imaging device that reduces current consumption without performing any processing.

1 is a configuration block diagram of an imaging apparatus as an embodiment of the present invention. 1 is a system configuration diagram showing an outline of a configuration of a CMOS image sensor to which the present invention is applied. It is a circuit diagram which shows an example of the circuit structure of a unit pixel. It is a block diagram which shows an example of a structure of the clock input part of a counter. It is a timing waveform diagram showing an example of the operation of the counter. It is a block diagram which shows an example of a structure of the counter which has a function which switches both a front count and a back count. It is a timing waveform diagram showing the operation of the counter when the signal input to the input range of the A / D converter is low. It is a timing waveform diagram showing the operation of the counter when the signal input to the input range of the A / D converter is high. It is the figure which showed the outline of the general black drawing process. It is a timing chart at the time of black drawing photography of the 1st example of the present invention. It is a flowchart at the time of black drawing photography of the 1st example of the present invention. It is a block diagram which shows the outline of the digital gain of 2nd Example of this invention. It is a flowchart at the time of high ISO sensitivity still image photography of the 2nd example of the present invention. It is a flowchart at the time of high ISO sensitivity moving image photographing of the second embodiment of the present invention.

[Example]
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

<Hardware configuration of digital camera>
FIG. 1 is a block diagram showing the configuration of an imaging apparatus 100 according to an embodiment of the present invention. In FIG. 1, 103 is a photographing lens group including a zoom lens and a focus lens, 101 is a shutter having a diaphragm function, 210 is an imaging unit and an A / D converter composed of a photodiode or the like that converts an optical image into an electric signal. This is a CMOS image sensor with a built-in. Reference numeral 102 denotes a barrier that prevents the imaging system including the imaging lens 103, the shutter 101, and the CMOS image sensor 210 from being soiled or damaged by covering the imaging unit including the imaging lens 103 of the digital camera 100.

  An image processing unit 24 performs predetermined pixel interpolation processing and color conversion processing on data from the CMOS image sensor 210 or data from the memory control unit 15. The image processing unit 24 performs predetermined calculation processing using the captured image data, and the system control unit 50 performs control based on the obtained calculation result to perform AF (autofocus) processing, AE (automatic exposure). Processing, EF (flash emission) processing is performed. The image processing unit 24 further performs predetermined calculation processing using the captured image data, and also performs AWB (auto white balance) processing based on the obtained calculation result.

  Output data from the CMOS image sensor 210 is directly written into the memory 32 via the image processing unit 24 and the memory control unit 15 or via the memory control unit 15. The memory 32 stores image data converted into digital data by the CMOS image sensor 210 and image data to be displayed on the display unit 28 or the eyepiece display unit 29. The memory 32 has a storage capacity sufficient to store a predetermined number of still images, a moving image and sound for a predetermined time.

  The memory 32 also serves as an image display memory (video memory). The display image data written in the memory 32 is displayed by the display unit 28 and the eyepiece display unit 29. The display unit 28 performs display on a display device such as an LCD. A digital signal once A / D converted by the CMOS image sensor 210 and stored in the memory 32 is sequentially transferred to the display unit 28 and displayed, thereby functioning as an electronic viewfinder (through image display). The eyepiece display unit 29 is a display unit provided in a view-type finder, and can display the same as the display unit 28.

  Reference numeral 40 denotes an exposure control means for controlling the shutter 101 having an aperture function, and has a flash light control function in cooperation with the flash 48. A focus control unit 42 drives a focus lens included in the photographing lens 103 to control focusing. The zoom control unit 44 controls zooming by driving a zoom lens included in the photographing lens 103. The barrier control means 46 controls the operation of the barrier 102. A flash 48 has an AF auxiliary light projecting function and a flash light control function.

  The exposure control means 40 and the focus control means 42 are controlled using the TTL method, and the system control unit 50 uses the exposure control means 40 and the focus control means based on the calculation result obtained by calculating the captured image data by the image processing unit 24. 42 is controlled.

  The nonvolatile memory 56 is an electrically erasable / recordable memory, and for example, a flash memory or the like is used. The nonvolatile memory 56 stores constants, programs, and the like for operating the system control unit 50. Here, the program is a program for executing various flowcharts described later in the present embodiment.

  Reference numeral 50 denotes a system control unit that controls the entire digital camera 100. By executing the program recorded in the non-volatile memory 56 described above, each process of the present embodiment to be described later is realized. A system memory 52 is an SDRAM. In the system memory 52, constants and variables for operation of the system control unit 50, programs read from the nonvolatile memory 56, and the like are expanded. The system control unit also performs display control by controlling the memory 32, the display unit 28, the eyepiece display unit 29, and the like.

  The system timer 53 is a time measuring unit that measures the time used for various controls and the time of a built-in clock. The mode switch 60, the first release switch 62, the second release switch 64, and the operation unit 70 are operation means for inputting various operation instructions to the system control unit 50. The mode switch 60 switches the operation mode of the system control unit 50 to any one of a still image recording mode, a moving image recording mode, a reproduction mode, and the like. The release switch has two stages, and the first release switch 62 is turned on when a release button provided in the digital camera 100 is operated, so-called half-press (shooting preparation instruction), and generates a first release switch signal SW1. .

  In response to the first release switch signal SW1, shooting preparation operations such as AF (autofocus) processing, AE (automatic exposure) processing, AWB (auto white balance) processing, and EF (flash emission) processing are started. The second release switch 64 is turned on when the operation of the release button is completed, that is, when it is fully pressed (shooting instruction), and generates a second release switch signal SW2. In response to the second release switch signal SW2, the system control unit 50 starts a series of photographing processing operations from reading a signal from the CMOS image sensor 210 to writing image data on the recording medium 105.

  Each operation member of the operation unit 70 is appropriately assigned a function for each scene by selecting and operating various function icons displayed on the display unit 28, and functions as various function buttons. Examples of the function buttons include an end button, a return button, an image advance button, a jump button, a narrowing button, and an attribute change button. For example, when a menu button is pressed, various setting menu screens are displayed on the display unit 28. The user can make various settings intuitively using the menu screen displayed on the display unit 28, the four-way button, and the SET button.

  A power control unit 80 includes a battery detection circuit, a DC-DC converter, a switch circuit that switches a block to be energized, and the like, and detects whether or not a battery is attached, the type of battery, and the remaining battery level. Further, the power control unit 80 controls the DC-DC converter based on the detection result and an instruction from the system control unit 50, and supplies a necessary voltage to each unit including the recording medium 105 for a necessary period.

  A power supply unit 30 includes a primary battery such as an alkaline battery or a lithium battery, a secondary battery such as a NiCd battery, a NiMH battery, or a Li battery, an AC adapter, or the like. Reference numeral 18 denotes an interface with a recording medium 105 such as a memory card or a hard disk. The recording medium 105 is a recording medium such as a memory card, and includes a semiconductor memory, a magnetic disk, or the like.

  FIG. 2 is a system configuration diagram showing an outline of the configuration of a solid-state imaging device, for example, a CMOS image sensor 210 used in the present invention. As shown in FIG. 2, a CMOS image sensor 210 according to this application example is integrated on a pixel array unit 211 formed on a semiconductor substrate (chip) (not shown) and the same semiconductor substrate as the pixel array unit 211. The peripheral circuit section includes a vertical scanning circuit 212, a column processing circuit 213, a horizontal transfer scanning circuit 214, a reference voltage generation circuit 215, an output amplifier 216, a signal processing circuit 217, and a timing control circuit 218. Note that the signal processing circuit 217 can be provided outside the chip.

  In the pixel array unit 211, unit pixels (not shown) including a photoelectric conversion element that photoelectrically converts incident visible light into a charge amount corresponding to the amount of light (hereinafter, may be simply referred to as “pixel”) are arranged in a matrix. Are two-dimensionally arranged. A specific configuration of the unit pixel will be described later.

  In the pixel array unit 211, pixel drive lines DL are formed along the row direction (pixel arrangement direction of the pixel rows) for each row with respect to the matrix-like pixel arrangement, and the vertical signal lines VL are provided for each column. It is formed along the column direction (pixel arrangement direction of the pixel column). In FIG. 2, the pixel drive line DL is illustrated as one line, but the number is not limited to one. One end of the pixel drive line DL is connected to an output end corresponding to each row of the vertical scanning circuit 212.

  The vertical scanning circuit 212 is configured by a shift register, an address decoder, and the like. Although a specific configuration is not illustrated, a readout scanning system for sequentially performing selective scanning in units of rows for a unit pixel that reads a signal; Unnecessary charges are swept out (reset) from the photoelectric conversion elements of the unit pixels in the readout row prior to the readout row by the shutter speed with respect to the readout row in which readout scanning is performed by the readout scanning system. It has a configuration having a sweep scanning system for performing sweep scanning.

  A so-called electronic shutter operation is performed by sweeping (reset) unnecessary charges by the sweep scanning system. Here, the electronic shutter operation refers to an operation in which the photoelectric charge of the photoelectric conversion element is discarded and a new exposure is started (photocharge accumulation is started).

  The signal read by the reading operation by the reading scanning system corresponds to the amount of light incident after the immediately preceding reading operation or electronic shutter operation. The period from the read timing by the previous read operation or the sweep timing by the electronic shutter operation to the read timing by the current read operation is the photocharge accumulation time (exposure time) in the unit pixel.

  A signal (analog electric signal) output from each unit pixel in the pixel row selectively scanned by the vertical scanning circuit 212 is supplied to the column processing circuit 213 through each vertical signal line VL. The column processing circuit 213 is a readout circuit having an A / D conversion function for reading out an analog electric signal output from each pixel 320 of the selected row while converting it into a digital signal for each pixel column of the pixel array unit 211. The detailed circuit configuration and circuit operation of the column processing circuit 213 will be described later.

  The horizontal transfer scanning circuit 214 includes a shift register, an address decoder, and the like, and sequentially selects circuit portions of each column of the column processing circuit 213. By the selective scanning by the horizontal transfer scanning circuit 214, pixel signals digitized for each pixel column by the column processing circuit 213 are sequentially read out to the horizontal signal line HL, and then the signal processing circuit 217 via the output amplifier 216. To be supplied.

  The reference voltage generation circuit 215 is a reference voltage Vslop used when A / D conversion is performed by the column processing circuit 213, more specifically, a reference voltage of a linearly changing slope waveform (RAMP waveform) having a certain slope. Generate Vslop.

  The signal processing circuit 217 performs various signal processing on the pixel signal supplied from the column processing circuit 213 via the horizontal signal line HL and the output amplifier 216 and outputs the result by selective scanning by the horizontal transfer scanning circuit 214. . As specific signal processing in the signal processing circuit 217, for example, black level adjustment, correction of variation for each column, color-related processing, and the like can be considered. However, these signal processes are merely examples.

The timing control circuit 218 includes a vertical scanning circuit 212, a column processing circuit 213, a horizontal transfer scanning circuit 214, a reference voltage generation circuit 215, and the like based on reference signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a master clock MCK. While controlling the timing of the circuit operation, the column processing circuit 213 generates a clock CLK having a fixed period used for A / D conversion.
(Circuit configuration of unit pixel)
FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of the unit pixel 320. As shown in FIG. 3, the unit pixel 320 according to this circuit example includes a photoelectric conversion element, for example, a photodiode 321, and four transistors including a transfer transistor 322, a reset transistor 323, an amplification transistor 324, and a selection transistor 325. It has become.

  Here, as the four transistors 322 to 325, for example, N-channel MOS transistors are used. However, the combination of conductivity types of the transfer transistor 322, the reset transistor 323, the amplification transistor 324, and the selection transistor 325 illustrated here is merely an example, and is not limited to these combinations.

  For the unit pixel 320, as the pixel drive line DL, for example, three drive wirings of a transfer line DL1, a reset line DL2, and a selection line DL3 are provided in common for each pixel in the same pixel row. One end of each of the transfer line DL1, the reset line DL2, and the selection line DL3 is connected to each output terminal corresponding to each pixel row of the vertical scanning circuit 212 shown in FIG.

  The photodiode 321 has an anode electrode connected to a negative power source (for example, ground), and photoelectrically converts received light into photocharge (here, photoelectrons) having a charge amount corresponding to the light amount. The cathode electrode of the photodiode 321 is electrically connected to the gate electrode of the amplification transistor 324 through the transfer transistor 322. A node 326 electrically connected to the gate electrode of the amplification transistor 324 is referred to as an FD (floating diffusion) portion.

  The transfer transistor 322 is connected between the cathode electrode of the photodiode 321 and the FD unit 326, and transfers a transfer pulse Vt at which a high level (for example, power supply potential VD) is active (hereinafter referred to as “High active”). By being applied to the gate electrode via the line DL1, the gate electrode is turned on, and the photoelectric charge photoelectrically converted by the photodiode 321 is transferred to the FD portion 326.

  In the reset transistor 323, the drain electrode is connected to the power supply line PL of the power supply potential VD, the source electrode is connected to the FD unit 326, and a high active reset pulse Vr is applied to the gate electrode via the reset line DL2. Thus, prior to the transfer of the signal charge from the photodiode 321 to the FD unit 326, the FD unit 326 is reset by discarding the charge of the FD unit 326 to the power supply line PL.

  The amplification transistor 324 has a gate electrode connected to the FD unit 326 and a drain electrode connected to the power supply line PL, and outputs the potential of the FD unit 326 after being reset by the reset transistor 323 as a reset signal (reset level) Vreset. The potential of the FD unit 326 after the transfer of the signal charge by the transfer transistor 322 is output as a light accumulation signal (signal level) Vsig.

  In the selection transistor 325, for example, the drain electrode is connected to the source electrode of the amplification transistor 324, the source electrode is connected to the vertical signal line VL, and a high active selection pulse Vs is applied to the gate electrode via the selection line DL3. The unit pixel 320 is turned on and the signal output from the amplification transistor 324 is relayed to the vertical signal line VL. Note that the selection transistor 325 may have a circuit configuration connected between the power supply line PL and the drain electrode of the amplification transistor 24.

  The unit pixel 320 having the above configuration includes an amplifying transistor 324 that converts charge into an electric signal, and a current source 319 connected between the vertical signal line VL and a reference potential node (for example, ground) for each column. Thereby, the electric charge accumulated in the pixel is read out to the vertical signal line VL as an electric signal.

  The unit pixel 320 is not limited to the pixel configuration including the four transistors 322 to 325 having the above-described configuration. For example, the pixel configuration including the three transistors that serve as the amplification transistor 324 and the selection transistor 325 is used. The configuration of the pixel circuit is not limited. In other words, any structure may be used as long as the charge accumulated in the pixel can be output as an electric signal to the common vertical signal line VL for each column.

(Column processing circuit)
Returning to FIG. 2, a specific circuit configuration of the column processing circuit 213 having the A / D conversion function will be described. As shown in FIG. 2, the column processing circuit 213 has a circuit configuration including a comparator 431, a counter 432, and a latch 433 arranged for each pixel column of the pixel array unit 211.

  The comparator 431 compares both inputs with the analog electric signal Vsl read from the unit pixel 320 to the vertical signal line VL as one input and the reference voltage Vslop having a ramp waveform generated by the reference voltage generation circuit 215 as the other input. The output is inverted at the timing when the analog electric signal Vsl and the reference voltage Vslop intersect. Specifically, for example, the comparator 431 outputs “H” level when the analog electric signal Vsl is lower than the reference voltage Vslop, and “L” at the timing when the analog electric signal Vsl and the reference voltage Vslop intersect. Invert to level. Note that the reference voltage generation circuit 215 starts generating the reference voltage Vslop having a ramp waveform under the timing control by the timing control circuit 218.

  Under the timing control by the timing control circuit 218, the counter 432 generates a reference voltage Vslop, and at the same time, starts a count operation in synchronization with a clock CLK having a fixed period supplied from the timing control circuit 218. . The counter 432 receives the inversion of the output of the comparator 431 and stops the counting operation at the timing when the analog electric signal Vsl and the reference voltage Vslop intersect.

  As an example, a gate circuit 434 is provided on the input side of the counter 432 as shown in FIG. The gate circuit 434 opens the gate while the output of the comparator 431 is at the “H” level, and supplies the clock CLK supplied from the timing control circuit 18 to the counter 432. Accordingly, the counter 432 performs a counting operation in synchronization with the clock CLK over a period from the generation timing of the reference voltage Vslop to the timing at which the analog electrical signal Vsl and the reference voltage Vslop intersect.

  The counter 432 converts the analog electric signal Vsl into a digital signal by changing the count value while having a one-to-one correspondence with a potential having the reference voltage Vslop. That is, the change in the reference voltage Vslop is for converting the change in voltage into a change in time, and the time is counted by the counter 432 in synchronization with the clock CLK of a certain period, thereby converting it into a digital value.

  As is clear from the above, the comparator 431 compares the analog electric signal Vsl with the reference voltage Vslop having a ramp waveform, thereby obtaining a magnitude (time information / time) corresponding to the magnitude of the analog electric signal Vsl. The comparison result with the pulse width is output. Further, the counter 432 performs a counting operation in synchronization with a clock CLK having a constant cycle over a period from the timing at which the reference voltage Vslop having the inclined waveform is generated to the timing at which the analog electric signal Vsl and the reference voltage Vslop are crossed. Thus, the count value is output as a digital signal corresponding to the magnitude of the analog electric signal Vsl.

  That is, the comparator 431 and the counter 432 constitute an A / D converter (A / D converter) that converts the analog electric signal Vsl into a digital signal. A count value of the counter 432, that is, a digital value corresponding to the magnitude of the analog electric signal Vsl is held in the latch 433 under timing control by the timing control circuit 218. The digital values for one row held in the latch 433 are sequentially read out to the horizontal signal line HL by selective scanning by the horizontal transfer scanning circuit 214 and supplied to the signal processing circuit 217 via the output amplifier 216.

  In the column processing circuit 213 configured as described above, the present embodiment is characterized in that the counter 432 has the following two counting functions. The first of the two counting functions is synchronized with the clock CLK over a period from the generation timing of the reference voltage Vslop until the output of the comparator 431 is inverted (the analog electric signal Vsl and the reference voltage Vslop intersect). This is a first count function (hereinafter referred to as “first count”) that performs a count operation.

  The second of the two count functions is a second count function in which the counter 432 performs a count operation in synchronization with the clock CLK from the timing when the output of the comparator 431 is inverted (hereinafter referred to as “post count”). It is. Specifically, for example, in the configuration illustrated in FIG. 4, the gate circuit 434 is opened by receiving the inversion of the output of the comparator 431, and the supply of the clock CLK to the counter 432 is started. The count operation is performed in synchronization with the clock CLK from the timing at which the output of is inverted.

  For example, in the case of the previous count, the count value of the counter 432 is initialized to zero before the count operation is started, and at the same time when the clock CLK is transmitted by the gate circuit 434, the count operation is started by the up-count. Then, at the timing when the output of the comparator 431 is inverted, the counter 432 stops the count operation and performs A / D conversion by holding the count value at that time.

  FIG. 5 shows an example of the operation of the counter 432. In the example of FIG. 5, the output of the comparator 431 is inverted at the 300th clock, and the count value at that time is held. Next, in the case of post-counting, the count value of the counter 432 is initialized to all 1 before the count operation starts, that is, to 1023 if the number of bits of the counter 432 is 10 bits. Then, the clock CLK starts to be supplied from the timing control circuit 218, but the counter 432 stops the counting operation because the gate circuit 434 is initially in the gate closed state.

  Thereafter, in response to the inversion of the output of the comparator 431, the gate circuit 434 enters the gate open state and starts transmission of the clock CLK to the counter 432, so that the counter 432 starts counting in synchronization with the clock CLK. However, at this time, the counter 432 counts down. Since the count operation is stopped when the clock CLK reaches 1023 clocks, the count value of the counter 132 becomes 300.

  In this embodiment, both the previous count and the subsequent count are used. However, the configuration of the count function is not limited to this. For example, in the post count, it is not always necessary to make the count down, and by performing the process of subtracting the count value from the maximum value Max in the subsequent processing block (for example, the signal processing circuit 217), A digital value similar to that in the case of down-counting can be obtained.

  As an example of the case of up-counting, taking the case of FIG. 5 as an example, when the post-count is set to the count-up method, the count value of the counter 432 becomes 723, and the digital value is obtained by performing the subtraction process of 1023-723 in the subsequent stage. 300 can be obtained.

  However, when the down-counting is performed in the post-counting, the count value when the counting operation is stopped can be used as it is, and there is no need to perform subtraction processing in a later processing block as in the case of up-counting. There is an advantage that processing in the processing block can be reduced.

  The point of the present embodiment is that a counter having a function of switching both the pre-count and post-count is used as the A / D conversion counter 432. Specifically, as shown in FIG. 6, the clock CLK input to the counter 432 is masked by the output of the comparator 431, but the output of the comparator 431 is switched between normal rotation and inversion by a switching circuit (SEL) 635. Thus, the drive switching between the first count and the second count is performed.

  In the circuit configuration of FIG. 6, in the gate circuit 434 and the switching circuit 635, the system control unit 50 appropriately switches the function of the counter 432 between the pre-count and the post-count according to the imaging mode. The circuit configuration itself of the control unit is not limited to this, and any configuration having a function of switching between the first count and the second count may be used.

  FIG. 7 shows the operation of the counter 432 when the signal input to the input range of the A / D conversion unit including the comparator 431 and the counter 432 is low. In the figure, the count operation written as drive A performs the pre-count operation shown in FIG. 5, and the count operation written as drive B performs the post-count operation shown in FIG.

  When the signal level is lower than the predetermined reference level, as shown in FIG. 7, the current consumption is small in the drive A which is the previous count. On the other hand, when the signal level is lower than a predetermined reference level, in the case of drive B, which is a post-count, the count operation is performed after the output of the comparator 431 is inverted, so that the count operation period is long. Current consumption increases.

  FIG. 8 shows the operation of the counter 432 when the signal input to the input range of the A / D converter is high. In this case, contrary to the case of FIG. 7, the period of the count operation until the output of the comparator 431 is inverted becomes longer, so that the current consumption of the drive A is greater than that of the drive B.

As described above, in the case of the first count, the current consumption of the counter 432 decreases in a relatively dark scene, and the current consumption of the counter 432 increases in a relatively bright scene. Conversely, in the case of the post-count, the current consumption of the counter 432 increases in a relatively dark scene, and the current consumption of the counter 432 decreases in a relatively bright scene.
[Characteristics of this embodiment]
The first embodiment of the present invention will be described below. In the first embodiment, an operation sequence in the case of using blacking processing will be described. The blacking process is a method for correcting fixed pattern noise as shown in FIG. After performing normal shooting, shooting is performed again in a light-shielded state. Then, the fixed pattern noise is removed by subtracting an image (black image) captured in a light-shielded state from the captured image.
A black image taken in a light-shielded state is always a dark image. For this reason, as shown in FIG. 10, the current count can be reduced without being influenced by the signal level acquired in the past and without performing wasteful processing by setting the count one frame ahead.

  Hereinafter, a flowchart of the blacking process will be described with reference to FIG. In S1101, exposure is performed at the timing when the shutter button 64 is pressed. In S1102, after the exposure is completed, the mechanical shutter 101 is closed to prevent unnecessary light from entering during charge transfer. In S1103, the signal level is read from the previous shooting frame used in the exposure time calculation or the like. In S1104, it is determined whether or not the signal level exceeds the reference level. If the signal level exceeds the reference level, reading is performed after A / D conversion is performed with a post-count as in S1105. If not, reading is performed after A / D conversion is performed with the previous count as in S1106.

  In step S1107, exposure is performed with the mechanical shutter closed to capture a black image. In step S1108, the system control unit 50 performs A / D conversion and reading with the previous count. Since the black image of the blacking process always becomes a dark image, the current consumption of the counter 432 can be reduced by performing the reading with the previous count. In step S1109, the black image is subtracted from the normal captured image to remove fixed pattern noise. In S1110, the RAW image is converted into a JPEG file, and the black-drawing shooting is completed.

  The second embodiment of the present invention will be described below. In the second embodiment, an operation sequence at high ISO sensitivity will be described. In the second embodiment, digital gain by bit shift is applied in order to increase ISO sensitivity. FIG. 12 shows a block diagram of the image processing unit 24. The digitized image signal from the CMOS image sensor 210 is output to the image processing unit 24. The image processing unit 24 includes an image interpolation processing unit 1201, a color conversion processing unit 1202, a digital gain 1203, and an image compression unit 1204. The digital gain 1203 is gained by bit shift.

  For example, when the signal level is doubled, that is, multiplied by 6 dB with the digital gain 1203, a 1-digit bit shift is performed to the left, and 0 is input to the least significant bit. When the user or camera system control unit 50 sets a high ISO sensitivity, it is expected that the luminance of the subject is low. Further, when the set digital gain of the high ISO sensitivity is 6 dB or more, it is predicted that the signal level output from the solid-state imaging device is less than half of the full range. In the case of this embodiment, since the full range is 10 bits 1023 counts, the count value is likely to be 511 or less.

  In such a case, the current consumption of the counter 432 can be reduced by performing reading using the previous count. Therefore, when a digital gain by bit shift is applied by 6 dB or more, A / D conversion using the first count is performed. By doing so, the current consumption of the counter 432 can be reduced without performing useless processing without being influenced by the brightness of the previous captured image.

  Hereinafter, a flowchart at the time of high ISO sensitivity still image shooting will be described with reference to FIG. In step S1301, exposure is performed when the shutter button 64 is pressed. In step S1302, the mechanical shutter 101 is closed after exposure is completed in order to prevent unnecessary light from entering during charge transfer. In step S1303, the value of the digital gain for actual shooting is read out. In S1304, it is determined whether or not the digital gain exceeds 6 dB. If the digital gain exceeds 6 dB, reading is performed after A / D conversion is performed using the previous count as in S1305. If not exceeded, A / D conversion is performed after selecting either the pre-count or the post-count according to the brightness as in S1306.

  In the case of still image shooting, the digital gain is determined after the shutter button 64 is pressed. Therefore, there is no difference in operation between the manual mode in which the user directly sets the ISO sensitivity and the auto mode in which the system control unit 50 automatically determines the ISO sensitivity. In S1307, the RAW image is converted into a JPEG file, and still image shooting is completed.

  Hereinafter, a flowchart at the time of high ISO sensitivity moving image shooting will be described with reference to FIG. In the case of moving image shooting, the digital gain is determined every frame. After the moving image mode is set by the mode changeover switch 60, moving image shooting is started when the shutter button 64 is pressed.

  In step S1401, the digital gain value is read before performing exposure. In S1402, it is determined whether or not the digital gain exceeds 6 dB. If the digital gain exceeds 6 dB, after exposure, after the exposure, A / D conversion is performed using the previous count as in S1403. If it does not exceed, after exposure, after the exposure, the pre-count or post-count is selected according to the brightness, and A / D conversion is performed for reading. In step S1405, the acquisition of one frame image constituting the moving image is terminated.

  In S1406, it is determined whether or not the moving image shooting is completed due to the pressing of the shutter button 64. If the moving image shooting has not ended, the process returns to S1401 to acquire the next one frame image. If movie shooting has been completed, the image group is compressed into a movie file such as MPEG as in S1307, and movie shooting is completed.

  In the present embodiment, the system control unit 50 prohibits post-counting according to the imaging mode. By doing so, the power consumption generated by the counter 432 can be reduced without being influenced by the signal level acquired in the past.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

210 CMOS image sensor 211 Pixel array unit 212 Vertical scanning circuit 213 Column processing circuit 214 Horizontal transfer scanning circuit 215 Reference voltage generation circuit 216 Output amplifier 217 Signal processing circuit 218 Timing control circuit 219 Current source 320 Unit pixel 321 Photodiode 322 Transfer transistor 323 Reset transistor 324 Amplification transistor 325 Select transistor 431 Comparator 432 Counter 433 Latch 434 Gate circuit 635 Switching circuit

Claims (5)

A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A column processing circuit having an A / D conversion unit that converts an analog signal output from the unit pixel into a digital signal in units of pixel columns of the pixel array unit;
The A / D converter compares the analog signal with an inclined reference voltage,
A comparator whose output is inverted at the timing when the analog signal and the reference voltage cross each other;
A first counting function that performs a counting operation from a timing at which the reference voltage is generated to a timing at which the output of the comparator is inverted in synchronization with a clock having a fixed period;
A counter having a second counting function for performing a counting operation after the timing at which the output of the comparator is inverted;
A system control unit that controls the entire imaging apparatus,
The solid-state imaging device, wherein the system control unit prohibits either the first count function or the second count function according to an imaging mode. A light shielding device for shielding the solid-state imaging device;
When shooting with the light-shielding device in a light-shielded state, the system control unit
The solid-state imaging device according to claim 1, wherein the second counting function is prohibited. An amplifier circuit for amplifying an output signal of the solid-state imaging device;
When the gain of the amplifier circuit exceeds a certain threshold, the system control unit,
The solid-state imaging device according to claim 1, wherein the second counting function is prohibited. A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A column processing circuit having an A / D conversion unit that converts an analog signal output from the unit pixel into a digital signal in units of pixel columns of the pixel array unit;
The A / D converter compares the analog signal with an inclined reference voltage,
A comparator whose output is inverted at the timing when the analog signal and the reference voltage cross each other;
A first counting function that performs a counting operation from a timing at which the reference voltage is generated to a timing at which the output of the comparator is inverted in synchronization with a clock having a fixed period;
A counter having a second counting function for performing a counting operation after the timing at which the output of the comparator is inverted;
A system control unit that controls the entire imaging apparatus,
The method for driving a solid-state imaging device, wherein the system control unit prohibits either the first count function or the second count function according to an imaging mode. A pixel array unit in which unit pixels including photoelectric conversion elements are arranged in a matrix;
A column processing circuit having an A / D conversion unit that converts an analog signal output from the unit pixel into a digital signal in units of pixel columns of the pixel array unit;
The A / D converter compares the analog signal with an inclined reference voltage,
A comparator whose output is inverted at the timing when the analog signal and the reference voltage cross each other;
A first counting function that performs a counting operation from a timing at which the reference voltage is generated to a timing at which the output of the comparator is inverted in synchronization with a clock having a fixed period;
A counter having a second counting function for performing a counting operation after the timing at which the output of the comparator is inverted;
A system control unit that controls the entire imaging apparatus,
The electronic apparatus, wherein the system control unit prohibits either the first count function or the second count function according to an imaging mode.