JP2018061089A - Drive circuit, optical print head and image formation apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make reduction of power consumption compatible with high accuracy detection of a defective part.SOLUTION: In the print head 33 of an image formation apparatus 1, the output buffer circuit 64 of a driver IC54 is provided with a PMOS transistor 85 having reduced current drive capability, in addition to a NMOS transistor 84 on the pull-up side. Consequently, when an output buffer circuit 64 is operated at high speed, the driver IC54 keeps the output voltage at an intermediate voltage Vm (about 3.5 (V)), thus reducing power consumption and EMI noise. Meanwhile, during quiescent time when high level signals are outputted continuously from the output buffer circuit 64, the driver IC54 raises the output voltage to the power supply voltage VDD (about 5(V)) by taking a raise time TU, and keeps the through current Is2 of an input buffer circuit 62 substantially at 0 (A), thus executing IDDq test accurately.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a drive circuit, an optical print head, and an image forming apparatus, and is suitable for application to, for example, an electrophotographic printer (hereinafter simply referred to as a printer).

  As a conventional printer, an electrostatic latent image is formed on the surface of a photosensitive drum by selectively irradiating light from an optical print head in which a plurality of light emitting elements such as LEDs (Light Emitting Diodes) are arranged and arranged in an exposure apparatus. The image is printed widely by developing the toner image by forming a toner image on the electrostatic latent image.

  In this exposure apparatus, for example, a plurality of light emitting elements (hereinafter also referred to as driven elements) and a driver IC (Integrated Circuit) provided with a plurality of element driving units for driving the respective light emitting elements include a predetermined circuit board. Above, they are attached in a state of being aligned along the main scanning direction.

  Some printers have also been proposed in which a plurality of driver ICs are cascade-connected in an exposure apparatus (see, for example, Patent Document 1). In such a printer, a serial type data signal representing a part of an image is supplied from a predetermined control circuit to the uppermost driver IC, and sequentially supplied from the upper driver IC to the lower driver IC. A data signal can be efficiently supplied to each driver IC.

Japanese Unexamined Patent Publication No. 2000-108407 (FIG. 1 etc.)

  In general, a printer tends to increase the amount of data with higher resolution and the like, but is required to shorten the printing time. For this reason, in the printer, it is conceivable to shorten the time required to transfer the data signal by increasing the operation speed of the driver IC. In addition, printers are required to reduce power consumption in the same way as general electric devices from the viewpoint of environmental protection.

  The driver IC is configured as, for example, a complementary metal oxide semiconductor (CMOS) circuit. In general, in a CMOS circuit, it is known that the power consumption increases substantially in proportion to the operation speed and increases in proportion to the square of the power supply voltage. That is, the driver IC increases the power consumption when the operating speed is increased, and the temperature rises accordingly. Therefore, in the driver IC, it is conceivable to reduce power consumption by reducing the power supply voltage.

  On the other hand, a manufacturing failure may occur in an optical print head of a printer due to factors such as a shift in the mounting position of a driver IC with respect to a circuit board during manufacture. When such a manufacturing defect occurs, a leakage current of about several μ [A] may occur in the optical print head. Thus, the optical print head can determine the presence or absence of manufacturing defects by detecting the presence or absence of this leakage current.

  However, the driver IC may have a push-pull circuit incorporated in an input buffer or the like to which a data signal is input from the upper stage side. In this push-pull circuit, through-current hardly occurs when the input voltage is relatively high, for example, 5 [V] due to the nature of the MOS transistor, but it is relatively low, for example, 3.3 [V]. A through current of about several m [A], that is, sufficiently larger than the leakage current flows. In this case, in the driver IC, the leak current is buried in the through current, and it is extremely difficult to detect the presence or absence of the leak current.

  That is, in the printer, if the power supply voltage of the driver IC is lowered, the power consumption can be reduced, but on the other hand, there is a possibility that a new problem may occur that it is impossible to determine whether there is a manufacturing defect using detection of leakage current.

  The present invention has been made in consideration of the above points, and intends to propose a drive circuit, an optical print head, and an image forming apparatus that can achieve both reduction in power consumption and high-precision detection of defective portions. .

  In order to solve such a problem, in the driving circuit of the present invention, an input buffer to which a data signal is input from the upper side, an element driving unit for driving a driven element based on the data signal, and a data signal to be output to the lower side And an output buffer for receiving the power supply voltage. The output buffer receives first power supply voltage and sets a high level of the data signal. The third switching means sets the low level of the data signal. The first switching means has a high-level output voltage lower than the power supply voltage, and the second switching means has a smaller current drive capability than the first switching means.

  Further, the optical print head of the present invention includes a drive circuit group in which a plurality of the drive circuits described above are cascade-connected, and the driven element is a light emitting element that emits light.

  Furthermore, in the image forming apparatus of the present invention, an image forming unit that generates an electrostatic latent image by exposing the photoreceptor with the optical print head described above, and forms an image based on the electrostatic latent image with a developer; A fixing unit for fixing the image on a predetermined medium is provided.

  According to the present invention, when an input data signal is switched to a high level in an output buffer of a drive circuit, a data signal having an output voltage lower than the power supply voltage is first output by the first switching means, and a sufficient time thereafter. When the time has elapsed, the output voltage of the data signal can be increased to the same level as the power supply voltage by the second switching means. Thus, according to the present invention, when a data signal is supplied to an inverter circuit composed of complementary elements on the lower stage side, the data signal input to the output buffer becomes a high level or a low level in a relatively short time. During the switching operation, the output voltage can be suppressed and power consumption and EMI noise can be reduced. On the other hand, at the time of a predetermined inspection, the present invention increases the output voltage by maintaining the input data signal at a high level, and suppresses the through current flowing in the input buffer in the drive circuit in the subsequent stage to almost 0 [A]. The presence or absence of leakage current can be detected with high accuracy.

  According to the present invention, it is possible to realize a drive circuit, an optical print head, and an image forming apparatus that can achieve both reduction in power consumption and highly accurate detection of a defective portion.

1 is a schematic diagram illustrating an overall configuration of an image forming apparatus. It is a basic diagram which shows the structure of an image forming unit. 1 is a schematic diagram illustrating a block configuration of an image forming apparatus. It is a basic diagram which shows the structure of a print head. It is a basic diagram which shows the circuit structure of a print head. It is a basic diagram which shows the circuit structure of the driver IC by 1st Embodiment. 1 is a schematic diagram showing a configuration of an output buffer circuit according to a first embodiment. It is a basic diagram which shows the waveform of each signal in a printing process. It is a basic diagram which shows the change of the voltage in the output buffer circuit by 1st Embodiment, and an electric current. It is a basic diagram which shows generation | occurrence | production of the through current in an input buffer circuit. It is a basic diagram which shows the structure of a general output buffer circuit. It is a basic diagram which shows the change of the voltage and electric current in a common output buffer circuit. It is a basic diagram which shows the structure of a PMOS transistor. It is a basic diagram which shows the structure of the output buffer circuit by 2nd Embodiment. It is a basic diagram which shows the circuit structure of the driver IC by 3rd Embodiment. It is a basic diagram which shows the structure of the output buffer circuit by 3rd Embodiment. It is a basic diagram which shows the circuit structure of the control voltage generation part in the 3rd Embodiment, and an element drive part. It is a basic diagram which shows the change of the voltage in the output buffer circuit by 3rd Embodiment, and an electric current. It is a basic diagram which shows the structure of the output buffer circuit by other embodiment.

  Hereinafter, modes for carrying out the invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[1. First Embodiment]
[1-1. Configuration of image forming apparatus]
As shown in FIG. 1, the image forming apparatus 1 according to the first embodiment is a so-called MFP (Multi Function Peripheral), and has a printer function for forming (that is, printing) an image on a sheet as a medium. It has a function as an image scanner for reading an image and a communication function. Therefore, the image forming apparatus 1 can operate as a printer, a copying machine (copying machine), a facsimile machine or the like by combining these functions. When the image forming apparatus 1 functions as a printer, a desired color image can be printed on a sheet P having a size such as A3 size or A4 size.

  In the image forming apparatus 1, various components are arranged inside a printer housing 2 formed in a substantially box shape. In the following description, the right end portion in FIG. 1 is defined as the front surface of the image forming apparatus 1, and the vertical direction, the horizontal direction, and the front-rear direction when viewed from the front are defined and described.

  The image forming apparatus 1 is configured to perform overall control by the control unit 3. The control unit 3 is connected to a host device (not shown) such as a computer device wirelessly or by wire. The control unit 3 executes print processing for forming a print image on the surface of the paper P when image data representing an image to be printed is given from the host device and printing of the image data is instructed.

  A paper storage cassette 4 that stores paper P is provided at the bottom of the printer housing 2. A paper feeding unit 5 is provided in front of and above the paper storage cassette 4. The paper feed unit 5 includes a hopping roller 6 disposed on the upper front side of the paper storage cassette 4, a conveyance guide 7 that guides the paper P upward along the conveyance path U, and registration rollers 8 that face each other across the conveyance path U. And a pinch roller 9 and the like.

  The paper feeding unit 5 picks up and conveys the paper P stored in the paper storage cassette 4 while separating them one by one by appropriately rotating each roller based on the control of the control unit 3. The guide 7 is advanced forward and upward along the conveyance path U, and is then folded back and upward to come into contact with the registration roller 8 and the pinch roller 9. The rotation of the registration roller 8 is appropriately suppressed. By applying a frictional force to the paper P between the registration roller 8 and the pinch roller 9, a so-called skew is performed in which the side of the paper P is inclined with respect to the traveling direction. Correct and make the top and bottom edges side to side, then send it back.

  On the rear side of the registration roller 8 and the pinch roller 9, a conveyance path U is formed substantially along the front-rear direction, and the middle conveyance unit 10 is disposed below the conveyance path U. The middle conveyance unit 10 includes a conveyance belt 14 formed of an endless belt around a front roller 11 disposed on the front side, a rear roller 12 disposed on the rear side, and a lower roller 13 disposed on the lower side. It has been configured. In addition, an adsorption roller 15 is provided on the upper side of the front roller 11 at a position opposed to the conveyance belt 14.

  When a driving force is transmitted to a rear roller 12 from a predetermined belt drive motor (not shown), the middle conveyance unit 10 drives the conveyance belt 14 by rotating the rear roller 12 in the arrow R2 direction. Let Thereby, the conveyor belt 14 travels the upper part along the conveyor path U, that is, the part stretched between the front roller 11 and the rear roller 12 in the backward direction. At this time, when the sheet P is delivered from the sheet feeding unit 5, the middle conveying unit 10 holds the sheet P together with the conveying belt 14 between the suction roller 15 and the front roller 11, and places the sheet P on the upper side of the conveying belt 14. In this state, the paper P is advanced backward as the conveyor belt 14 travels.

  Four image forming units 16C, 16M, 16Y and 16K are arranged in order from the rear side to the front side on the upper side of the middle conveyance unit 10 and on the opposite side of the middle conveyance unit 10 across the conveyance path U. ing. The image forming units 16C, 16M, 16Y, and 16K (hereinafter collectively referred to as the image forming unit 16) correspond to cyan (C), magenta (M), yellow (Y), and black (K), respectively. However, only the colors are different, and both are configured similarly.

  As shown in the schematic side view of FIG. 2, the image forming unit 16 includes an image forming unit 31, a toner cartridge 32, and a print head 33, and a transfer roller 17 disposed below the image forming unit 31. The conveying belt 14 is sandwiched between the two. Incidentally, the image forming unit 16 and each component constituting the image forming unit 16 have a sufficient length in the left-right direction according to the length in the left-right direction of the paper P. For this reason, many parts are relatively long in the left-right direction with respect to the length in the front-rear direction and the up-down direction, and are formed in an elongated shape along the left-right direction.

  The toner cartridge 32 contains toner as a developer, is disposed above the image forming unit 31, and is attached above the image forming unit 31. The toner cartridge 32 supplies the stored toner to the toner storage unit 34 of the image forming unit 31. In addition to the toner accommodating portion 34, the image forming portion 31 incorporates a supply roller 35, a developing roller 36, a regulating blade 37, a photosensitive drum 38, and a charging roller 39.

  The supply roller 35 is formed in a cylindrical shape having a central axis along the left-right direction, and an elastic layer made of a conductive urethane rubber foam or the like is formed on the peripheral side surface thereof. The developing roller 36 is formed in a cylindrical shape having a central axis along the left-right direction, and an elastic layer having elasticity, a surface layer having conductivity, and the like are formed on the peripheral side surface thereof. The regulating blade 37 is made of, for example, a stainless steel plate having a predetermined thickness, and a part thereof is brought into contact with the peripheral side surface of the developing roller 36 in a slightly elastically deformed state. The photosensitive drum 38 is formed in a cylindrical shape with the central axis extending in the left-right direction, and a thin-film charge generation layer and a charge transport layer are sequentially formed on the peripheral side surface so that the photosensitive drum 38 can be charged. . The charging roller 39 is formed in a cylindrical shape with the central axis extending in the left-right direction, and a conductive elastic body is coated on the peripheral side surface thereof, and the peripheral side surface is brought into contact with the peripheral side surface of the photosensitive drum 38. ing.

  Further, a static elimination light source 20 is provided at a position on the front lower side of the image forming unit 31 and upstream of the contact portion between the photosensitive drum 38 and the conveyance belt 14. The static elimination light source 20 is adapted to remove charged static electricity by irradiating the photosensitive drum 38 with predetermined light.

  The image forming unit 31 is supplied with a driving force from a motor (not shown) to rotate the supply roller 35, the developing roller 36, and the charging roller 39 in the direction indicated by the arrow R2 (counterclockwise in the drawing), and the photosensitive member. The drum 38 is rotated in the direction of arrow R1 (clockwise in the figure). Further, the image forming unit 31 applies a predetermined bias voltage to the supply roller 35, the developing roller 36, the regulating blade 37, and the charging roller 39 to charge each of them.

  The supply roller 35 attaches the toner in the toner accommodating portion 34 to the peripheral side surface by charging, and causes the toner to adhere to the peripheral side surface of the developing roller 36 by rotation. The developing roller 36 abuts the peripheral side surface against the peripheral side surface of the photosensitive drum 38 after excess toner is removed from the peripheral side surface by the regulating blade 37. At this time, the toner adhering to the peripheral side surface of the developing roller 36 is charged to a negative potential.

  On the other hand, the charging roller 39 is in contact with the photosensitive drum 38 in a charged state, thereby uniformly charging the peripheral side surface of the photosensitive drum 38 negatively. In the print head 33, light emitting elements made up of a large number of LEDs (Light Emitting Diodes) are linearly arranged along the left-right direction which is the main scanning direction. The print head 33 emits light with a light emission pattern based on an image data signal supplied from the control unit 3 (FIG. 1) (details will be described later), thereby exposing the photosensitive drum 38 and emitting light. Only raise the potential. Thereby, an electrostatic latent image is formed on the peripheral side surface of the photosensitive drum 38 in the vicinity of the upper end thereof.

  Subsequently, the photosensitive drum 38 is rotated in the direction of the arrow R <b> 1 to bring the portion where the electrostatic latent image is formed into contact with the developing roller 36. As a result, toner adheres to the peripheral side surface of the photosensitive drum 38 based on the electrostatic latent image, and the toner image based on the image data is developed.

  The transfer roller 17 is positioned directly below the photosensitive drum 38, and the upper portion of the conveyance belt 14 is sandwiched between the vicinity of the upper end of the peripheral side surface and the vicinity of the lower end of the photosensitive drum 38. A predetermined bias voltage is applied to the transfer roller 17 and a driving force is supplied from a motor (not shown) to rotate in the direction of the arrow R2. Thereby, the image forming unit 16 can transfer the toner image developed on the peripheral side surface of the photosensitive drum 38 to the paper P when the paper P is being transported along the transport path U.

  In this way, each image forming unit 16 advances backward while sequentially transferring and superimposing the toner images of the respective colors on the paper P conveyed from the front along the conveyance path U.

  A fixing unit 21 is provided in the vicinity of the rear end of the middle conveyance unit 10. The fixing unit 21 includes a heating roller 21 </ b> A and a pressure roller 21 </ b> B that are arranged to face each other with the conveyance path U therebetween. The heating roller 21A is formed in a cylindrical shape with a central axis directed in the left-right direction, and a heater is provided inside. The pressure roller 21B is formed in a cylindrical shape similar to the heating roller 21A, and presses the upper surface against the lower surface of the heating roller 21A with a predetermined pressing force.

  The fixing unit 21 heats the heating roller 21A and rotates the heating roller 21A and the pressure roller 21B in predetermined directions based on the control of the control unit 3, respectively. As a result, the fixing unit 21 applies heat and pressure to the paper P received from the middle conveyance unit 10, that is, the paper P on which the four color toner images are transferred, to fix the toner, and further to the rear.

  A paper discharge unit 22 is disposed behind the fixing unit 21. The paper discharge unit 22 is configured by a combination of a guide for guiding the paper P, a plurality of transport rollers, and the like, like the paper supply unit 5. The paper discharge unit 22 rotates the respective conveyance rollers appropriately according to the control of the control unit 3, thereby conveying the paper P delivered from the fixing unit 21 rearward and upward and then folding it forward. It discharges to the discharge tray 2T formed on the upper surface.

  Further, paper sensors 25, 26, 27 and 28 for detecting the paper P are appropriately provided at a plurality of locations along the transport path U in the printer housing 2. The sheet sensor 25 and the like detect the presence or absence of the sheet P in the transport path U, and notify the control unit 3 of the obtained detection result. In response to this, the control unit 3 appropriately controls the rotation of each conveyance roller, the travel of the conveyance belt 14 in the middle conveyance unit 10, and the like.

  Next, the block configuration of the image forming apparatus 1 will be described with reference to FIG. The control unit 3 receives a control signal S1 from a host device (not shown) such as a computer device, and starts a printing operation based on a print instruction included in the control signal S1.

  Specifically, the control unit 3 first determines whether or not the fixing unit 21 is within a predetermined temperature range by a fixing device temperature sensor 21C (FIG. 3) provided in the fixing unit 21 (FIG. 1). To do. At this time, if the temperature of the fixing unit 21 is less than this temperature range, the control unit 3 energizes and heats the heating roller 21A (FIG. 1) to adjust the temperature of the fixing unit 21 to this temperature range.

  Further, the control unit 3 rotates the development / transfer process motor 44 via the driver 43 and operates the high-voltage power supply 41 for charging, whereby each roller such as the charging roller 39 in the image forming unit 16 (FIG. 2) is operated. Rotate and charge.

  Further, the control unit 3 rotates the paper feed motor 46 via the driver 45 to rotate the hopping roller 6 and the like of the paper feed unit 5 (FIG. 1). It is sent out while being separated and conveyed along the conveyance path U. Further, the control unit 3 recognizes the position of the paper P, the state of conveyance, and the like based on the detection result obtained from the paper sensors 25 to 28 and adjusts the conveyance speed.

  On the other hand, the image processing unit 48 performs predetermined image processing on the image data supplied from the host device to generate image forming data for each page. Based on the detection result by the paper sensor 26, the control unit 3 sends a timing signal S3 to the image processing unit 48 when the paper P reaches a printable position, for example, immediately before the image forming apparatus 16K (FIG. 1). Send. The timing signal S3 includes a main scanning synchronization signal, a sub scanning synchronization signal, and the like.

  In response to this, the image processing unit 48 generates a video signal S2 obtained by separating the generated image forming data for each line, and transmits the video signal S2 to the control unit 3. The control unit 3 generates print data signals HD-DATA3, HD-DATA2, HD-DATA1 and HD-DATA0 (hereinafter collectively referred to as HD-DATA) based on the video signal S2, and generates these signals as a clock signal HD-. It is transmitted to the print head 33 of the image forming unit 16 (FIG. 2) together with CLK. That is, the control unit 3 transmits the print data for four pixels to the print head 33 in parallel at every time interval based on the clock signal HD-CLK using the four types of print data signals HD-DATA3 to HD-DATA0. .

  Further, the control unit 3 transmits the print data signal HD-DATA to the print head 33 and then transmits the latch signal HD-LOAD, thereby holding the print data signal HD-DATA in the print head 33. Further, the control unit 3 supplies a strobe signal HD-STB-N indicating the timing at which the light emitting element should actually emit light to the print head 33. Incidentally, the strobe signal HD-STB-N has a negative logic, and the light emitting element of the print head 33 is caused to emit light during the low level period.

  Thus, the print head 33 can form an electrostatic latent image line by line on the peripheral side surface of the photosensitive drum 38 by causing each light emitting element to emit light in a light emission pattern based on the image data.

[1-2. Printhead configuration]
Next, the configuration of the print head 33 will be described with reference to FIG. FIG. 4 is a schematic cross-sectional view of the print head 33. For convenience of explanation, FIG. 4 shows a state in which the print head 33 in FIG. 2 is half-rotated on the paper surface, that is, a state in which the up-down direction and the front-rear direction are both reversed. Hereinafter, the upper direction in FIG. 4 is also referred to as an irradiation direction, and the lower direction is also referred to as a counter-irradiation direction.

  A print head 33 as an optical print head is configured around a base member 51. The base member 51 is formed in a flat rectangular parallelepiped shape or plate shape having a short length in the front-rear direction and a shorter length in the vertical direction than the length in the left-right direction, and has sufficient strength. doing. A printed wiring board 52 is provided on the irradiation direction side (that is, the lower side) of the base member 51. Compared with the base member 51, the printed wiring board 52 has substantially the same length in the left-right direction and the front-rear direction, and the length in the up-down direction is slightly shorter, that is, thinner. The printed wiring board 52 is made of, for example, glass epoxy resin, and predetermined circuit patterns are formed on the upper and lower surfaces.

  On the irradiation direction side of the printed wiring board 52, for example, a large number of light emitting element chips 53 such as 26 are so-called aligned in the left-right direction (hereinafter also referred to as the main scanning direction). It is attached by die bonding technology. In each light emitting element chip 53, for example, a large number of light emitting elements (for example, LEDs) such as 192 are formed in a state aligned in the left-right direction.

  On the irradiation direction side of the printed wiring board 52, a large number of driver ICs (Integrated Circuits) 54 such as 26 are arranged in a line along the left-right direction on the rear side of each light emitting element chip 53, for example. It is attached in the state. Each driver IC 54 serving as a drive circuit is provided with 192 element driving units for driving 192 light emitting elements provided on the light emitting element chip 53. For convenience of explanation, hereinafter, the 26 driver ICs 54 (that is, drive circuits) are collectively referred to as a drive circuit group, and the light emitting elements are also referred to as driven elements.

  As described above, since 26 light emitting element chips 53 are provided on the printed wiring board 52 and 192 light emitting elements are provided on each light emitting element chip 53, a total of 4992 light emitting elements are provided. It will be. In addition, the print head 33 (FIGS. 2 and 4) has, for example, a length in the left-right direction substantially equal to the length of the short side (210 [mm]) in the A4 size, and 4992 pieces within this length range. The light emitting elements are arranged at equal intervals. Accordingly, the print head 33 can generate an electrostatic latent image having a resolution of 600 [dpi] on the peripheral side surface of the photosensitive drum 38 (FIG. 2).

  Incidentally, each light emitting element chip 53 and each driver IC 54 are electrically connected with a circuit pattern formed on the printed wiring board 52 by a plurality of bonding wires (not shown).

  In the print head 33 (FIG. 4), the base member 51 and the printed wiring board 52 described above are attached to a holder 56. The holder 56 as a whole has a shape obtained by removing a side surface on the side opposite to the irradiation direction from a hollow quadrangular prism formed along the left-right direction, and its cross section is inverted upside down from the capital letter “U”. The shape is such that the side opposite to the irradiation direction is opened.

  A support portion 56 </ b> A that supports the printed wiring board 52 is formed on the inner surface of the holder 56 on the irradiation direction side. The print head 33 is inserted in a state where the printed wiring board 52 and the base member 51 are overlapped in the holder 56 at the time of manufacture, and clamp members 57 and 58 are further attached. The clamp members 57 and 58 are both made of metal, and are fixed in a state where the irradiation direction surface of the printed wiring board 52 is in contact with the support portion 56 </ b> A of the holder 56 through the base member 51 by the action of elastic force. . As a result, the positional relationship between the light emitting element of the light emitting element chip 53 attached to the printed wiring board 52 and the holder 56 is determined.

  An attachment hole 56H that is an elongated long hole extending in the left-right direction and penetrates in the vertical direction is formed near the center of the irradiation direction side portion of the holder 56, and the rod lens array 59 is attached to the attachment hole 56H. The rod lens array 59 has a configuration in which a plurality of minute lenses having optical axes along the vertical direction are arranged in the horizontal direction so that each lens is focused on each light emitting element of the light emitting element chip 53. The fixing position is fixed in the adjusted state.

  Next, the circuit configuration of the print head 33 will be described with reference to FIG. In the print head 33, a plurality of driver ICs 54 are cascade-connected to each other. That is, the print head 33 is connected in series from the uppermost driver IC 54 to the lowermost driver IC 54. In the print head 33, one light emitting element chip 53 is connected to one driver IC 54.

  5 shows only two driver ICs 54 from the uppermost side and two light emitting element chips 53 corresponding to each of them as a part of the print head 33, and the other driver ICs 54 and the light emitting element chips 53. Is omitted.

  Each driver IC 54 is supplied with the latch signal HD-LOAD, the clock signal HD-CLK, and the strobe signal HD-STB-N from the control unit 3 (FIGS. 1 and 3), respectively, and the latch terminal LOAD, the clock terminal CLK, and the strobe terminal. Each is input to the STB. Each driver IC 54 is supplied with a power supply voltage (VDD) and a predetermined reference voltage (VREF), and has a ground terminal GND connected to the ground (GND).

  Further, each driver IC 54 has four data input terminals DATAI (DATAI3, DATAI2, DATAI1, and DATAI0) to which a print data signal is input, and four data output terminals DATAO (DATAO3, DATAO2, DATAO1) that output the print data signal. And DATAO0). Between the two cascaded driver ICs 54, the four data output terminals DATAO in the upper driver IC 54 are connected to the four data input terminals DATAI in the lower driver IC 54, respectively.

  The uppermost driver IC 54 receives four types of print data signals HD-DATA (HD-DATA3 to HD-DATA0) from the control unit 3 (FIGS. 1 and 3) to four data input terminals DATAI (DATAI3 to DATAI0). Each is entered. The uppermost driver IC 54 outputs four types of data signals from the four data output terminals DATAO (DATAO3 to DATAO0), and supplies them to the next driver IC54. That is, the driver ICs 54 in the second and subsequent stages acquire each print data signal from the driver IC 54 on the upper stage side and supply each print data signal to the driver IC 54 on the lower stage side.

  In each driver IC 54, 192 output terminals DO1 to DO192 are connected to anode terminals of 192 light emitting elements (that is, light emitting diodes) LE provided in the light emitting element chip 53, respectively. The cathode terminal of each light emitting element LE is connected to the ground (GND).

  In this way, the print head 33 sequentially supplies the print data signal to all the driver ICs 54 by sequentially transferring the print data signal from the upper side to the lower side between the driver ICs 54 connected in cascade with each other. Each light emitting element LE of each light emitting element chip 53 is driven (that is, light is emitted).

  By the way, as described above, a large number of 26 light emitting element chips 53 and driver ICs 54 are mounted on the printed wiring board 52 in the print head 33. For this reason, in the print head 33, even if one driver IC 54 is a defective product at the time of manufacture, or even when a mounting failure occurs due to a displacement of the mounting position with respect to the printed wiring board 52, the print head 33 33 as a whole becomes defective.

  For this reason, in the print head 33, it is desirable to inspect whether there is a manufacturing defect or a mounting defect in the driver IC 54 when the light emitting element chip 53 and the driver IC 54 are mounted on the printed wiring board 52. For example, in the print head 33, a predetermined jig is appropriately connected to the printed wiring board 52, and a current flowing through the driver IC 54 is detected in a state where a predetermined signal is supplied. A test method called an IDDq test is known. If the print head 33 can perform the IDDq test normally, it can detect the presence or absence of a failure with high accuracy in a relatively short time.

[1-3. Circuit configuration of driver IC]
Next, the circuit configuration of the driver IC 54 will be described with reference to FIG. The clock buffer circuit 61 appropriately shapes and amplifies the clock signal HD-CLK (FIG. 5) supplied from the clock terminal CLK, and then supplies it to the clock terminals of the flip-flop (FF) circuit 63 (63A1 to 63D48). To do.

  The input buffer circuit 62D appropriately shapes and amplifies the print data signal HD-DATA3 input from the data input terminal DATAI3, and then to the input terminal of the flip-flop circuit 63D1 (shown as an English letter “D” in the figure). Supply. The flip-flop circuit 63D1 supplies the print data signal HD-DATA3 from the output terminal (shown as the letter “Q” in the drawing) to the latch circuit 71 and the correction value storage unit 75 at a timing in accordance with the clock signal HD-CLK. At the same time, it is supplied to a flip-flop circuit 63D2 (not shown) in the subsequent stage.

  In the driver IC 54, 48 flip-flop circuits 63D1 to 63D48 are cascade-connected. For this reason, each flip-flop circuit 63 sequentially supplies the print data signal HD-DATA3 to the flip-flop circuit 63 in the next stage at a cycle in accordance with the clock signal HD-CLK. In other words, each flip-flop circuit 63 shifts the print data signal HD-DATA3 to the flip-flop circuit 63 at the next stage in synchronization with the clock signal HD-CLK.

  The lowermost flip-flop circuit 63D48 supplies the print data signal HD-DATA3 to the output buffer circuit 64D. The output buffer circuit 64D shapes and amplifies the supplied print data signal HD-DATA3 as appropriate, and supplies it to the data output terminal DATAO3 (details will be described later).

  That is, the driver IC 54 sequentially shifts the print data signal HD-DATA3 input from the data input terminal DATAI3 to the subsequent stage side (that is, the lower stage side) by the flip-flop circuits 63D1 to 63D48 in synchronization with the clock signal HD-CLK. . For convenience of explanation, the input buffer circuit 62D, the flip-flop circuits 63D1 to 63D48, and the output buffer circuit 64D will be collectively referred to as a shift register circuit 60D below.

  The driver IC 54 includes input buffer circuits 62C, 62B, and 62A configured similarly to the input buffer circuit 62D, and flip-flop circuits 63C1 to 63C48, 63B1 to 63B48, and 63A1 configured similar to the flip-flop circuits 63D1 to 63D48. To 63A48. Further, the driver IC 54 is provided with output buffer circuits 64C, 64B and 64A configured similarly to the output buffer circuit 64D.

  That is, the driver IC 54 is formed with 48 stages of shift register circuits 60C, 60B, and 60A configured in the same manner as the shift register circuit 60D. The shift register circuits 60C, 60B, and 60A shift the print data signals HD-DATA2, HD-DATA1, and HD-DATA0, respectively.

  The driver IC 54 includes 192 latch circuits 71 and 192 correction value storage units 75 and 192 corresponding to the flip-flop circuits 63 (63D1 to 63D48, 63C1 to 63C48, 63B1 to 63B48, and 63A1 to 63A48), respectively. The element driving units 77 are provided.

  The latch buffer circuit 65 appropriately shapes and amplifies the latch signal HD-LOAD supplied from the latch terminal LOAD, supplies the latch signal HD-LOAD to each latch circuit 71, and supplies the latch circuit 71 to the NOR circuit 73 and the driver control unit 74, respectively. . Each latch circuit 71 latches the print data signal HD-DATA (HD-DATA3 to HD-DATA0) stored in each flip-flop circuit 63 in accordance with the latch signal HD-LOAD, and supplies it to the element driving unit 77.

  On the other hand, the strobe terminal STB is connected to the pull-up resistor 72, the NOR circuit 73, and the driver control unit 74, respectively. Therefore, the strobe signal HD-STB-N supplied to the strobe terminal STB is supplied to the NOR circuit 73 and the driver control unit 74, respectively.

  The NOR circuit 73 calculates the NOR (negative OR) of the strobe signal HD-STB-N and the latch signal HD-LOAD, thereby generating the element drive control signal DRV ON-N, and outputs the element drive control signal DRV ON-N. To supply.

  Based on the strobe signal HD-STB-N and the latch signal HD-LOAD, the driver control unit 74 (denoted as CTRL in FIG. 6) has four types of memory write signals W3, W2, W1, and W0 and a standby signal STBY- Each P is generated. The memory write signal W (W3 to W0) is a signal for instructing the correction value storage unit 75 to store a correction value (described later), and is supplied to each correction value storage unit 75. The standby signal STBY-P is a signal for instructing whether to operate each element driving unit 77 or to set the standby state with reduced power consumption without operating each element driving unit 77, and is supplied to the control voltage generating unit 76.

  When the standby signal STBY-P is at a low level, the control voltage generation unit 76 (denoted as ADJ in FIG. 6) supplies the reference voltage VREF to each element driving unit 77 to operate, while the standby signal STBY-P Is at the high level, the supply of the reference voltage VREF is stopped, and each element driving unit 77 is set in a standby state.

  By the way, the light emitting elements LE of the light emitting element chip 53 (FIG. 5) have different current values to be supplied in order to emit a predetermined amount of light, that is, have variations in light emission characteristics. Therefore, the print head 33 should be supplied to each light emitting element LE in order to emit light of a constant light amount after the light emitting characteristics of each light emitting element LE are measured using a predetermined measuring device after the manufacture. A current value is calculated as a correction value from a predetermined reference current value. This correction value is expressed as 4-bit correction data, and is stored in a nonvolatile storage unit (not shown) such as an EEPROM (Electronically Erasable and Programmable Read Only Memory).

  This correction value is supplied to each correction value storage unit 75 of each driver IC 54 before performing the printing process. The correction value storage unit 75 (denoted by MEM in FIG. 6) stores 4-bit correction data and can supply the correction data to the element driving unit 77.

  For example, when the memory write signal W (W3 to W0) is supplied, the correction value storage unit 75 regards this as an address. At this time, the flip-flop circuit 63 is supplied with a print data signal based on correction data stored in a nonvolatile storage unit (not shown). The correction value storage unit 75 regards the print data signal supplied from the flip-flop circuit 63 as 1-bit correction data, and stores 1-bit correction data at the address indicated by the memory write signal W.

  The correction value storage unit 75 can store correction data for 4 bits by repeating such processing while the memory write signal W is sequentially changed. The correction value storage unit 75 supplies the correction data stored in this way to the element driving unit 77 from the output terminals Q3, Q2, Q1, and Q0.

  The element driving unit 77 (denoted as DRV in FIG. 6) is supplied with the element driving control signal DRV ON-N from the NOR circuit 73, supplied with the control voltage V from the control voltage generating unit 76, and with the print data signal from the latch circuit 71. HD-DATA is supplied, and correction data is further supplied from the correction value storage unit 75. When the print data signal HD-DATA is at a high level and the element drive control signal DRV ON-N is also at a high level, the element drive unit 77 generates a drive current having a magnitude based on the correction data, Light is supplied from the output terminal DO to the light emitting element LE (FIG. 5).

[1-4. Configuration and basic operation of output buffer circuit]
Next, the configuration of the output buffer circuit 64 (64D to 64A) will be described with reference to FIG. FIG. 7A shows a symbol (circuit symbol) of the output buffer circuit 64, which is used in the circuit diagram of FIG. 7A also shows an input terminal PA and an output terminal PY for convenience of explanation.

  FIG. 7B is a circuit diagram showing the internal configuration of the output buffer circuit 64. The output buffer circuit 64 includes inverters 81 and 82, NMOS (N Metal Oxide Semiconductor) transistors 83 and 84, and a PMOS transistor 85. The inverter 81 has an input terminal connected to the input terminal PA of the output buffer circuit 64, and an output terminal connected to the input terminal of the inverter 82, the gate terminal of the NMOS transistor 83, and the gate terminal of the PMOS transistor 85.

  The output terminal of the inverter 82 is connected to the gate terminal of the NMOS transistor 84 through the point PC. The power supply voltage VDD is supplied to the drain terminal of the NMOS transistor 84 and the source terminal of the PMOS transistor 85, respectively. The source terminal of the NMOS transistor 83 is connected to the ground. The drain terminal of the NMOS transistor 83, the source terminal of the NMOS transistor 84, and the drain terminal of the PMOS transistor 85 are all connected to the output terminal PY of the output buffer circuit 64.

  Further, the PMOS transistor 85 has an extremely small element area, the current driving capability is remarkably small, and the saturation current is also small as compared with the NMOS transistor 84. For example, the saturation current of the NMOS transistor 84 is several tens [mA], whereas the saturation current of the PMOS transistor 85 is several tens [μA].

  The output buffer circuit 64 sets the output of the inverter 81 to a high level when a low level signal (for example, the print data signal HD-DATA) is input to the input terminal PA. Accordingly, the NMOS transistor 83 is turned on and the PMOS transistor 85 is turned off. As a result, in the output buffer circuit 64, the output terminal PY has the same potential as the ground, and a low level signal is output from the output terminal PY. For convenience of explanation, the voltage of the signal output from the output terminal PY is hereinafter also referred to as an output voltage.

  On the other hand, when a high level signal is input to the input terminal PA, the output buffer circuit 64 sets the output of the inverter 81, that is, the potential at the point PB to the low level. As a result, the output buffer circuit 64 sets the output of the inverter 82, that is, the potential of the point PC to a high level so as to be substantially equal to the power supply voltage VDD. As a result, although the NMOS transistor 84 is turned on, a potential difference corresponding to the threshold voltage Vt is generated between the gate and the source.

  Therefore, in the output buffer circuit 64, immediately after the high level signal is input to the input terminal PA, the potential of the output terminal PY connected to the source terminal of the NMOS transistor 84 is higher than the power supply voltage VDD which is the potential of the gate terminal. Is also lowered by the threshold voltage Vt. For example, in the output buffer circuit 64, when the power supply voltage VDD is about 5 [V], the threshold voltage Vt is about 1.5 [V], so the voltage of the output terminal PY that is at a high level (that is, the output voltage) is high. It becomes about 3.5 [V]. For convenience of explanation, a voltage lower than the power supply voltage VDD by the threshold voltage Vt is hereinafter referred to as an intermediate voltage Vm.

  At this time, in the output buffer circuit 64, since the potential at the point PB is substantially 0 [V], the PMOS transistor 85 is turned on and tries to pull up the voltage (output voltage) of the output terminal PY to the power supply voltage VDD. However, the PMOS transistor 85 has an extremely small current driving capability as compared with the NMOS transistor 84, and therefore has a very large time constant. That is, the PMOS transistor 85 pulls up the output voltage to the power supply voltage VDD over a sufficiently longer time than the NMOS transistor 84. Hereinafter, the time required to raise the output voltage from approximately 0 [V] to approximately the same level as the power supply voltage VDD by the PMOS transistor 85 is also referred to as a pull-up time TU.

  That is, when a high level signal is input to the input terminal PA, the output buffer circuit 64 immediately sets the output voltage to the intermediate voltage Vm (about 3.5 [V]) by the NMOS transistor 84, and then the PMOS transistor 85. As a result, the power supply voltage is increased to almost the power supply voltage VDD (about 5 [V]) over a sufficiently long pull-up time TU.

  As described above, when a high level signal is input to the input terminal PA, the output buffer circuit 64 changes the output voltage, which is the voltage of the output terminal PY, with the passage of time.

[1-5. Printing operation]
Next, the operation of each unit and the signal waveform and the like when performing printing processing in the image forming apparatus 1 will be described. When the control unit 3 (FIG. 3) detects that the paper P (FIG. 1) has been conveyed and has reached a printable position, the control unit 3 (FIG. 3) gives a predetermined waveform to the image processing unit 48 as shown in the signal waveform of FIG. The timing signal S3 is transmitted every line cycle TL1 (that is, the signal level is temporarily lowered to a low level). In response to this, the image processing unit 48 receives the video signal S2 edited in units of pages, line by line, based on image data supplied from a host device (not shown).

  Subsequently, the control unit 3 sequentially distributes the video signal S2 corresponding to the print data for one line into four print data signals HD-DATA3, HD-DATA2, HD-DATA1, and HD-DATA0 for each dot, This is supplied to the uppermost driver IC 54 (FIG. 5) in the print head 33.

  Incidentally, since the control unit 3 uses four print data signals HD-DATA, 4992 dots of data corresponding to 4992 light emitting elements LE are converted into 4992/4 = 1248 pulses of clock signal HD-CLK. Can be transmitted.

  Further, when the control unit 3 receives the video signal S2 for one line from the image processing unit 48, the control unit 3 transmits a latch signal HD-LOAD to each driver IC 54 (that is, temporarily rises to a high level), thereby printing data. The signal HD-DATA is held in each latch circuit 71 (FIG. 6). For this reason, the control unit 3 receives each light emitting element in a pattern based on the print data signal HD-DATA held in each latch circuit 71 while the video signal S2 of the next line is received from the image processing unit 48. The LE can be caused to emit light, that is, the printing process can proceed.

  Next, the control unit 3 transmits the strobe signal HD-STB-N to each driver IC 54 (that is, temporarily falls to the low level), so that the supplied print data signal HD-DATA is at the high level. A drive current is supplied from the output terminal DO of the element driving unit 77 (FIG. 6) to each light emitting element LE (FIG. 5). As a result, the print head 33 (FIG. 2) can form image data based on the electrostatic latent image line by line on the peripheral side surface of the photosensitive drum 38.

  Next, the operation of each part, the signal waveform, etc. in the output buffer circuit 64 (FIG. 7B) will be described. Here, as shown in FIG. 9, the print data signal HD-DATA supplied to the output buffer circuit 64 switches from the value “0” to the value “1” at time T1, and the potential of the input terminal PA changes from low level to high. Assume that you have been launched to a level.

  At this time, the potential at the point PB changes from the high level to the low level. Further, the potential at the point PC changes from the low level to the high level. As a result, in the output buffer circuit 64, the NMOS transistor 84 is turned on, and the output terminal PY changes from the low level to the high level. At this time, in the output buffer circuit 64, as described above, the output voltage is immediately set to the intermediate voltage Vm (about 3.5 [V]) by the NMOS transistor 84, and then the power supply voltage is sufficiently long by the PMOS transistor 85. It tries to increase to the same level as VDD (about 5 [V]).

  However, in the print head 33, the clock period TC (FIG. 9), which is the period of the clock signal HD-CLK (FIG. 8), is the pulling time that is the time required for the PMOS transistor 85 to raise the output voltage to the power supply voltage VDD. It is sufficiently shorter than TU. Therefore, in the print head 33, the time corresponding to the clock cycle TC elapses while the output voltage hardly rises from the intermediate voltage Vm.

  In the print head 33, the NMOS transistor 84 transitions from the off state to the on state at time T1, and the NMOS transistor 83 transitions from the on state to the off state almost simultaneously. Therefore, in the print head 33, the through current Is1 flows from the supply terminal of the power supply voltage VDD to the ground for a very short time at the time point T1. As shown in FIG. 9, the maximum value of the through current Is1 is referred to as a peak current Ip1.

  Next, in the output buffer circuit 64, the supplied print data signal HD-DATA is switched from the value “1” to the value “0” at the time T2 when the clock cycle TC has elapsed from the time T1, and the potential of the input terminal PA is high. Assume that the level has been lowered from the low level.

  At this time, the potential at the point PB changes from the low level to the high level. Further, the potential of the point PC changes from the high level to the low level. As a result, in the output buffer circuit 64, the NMOS transistor 84 is turned off and the NMOS transistor 83 is turned on, so that the output terminal PY changes from the high level (that is, the intermediate voltage Vm) to the low level (that is, approximately 0 [V]). And transition.

  Thereafter, the output buffer circuit 64 changes the potential of the input terminal PA to the high level or the low level at the time points T3 and T4 similarly to the time points T1 and T2, respectively, and in response thereto, the output voltage similarly to the time points T1 and T2. Is shifted to a high level (ie, intermediate voltage Vm) or a low level (ie, approximately 0 [V]).

  As described above, in the output buffer circuit 64, the potential of the output terminal PY is also switched to the high level or the low level in response to the potential of the input terminal PA being switched to the high level or the low level, but is output from the output terminal PY. The amplitude of the signal is about 3.5 [V] which is the magnitude of the intermediate voltage Vm.

  Further, it is assumed that the output buffer circuit 64 holds this state after the elapse of the clock cycle TC after the potential of the input terminal PA is raised from the low level to the high level at the time T5, similarly to the time T1. . In this case, the output voltage of the output buffer circuit 64 immediately becomes the intermediate voltage Vm by the NMOS transistor 84, and then is gradually raised by the PMOS transistor 85 that is kept on, and eventually the pull-up time TU elapses. Then, the power supply voltage VDD is almost reached.

[1-6. Through current]
Next, a through current generated in the input buffer circuit 62 (FIG. 6) of the driver IC 54 will be described. FIG. 10A shows the circuit configuration of the output buffer circuit 64D in the upper driver IC 54A and the input buffer circuit 62D in the lower driver IC 54B in the two driver ICs 54A and 54B connected in cascade with each other. Yes. The output buffer circuit 64D is configured in the same manner as in FIG.

  The input buffer circuit 62D is configured such that two stages of inverter circuits having a so-called push-pull configuration are connected in series. That is, in the input buffer circuit 62D, the inverter circuit 91 in the previous stage is configured by the PMOS transistor 92 and the NMOS transistor 93, and the inverter circuit 94 in the subsequent stage is configured by the PMOS transistor 95 and the NMOS transistor 96.

  The PMOS transistor 92 has a gate terminal connected to the data input terminal DATAI3 of the driver IC 54B, a source terminal supplied with the power supply voltage VDD, and a drain terminal connected to the point PJ. The NMOS transistor 93 has a gate terminal connected to the data input terminal DATAI3 of the driver IC 54B, a source terminal connected to the ground, and a drain terminal connected to the point PJ. The gate terminals of the PMOS transistor 95 and the NMOS transistor 96 are connected to the point PJ.

  Here, the input / output characteristics in the inverter circuit 91, that is, the relationship between the input potential Vi and the output potential Vo can be schematically represented by a curve as shown in FIG. Here, the input potential Vi is a potential at the data input terminal DATAI3, and the output potential Vo is a potential at the point PJ.

  In the inverter circuit 91, when the input potential Vi is 0 [V], the output potential Vo is 5 [V] which is the power supply voltage VDD. In the inverter circuit 91, when the input potential Vi increases from 0 [V] and approaches a threshold potential Vt * (for example, 1.5 [V]), the output potential Vo starts to decrease. Further, in the inverter circuit 91, when the input potential Vi approaches 5 [V], the output potential Vo becomes 0 [V].

  On the other hand, the through current Is2 in the inverter circuit 91, that is, the relationship between the magnitude of the current flowing from the source terminal of the PMOS transistor 92 through the point PJ to the source terminal of the NMOS transistor 93 and the input potential Vi is as shown in FIG. Can be schematically represented by a simple curve.

  In the inverter circuit 91, when the input potential Vi is 0 [V], the through current Is2 is substantially 0 [A]. In the inverter circuit 91, as the input potential Vi increases from 0 [V], the through current Is2 increases. When the input potential Vi reaches the threshold potential Vt *, the through current Is2 is the maximum. The peak current Ip2 [A] is obtained.

  Further, in the inverter circuit 91, when the input potential Vi rises above the threshold potential Vt *, the through current Is2 decreases, but even when the input potential Vi becomes the intermediate voltage Vm (about 3.5 [V]). The through current Is2 is about several tens of m [A]. Eventually, in the inverter circuit 91, when the input potential Vi further rises to 5 [V] which is equal to the power supply voltage VDD, the through current Is2 becomes almost 0 [A].

  As can be seen from FIG. 10C, in the inverter circuit 91, the potential of the data input terminal DATAI3 in the upper driver IC 54B, that is, the output voltage in the output buffer circuit 64D of the lower driver IC 54A is the intermediate voltage Vm (about 3). .5 [V]), a through current Is2 is generated. In this case, the print head 33 cannot accurately detect the presence or absence of leakage current that occurs when there is a manufacturing defect, and the so-called IDDq test may not be performed normally.

  On the other hand, in the inverter circuit 91, when the potential of the data input terminal DATAI3 in the driver IC 54B, that is, the output voltage in the output buffer circuit 64D of the driver IC 54A is the power supply voltage VDD (about 5 [V]), the through current Is2 is set to almost 0 [ A]. In this case, the print head 33 can accurately detect the presence or absence of a leakage current that occurs when there is a defective portion, and the so-called IDDq test can be normally performed.

[1-7. Effect]
In the above configuration, the print head 33 of the image forming apparatus 1 according to the first embodiment includes the NMOS transistor 84 and the PMOS transistor 85 on the pull-up side in the output buffer circuit 64 (FIG. 7B) of the driver IC 54. Connected in parallel. Among these transistors, the PMOS transistor 85 has an extremely small device area, a significantly smaller current drive capability, and a smaller saturation current than the NMOS transistor 84.

  Here, for comparison with the output buffer circuit 64, an output buffer circuit 164 having a general push-pull configuration as shown in FIG. 11 is assumed. Compared with the output buffer circuit 64, the output buffer circuit 164 is provided with a PMOS transistor 186 while the inverter 82, the NMOS transistor 84, and the PMOS transistor 85 are omitted. As with the PMOS transistor 85 of the output buffer circuit 64, the PMOS transistor 186 has a gate terminal connected to the point PB, a source terminal supplied with the power supply voltage VDD, and a drain terminal connected to the output terminal PY.

  When a low level signal is input to the input terminal PA, the output buffer circuit 164 sets the output of the inverter 81 to a high level. Accordingly, the NMOS transistor 83 is turned on and the PMOS transistor 186 is turned off. As a result, in the output buffer circuit 64, the output terminal PY has the same potential as the ground, and a low level signal is output from the output terminal PY.

  On the other hand, when a high level signal is input to the input terminal PA, the output buffer circuit 164 sets the output of the inverter 81 to a low level. Accordingly, the NMOS transistor 83 is turned off, and the PMOS transistor 186 is immediately turned on. As a result, the output buffer circuit 164 has the output terminal PY at the same potential as the power supply voltage VDD, and outputs a high level signal of about 5 [V] from the output terminal PY.

  That is, in the output buffer circuit 164, as shown in the waveform diagram of FIG. 12 corresponding to FIG. 9, the output voltage varies greatly between the ground and the power supply voltage VDD, that is, full swing.

  Therefore, in the output buffer circuit 164, the through current Is3 is almost 0 [A] in the input buffer circuit 62 (FIGS. 6 and 10A), and the IDDq test can be performed normally, but the power consumption is relatively low. growing. In the output buffer circuit 164, as in the case of the output buffer circuit 64, a through current Is3 is generated for a moment. In the output buffer circuit 164, when a high level signal is output, the output voltage is about 5 [V]. Therefore, the peak current Ip3 in the through current Is3 has a relatively large value according to the output voltage. .

  In general, the power consumption Pd in the CMOS output circuit is obtained by using the operating frequency f in the CMOS output circuit, the load capacitance (equivalent capacitance, capacitance) CL connected to the output terminal, and the power supply voltage Vdd as follows: ) Expression. However, the load capacitance CL includes the input capacitance of the input buffer circuit that receives the signal of the CMOS output circuit, the capacitance of the signal wiring, the capacitance generated parasitically at the output terminal of the CMOS output circuit, and the like.

Pd = f × CL × Vdd ² (1)

  As can be seen from the equation (1), the driver IC 54 having the output buffer circuit 64 that is a CMOS output circuit has power consumption approximately proportional to the operating frequency f and proportional to the square of the power supply voltage Vdd. Along with this, the temperature also rises. Further, in the driver IC 54, charging and discharging of the load capacitance CL described above are performed as data is transferred, and accordingly, EMI (Electro Magnetic Interference) noise is generated.

  In contrast, in the output buffer circuit 64 according to the first embodiment, since the NMOS transistor 84 is provided on the pull-up side (FIG. 7B), the output buffer circuit 64 is relatively fast at a speed synchronized with the clock signal HD-CLK. When operating (hereinafter referred to as operating), the output voltage when the output terminal PY is set to the high level can be suppressed to the intermediate voltage Vm (about 3.5 [V]). This corresponds to the case where the power supply voltage Vdd is reduced to about 3.5 [V] in the above-described equation (1). Therefore, in the output buffer circuit 64, the power consumption can be reduced to about ½ compared to the output buffer circuit 164, that is, the power supply voltage Vdd is about 5 [V], and the temperature rises. Can also be significantly reduced.

  In operation, the output buffer circuit 64 suppresses the output voltage to the intermediate voltage Vm, so that the magnitude of the peak current Ip1 (FIG. 9) in the through current Is1 is changed to the through current Is3 of the output buffer circuit 164 (FIG. 11). Can be suppressed to be smaller than the peak current Ip3 (FIG. 12). As a result, the driver IC 54 can reduce charging and discharging currents with respect to the load capacitance CL that accompanies the data transfer, so that EMI noise can also be reduced.

  Further, when the output buffer circuit 64 continues to output a high level signal, the output voltage is raised from the intermediate voltage Vm (about 3.5 [V]) with time, and the pull-up time TU (FIG. 9) has elapsed. As a result, the power supply voltage VDD is set to approximately 5 [V] (hereinafter referred to as a stationary state). At this time, in the input buffer circuit 62 (FIG. 10A) connected to the output buffer circuit 64, the through current Is2 can be substantially 0 [A] (FIG. 10C). For this reason, the print head 33 can accurately detect a leakage current of about several μ [A] that occurs when there is a manufacturing defect, so that the so-called IDDq test can be performed normally.

  From another point of view, the output buffer circuit 64 has two requests that are incompatible with each other with respect to the output voltage. That is, on the one hand, the power supply voltage VDD is desired to be reduced in order to reduce power consumption and EMI noise, and on the other hand, a through current Is2 on the input buffer circuit 62 side in order to realize the IDDq test. In order to suppress this, the power supply voltage VDD is desired to be approximately the same.

  Of these, reduction of power consumption and reduction of EMI noise are requirements when printing processing is performed after the print head 33 is incorporated in the image forming apparatus 1, and the output voltage in the output buffer circuit 64 in accordance with the print data signal. Can be said to be a requirement at the time of the above-described operation.

  On the other hand, the realization of the IDDq test is a request when an inspection or the like before the print head 33 is incorporated into the image forming apparatus 1 is performed, and when the output voltage in the output buffer circuit 64 remains substantially constant, that is, It can be said that this is a request at rest.

  That is, in the output buffer circuit 64, the required output voltage varies depending on the situation (during operation or at rest). Therefore, in the output buffer circuit 64, an NMOS transistor 84 that operates in a very short time and a PMOS transistor 85 that operates over a relatively long time are connected in parallel (FIG. 7B). As a result, the output buffer circuit 64 can both suppress the output voltage to the intermediate voltage Vm during operation and increase it to the power supply voltage VDD when stationary. At this time, the output buffer circuit 64 does not need to change (that is, switch) the connection of each part by a switch or the like, and the circuit can be configured extremely simply.

  Further, the PMOS transistor 85 of the output buffer circuit 64 has a very small element area, thereby suppressing a current driving capability and a saturation current. For example, as shown in a schematic diagram in FIG. 13, the gate length GL of such a PMOS transistor 85 is determined by a process rule at the time of designing, so that the gate width GW has a size (length) that matches a desired saturation current. ). In other words, the PMOS transistor 85 can be adjusted to a desired saturation current only by appropriately setting the length of each part in the exposure pattern within a two-dimensional plane, for example.

  13A is a schematic cross-sectional view of the PMOS transistor 85, and FIG. 13B is a schematic plan view. 13A and 13B, in the PMOS transistor 85, the insulating layer Y2 is formed above the n-type silicon layer Y1, and the gate metal layer Y3G is provided above the insulating layer Y2. Further, a drain region Y1D and a source region Y1S are formed in the silicon layer Y1 at portions located on both sides of the gate metal layer Y3G, respectively, by implanting impurities.

  By the way, in the input buffer circuit 62 (FIGS. 6 and 10A), the threshold potential Vt * of the inverter circuit 91 is set to about 1.5 [V] in a typical design. As a result, the input buffer circuit 62 conforms to a so-called TTL (Transistor Transistor Logic) level interface and can be connected to, for example, the SN74LS series which is a typical IC of Texas Instruments. The input buffer circuit 62 can also be directly connected to a CMOS ASIC (Application Specific Integrated Circuit) having a power supply voltage of about 3.3 [V], as in the control unit 3 (FIG. 3).

  That is, in the operation of the driver IC 54, the input buffer circuit 62 (FIG. 10A) connected to the output terminal PY is supplied with a signal of about 3.5 [V] output from the output buffer circuit 64 on the upper stage side. Can be accepted as is. Therefore, in the driver IC 54, it is not necessary to change the configuration of the input buffer circuit 62 from the configuration of a general inverter circuit.

  According to the above configuration, in the print head 33 of the image forming apparatus 1 according to the first embodiment, in the output buffer circuit 64 of the driver IC 54, in addition to the NMOS transistor 84 on the pull-up side, the current drive capability is further increased. A small PMOS transistor 85 is provided. Therefore, the driver IC 54 suppresses the output voltage to the intermediate voltage Vm (about 3.5 [V]) during the operation of operating the output buffer circuit 64 at high speed, thereby reducing power consumption and EMI noise. On the other hand, the driver IC 54 raises the output voltage to the power supply voltage VDD (about 5 [V]) over the pull-up time TU at the time of stationary in which the high-level signal is continuously output from the output buffer circuit 64, and the input buffer The IDDq test can be performed with high accuracy by suppressing the through current Is2 of the circuit 62 to approximately 0 [A].

[2. Second Embodiment]
The image forming apparatus 201 (FIG. 1) according to the second embodiment is different from the image forming apparatus 1 according to the first embodiment in that it has a print head 233 (FIG. 2) instead of the print head 33. However, the other points are similarly configured. The print head 233 (FIG. 5) differs from the print head 33 according to the first embodiment in that it has a driver IC 254 instead of the driver IC 54, but is configured in the same manner in other respects.

  The driver IC 254 is different from the driver IC 54 (FIG. 6) according to the first embodiment in that the driver IC 254 has an output buffer circuit 264 instead of the output buffer circuit 64, and is configured similarly in other points. Yes. As shown in FIGS. 14A and 14B corresponding to FIGS. 7A and 7B, the output buffer circuit 264 is a bipolar NPN that replaces the NMOS transistor 84 as compared with the output buffer circuit 64. A transistor 284 is provided. The NPN transistor 284 has a base terminal connected to the output terminal of the inverter 82, a collector terminal supplied with the power supply voltage VDD, and an emitter terminal connected to the output terminal PY of the output buffer circuit 264.

  In the output buffer circuit 264, the device area of the PMOS transistor 85 is extremely small compared to the NPN transistor 284 as in the first embodiment, the current driving capability is remarkably small, and the saturation current is also small. Yes. For example, the saturation current of the NPN transistor 284 is several tens [mA] as in the case of the NMOS transistor 84, and is sufficiently larger than the several tens [μA] that is the saturation current of the PMOS transistor 85.

  With this configuration, when a low-level signal (for example, the print data signal HD-DATA) is input to the input terminal PA, the output buffer circuit 264 sets the output terminal PY to the same level as the ground as in the first embodiment. A low level signal is output from the output terminal PY.

  On the other hand, when a high level signal is input to the input terminal PA, the output buffer circuit 264 sets the output of the inverter 81, that is, the potential at the point PB to the low level. As a result, the output buffer circuit 264 sets the output of the inverter 82, that is, the potential of the point PC to a high level, and is substantially equal to the power supply voltage VDD.

  The NPN transistor 284 is turned on when the power supply voltage VDD is applied to the base terminal, but the base-emitter voltage corresponds to the forward voltage VF at the PN junction of silicon. Therefore, the output voltage of the output buffer circuit 264 becomes an intermediate voltage Vm2 that is lower than the power supply voltage VDD by the forward voltage VF. For example, in the NPN transistor 284, since the power supply voltage VDD is about 5 [V] and the forward voltage VF is about 0.6 [V], the intermediate voltage Vm2 is reduced from 5 [V] to 0.6 [V]. 4.4 [V].

  That is, when a high level signal is input to the input terminal PA, the output buffer circuit 264 immediately sets the output voltage to the intermediate voltage Vm2 (about 4.4 [V]) by the NPN transistor 284. Further, when a high level signal continues to be input to the input terminal PA as it is, the output buffer circuit 264 supplies the output voltage to the power supply over a sufficiently long pull-up time by the PMOS transistor 85 as in the first embodiment. The voltage is increased to VDD (about 5 [V]).

  As a result, the output buffer circuit 264 can reduce power consumption and EMI noise during operation as compared to the general push-pull output buffer circuit 164 (FIG. 11), as in the first embodiment. On the other hand, the IDDq test can be performed with high accuracy by suppressing the through current Is2 of the input buffer circuit 62 to approximately 0 [A] when stationary.

[3. Third Embodiment]
The image forming apparatus 301 (FIG. 1) according to the third embodiment is different from the image forming apparatus 1 according to the first embodiment in that it includes a print head 333 (FIG. 2) instead of the print head 33. However, the other points are similarly configured. The print head 333 (FIG. 5) is different from the print head 33 according to the first embodiment in that it has a driver IC 354 instead of the driver IC 54, but is configured in the same manner for other points.

[3-1. Configuration of Driver IC and Output Buffer Circuit]
As shown in FIG. 15 corresponding to FIG. 6, the driver IC 354 has an output buffer circuit 364 (364D, 364C, 364B, and 364A) in place of the output buffer circuit 64 as compared with the driver IC 54, and each output buffer. The difference is that the standby signal STBY-P is supplied to the circuit 364, and the other points are similarly configured.

  As shown in FIG. 16A corresponding to FIG. 7A, the output buffer circuit 364 has an input terminal PS added as compared with the output buffer circuit 64. In addition to this, the output buffer circuit 364 includes a NAND circuit 387 at a position where the output buffer circuit 364 interrupts between the input terminal PA and the gate terminal of the PMOS transistor 85 as shown in FIG. 16B corresponding to FIG. However, the other points are configured in the same manner.

  In other words, the NAND circuit 387 has one input terminal connected to the input terminal PA of the output buffer circuit 364 and the output terminal connected to the gate terminal of the PMOS transistor 85 via the point PD. Further, the NAND circuit 387 has the other input terminal connected to the input terminal PS.

  With this configuration, when the standby signal STBY-P supplied to the input terminal PS is at a high level, the output buffer circuit 364 has a function equivalent to that of the inverter 81 with respect to the signal input to the input terminal PA. Therefore, the operation is the same as that of the output buffer circuit 64 according to the first embodiment.

  In this case, when a low level signal is input to the input terminal PA, the output buffer circuit 364 outputs the low level signal from the output terminal PY with the NMOS transistor 83 equalizing the output voltage to the ground. Further, when a high level signal is input to the input terminal PA, the output buffer circuit 364 immediately sets the output voltage to the intermediate voltage Vm (about 3.5 [V]) by the NMOS transistor 84, and then further the PMOS transistor 85. As a result, the power supply voltage is increased to almost the power supply voltage VDD (about 5 [V]) over a sufficiently long pull-up time TU.

  On the other hand, when the standby signal STBY-P supplied to the input terminal PS is at a low level, the output buffer circuit 364 is connected to the output terminal and the dot of the NAND circuit 387 regardless of the signal level of the signal input to the input terminal PA. PD is always high, and the PMOS transistor 85 is always off.

  In this case, when a low level signal is input to the input terminal PA, the output buffer circuit 364 outputs the low level signal from the output terminal PY with the NMOS transistor 83 equalizing the output voltage to the ground. Further, when a high level signal is input to the input terminal PA, the output buffer circuit 364 immediately sets the output voltage to the intermediate voltage Vm (about 3.5 [V]) by the NMOS transistor 84. At this time, since the PMOS transistor 85 is in the OFF state, the output buffer circuit 364 maintains the output voltage as the intermediate voltage Vm regardless of the passage of time.

  As described above, when the standby signal supplied to the input terminal PS is at a high level, the output buffer circuit 364 causes the PMOS transistor 85 to function as in the first embodiment, while the standby signal is at a low level. Thus, the operation of the PMOS transistor 85 can be stopped.

[3-2. Control of operation status by standby signal]
Next, how the operation state of each unit is changed by the standby signal in the driver IC 354 will be described with reference to FIG. FIG. 17 schematically illustrates the control voltage generation unit 76 and one element driving unit 77 extracted from the driver IC 354 and further omits a part thereof.

  The control voltage generator 76 is mainly composed of an operational amplifier 411, PMOS transistors 412 and 413, and a resistor 414. The inverting input terminal of the operational amplifier 411 is connected to the VREF input terminal to which the reference voltage Vref is input. The non-inverting input terminal of the operational amplifier 411 is connected to the ground via the resistor 414.

  The standby terminal STBY of the control voltage generator 76 is connected to the standby input terminal of the operational amplifier 411 and the gate terminal of the PMOS transistor 413. The standby terminal STBY is supplied with a standby signal STBY-P for instructing the shift to the low power consumption mode (that is, the operation mode with reduced power consumption) from the driver control unit 74 (FIG. 15).

  The output terminal of the operational amplifier 411 is connected to the gate terminal of the PMOS transistor 412 and the element driver 77, and supplies the control voltage Vcontrol to each. The PMOS transistors 412 and 413 are connected in series with each other. That is, the power supply voltage VDD is supplied to the source terminal of the PMOS transistor 412. The drain terminal of the PMOS transistor 412 is connected to the source terminal of the PMOS transistor 413. The drain terminal of the PMOS transistor 413 is connected to the output terminal of the operational amplifier 411 and the resistor 414.

  On the other hand, the element driving unit 77 is mainly configured by an AND circuit 421, a PMOS transistor 422, an NMOS transistor 423, and a PMOS transistor 424. The AND circuit 421 receives the above-described element drive control signal DRV ON-N (FIG. 15) and correction data supplied from the correction value storage unit 75, and has output terminals of the PMOS transistor 422 and the NMOS transistor 423. Each is connected to a gate terminal.

  In the PMOS transistor 422, the power supply voltage VDD is supplied to the source terminal, and the drain terminal is connected to the drain terminal of the NMOS transistor 423 and the gate terminal of the PMOS transistor 424, respectively. The source terminal of the NMOS transistor 423 is connected to the control voltage generator 76 and is supplied with the control voltage Vcontrol described above. In other words, the PMOS transistor 422 and the NMOS transistor 423 constitute an inverter circuit. The output of the inverter circuit is input to the gate terminal of the PMOS transistor 422.

  In the PMOS transistor 424, the power supply voltage VDD is supplied to the source terminal, and the drain terminal is connected to the anode terminal of the light emitting element LE in the light emitting element chip 53. Incidentally, the cathode terminal of the light emitting element LE is connected to the ground.

  Here, when the resistance value of the resistor 414 of the control voltage generator 76 is Rref [Ω] and the current value flowing through the resistor 414 is Iref, the current value Iref is obtained by using the reference voltage Vref and the resistance value Rref. The following equation (2) can be expressed.

  Iref = Vref / Rref (2)

  The magnitude of the current value Iref is substantially equal to the magnitude of the drain current flowing through the drain terminal of the PMOS transistor 412.

  On the other hand, in the element driving unit 77, when the light emitting element LE emits light, the PMOS transistor 424 is in the on state and the NMOS transistor 423 is also in the on state. Therefore, a voltage obtained by subtracting the control voltage Vcontrol from the power supply voltage VDD is applied between the gate and source of the PMOS transistor 424. This voltage is equivalent to the voltage between the gate and source of the PMOS transistor 412. The PMOS transistor 424 and the PMOS transistor 412 both operate in the saturation region and are in a current mirror relationship with each other.

  Therefore, in the driver IC 354, by changing the magnitude of the drain current of the PMOS transistor 412, that is, the current value Iref in the resistor 414, a drain current having a magnitude substantially proportional to the current value Iref is caused to flow to the PMOS transistor 424. That is, it can be supplied to the light emitting element LE. In other words, the driver IC 354 can adjust the magnitude of the drive current supplied to the light emitting element LE by adjusting the magnitude of the current value Iref in the resistor 414.

  In the driver IC 354, when the standby signal STBY-P becomes a high level substantially equal to the power supply voltage VDD, the consumption current of the operational amplifier 411 becomes substantially 0 [A], and the potential at the gate terminal of the PMOS transistor 413 becomes the power supply voltage. It becomes almost equal to VDD, and the PMOS transistor 413 is turned off. As a result, in the driver IC 354, the current value Iref in the resistor 414 is set to approximately 0 [A], so that the currents flowing through the control voltage generator 76 and the element driver 77 are both set to approximately 0 [A]. Can do.

  Similarly to the driver IC 54 according to the first embodiment, the driver IC 354 is configured with other circuits using CMOS elements, so that the static current consumption is almost 0 [A]. As a result, even in the print head 333 provided with the driver IC 354, the current consumption in the low power consumption mode can be set to approximately 0 [A].

[3-3. Effect]
In the configuration described above, the print head 333 of the image forming apparatus 301 according to the third embodiment includes a NAND in the output buffer circuit 364 of the driver IC 354 in addition to the configuration similar to the output buffer circuit 64 according to the first embodiment. A circuit 387 is provided to input a standby signal STBY-P (FIG. 16).

  In the image forming apparatus 301, the standby signal STBY-P is at a low level in a state where each part in the driver IC 354 is operating due to print processing or the like, and the output buffer circuit 364 receives a print data signal or the like. Signals are sequentially input, and the signal level of the output terminal PY changes relatively quickly according to this.

  At this time, in the output buffer circuit 364, since the standby signal STBY-P is at a low level, the PMOS transistor 85 is always turned off regardless of the signal level of the signal input to the input terminal PA. For this reason, when a high level signal is input to the input terminal PA, the output buffer circuit 364 immediately sets the output voltage to the intermediate voltage Vm (about 3.5 [V]) by the NMOS transistor 84 and then passes the time. Regardless, this intermediate voltage Vm can be maintained.

  In other words, in the output buffer circuit 364, even when a certain amount of time has passed since the output voltage was switched to a high level, for example, when a high level continues for a while in the supplied print data signal, the output voltage is reduced. Since the intermediate voltage Vm can be maintained, there is no increase in power consumption or EMI noise.

  On the other hand, in the output buffer circuit 364, when both the standby signal STBY-P and the input terminal PA are at a high level, for example, at time T6 in FIG. 18 corresponding to FIG. 9, the PMOS transistor 85 is turned on. As a result, the output buffer circuit 364 gradually increases the output voltage from the intermediate voltage Vm (about 3.5 [V]), and is substantially equal to the power supply voltage VDD (about 5 [V]) after the pull-up time TU has elapsed. can do.

  Therefore, in the print head 333 in which the driver IC 354 is incorporated, when performing the IDDq test in the manufacturing process, the output voltage of the output buffer circuit 364 is almost equal to the power supply voltage VDD by setting the standby signal STBY-P to the high level. And the through current Is2 in the input buffer circuit 62 can be set to approximately 0 [A].

  In the driver IC 354, when the standby signal STBY-P is at a high level, the current flowing in each part of the control voltage generation unit 76 and the element driving unit 77 is almost 0 [A]. The static current consumption is almost 0 [A]. That is, the print head 333 can set the through current Is2 of the input buffer circuit 62 to almost 0 [A] only by setting the standby signal STBY-P to the high level, and the static consumption current of each circuit in the driver IC 354 is also increased. It can be almost 0 [A]. As a result, the print head 333 can eliminate the influence of other currents as much as possible in the IDDq test, so that the leak current can be detected with extremely high accuracy.

  Further, when the print head 333 shifts to the standby mode for the purpose of reducing power consumption after being incorporated into the image forming apparatus 301, each circuit in the driver IC 354 is set to high level by setting the standby signal STBY-P to high level. The static current consumption at can be made almost 0 [A]. At this time, in the print head 333, since the standby signal STBY-P is at the high level, the voltage when the output signal of the output buffer circuit 364 is set to the high level can be made equal to the power supply voltage VDD. The through current Is2 can be made almost 0 [A], which can contribute to reduction of power consumption.

  From another viewpoint, in the output buffer circuit 364, in addition to the standby signal STBY-P, various other signals existing in the driver IC 354, for example, the latch signal HD- It is conceivable to use LOAD or the like or generate a new signal.

  However, in the output buffer circuit 364, the output voltage can be maintained at the intermediate voltage Vm during the printing operation or the like by intentionally inputting the standby signal STBY-P to the input terminal PS. In addition, in the output buffer circuit 364, when the IDDq test is performed, the standby signal STBY-P is set to the high level, and the through current Is2 of the input buffer circuit 62 is set to approximately 0 [A] without performing any other processing. In addition, the static current consumption of each circuit in the driver IC 354 can be made substantially 0 [A] at the same time.

  In other respects, the driver IC 354 can achieve the same effects as the driver IC 54 according to the first embodiment.

  According to the above configuration, the print head 333 of the image forming apparatus 301 according to the third embodiment inputs the standby signal STBY-P to the output buffer circuit 364 of the driver IC 354. Since the print head 333 sets the standby signal STBY-P to the low level during operation, the PMOS transistor 85 of the output buffer circuit 364 is always turned off, and the intermediate voltage Vm can be maintained when the output voltage is set to the high level. There is no increase in power consumption or EMI noise. On the other hand, the print head 333 sets the standby signal STBY-P to the high level in the IDDq test, so that the static consumption current of each circuit in the driver IC 354 in addition to the through current Is2 of the input buffer circuit 62 is substantially 0 [ A], the leakage current can be detected with extremely high accuracy.

[4. Other Embodiments]
In the above-described first embodiment, the case where the NMOS transistor 84 is used on the pull-up side of the output buffer circuit 64 has been described (FIG. 7B). In the second embodiment, the case where the NPN transistor 284 is used on the pull-up side of the output buffer circuit 264 has been described (FIG. 16B). However, the present invention is not limited to this, and various switching elements may be used on the pull-up side of the output buffer circuit 64 and the like. In this case, when the output terminal PY is set to the high level by the operation of the switching element, it is only necessary to reduce the power consumption and the EMI noise by lowering the potential below the power supply voltage VDD. The same applies to the third embodiment.

  Further, in the above-described first embodiment, the case where the driver IC 54 drives (that is, emits light) the light emitting element LE that is a light emitting diode has been described. However, the present invention is not limited to this, and various elements that emit light such as a light emitting thyristor and an organic EL element may be driven by a driver IC 54, or a medium such as a heating element used in a thermal print head. On the other hand, various elements for forming an image may be driven by various methods. The same applies to the second and third embodiments.

  Further, in the above-described third embodiment, the case where the NMOS transistor 84 is used on the pull-up side of the output buffer circuit 364 has been described (FIG. 16B). However, the present invention is not limited to this. For example, an NPN transistor 284 may be used as in the output buffer circuit 264 (FIG. 13B) according to the second embodiment. That is, as shown in FIGS. 19A and 19B corresponding to FIGS. 16A and 16B, the output buffer circuit 464 can use an NPN transistor 284 instead of the NMOS transistor 84 on the pull-up side. .

  Further, in the above-described third embodiment, the case where the standby signal STBY-P is supplied to the input terminal PS of the output buffer circuit 364 has been described. However, the present invention is not limited to this, and various other signals may be supplied to the input terminal PS. In short, it is only necessary that the PMOS transistor 85 can be turned on in the output buffer circuit 364 (FIG. 16B) by supplying some signal at least when performing the IDDq test.

  Further, in the above-described first embodiment, the case where the present invention is applied to the image forming apparatus 1 that is an MFP has been described. However, the present invention is not limited to this. For example, the present invention may be applied to various electronic devices having a function of forming a toner image by an electrophotographic method and fixing it on a sheet, such as a copying machine or a facsimile machine. Further, the present invention is not limited to a device that performs so-called color printing by using a plurality of image forming units 16 corresponding to a plurality of colors, and may be applied to a device that performs single color (monochrome) printing by one image forming unit 16. . The same applies to the second and third embodiments.

  Furthermore, in the third embodiment described above, the saturation current of the PMOS transistor 85 is made sufficiently smaller than that of the NMOS transistor 84 in the output buffer circuit 364, so that a sufficiently long pull is obtained as in the first embodiment. The case where the output voltage is raised from the intermediate voltage Vm to the power supply voltage VDD over the upper time TU has been described. However, the present invention is not limited to this. For example, by making the saturation current of the PMOS transistor 85 equal to that of the NMOS transistor 84, the output voltage may be raised from the intermediate voltage Vm to the power supply voltage VDD in a very short time. . In this case, the PMOS transistor 85 can be appropriately switched to the on state or the off state by the standby signal STBY-P.

  Furthermore, in the first embodiment described above, a plurality of driver ICs 54 are cascade-connected, and the output voltage in the upper stage output buffer circuit 64 is increased to the same level as the power supply voltage VDD in the IDDq test, thereby lowering the input buffer on the lower stage side. The case where the through current Is2 (FIG. 10) in the circuit 62 is set to approximately 0 [A] has been described. However, the present invention is not limited to this. For example, various circuits different from the driver IC 54 may be connected to the output buffer circuit 64 as a lower circuit. In this case, if the output terminal PY of the output buffer circuit 64 is connected to the input terminal of an inverter circuit composed of complementary elements such as a CMOS circuit in the lower circuit, the case of the input buffer circuit 62 Similarly to the above, the conduction current Is2 can be set to approximately 0 [A]. The same applies to the second and third embodiments.

  Furthermore, the present invention is not limited to the above-described embodiments and other embodiments. That is, the scope of the present invention extends to embodiments in which some or all of the above-described embodiments and other embodiments described above are arbitrarily combined, and embodiments in which some are extracted. It is.

  Furthermore, in the first embodiment described above, the driver IC 54 as a drive circuit is constituted by an input buffer circuit 62 as an input buffer, an element drive unit 77 as an element drive unit, and an output buffer circuit 64 as an output buffer. The case of configuring was described. In this case, the output buffer is constituted by the NMOS transistor 84 as the first switching means, the PMOS transistor 85 as the second switching means, and the NMOS transistor 83 as the third switching means. However, the present invention is not limited to this, and a driving circuit is constituted by an input buffer, an element driving unit, and an output buffer having various other configurations, and a first switching unit and a second switching unit having other various configurations. And the third switching means may constitute an output buffer.

  The present invention can be used in, for example, an MFP that performs printing by forming a toner image by an electrophotographic method and fixing the toner image on a sheet.

  1, 201, 301 ... Image forming apparatus, 16 ... Image forming unit, 33, 233, 333 ... Print head, 52 ... Printed wiring board, 53 ... Light emitting element chip, 54, 254, 354 ... Driver IC, 62... Input buffer circuit, 64, 264, 364... Output buffer circuit, 74... Driver control unit, 76... Control voltage generation unit, 77. 84, 93, 96, 423 ... NMOS transistor, 85, 92, 95, 186, 412, 413, 422, 424 ... PMOS transistor, 91, 94 ... inverter circuit, 244, 414 ... resistance, 284 ... ... NPN transistor, 387 ... NAND circuit, 411 ... operational amplifier, 421 ... AND circuit, DATAI ... data input terminal , DATAO ... Data output terminal, DRVON-N ... Element drive control signal, GL ... Gate length, GW ... Gate width, HD-CLK ... Clock signal, HD-DATA ... Print data signal, HD-LOAD ... Latch signal, Is1, Is2, Is3 ... Through current, LE ... Light emitting element, PA, PS ... Input terminal, PY ... Output terminal, STBY-P ... Standby signal, TC ... Clock cycle, TU …… Pull-up time, VDD …… Power supply voltage, VF …… Forward voltage, VREF …… Reference voltage, Vm, Vm2 …… Intermediate voltage, Vt …… Threshold voltage.

Claims (9)

An input buffer to which a data signal is input from the upper stage side;
An element driver for driving the driven element based on the data signal;
An output buffer for outputting the data signal to the lower side,
The output buffer is
First switching means and second switching means for receiving a supply of power supply voltage and respectively setting a high level of the data signal;
Third switching means for setting the low level of the data signal,
The first switching means has a high level output voltage lower than the power supply voltage,
The drive circuit characterized in that the second switching means has a smaller current drive capability than the first switching means. The second switching means is a PMOS transistor;
The drive circuit according to claim 1, wherein a high-level output voltage in the second switching unit is equal to the power supply voltage. The time required for the second switching means to start the output at a high level until the output voltage reaches a voltage equivalent to the power supply voltage is longer than the cycle of the data signal. Item 3. The drive circuit according to Item 2. The first switching means is an NMOS transistor;
The drive circuit according to claim 1, wherein the high-level output voltage in the first switching unit is a value obtained by subtracting a threshold voltage of the NMOS transistor from the power supply voltage. The first switching means is a bipolar NPN transistor,
The drive circuit according to claim 1, wherein the high-level output voltage in the first switching means is a value obtained by subtracting a base-emitter voltage of the NPN transistor from the power supply voltage. The second switching means operates in accordance with the standby signal when the element driving unit transitions to a standby state in which the driven element is not driven in accordance with a predetermined standby signal. A driving circuit according to any one of the above. A drive circuit group comprising a plurality of cascaded drive circuits according to any one of claims 1 to 6,
The driven element is a light emitting element that emits light. The optical print head according to claim 7, wherein the input buffer of the driving circuit supplies the data signal to an inverter circuit configured by complementary elements. An image forming unit that generates an electrostatic latent image by exposing a photosensitive member by the optical print head according to claim 7 or 8, and forms an image based on the electrostatic latent image by a developer;
An image forming apparatus comprising: a fixing unit that fixes the image on a predetermined medium.

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